HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Changelog

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HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib

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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

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Select second commit Show combined diff		Commit Message	Age	Author	Refs
	`r688:c0c43c9d60f1 D`	Added lfr_output_save module in lpp_sim lib : this module permits to write in file all evolution of the analog LFR's output during a simulation Added test Test_DAC_to_File : an implementation example of lfr_output_save module.	Mon, 09 Jan 2017 15:17:46	pellion	Simu-LFR-FM tip	0
	`r687:88431f3070cd D`	Renamed the SPW_Light test directory from Validation_SPW_light to Test_SPW_Light. Added Test ADC RHF1401	Fri, 06 Jan 2017 20:12:06	pellion	Simu-LFR-FM	0
	`r686:ea8efb0bdfd4 D`	For simulation : Added spw-light->[TO]->txt-file and txt-file->[TO]->spw-light module Added test of those 2 IP with the spw-light	Thu, 05 Jan 2017 19:09:10	pellion	Simu-LFR-FM	0
	`r685:17d0356c0267 D`	Fixed top LFR-FM for simulation.	Thu, 05 Jan 2017 14:24:10	Jean-christophe Pellion	Simu-LFR-FM	0
	`r684:f4b71d81044a D`	Simu MINI-LFR testbench WIP	Thu, 05 Jan 2017 10:18:37	Jean-christophe Pellion	Simu-Mini-LFR	0
	`r683:892a270271d8 D`	Added missing opencores files.	Thu, 05 Jan 2017 10:40:13	jeandet	default	0
	`r682:c53e1b6b3045 D`	Few fixes. Whole LFR simulation WIP.	Wed, 04 Jan 2017 23:44:54	jeandet	default	0
	`r681:9d85f9f8f05a D`	MiniSpartan6: added ftdi chip config to switch between UART and Async FIFO. added few WIP designs with either spwlight core, FIFO_deom IP... Libs: added SpaceWire Light IP (Works really well!) started design of ahb_ftdi_fifo -> same protocol than AHBUART but over FTDI's Async FIFO interface. This might lead to much faster transfers UP to 12MB/s.	Wed, 04 Jan 2017 17:43:11	jeandet	default	0
	`r680:45edea4f35b8 D`	added re-run option to LFR filter random ram init test.	Wed, 21 Dec 2016 16:37:26	Jean-christophe Pellion	default	0
	`r679:04a44bf50f11 D`	Étiquette broken_iir_ram_simu ajoutée à la révision 98208521c583	Tue, 20 Dec 2016 20:08:50	Jean-christophe Pellion	broken_iir_ram	0
	`r678:98208521c583 D`	Reverted IIR filters RAM bug correction /!\ for test purpose only	Tue, 20 Dec 2016 20:08:21	Jean-christophe Pellion	broken_iir_ram broken_iir_ram_simu	0
	`r677:0fe5660f948f D`	Nop	Tue, 20 Dec 2016 20:01:06	Jean-christophe Pellion	default	0
	`r676:0a7aa144c9d5 D`	Few updates. Added LFR filter random ram init test.	Tue, 20 Dec 2016 19:57:49	Jean-christophe Pellion	default	0
	`r675:1993321a17d7 D`	Fusion	Tue, 20 Dec 2016 10:11:06	Alexis Jeandet	merge default	0
	`r674:b0efa9138022 D`	Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)	Tue, 20 Dec 2016 10:10:38	Alexis Jeandet	default	0
	`r673:d703390a92ae D`	updated test LFR_time_managment	Tue, 13 Dec 2016 16:55:17	pellion	default	0
	`r672:232c8ecfb720 D`	Cleaned LFR-EQM designs	Tue, 13 Dec 2016 10:41:16	Alexis Jeandet	default	0
	`r671:fb1595662984 D`	Clean LFR-EQM boards Updated SOLO_LFR_LFR-EQM top (changed lfr-version number)	Tue, 13 Dec 2016 10:38:06	Alexis Jeandet	default	0
	`r670:b68575ae3d3b D`	Renamed LFR-EQM-WFS_MS project to SOLO_LFR_LFR-EQM	Tue, 13 Dec 2016 10:23:10	Alexis Jeandet	default	0
	`r669:6e6166be9c6f D`	Étiquette SOLO_LFR_01-5B (LFR-FM) ajoutée à la révision f6e57cae6ba0	Tue, 13 Dec 2016 10:01:59	Alexis Jeandet	default	0
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