HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Changelog

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HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib

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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

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Select second commit Show combined diff		Commit Message	Age	Author	Refs
	`r683:892a270271d8 D`	Added missing opencores files.	Thu, 05 Jan 2017 10:40:13	jeandet	default	0
	`r682:c53e1b6b3045 D`	Few fixes. Whole LFR simulation WIP.	Wed, 04 Jan 2017 23:44:54	jeandet	default	0
	`r681:9d85f9f8f05a D`	MiniSpartan6: added ftdi chip config to switch between UART and Async FIFO. added few WIP designs with either spwlight core, FIFO_deom IP... Libs: added SpaceWire Light IP (Works really well!) started design of ahb_ftdi_fifo -> same protocol than AHBUART but over FTDI's Async FIFO interface. This might lead to much faster transfers UP to 12MB/s.	Wed, 04 Jan 2017 17:43:11	jeandet	default	0
	`r680:45edea4f35b8 D`	added re-run option to LFR filter random ram init test.	Wed, 21 Dec 2016 16:37:26	Jean-christophe Pellion	default	0
	`r677:0fe5660f948f D`	Nop	Tue, 20 Dec 2016 20:01:06	Jean-christophe Pellion	default	0
	`r676:0a7aa144c9d5 D`	Few updates. Added LFR filter random ram init test.	Tue, 20 Dec 2016 19:57:49	Jean-christophe Pellion	default	0
	`r675:1993321a17d7 D`	Fusion	Tue, 20 Dec 2016 10:11:06	Alexis Jeandet	merge default	0
	`r674:b0efa9138022 D`	Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)	Tue, 20 Dec 2016 10:10:38	Alexis Jeandet	default	0
	`r673:d703390a92ae D`	updated test LFR_time_managment	Tue, 13 Dec 2016 16:55:17	pellion	default	0
	`r672:232c8ecfb720 D`	Cleaned LFR-EQM designs	Tue, 13 Dec 2016 10:41:16	Alexis Jeandet	default	0
	`r671:fb1595662984 D`	Clean LFR-EQM boards Updated SOLO_LFR_LFR-EQM top (changed lfr-version number)	Tue, 13 Dec 2016 10:38:06	Alexis Jeandet	default	0
	`r670:b68575ae3d3b D`	Renamed LFR-EQM-WFS_MS project to SOLO_LFR_LFR-EQM	Tue, 13 Dec 2016 10:23:10	Alexis Jeandet	default	0
	`r669:6e6166be9c6f D`	Étiquette SOLO_LFR_01-5B (LFR-FM) ajoutée à la révision f6e57cae6ba0	Tue, 13 Dec 2016 10:01:59	Alexis Jeandet	default	0
	`r668:f6e57cae6ba0 D`	Updated SOLO_LFR_LFR-FM designs => added DATA_SHAPING_SATURATION in LPP_FILTER => changed boards number : LPP_LFR_BOARD_LFR_FM & X"015B"	Fri, 09 Dec 2016 14:22:54	Alexis Jeandet	default SOLO_LFR_01-5B (L...	0
	`r667:f5c31dc5d20d D`	Renamed design LFR-RTAX_keypoint into SOLO_LFR_LFR-FM Created LFR-FM boards Copied LFR-FM files from LFR-EQM in LFR-FM	Thu, 08 Dec 2016 13:51:27	Alexis Jeandet	default	0
	`r666:165069c8bf8d D`	Forward DATA_SHAPING_SATURATION generic from lpp_lfr to lpp_lfr_filter.	Wed, 07 Dec 2016 16:00:11	jeandet	default	0
	`r665:d5eea55633d7 D`	Deleted older LFR-EM's design	Wed, 07 Dec 2016 15:28:42	Alexis Jeandet	default	0
	`r664:35f5f9f216cf D`	Fusion	Wed, 07 Dec 2016 15:23:33	Alexis Jeandet	merge default	0
	`r663:6a09076d1642 D`	Étiquette SOLO_LFR_01-5B (LFR-EM) ajoutée à la révision f19abbf47ea7	Wed, 07 Dec 2016 15:09:45	Alexis Jeandet	default	0
	`r662:f19abbf47ea7 D`	Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards Renamed LFR-em-WFP_MS designs in SOLO_LFR_LFR-EM designs Updated LFR-EM boards constraints => PDC file => SDC file for the place and route Updated SOLO_LFR_LFR-EM designs => added DATA_SHAPING_SATURATION in LPP_FILTER => changed boards number : LPP_LFR_BOARD_LFR_EM & X"015B"	Wed, 07 Dec 2016 14:03:57	Alexis Jeandet	default SOLO_LFR_01-5B (L...	0
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