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1 TECHNOLOGY=Spartan6
2 ISETECH="Spartan6"
3 PACKAGE=ftg256
4 PART=XC6SLX25
5 SPEED=-3
6 SYNFREQ=25
7
8 MANUFACTURER=Xilinx
9 MGCPART=XC6SLX25$(PACKAGE)
10 MGCTECHNOLOGY=SPARTAN-6
11 MGCPACKAGE=$(PACKAGE)
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1 # Clocks
2 NET "CLK50" PERIOD = 20 ns | LOC = "K3";
3 #NET "CLK32" PERIOD = 31.25 ns | LOC = "J4";
4
5 # LEDs
6 NET "LEDS<0>" LOC="P11" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
7 NET "LEDS<1>" LOC="N9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
8 NET "LEDS<2>" LOC="M9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
9 NET "LEDS<3>" LOC="P9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
10 NET "LEDS<4>" LOC="T8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
11 NET "LEDS<5>" LOC="N8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
12 NET "LEDS<6>" LOC="P8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
13 NET "LEDS<7>" LOC="P7" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
14
15 # DIP Switches
16 NET "SW<1>" LOC="L1" | IOSTANDARD=LVTTL | PULLUP;
17 NET "SW<2>" LOC="L3" | IOSTANDARD=LVTTL | PULLUP;
18 NET "SW<3>" LOC="L4" | IOSTANDARD=LVTTL | PULLUP;
19 NET "SW<4>" LOC="L5" | IOSTANDARD=LVTTL | PULLUP;
20
21 NET "uart_rxd" LOC="M7" | IOSTANDARD=LVTTL;
22 NET "uart_txd" LOC="N6" | IOSTANDARD=LVTTL;
23
24 # SDRAM
25 NET "dram_udqm" LOC="F15" | IOSTANDARD=LVTTL;
26 NET "dram_clk" LOC="G16" | IOSTANDARD=LVTTL;
27 NET "dram_cke" LOC="H16" | IOSTANDARD=LVTTL;
28 NET "dram_ba_1" LOC="T14" | IOSTANDARD=LVTTL;
29 NET "dram_ba_0" LOC="R14" | IOSTANDARD=LVTTL;
30 NET "dram_cs_n" LOC="R1" | IOSTANDARD=LVTTL;
31 NET "dram_ras_n" LOC="R2" | IOSTANDARD=LVTTL;
32 NET "dram_cas_n" LOC="T4" | IOSTANDARD=LVTTL;
33 NET "dram_we_n" LOC="R5" | IOSTANDARD=LVTTL;
34 NET "dram_ldqm" LOC="T5" | IOSTANDARD=LVTTL;
35 NET "dram_addr<0>" LOC="T15" | IOSTANDARD=LVTTL;
36 NET "dram_addr<1>" LOC="R16" | IOSTANDARD=LVTTL;
37 NET "dram_addr<2>" LOC="P15" | IOSTANDARD=LVTTL;
38 NET "dram_addr<3>" LOC="P16" | IOSTANDARD=LVTTL;
39 NET "dram_addr<4>" LOC="N16" | IOSTANDARD=LVTTL;
40 NET "dram_addr<5>" LOC="M15" | IOSTANDARD=LVTTL;
41 NET "dram_addr<6>" LOC="M16" | IOSTANDARD=LVTTL;
42 NET "dram_addr<7>" LOC="L16" | IOSTANDARD=LVTTL;
43 NET "dram_addr<8>" LOC="K15" | IOSTANDARD=LVTTL;
44 NET "dram_addr<9>" LOC="K16" | IOSTANDARD=LVTTL;
45 NET "dram_addr<10>" LOC="R15" | IOSTANDARD=LVTTL;
46 NET "dram_addr<11>" LOC="J16" | IOSTANDARD=LVTTL;
47 NET "dram_addr<12>" LOC="H15" | IOSTANDARD=LVTTL;
48 NET "dram_dq<0>" LOC="T13" | IOSTANDARD=LVTTL;
49 NET "dram_dq<1>" LOC="T12" | IOSTANDARD=LVTTL;
50 NET "dram_dq<2>" LOC="R12" | IOSTANDARD=LVTTL;
51 NET "dram_dq<3>" LOC="T9" | IOSTANDARD=LVTTL;
52 NET "dram_dq<4>" LOC="R9" | IOSTANDARD=LVTTL;
53 NET "dram_dq<5>" LOC="T7" | IOSTANDARD=LVTTL;
54 NET "dram_dq<6>" LOC="R7" | IOSTANDARD=LVTTL;
55 NET "dram_dq<7>" LOC="T6" | IOSTANDARD=LVTTL;
56 NET "dram_dq<8>" LOC="F16" | IOSTANDARD=LVTTL;
57 NET "dram_dq<9>" LOC="E15" | IOSTANDARD=LVTTL;
58 NET "dram_dq<10>" LOC="E16" | IOSTANDARD=LVTTL;
59 NET "dram_dq<11>" LOC="D16" | IOSTANDARD=LVTTL;
60 NET "dram_dq<12>" LOC="B16" | IOSTANDARD=LVTTL;
61 NET "dram_dq<13>" LOC="B15" | IOSTANDARD=LVTTL;
62 NET "dram_dq<14>" LOC="C16" | IOSTANDARD=LVTTL;
63 NET "dram_dq<15>" LOC="C15" | IOSTANDARD=LVTTL;
64
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1
2 -g DebugBitstream:No
3 -g Binary:no
4 -b
5 -g CRC:Enable
6 -g ConfigRate:6
7 -g ProgPin:PullUp
8 -g DonePin:PullUp
9 -g TckPin:PullUp
10 -g TdiPin:PullUp
11 -g TdoPin:PullUp
12 -g TmsPin:PullUp
13 -g UnusedPin:PullDown
14 -g UserID:0xFFFFFFFF
15 -g StartUpClk:CCLK
16 -g DONE_cycle:4
17 -g GTS_cycle:5
18 -g GWE_cycle:6
19 -g LCK_cycle:NoWait
20 -g Security:None
21 -g Persist:No
22 -g ReadBack
23 -g DonePipe:No
24 -g DriveDone:Yes
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2016, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use ieee.numeric_std.all;
25
26 library grlib;
27 use grlib.amba.all;
28 use grlib.stdlib.all;
29 use grlib.devices.all;
30 library lpp;
31 use lpp.apb_devices_list.all;
32 use lpp.lpp_amba.all;
33 use lpp.general_purpose.TimeGenAdvancedTrigger;
34
35
36 entity APB_ADVANCED_TRIGGER_v is
37 generic (
38 pindex : integer;
39 paddr : integer;
40 count : integer range 1 to 16 := 1
41 );
42 port (
43 rstn : in std_ulogic;
44 clk : in std_ulogic;
45 apbi : in apb_slv_in_type;
46 apbo : out apb_slv_out_type;
47
48 SPW_Tickout : IN STD_LOGIC;
49 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
50 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
51
52 Trigger : OUT STD_LOGIC_VECTOR(count-1 DOWNTO 0)
53 );
54 end;
55
56
57 architecture beh of APB_ADVANCED_TRIGGER_v is
58
59 constant REVISION : integer := 1;
60
61 constant pconfig : apb_config_type := (
62 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADVANCED_TRIGGER_v, 0, REVISION, 0),
63 1 => apb_iobar(paddr, 16#fff#));
64
65
66
67 type adv_trig_type is record
68 TrigPeriod : STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15
69 TrigShift : STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps
70 Restart : STD_LOGIC;
71 StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch
72 BypassTickout : STD_LOGIC; -- if set then Trigger output is driven by SPW tickout
73 end record;
74
75 type adv_trig_regs is record
76 CFG : STD_LOGIC_VECTOR(31 DOWNTO 0);
77 Restart : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 end record;
80
81 type adv_trig_regs_array is array(count-1 downto 0) of adv_trig_regs;
82 type adv_trig_type_array is array(count-1 downto 0) of adv_trig_type;
83
84 signal r : adv_trig_regs_array;
85 signal adv_trig : adv_trig_type_array;
86 signal Rdata : std_logic_vector(31 downto 0);
87
88
89 begin
90
91
92 adv_trig_loop: FOR I IN 0 TO count-1 GENERATE
93 adv_trig_i: TimeGenAdvancedTrigger
94 PORT MAP(
95 clk => clk,
96 rstn => rstn,
97
98 SPW_Tickout => SPW_Tickout,
99
100 CoarseTime => CoarseTime,
101 FineTime => FineTime,
102
103 TrigPeriod => adv_trig(i).TrigPeriod,
104 TrigShift => adv_trig(i).TrigShift,
105 Restart => adv_trig(i).Restart,
106 StartDate => adv_trig(i).StartDate,
107
108 BypassTickout => adv_trig(i).BypassTickout,
109 Trigger => Trigger(i)
110
111 );
112
113 adv_trig(i).BypassTickout <= r(i).CFG(0);
114 adv_trig(i).TrigPeriod <= r(i).CFG(7 downto 4);
115 adv_trig(i).TrigShift <= r(i).CFG(31 downto 16);
116 adv_trig(i).Restart <= r(i).Restart(0);
117 adv_trig(i).StartDate <= r(i).StartDate;
118 END GENERATE;
119
120 process(rstn,clk)
121 Variable I : integer :=0;
122 begin
123 if rstn = '0' then
124 rst_loop: FOR I IN 0 TO count-1 LOOP
125 r(i).CFG(31 DOWNTO 1) <= (others=>'0');
126 r(i).CFG(0) <= '0';
127 r(i).Restart <= (others=>'0');
128 r(i).StartDate <= (others=>'0');
129 END LOOP;
130 elsif clk'event and clk = '1' then
131 I := to_integer(UNSIGNED(apbi.paddr(8-1 downto 4)));
132 --APB Write OP
133 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
134 case apbi.paddr(3 downto 2) is
135 when "00" =>
136 r(I).CFG <= apbi.pwdata;
137 when "01" =>
138 r(I).Restart <= apbi.pwdata;
139 when "10" =>
140 r(I).StartDate <= apbi.pwdata;
141 when others =>
142 null;
143 end case;
144 end if;
145
146 --APB READ OP
147 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
148 case apbi.paddr(3 downto 2) is
149 when "00" =>
150 Rdata <= r(I).CFG;
151 when "01" =>
152 Rdata <= r(I).Restart;
153 when "10" =>
154 Rdata <= r(I).StartDate;
155 when others =>
156 Rdata <= std_logic_vector(to_unsigned(count,32));
157 end case;
158 end if;
159
160 end if;
161
162 end process;
163 apbo.pconfig <= pconfig;
164 apbo.prdata <= Rdata when apbi.penable = '1';
165 apbo.pirq <= (OTHERS => '0');
166 apbo.pindex <= pindex;
167
168 end beh;
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=testbench
5 BOARD=MiniSpartan6p
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=./default.ucf
9 UCF_PLANAHEAD=$(UCF)
10 QSF=
11 EFFORT=high
12 XSTOPT=-uc testbench.xcf
13 SYNPOPT="set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
14 VHDLSYNFILES= onboardTest.vhd
15 VHDLSIMFILES= tb.vhd
16 SIMTOP=testbench
17 CLEAN=soft-clean
18
19 TECHLIBS = unisim
20
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi
23
24 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \
26 grlfpc \
27 ./dsp/lpp_fft_rtax \
28 ./amba_lcd_16x2_ctrlr \
29 ./general_purpose/lpp_AMR \
30 ./general_purpose/lpp_balise \
31 ./general_purpose/lpp_delay \
32 ./lpp_bootloader \
33 ./lpp_sim/CY7C1061DV33 \
34 ./lpp_uart \
35 ./lpp_usb \
36 ./dsp/lpp_fft \
37 ./lpp_leon3_soc \
38 ./lpp_debug_lfr
39
40 FILESKIP = i2cmst.vhd \
41 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
43 Top_MatrixSpec.vhd \
44 APB_FFT.vhd \
45 lpp_lfr_ms_FFT.vhd \
46 lpp_lfr_apbreg.vhd \
47 CoreFFT.vhd \
48 lpp_lfr_ms.vhd \
49 lpp_lfr_sim_pkg.vhd \
50 mtie_maps.vhd \
51 ftsrctrlc.vhd \
52 ftsdctrl.vhd \
53 ftsrctrl8.vhd \
54 ftmctrl.vhd \
55 ftsdctrl64.vhd \
56 ftahbram.vhd \
57 ftahbram2.vhd \
58 sramft.vhd \
59 nandfctrlx.vhd
60
61 include $(GRLIB)/bin/Makefile
62 include $(GRLIB)/software/leon3/Makefile
63
64 ################## project specific targets ##########################
65
66
67 test:ghdl-run
68
69 flash:
70 xc3sprog -c ftdi -p0 testbench.bit
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1 # Clocks
2 NET "CLK50" PERIOD = 20 ns | LOC = "K3";
3 # LEDs
4 NET "LEDS<0>" LOC="P11" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
5 NET "LEDS<1>" LOC="N9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
6 NET "LEDS<2>" LOC="M9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
7 NET "LEDS<3>" LOC="P9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
8 NET "LEDS<4>" LOC="T8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
9 NET "LEDS<5>" LOC="N8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
10 NET "LEDS<6>" LOC="P8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
11 NET "LEDS<7>" LOC="P7" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
12
13 # DIP Switches
14 NET "SW<1>" LOC="L1" | IOSTANDARD=LVTTL | PULLUP;
15 NET "SW<2>" LOC="L3" | IOSTANDARD=LVTTL | PULLUP;
16 NET "SW<3>" LOC="L4" | IOSTANDARD=LVTTL | PULLUP;
17 NET "SW<4>" LOC="L5" | IOSTANDARD=LVTTL | PULLUP;
18
19 NET "uart_rxd" LOC="M7" | IOSTANDARD=LVTTL;
20 NET "uart_txd" LOC="N6" | IOSTANDARD=LVTTL;
21
22
23 NET "Trigger<0>" LOC="E7" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
24 NET "Trigger<1>" LOC="C8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
25 NET "Trigger<2>" LOC="D8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
26 NET "Trigger<3>" LOC="E8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
27
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1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
5 USE IEEE.std_logic_signed.ALL;
6
7 LIBRARY techmap;
8 USE techmap.gencomp.ALL;
9 use techmap.allclkgen.all;
10
11 library gaisler;
12 use gaisler.uart.all;
13 use gaisler.misc.all;
14
15 library grlib;
16 use grlib.stdlib.all;
17 use grlib.amba.all;
18 use grlib.devices.all;
19
20 LIBRARY std;
21 USE std.textio.ALL;
22
23 LIBRARY lpp;
24 USE lpp.general_purpose.ALL;
25 USE lpp.lpp_amba.all;
26 USE lpp.lpp_lfr_management.ALL;
27
28 ENTITY testbench IS
29 port (
30 CLK50 : in std_logic;
31 LEDS : inout std_logic_vector(7 downto 0);
32 SW : in std_logic_vector(4 downto 1);
33 Trigger : out STD_LOGIC_VECTOR(3 DOWNTO 0);
34 uart_txd : out std_logic; -- DSU tx data
35 uart_rxd : in std_logic -- DSU rx data
36 );
37 END;
38
39 ARCHITECTURE behav OF testbench IS
40
41 SIGNAL TSTAMP : INTEGER := 0;
42 SIGNAL clk_50 : STD_LOGIC := '0';
43 SIGNAL clk : STD_LOGIC := '0';
44 SIGNAL rstn : STD_LOGIC;
45 SIGNAL rst : STD_LOGIC;
46 SIGNAL resetn : STD_LOGIC;
47 SIGNAL rstraw : STD_LOGIC;
48
49 --AMBA bus standard interface signals--
50 signal apbi : apb_slv_in_type;
51 signal apbo : apb_slv_out_vector := (others => apb_none);
52 signal ahbsi : ahb_slv_in_type;
53 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
54 signal ahbmi : ahb_mst_in_type;
55 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
56
57
58 signal dui : uart_in_type;
59 signal duo : uart_out_type;
60
61 SIGNAL SPW_Tickout : std_logic:='0';
62 SIGNAL CoarseTime : STD_LOGIC_VECTOR(31 DOWNTO 0):=(others=>'0');
63 SIGNAL FineTime : STD_LOGIC_VECTOR(15 DOWNTO 0):=(others=>'0');
64 SIGNAL SubFineTime : integer range 0 to 49999999:=0;
65
66 BEGIN
67
68
69 clk_25:PROCESS(clk_50)
70 BEGIN
71 IF clk_50'EVENT AND clk_50 = '1' THEN
72 clk <= not clk;
73 END IF;
74 END PROCESS;
75
76 resetn <= SW(1);
77 LEDS <= CoarseTime(7 downto 0);
78
79 uart_txd <= duo.txd;
80 dui.rxd <= uart_rxd;
81
82 clk_pad : clkpad generic map (tech => spartan6) port map (CLK50, clk_50);
83
84 resetn_pad : inpad generic map (tech => spartan6) port map (resetn, rst);
85 rst0 : rstgen -- reset generator (reset is active LOW)
86 port map (rst, clk, '1', rstn, rstraw);
87 ----------------------------------------------------------------------
88 --- AHB CONTROLLER --------------------------------------------------
89 ----------------------------------------------------------------------
90
91 ahb0 : ahbctrl -- AHB arbiter/multiplexer
92 generic map (defmast => 0, split => 1,
93 rrobin => 1, ioaddr => 16#FFF#,
94 nahbm => 1, nahbs => 1)
95
96 port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
97
98
99 dcom0: ahbuart -- Debug UART
100 generic map (hindex => 0, pindex => 0, paddr => 0)
101 port map (rstn, clk, dui, duo, apbi, apbo(0), ahbmi, ahbmo(0));
102
103 ----------------------------------------------------------------------
104 --- APB Bridge ------------------------------------------------------
105 ----------------------------------------------------------------------
106
107 apb0 : apbctrl -- AHB/APB bridge
108 generic map (hindex => 0, haddr => 16#800#)
109 port map (rstn, clk, ahbsi, ahbso(0), apbi, apbo );
110
111
112 spw_time:PROCESS(clk,rstn)
113 BEGIN
114 IF rstn = '0' THEN
115 SPW_Tickout <= '0';
116 SubFineTime <= 0;
117 ELSIF clk'EVENT AND clk = '1' THEN
118 if SubFineTime = 24999999 then
119 SubFineTime <= 0;
120 SPW_Tickout <= '1';
121 else
122 SPW_Tickout <= '0';
123 SubFineTime <= SubFineTime + 1;
124 end if;
125 END IF;
126 END PROCESS;
127
128
129 ----------------------------------------------------------------------
130 --- APB_ADVANCED_TRIGGER_v -> Device Under Test ---------------------
131 ----------------------------------------------------------------------
132
133 DUT: APB_ADVANCED_TRIGGER_v
134 generic map(
135 pindex => 1,
136 paddr => 1,
137 count => 4
138 )
139 port map(
140 rstn => rstn,
141 clk => clk,
142 apbi => apbi,
143 apbo => apbo(1),
144
145 SPW_Tickout => SPW_Tickout,
146 CoarseTime => CoarseTime,
147 FineTime => FineTime,
148
149 Trigger => Trigger
150 );
151
152 -------------------------------------------------------------------------------
153 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
154 -------------------------------------------------------------------------------
155 apb_lfr_management_1 : apb_lfr_management
156 GENERIC MAP (
157 tech => spartan6,
158 pindex => 2,
159 paddr => 2,
160 pmask => 16#fff#,
161 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
162 PORT MAP (
163 clk25MHz => clk,
164 resetn_25MHz => rstn,
165 grspw_tick => SPW_Tickout,
166 apbi => apbi,
167 apbo => apbo(2),
168 HK_sample => (others=>'0'),
169 HK_val => '0',
170 HK_sel => open,
171 DAC_SDO => OPEN,
172 DAC_SCK => OPEN,
173 DAC_SYNC => OPEN,
174 DAC_CAL_EN => OPEN,
175 coarse_time => CoarseTime,
176 fine_time => FineTime,
177 LFR_soft_rstn => open
178 );
179
180
181 END;
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1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
5 USE IEEE.std_logic_signed.ALL;
6 USE IEEE.MATH_real.ALL;
7
8 LIBRARY techmap;
9 USE techmap.gencomp.ALL;
10
11 library gaisler;
12 use gaisler.libdcom.all;
13 use gaisler.sim.all;
14 use gaisler.uart.all;
15
16 library grlib;
17 use grlib.stdlib.all;
18 use grlib.amba.all;
19 use grlib.devices.all;
20
21 LIBRARY std;
22 USE std.textio.ALL;
23
24 LIBRARY lpp;
25 USE lpp.general_purpose.ALL;
26 USE lpp.lpp_amba.all;
27
28 ENTITY testbench IS
29
30 END;
31
32 ARCHITECTURE behav OF testbench IS
33
34 SIGNAL TSTAMP : INTEGER := 0;
35 SIGNAL clk : STD_LOGIC := '0';
36 SIGNAL rstn : STD_LOGIC;
37
38 --AMBA bus standard interface signals--
39 signal apbi : apb_slv_in_type;
40 signal apbo : apb_slv_out_vector := (others => apb_none);
41 signal ahbsi : ahb_slv_in_type;
42 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
43 signal ahbmi : ahb_mst_in_type;
44 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
45
46
47 signal dui : uart_in_type;
48 signal duo : uart_out_type;
49 signal dsutx : STD_LOGIC;
50 signal dsurx : STD_LOGIC;
51
52 SIGNAL end_of_simu : STD_LOGIC := '0';
53
54 constant lresp : boolean := false;
55
56 SIGNAL SPW_Tickout : std_logic:='0';
57 SIGNAL CoarseTime : STD_LOGIC_VECTOR(31 DOWNTO 0):=(others=>'0');
58 SIGNAL FineTime : STD_LOGIC_VECTOR(15 DOWNTO 0):=(others=>'0');
59 SIGNAL Trigger : STD_LOGIC_VECTOR(3 DOWNTO 0);
60
61 BEGIN
62
63 -----------------------------------------------------------------------------
64 -- CLOCK and RESET
65 -----------------------------------------------------------------------------
66 PROCESS
67 BEGIN -- PROCESS
68 WAIT UNTIL clk = '1';
69 rstn <= '0';
70 WAIT UNTIL clk = '1';
71 WAIT UNTIL clk = '1';
72 WAIT UNTIL clk = '1';
73 rstn <= '1';
74 WAIT UNTIL end_of_simu = '1';
75 WAIT UNTIL clk = '1';
76 assert false report "end of test" severity note;
77 -- Wait forever; this will finish the simulation.
78 wait;
79 END PROCESS;
80 -----------------------------------------------------------------------------
81
82 clk_25M_gen:PROCESS
83 BEGIN
84 IF end_of_simu /= '1' THEN
85 clk <= NOT clk;
86 TSTAMP <= TSTAMP+20;
87 WAIT FOR 20 ns;
88 ELSE
89 assert false report "end of test" severity note;
90 WAIT;
91 END IF;
92 END PROCESS;
93
94 -----------------------------------------------------------------------------
95 -- CoarseTime and FineTime
96 -----------------------------------------------------------------------------
97
98 SpwFineTime:PROCESS
99 BEGIN
100 IF end_of_simu /= '1' THEN
101 IF SPW_Tickout = '1' then
102 FineTime <= (others=>'0');
103 ELSE
104 FineTime <= std_logic_vector(UNSIGNED(FineTime) + 1);
105 END IF;
106 WAIT FOR 15 us;
107 ELSE
108 assert false report "end of test" severity note;
109 WAIT;
110 END IF;
111 END PROCESS;
112
113 SpwCoarseTime:PROCESS
114 BEGIN
115 IF end_of_simu /= '1' THEN
116 wait until SPW_Tickout = '1';
117 CoarseTime <= std_logic_vector(UNSIGNED(CoarseTime) + 1);
118 ELSE
119 assert false report "end of test" severity note;
120 WAIT;
121 END IF;
122 END PROCESS;
123
124 SPWTickout:PROCESS
125 BEGIN
126 IF end_of_simu /= '1' THEN
127 wait for (1000 ms - 20 ns);
128 SPW_Tickout <= '1';
129 wait for 20 ns;
130 SPW_Tickout <= '0';
131 ELSE
132 assert false report "end of test" severity note;
133 WAIT;
134 END IF;
135 END PROCESS;
136
137
138
139 ----------------------------------------------------------------------
140 --- AHB CONTROLLER --------------------------------------------------
141 ----------------------------------------------------------------------
142
143 ahb0 : ahbctrl -- AHB arbiter/multiplexer
144 generic map (defmast => 0, split => 1,
145 rrobin => 1, ioaddr => 16#FFF#,
146 nahbm => 1, nahbs => 1)
147
148 port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
149
150
151 dcom0: ahbuart -- Debug UART
152 generic map (hindex => 0, pindex => 0, paddr => 0)
153 port map (rstn, clk, dui, duo, apbi, apbo(0), ahbmi, ahbmo(0));
154 dsutx <= duo.txd;
155 dui.rxd <= dsurx;
156
157 ----------------------------------------------------------------------
158 --- APB Bridge ------------------------------------------------------
159 ----------------------------------------------------------------------
160
161 apb0 : apbctrl -- AHB/APB bridge
162 generic map (hindex => 0, haddr => 16#800#)
163 port map (rstn, clk, ahbsi, ahbso(0), apbi, apbo );
164
165
166 ----------------------------------------------------------------------
167 --- APB_ADVANCED_TRIGGER_v -> Device Under Test ---------------------
168 ----------------------------------------------------------------------
169
170 DUT: APB_ADVANCED_TRIGGER_v
171 generic map(
172 pindex => 1,
173 paddr => 1,
174 count => 4
175 )
176 port map(
177 rstn => rstn,
178 clk => clk,
179 apbi => apbi,
180 apbo => apbo(1),
181
182 SPW_Tickout => SPW_Tickout,
183 CoarseTime => CoarseTime,
184 FineTime => FineTime,
185
186 Trigger => Trigger
187 );
188
189
190
191 dsucom : process
192 variable w32 : std_logic_vector(31 downto 0);
193 constant txp : time := 160 * 1 ns;
194 procedure writeReg(signal dsutx : out std_logic; address : integer; value : integer) is
195 begin
196 txc(dsutx, 16#c0#, txp); --control byte
197 txa(dsutx, (address / (256*256*256)) , (address / (256*256)), (address / (256)), address, txp); --adress
198 txa(dsutx, (value / (256*256*256)) , (value / (256*256)), (value / (256)), value, txp); --write data
199 end;
200
201 procedure readReg(signal dsurx : in std_logic; signal dsutx : out std_logic; address : integer; value: out std_logic_vector) is
202
203 begin
204 txc(dsutx, 16#a0#, txp); --control byte
205 txa(dsutx, (address / (256*256*256)) , (address / (256*256)), (address / (256)), address, txp); --adress
206 rxi(dsurx, value, txp, lresp); --write data
207 end;
208
209 procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
210 variable c8 : std_logic_vector(7 downto 0);
211 begin
212 dsutx <= '1';
213 wait for 5000 ns;
214 txc(dsutx, 16#55#, txp);
215
216 writeReg(dsutx,16#8000100#,16#00#);
217
218 end;
219
220 begin
221
222 dsucfg(dsutx, dsurx);
223
224 wait for 1000 ms;
225 end_of_simu <= '1';
226 wait;
227 end process;
228
229 all_apbo : FOR I IN 0 TO 15 GENERATE
230 apbo_not_used : IF I /= 1 AND I /= 0 GENERATE
231 apbo(I) <= apb_none;
232 END GENERATE apbo_not_used;
233 END GENERATE all_apbo;
234
235 END;
Show file before | Show file after | Hide comments
@@ -35,15 +35,14 use lpp.general_purpose.TimeGenAdvancedT
35 entity APB_ADVANCED_TRIGGER is
35 entity APB_ADVANCED_TRIGGER is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0
39 pmask : integer := 16#fff#;
39 );
40 pirq : integer := 0);
41 port (
40 port (
42 rstn : in std_ulogic;
41 rstn : in std_ulogic;
43 clk : in std_ulogic;
42 clk : in std_ulogic;
44 apbi : in apb_slv_in_type;
43 apbi : in apb_slv_in_type;
45 apbo : out apb_slv_out_type;
44 apbo : out apb_slv_out_type;
46
45
47 SPW_Tickout : IN STD_LOGIC;
46 SPW_Tickout : IN STD_LOGIC;
48 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
48 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -59,7 +58,7 constant REVISION : integer := 1;
59
58
60 constant pconfig : apb_config_type := (
59 constant pconfig : apb_config_type := (
61 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADVANCED_TRIGGER, 0, REVISION, 0),
60 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADVANCED_TRIGGER, 0, REVISION, 0),
62 1 => apb_iobar(paddr, pmask));
61 1 => apb_iobar(paddr, 16#fff#));
63
62
64
63
65
64
@@ -116,19 +115,20 adv_trig0: TimeGenAdvancedTrigger
116 process(rstn,clk)
115 process(rstn,clk)
117 begin
116 begin
118 if rstn = '0' then
117 if rstn = '0' then
119 r.CFG <= (others=>'0');
118 r.CFG(31 DOWNTO 1) <= (others=>'0');
119 r.CFG(0) <= '0';
120 r.Restart <= (others=>'0');
120 r.Restart <= (others=>'0');
121 r.StartDate <= (others=>'0');
121 r.StartDate <= (others=>'0');
122 elsif clk'event and clk = '1' then
122 elsif clk'event and clk = '1' then
123
123
124 --APB Write OP
124 --APB Write OP
125 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
125 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
126 case apbi.paddr(3 downto 2) is
126 case apbi.paddr(8-1 downto 2) is
127 when "00" =>
127 when "000000" =>
128 r.CFG <= apbi.pwdata;
128 r.CFG <= apbi.pwdata;
129 when "01" =>
129 when "000001" =>
130 r.Restart <= apbi.pwdata;
130 r.Restart <= apbi.pwdata;
131 when "10" =>
131 when "000010" =>
132 r.StartDate <= apbi.pwdata;
132 r.StartDate <= apbi.pwdata;
133 when others =>
133 when others =>
134 null;
134 null;
@@ -137,21 +137,23 begin
137
137
138 --APB READ OP
138 --APB READ OP
139 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
139 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
140 case apbi.paddr(3 downto 2) is
140 case apbi.paddr(8-1 downto 2) is
141 when "00" =>
141 when "000000" =>
142 Rdata <= r.CFG;
142 Rdata <= r.CFG;
143 when "01" =>
143 when "000001" =>
144 Rdata <= r.Restart;
144 Rdata <= r.Restart;
145 when "10" =>
145 when "000010" =>
146 Rdata <= r.StartDate;
146 Rdata <= r.StartDate;
147 when others =>
147 when others =>
148 Rdata <= r.Restart;
148 Rdata <= r.Restart;
149 end case;
149 end case;
150 end if;
150 end if;
151
151
152 end if;
152 end if;
153 apbo.pconfig <= pconfig;
154 end process;
153 end process;
155
154
155 apbo.pconfig <= pconfig;
156 apbo.prdata <= Rdata when apbi.penable = '1';
156 apbo.prdata <= Rdata when apbi.penable = '1';
157 apbo.pirq <= (OTHERS => '0');
158 apbo.pindex <= pindex;
157 end beh;
159 end beh;
Show file before | Show file after | Hide comments
@@ -44,6 +44,7 PACKAGE apb_devices_list IS
44 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
44 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
45 constant APB_ADC_READER : amba_device_type := 16#F1#;
45 constant APB_ADC_READER : amba_device_type := 16#F1#;
46 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
46 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
47 CONSTANT LPP_APB_ADVANCED_TRIGGER : amba_device_type := 16#A3#;
47 CONSTANT LPP_APB_ADVANCED_TRIGGER : amba_device_type := 16#A3#;
48
48 CONSTANT LPP_APB_ADVANCED_TRIGGER_v : amba_device_type := 16#A4#;
49
49 END;
50 END;
Show file before | Show file after | Hide comments
@@ -32,9 +32,8 package lpp_amba is
32 component APB_ADVANCED_TRIGGER is
32 component APB_ADVANCED_TRIGGER is
33 generic (
33 generic (
34 pindex : integer := 0;
34 pindex : integer := 0;
35 paddr : integer := 0;
35 paddr : integer := 0
36 pmask : integer := 16#fff#;
36 );
37 pirq : integer := 0);
38 port (
37 port (
39 rstn : in std_ulogic;
38 rstn : in std_ulogic;
40 clk : in std_ulogic;
39 clk : in std_ulogic;
@@ -49,6 +48,26 component APB_ADVANCED_TRIGGER is
49 );
48 );
50 end component;
49 end component;
51
50
51 component APB_ADVANCED_TRIGGER_v is
52 generic (
53 pindex : integer;
54 paddr : integer;
55 count : integer range 1 to 8 := 1
56 );
57 port (
58 rstn : in std_ulogic;
59 clk : in std_ulogic;
60 apbi : in apb_slv_in_type;
61 apbo : out apb_slv_out_type;
62
63 SPW_Tickout : IN STD_LOGIC;
64 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
66
67 Trigger : OUT STD_LOGIC_VECTOR(count-1 DOWNTO 0)
68 );
69 end component;
70
52 component APB_SIMPLE_DIODE is
71 component APB_SIMPLE_DIODE is
53 generic (
72 generic (
54 pindex : integer := 0;
73 pindex : integer := 0;
Show file before | Show file after | Hide comments
@@ -1,3 +1,4
1 apb_devices_list.vhd
1 apb_devices_list.vhd
2 lpp_amba.vhd
2 lpp_amba.vhd
3 APB_ADVANCED_TRIGGER.vhd
3 APB_ADVANCED_TRIGGER.vhd
4 APB_ADVANCED_TRIGGER_v.vhd
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