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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Renamed the SPW_Light test directory from Validation_SPW_light to Test_SPW_Light....
pellion -
r687:88431f3070cd Simu-LFR-FM draft
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 LIBRARY std;
28 USE std.textio.ALL;
29
30 ENTITY lfr_input_gen IS
31
32 GENERIC(
33 FNAME : STRING := "input.txt"
34 );
35
36 PORT (
37 end_of_simu : OUT STD_LOGIC;
38 ---------------------------------------------------------------------------
39 rhf1401_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
40 -- ADC --------------------------------------------------------------------
41 adc_rhf1401_smp_clk : IN STD_LOGIC;
42 adc_rhf1401_oeb_bar_ch : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
43 adc_bias_fail_sel : IN STD_LOGIC;
44 -- HK ---------------------------------------------------------------------
45 hk_rhf1401_smp_clk : IN STD_LOGIC;
46 hk_rhf1401_oeb_bar_ch : IN STD_LOGIC;
47 hk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 ---------------------------------------------------------------------------
49 error_oeb : OUT STD_LOGIC;
50 error_hksel : OUT STD_LOGIC
51 );
52
53 END ENTITY lfr_input_gen;
54
55 ARCHITECTURE beh OF lfr_input_gen IS
56
57 FILE input_file : TEXT OPEN read_mode IS FNAME;
58
59 TYPE SAMPLE_VECTOR_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(13 DOWNTO 0);
60 SIGNAL sample_vector : SAMPLE_VECTOR_TYPE(1 TO 16);
61
62 SIGNAL sample_vector_adc : SAMPLE_VECTOR_TYPE(1 TO 13);
63 SIGNAL sample_vector_hk : SAMPLE_VECTOR_TYPE(14 TO 16);
64
65 SIGNAL sample_vector_reg : SAMPLE_VECTOR_TYPE(1 TO 16);
66 SIGNAL sample_vector_adc_reg : SAMPLE_VECTOR_TYPE(1 TO 13);
67 SIGNAL sample_vector_hk_reg : SAMPLE_VECTOR_TYPE(14 TO 16);
68
69
70 SIGNAL oeb_bar_ch : STD_LOGIC_VECTOR(8 DOWNTO 0);
71
72 BEGIN -- ARCHITECTURE beh
73
74 -----------------------------------------------------------------------------
75 -- Data orginization in the input file :
76 -----------------------------------------------------------------------------
77 -- Exemple of input.txt file :
78 -- Time1 B1 B2 B3 BIAS1 BIAS2 BIAS3 BIAS4 BIAS5 V1 V2 V3 GND1 GND2 HK1 HK2 HK3
79 -- Time2 B1 B2 B3 BIAS1 BIAS2 BIAS3 BIAS4 BIAS5 V1 V2 V3 GND1 GND2 HK1 HK2 HK3
80 -----------------------------------------------------------------------------
81 -- Time : integer. Duration time (in ns) to set the following data
82 -- Data : unsigned (0 to 255). A part of the message.
83 -----------------------------------------------------------------------------
84
85 -----------------------------------------------------------------------------
86 PROCESS IS
87 VARIABLE line_var : LINE;
88 VARIABLE waiting_time : INTEGER;
89 VARIABLE value : INTEGER;
90 BEGIN -- PROCESS
91
92 IF endfile(input_file) THEN
93 end_of_simu <= '1';
94 ELSE
95 end_of_simu <= '0';
96 readline(input_file, line_var);
97 read(line_var, waiting_time);
98 FOR sample_index IN 1 TO 16 LOOP
99 read(line_var, value);
100 sample_vector(sample_index) <= STD_LOGIC_VECTOR(to_unsigned(value, 14));
101 END LOOP; -- sample
102
103 WAIT FOR waiting_time * 1 ns;
104 END IF;
105
106 END PROCESS;
107
108 all_adc_sample: FOR sample_index IN 1 TO 13 GENERATE
109 sample_vector_adc(sample_index) <= sample_vector (sample_index);
110 sample_vector_reg(sample_index) <= sample_vector_adc_reg(sample_index);
111 END GENERATE all_adc_sample;
112 all_hk_sample: FOR sample_index IN 14 TO 16 GENERATE
113 sample_vector_hk (sample_index) <= sample_vector (sample_index);
114 sample_vector_reg(sample_index) <= sample_vector_hk_reg(sample_index);
115 END GENERATE all_hk_sample;
116
117
118 -----------------------------------------------------------------------------
119 PROCESS IS
120 BEGIN -- PROCESS
121 WAIT UNTIL adc_rhf1401_smp_clk = '1';
122 sample_vector_adc_reg <= sample_vector_adc;
123 END PROCESS;
124
125 PROCESS IS
126 BEGIN -- PROCESS
127 WAIT UNTIL hk_rhf1401_smp_clk = '1';
128 sample_vector_hk_reg <= sample_vector_hk;
129 END PROCESS;
130 -----------------------------------------------------------------------------
131
132 oeb_bar_ch <= hk_rhf1401_oeb_bar_ch & adc_rhf1401_oeb_bar_ch;
133
134 PROCESS (oeb_bar_ch, sample_vector_reg, hk_sel) IS
135 BEGIN -- PROCESS
136 error_oeb <= '0';
137 error_hksel <= '0';
138 CASE oeb_bar_ch IS
139 WHEN "111111111" => NULL;
140 WHEN "111111110" => IF adc_bias_fail_sel = '1' THEN rhf1401_data <= sample_vector_reg(4); ELSE rhf1401_data <= sample_vector_reg( 9); END IF;
141 WHEN "111111101" => IF adc_bias_fail_sel = '1' THEN rhf1401_data <= sample_vector_reg(5); ELSE rhf1401_data <= sample_vector_reg(10); END IF;
142 WHEN "111111011" => IF adc_bias_fail_sel = '1' THEN rhf1401_data <= sample_vector_reg(6); ELSE rhf1401_data <= sample_vector_reg(11); END IF;
143 WHEN "111110111" => IF adc_bias_fail_sel = '1' THEN rhf1401_data <= sample_vector_reg(7); ELSE rhf1401_data <= sample_vector_reg(12); END IF;
144 WHEN "111101111" => IF adc_bias_fail_sel = '1' THEN rhf1401_data <= sample_vector_reg(8); ELSE rhf1401_data <= sample_vector_reg(13); END IF;
145 WHEN "111011111" => rhf1401_data <= sample_vector_reg(1);
146 WHEN "110111111" => rhf1401_data <= sample_vector_reg(2);
147 WHEN "101111111" => rhf1401_data <= sample_vector_reg(3);
148 WHEN "011111111" =>
149 CASE hk_sel IS
150 WHEN "00" => rhf1401_data <= sample_vector_reg(14);
151 WHEN "01" => rhf1401_data <= sample_vector_reg(15);
152 WHEN "10" => rhf1401_data <= sample_vector_reg(16);
153 WHEN OTHERS => error_hksel <= '1';
154 END CASE;
155 WHEN OTHERS => error_oeb <= '1';
156 END CASE;
157 END PROCESS;
158 -----------------------------------------------------------------------------
159
160 END ARCHITECTURE beh;
161
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=testbench
5 BOARD=LFR-FM
6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=
9 QSF=
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT=
13 VHDLSYNFILES=
14 VHDLSIMFILES= tb.vhd
15 SIMTOP=testbench
16 CLEAN=soft-clean
17
18 TECHLIBS = axcelerator
19
20
21 LIBSKIP = tmtc openchip hynix cypress ihp usbhc fmf gsi spansion eth micron
22
23 DIRSKIP = leon2 leon2ft crypto usb satcan ddr greth grusbhc \
24 leon4 leon4v0 l2cache iommu slink ascs pwm net spi can \
25 ./amba_lcd_16x2_ctrlr \
26 ./general_purpose/lpp_AMR \
27 ./general_purpose/lpp_balise \
28 ./general_purpose/lpp_delay \
29 ./lpp_bootloader \
30 ./lpp_uart \
31 ./lpp_usb \
32 ./lpp_debug_lfr \
33 ./dsp/lpp_fft
34
35 FILESKIP = i2cmst.vhd \
36 APB_MULTI_DIODE.vhd \
37 APB_MULTI_DIODE.vhd \
38 Top_MatrixSpec.vhd \
39 APB_FFT.vhd \
40 lpp_lfr_sim_pkg.vhd
41
42 include $(GRLIB)/bin/Makefile
43 include $(GRLIB)/software/leon3/Makefile
44 ################## project specific targets ##########################
45 distclean:myclean
46
47 myclean:
48 rm -f input.txt output_fx.txt *.log
49 rm -rf ./2016*
50
51 test: | ghdl ghdl-run archivate
52
53
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1 10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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110 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
111 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
112 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
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121 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
122 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
123 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
124 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
125 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
126 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
127 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
128 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
129 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
130 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
131 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
132 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
133 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
134 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
135 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
136 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
137 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
138 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
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147 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
148 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
149 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
150 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
151 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
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153 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
154 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
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160 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
161 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
162 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
163 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
164 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
165 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
166 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
167 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
168 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
169 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
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180 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
181 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
182 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
183 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
184 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
185 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
186 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
187 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
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195 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
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197 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
198 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
199 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
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201 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
202 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
203 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
204 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
205 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
206 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
207 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
208 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
209 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
210 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
211 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
212 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
213 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
214 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
215 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
216 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
217 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
218 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
219 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
220 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
221 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
222 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
223 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
224 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
225 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
226 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
227 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
228 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
229 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
230 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
231 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
232 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
233 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
234 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
235 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
236 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
237 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
238 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
239 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
240 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
241 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
242 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
243 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
244 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
245 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
246 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
247 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
248 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
249 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
250 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
251 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
252 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
253 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
254 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
255 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
256 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
257 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
258 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
259 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
260 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
261 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
262 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
263 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
264 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
265 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
266 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
267 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
268 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
269 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
270 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
271 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
272 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
273 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
274 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
275 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
276 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
277 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
278 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
279 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
280 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
281 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
282 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
283 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
284 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
285 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
286 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
287 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
288 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
289 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
290 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
291 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
292 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
293 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
294 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
295 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
296 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
297 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
298 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
299 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
300 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
301 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
302 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
303 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
304 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
305 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
306 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
307 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
308 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
309 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
310 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
311 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
312 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
313 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
314 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
315 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
316 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
317 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
318 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
319 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
320 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
321 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
322 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
323 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
324 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
325 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
326 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
327 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
328 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
329 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
330 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
331 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
332 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
333 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
334 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
335 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
336 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
337 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
338 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
339 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
340 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
341 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
342 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
343 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
344 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
345 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
346 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
347 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
348 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
349 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
350 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
351 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
352 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
353 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
354 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
355 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
356 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
357 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
358 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
359 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
360 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
361 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
362 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
363 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
364 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
365 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
366 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
367 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
368 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
369 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
370 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
371 110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
372 110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
373 110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3
374 110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
375 110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
376 110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6
377 110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
378 110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8
379 110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9
380 110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10
381 110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11
382 110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12
383 110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13
384 110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
385 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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@@ -0,0 +1,141
1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
5 USE IEEE.std_logic_signed.ALL;
6 USE IEEE.MATH_real.ALL;
7
8 LIBRARY techmap;
9 USE techmap.gencomp.ALL;
10
11 LIBRARY std;
12 USE std.textio.ALL;
13
14 LIBRARY opencores;
15 USE opencores.spwpkg.ALL;
16 USE opencores.spwambapkg.ALL;
17
18 LIBRARY lpp;
19 USE lpp.lpp_sim_pkg.ALL;
20 USE lpp.lpp_ad_conv.ALL;
21
22 ENTITY testbench IS
23 END;
24
25 ARCHITECTURE behav OF testbench IS
26
27 SIGNAL TSTAMP : INTEGER := 0;
28
29 SIGNAL clk_25 : STD_LOGIC := '0';
30 SIGNAL rstn_25 : STD_LOGIC;
31 SIGNAL clk_24 : STD_LOGIC := '0';
32 SIGNAL rstn_24 : STD_LOGIC;
33
34 SIGNAL end_of_simu : STD_LOGIC := '0';
35
36 SIGNAL ADC_smpclk_s : STD_LOGIC;
37
38 SIGNAL ADC_data : Samples14;
39 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
40 SIGNAL sample : Samples14v(8 DOWNTO 0);
41 SIGNAL sample_val : STD_LOGIC;
42
43 BEGIN
44
45 -----------------------------------------------------------------------------
46 -- CLOCK and RESET
47 -----------------------------------------------------------------------------
48 PROCESS
49 BEGIN -- PROCESS
50 WAIT UNTIL clk_25 = '1';
51 rstn_25 <= '0';
52 WAIT UNTIL clk_25 = '1';
53 WAIT UNTIL clk_25 = '1';
54 WAIT UNTIL clk_25 = '1';
55 rstn_25 <= '1';
56 WAIT UNTIL end_of_simu = '1';
57 WAIT FOR 10 ps;
58 ASSERT false REPORT "end of test" SEVERITY note;
59 -- Wait forever; this will finish the simulation.
60 WAIT;
61 END PROCESS;
62 -----------------------------------------------------------------------------
63 clk_25_gen : PROCESS
64 BEGIN
65 IF end_of_simu /= '1' THEN
66 clk_25 <= NOT clk_25;
67 TSTAMP <= TSTAMP+20;
68 WAIT FOR 20 ns;
69 ELSE
70 WAIT FOR 20 ps;
71 ASSERT false REPORT "end of test" SEVERITY note;
72 WAIT;
73 END IF;
74 END PROCESS;
75
76 -----------------------------------------------------------------------------
77 -- CLOCK and RESET
78 -----------------------------------------------------------------------------
79 PROCESS
80 BEGIN -- PROCESS
81 WAIT UNTIL clk_24 = '1';
82 rstn_24 <= '0';
83 WAIT UNTIL clk_24 = '1';
84 WAIT UNTIL clk_24 = '1';
85 WAIT UNTIL clk_24 = '1';
86 rstn_24 <= '1';
87 WAIT UNTIL end_of_simu = '1';
88 WAIT FOR 10 ps;
89 ASSERT false REPORT "end of test" SEVERITY note;
90 -- Wait forever; this will finish the simulation.
91 WAIT;
92 END PROCESS;
93 -----------------------------------------------------------------------------
94 clk_24_gen : PROCESS
95 BEGIN
96 IF end_of_simu /= '1' THEN
97 clk_24 <= NOT clk_24;
98 WAIT FOR 20345 ps;
99 ELSE
100 WAIT FOR 20 ps;
101 ASSERT false REPORT "end of test" SEVERITY note;
102 WAIT;
103 END IF;
104 END PROCESS;
105
106 -----------------------------------------------------------------------------
107 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
108 GENERIC MAP (
109 ChanelCount => 9,
110 ncycle_cnv_high => 12,
111 ncycle_cnv => 25,
112 FILTER_ENABLED => 16#FF#)
113 PORT MAP (
114 cnv_clk => clk_24,
115 cnv_rstn => rstn_24,
116 cnv => ADC_smpclk_s,
117 clk => clk_25,
118 rstn => rstn_25,
119 ADC_data => ADC_data,
120 ADC_nOE => ADC_OEB_bar_CH_s,
121 sample => sample,
122 sample_val => sample_val);
123
124 -----------------------------------------------------------------------------
125 lfr_input_gen_1: lfr_input_gen
126 GENERIC MAP (
127 FNAME => "adc_input.txt")
128 PORT MAP (
129 end_of_simu => end_of_simu,
130 rhf1401_data => ADC_data,
131 adc_rhf1401_smp_clk => ADC_smpclk_s,
132 adc_rhf1401_oeb_bar_ch => ADC_OEB_bar_CH_s(7 DOWNTO 0),
133 adc_bias_fail_sel => '0',
134 hk_rhf1401_smp_clk => ADC_smpclk_s,
135 hk_rhf1401_oeb_bar_ch => ADC_OEB_bar_CH_s(8),
136 hk_sel => "00",
137 error_oeb => OPEN,
138 error_hksel => OPEN);
139 -----------------------------------------------------------------------------
140
141 END;
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@@ -0,0 +1,53
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=testbench
5 BOARD=LFR-FM
6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=
9 QSF=
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT=
13 VHDLSYNFILES=
14 VHDLSIMFILES= $(VHDLIB)/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd tb.vhd
15 SIMTOP=testbench
16 CLEAN=soft-clean
17
18 TECHLIBS = axcelerator
19
20
21 LIBSKIP = tmtc openchip hynix cypress ihp usbhc fmf gsi spansion eth micron
22
23 DIRSKIP = leon2 leon2ft crypto usb satcan ddr greth grusbhc \
24 leon4 leon4v0 l2cache iommu slink ascs pwm net spi can \
25 ./amba_lcd_16x2_ctrlr \
26 ./general_purpose/lpp_AMR \
27 ./general_purpose/lpp_balise \
28 ./general_purpose/lpp_delay \
29 ./lpp_bootloader \
30 ./lpp_uart \
31 ./lpp_usb \
32 ./lpp_debug_lfr \
33 ./dsp/lpp_fft
34
35 FILESKIP = i2cmst.vhd \
36 APB_MULTI_DIODE.vhd \
37 APB_MULTI_DIODE.vhd \
38 Top_MatrixSpec.vhd \
39 APB_FFT.vhd \
40 lpp_lfr_sim_pkg.vhd
41
42 include $(GRLIB)/bin/Makefile
43 include $(GRLIB)/software/leon3/Makefile
44 ################## project specific targets ##########################
45 distclean:myclean
46
47 myclean:
48 rm -f input.txt output_fx.txt *.log
49 rm -rf ./2016*
50
51 test: | ghdl ghdl-run archivate
52
53
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@@ -0,0 +1,7
1 20 3
2 28
3 14
4 32
5 1500 2
6 18
7 200
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@@ -0,0 +1,7
1 28
2 14
3 32
4 TIME= 45020
5 18
6 200
7 TIME= 47660
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@@ -0,0 +1,213
1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
5 USE IEEE.std_logic_signed.ALL;
6 USE IEEE.MATH_real.ALL;
7
8 LIBRARY techmap;
9 USE techmap.gencomp.ALL;
10
11 LIBRARY std;
12 USE std.textio.ALL;
13
14 LIBRARY opencores;
15 USE opencores.spwpkg.ALL;
16 USE opencores.spwambapkg.ALL;
17
18 LIBRARY lpp;
19 USE lpp.lpp_sim_pkg.ALL;
20
21 ENTITY testbench IS
22 END;
23
24 ARCHITECTURE behav OF testbench IS
25
26 SIGNAL TSTAMP : INTEGER := 0;
27 SIGNAL clk : STD_LOGIC := '0';
28 SIGNAL rst : STD_LOGIC;
29
30 SIGNAL end_of_simu : STD_LOGIC := '0';
31
32 SIGNAL autostart : STD_LOGIC := '1';
33 SIGNAL linkstart : STD_LOGIC := '1';
34 SIGNAL linkdis : STD_LOGIC := '0';
35 SIGNAL ctrl_in : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
36 SIGNAL time_in : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
37 SIGNAL txwrite : STD_LOGIC := '0';
38 SIGNAL txflag : STD_LOGIC := '0';
39 SIGNAL txdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
40 SIGNAL txrdy : STD_LOGIC;
41 SIGNAL txhalff : STD_LOGIC;
42 SIGNAL tick_out : STD_LOGIC;
43 SIGNAL ctrl_out : STD_LOGIC_VECTOR(1 DOWNTO 0);
44 SIGNAL time_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
45 SIGNAL rxvalid : STD_LOGIC;
46 SIGNAL rxhalff : STD_LOGIC;
47 SIGNAL rxflag : STD_LOGIC;
48 SIGNAL rxdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
49 SIGNAL rxread : STD_LOGIC := '0';
50 SIGNAL started : STD_LOGIC;
51 SIGNAL connecting : STD_LOGIC;
52 SIGNAL running : STD_LOGIC;
53 SIGNAL errdisc : STD_LOGIC;
54 SIGNAL errpar : STD_LOGIC;
55 SIGNAL erresc : STD_LOGIC;
56 SIGNAL errcred : STD_LOGIC;
57
58 SIGNAL spw_di : std_logic;
59 SIGNAL spw_si : std_logic;
60 SIGNAL spw_do : std_logic;
61 SIGNAL spw_so : std_logic;
62
63 BEGIN
64
65 -----------------------------------------------------------------------------
66 -- CLOCK and RESET
67 -----------------------------------------------------------------------------
68 PROCESS
69 BEGIN -- PROCESS
70 WAIT UNTIL clk = '1';
71 rst <= '1';
72 WAIT UNTIL clk = '1';
73 WAIT UNTIL clk = '1';
74 WAIT UNTIL clk = '1';
75 rst <= '0';
76 WAIT UNTIL end_of_simu = '1';
77 WAIT FOR 10 ps;
78 ASSERT false REPORT "end of test" SEVERITY note;
79 -- Wait forever; this will finish the simulation.
80 WAIT;
81 END PROCESS;
82 -----------------------------------------------------------------------------
83
84 clk_50M_gen : PROCESS
85 BEGIN
86 IF end_of_simu /= '1' THEN
87 clk <= NOT clk;
88 TSTAMP <= TSTAMP+20;
89 WAIT FOR 10 ns;
90 ELSE
91 WAIT FOR 10 ps;
92 ASSERT false REPORT "end of test" SEVERITY note;
93 WAIT;
94 END IF;
95 END PROCESS;
96
97
98 SPW : spwstream
99
100 GENERIC MAP(
101 sysfreq => 50.0e6,
102 txclkfreq => 50.0e6,
103 rximpl => impl_generic,
104 rxchunk => 1,
105 tximpl => impl_generic,
106 rxfifosize_bits => 11,
107 txfifosize_bits => 11
108 )
109
110 PORT MAP(
111 -- System clock.
112 clk => clk,
113 rxclk => clk,
114 txclk => clk,
115 rst => rst,
116
117
118 autostart => autostart, -- Enables automatic link start on receipt of a NULL character.
119 linkstart => linkstart, -- Enables link start once the Ready state is reached. Without autostart or linkstart, the link remains in state Ready.
120 linkdis => linkdis, -- Do not start link (overrides linkstart and autostart) and/or disconnect a running link.
121
122 txdivcnt => X"00",
123
124
125 -------------------------------------------------------------------------
126 -- TimeCode transmission
127 tick_in => '0', -- High for one clock cycle to request transmission of a TimeCode. The request is registered inside the entity until it can be processed.
128 ctrl_in => ctrl_in, -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
129 time_in => time_in, -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
130 -------------------------------------------------------------------------
131
132 -------------------------------------------------------------------------
133 -- ### tx data ### tb -> SPW-light
134 txwrite => txwrite, -- Pulled high by the application to write an N-Char to the transmit queue.
135 -- If "txwrite" and "txrdy" are both high on the rising edge of "clk", a character is added to the transmit queue.
136 -- This signal has no effect if "txrdy" is low.
137 txflag => txflag, -- Control flag to be sent with the next N_Char. Must be valid while txwrite is high.
138 txdata => txdata, -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. Must be valid while txwrite is high.
139 txrdy => txrdy, -- High if the entity is ready to accept an N-Char for transmission.
140 txhalff => txhalff, -- High if the transmission queue is at least half full.
141 -------------------------------------------------------------------------
142
143 -------------------------------------------------------------------------
144 -- TimeCode reception
145 tick_out => tick_out, -- High for one clock cycle if a TimeCode was just received.
146 ctrl_out => ctrl_out, -- Control bits of the last received TimeCode.
147 time_out => time_out, -- Counter value of the last received TimeCode.
148 -------------------------------------------------------------------------
149
150
151 -------------------------------------------------------------------------
152 -- ### rx data ### tb <- SPW-light
153 rxvalid => rxvalid, -- High if "rxflag" and "rxdata" contain valid data. This signal is high unless the receive FIFO is empty.
154 rxhalff => rxhalff, -- High if the receive FIFO is at least half full.
155 rxflag => rxflag, -- High if the received character is EOP or EEP; low if the received character is a data byte. Valid if "rxvalid" is high.
156 rxdata => rxdata, -- Received byte, or "00000000" for EOP or "00000001" for EEP. Valid if "rxvalid" is high.
157 rxread => rxread, -- Pulled high by the application to accept a received character.
158 -- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
159 -- a character is removed from the receive FIFO and "rxvalid", "rxflag" and "rxdata" are updated.
160 -- This signal has no effect if "rxvalid" is low.
161 -------------------------------------------------------------------------
162
163 -------------------------------------------------------------------------
164 -- STATUS
165 started => started, -- High if the link state machine is currently in the Started state.
166 connecting => connecting, -- High if the link state machine is currently in the Connecting state.
167 running => running, -- High if the link state machine is currently in the Run state, indicatin that the link is fully operational.
168 -- If none of started, connecting or running is high, the link is in an initial state and the transmitter is not yet enabled.
169
170 errdisc => errdisc, -- Disconnect detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing.
171 errpar => errpar, -- Parity error detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing.
172 erresc => erresc, -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing.
173 errcred => errcred, -- Credit error detected. Triggers a reset and reconnect of the link. This indication is auto-clearing.
174 -------------------------------------------------------------------------
175
176 spw_di => spw_di, -- Data In signal from SpaceWire bus.
177 spw_si => spw_si, -- Strobe In signal from SpaceWire bus.
178 spw_do => spw_do, -- Data Out signal to SpaceWire bus.
179 spw_so => spw_so -- Strobe Out signal to SpaceWire bus.
180 );
181
182
183 spw_si <= spw_so;
184 spw_di <= spw_do;
185
186 spw_sender_1: spw_sender
187 GENERIC MAP (
188 FNAME => "spw_input.txt")
189 PORT MAP (
190 end_of_simu => OPEN,
191 start_of_simu => running,
192 clk => clk,
193
194 txwrite => txwrite,
195 txflag => txflag,
196 txdata => txdata,
197 txrdy => txrdy,
198 txhalff => txhalff);
199
200 spw_receiver_1: spw_receiver
201 GENERIC MAP (
202 FNAME => "spw_output.txt")
203 PORT MAP (
204 end_of_simu => '0',
205 timestamp => TSTAMP,
206 clk => clk,
207 rxread => rxread,
208 rxflag => rxflag,
209 rxdata => rxdata,
210 rxvalid => rxvalid,
211 rxhalff => rxhalff);
212
213 END;
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@@ -89,6 +89,9 PACKAGE lpp_sim_pkg IS
89 );
89 );
90 END COMPONENT;
90 END COMPONENT;
91
91
92 -----------------------------------------------------------------------------
93 -- SPW
94 -----------------------------------------------------------------------------
92 COMPONENT spw_sender IS
95 COMPONENT spw_sender IS
93 GENERIC (
96 GENERIC (
94 FNAME : STRING);
97 FNAME : STRING);
@@ -116,6 +119,25 PACKAGE lpp_sim_pkg IS
116 rxvalid : in STD_LOGIC;
119 rxvalid : in STD_LOGIC;
117 rxhalff : out STD_LOGIC);
120 rxhalff : out STD_LOGIC);
118 END COMPONENT spw_receiver;
121 END COMPONENT spw_receiver;
122
123 -----------------------------------------------------------------------------
124 -- LFR-I/O
125 -----------------------------------------------------------------------------
126 COMPONENT lfr_input_gen IS
127 GENERIC (
128 FNAME : STRING);
129 PORT (
130 end_of_simu : OUT STD_LOGIC;
131 rhf1401_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
132 adc_rhf1401_smp_clk : IN STD_LOGIC;
133 adc_rhf1401_oeb_bar_ch : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
134 adc_bias_fail_sel : IN STD_LOGIC;
135 hk_rhf1401_smp_clk : IN STD_LOGIC;
136 hk_rhf1401_oeb_bar_ch : IN STD_LOGIC;
137 hk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
138 error_oeb : OUT STD_LOGIC;
139 error_hksel : OUT STD_LOGIC);
140 END COMPONENT lfr_input_gen;
119
141
120 END lpp_sim_pkg;
142 END lpp_sim_pkg;
121
143
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@@ -5,3 +5,4 lpp_sim_pkg.vhd
5 lpp_lfr_sim_pkg.vhd
5 lpp_lfr_sim_pkg.vhd
6 spw_sender.vhd
6 spw_sender.vhd
7 spw_receiver.vhd
7 spw_receiver.vhd
8 lfr_input_gen.vhd
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