# HG changeset patch # User pellion # Date 2017-01-06 20:12:06 # Node ID 88431f3070cdba73baa02ff12e3460d9650812a4 # Parent ea8efb0bdfd4cd6b7f814bf9632c8b5737d39a6a Renamed the SPW_Light test directory from Validation_SPW_light to Test_SPW_Light. Added Test ADC RHF1401 diff --git a/lib/lpp/lpp_sim/lfr_input_gen.vhd b/lib/lpp/lpp_sim/lfr_input_gen.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/lfr_input_gen.vhd @@ -0,0 +1,161 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +LIBRARY std; +USE std.textio.ALL; + +ENTITY lfr_input_gen IS + + GENERIC( + FNAME : STRING := "input.txt" + ); + + PORT ( + end_of_simu : OUT STD_LOGIC; + --------------------------------------------------------------------------- + rhf1401_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); + -- ADC -------------------------------------------------------------------- + adc_rhf1401_smp_clk : IN STD_LOGIC; + adc_rhf1401_oeb_bar_ch : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + adc_bias_fail_sel : IN STD_LOGIC; + -- HK --------------------------------------------------------------------- + hk_rhf1401_smp_clk : IN STD_LOGIC; + hk_rhf1401_oeb_bar_ch : IN STD_LOGIC; + hk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + --------------------------------------------------------------------------- + error_oeb : OUT STD_LOGIC; + error_hksel : OUT STD_LOGIC + ); + +END ENTITY lfr_input_gen; + +ARCHITECTURE beh OF lfr_input_gen IS + + FILE input_file : TEXT OPEN read_mode IS FNAME; + + TYPE SAMPLE_VECTOR_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(13 DOWNTO 0); + SIGNAL sample_vector : SAMPLE_VECTOR_TYPE(1 TO 16); + + SIGNAL sample_vector_adc : SAMPLE_VECTOR_TYPE(1 TO 13); + SIGNAL sample_vector_hk : SAMPLE_VECTOR_TYPE(14 TO 16); + + SIGNAL sample_vector_reg : SAMPLE_VECTOR_TYPE(1 TO 16); + SIGNAL sample_vector_adc_reg : SAMPLE_VECTOR_TYPE(1 TO 13); + SIGNAL sample_vector_hk_reg : SAMPLE_VECTOR_TYPE(14 TO 16); + + + SIGNAL oeb_bar_ch : STD_LOGIC_VECTOR(8 DOWNTO 0); + +BEGIN -- ARCHITECTURE beh + + ----------------------------------------------------------------------------- + -- Data orginization in the input file : + ----------------------------------------------------------------------------- + -- Exemple of input.txt file : + -- Time1 B1 B2 B3 BIAS1 BIAS2 BIAS3 BIAS4 BIAS5 V1 V2 V3 GND1 GND2 HK1 HK2 HK3 + -- Time2 B1 B2 B3 BIAS1 BIAS2 BIAS3 BIAS4 BIAS5 V1 V2 V3 GND1 GND2 HK1 HK2 HK3 + ----------------------------------------------------------------------------- + -- Time : integer. Duration time (in ns) to set the following data + -- Data : unsigned (0 to 255). A part of the message. + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + PROCESS IS + VARIABLE line_var : LINE; + VARIABLE waiting_time : INTEGER; + VARIABLE value : INTEGER; + BEGIN -- PROCESS + + IF endfile(input_file) THEN + end_of_simu <= '1'; + ELSE + end_of_simu <= '0'; + readline(input_file, line_var); + read(line_var, waiting_time); + FOR sample_index IN 1 TO 16 LOOP + read(line_var, value); + sample_vector(sample_index) <= STD_LOGIC_VECTOR(to_unsigned(value, 14)); + END LOOP; -- sample + + WAIT FOR waiting_time * 1 ns; + END IF; + + END PROCESS; + + all_adc_sample: FOR sample_index IN 1 TO 13 GENERATE + sample_vector_adc(sample_index) <= sample_vector (sample_index); + sample_vector_reg(sample_index) <= sample_vector_adc_reg(sample_index); + END GENERATE all_adc_sample; + all_hk_sample: FOR sample_index IN 14 TO 16 GENERATE + sample_vector_hk (sample_index) <= sample_vector (sample_index); + sample_vector_reg(sample_index) <= sample_vector_hk_reg(sample_index); + END GENERATE all_hk_sample; + + + ----------------------------------------------------------------------------- + PROCESS IS + BEGIN -- PROCESS + WAIT UNTIL adc_rhf1401_smp_clk = '1'; + sample_vector_adc_reg <= sample_vector_adc; + END PROCESS; + + PROCESS IS + BEGIN -- PROCESS + WAIT UNTIL hk_rhf1401_smp_clk = '1'; + sample_vector_hk_reg <= sample_vector_hk; + END PROCESS; + ----------------------------------------------------------------------------- + + oeb_bar_ch <= hk_rhf1401_oeb_bar_ch & adc_rhf1401_oeb_bar_ch; + + PROCESS (oeb_bar_ch, sample_vector_reg, hk_sel) IS + BEGIN -- PROCESS + error_oeb <= '0'; + error_hksel <= '0'; + CASE oeb_bar_ch IS + WHEN "111111111" => NULL; + WHEN "111111110" => IF adc_bias_fail_sel = '1' THEN rhf1401_data <= sample_vector_reg(4); ELSE rhf1401_data <= sample_vector_reg( 9); END IF; + WHEN "111111101" => IF adc_bias_fail_sel = '1' THEN rhf1401_data <= sample_vector_reg(5); ELSE rhf1401_data <= sample_vector_reg(10); END IF; + WHEN "111111011" => IF adc_bias_fail_sel = '1' THEN rhf1401_data <= sample_vector_reg(6); ELSE rhf1401_data <= sample_vector_reg(11); END IF; + WHEN "111110111" => IF adc_bias_fail_sel = '1' THEN rhf1401_data <= sample_vector_reg(7); ELSE rhf1401_data <= sample_vector_reg(12); END IF; + WHEN "111101111" => IF adc_bias_fail_sel = '1' THEN rhf1401_data <= sample_vector_reg(8); ELSE rhf1401_data <= sample_vector_reg(13); END IF; + WHEN "111011111" => rhf1401_data <= sample_vector_reg(1); + WHEN "110111111" => rhf1401_data <= sample_vector_reg(2); + WHEN "101111111" => rhf1401_data <= sample_vector_reg(3); + WHEN "011111111" => + CASE hk_sel IS + WHEN "00" => rhf1401_data <= sample_vector_reg(14); + WHEN "01" => rhf1401_data <= sample_vector_reg(15); + WHEN "10" => rhf1401_data <= sample_vector_reg(16); + WHEN OTHERS => error_hksel <= '1'; + END CASE; + WHEN OTHERS => error_oeb <= '1'; + END CASE; + END PROCESS; + ----------------------------------------------------------------------------- + +END ARCHITECTURE beh; + diff --git a/lib/lpp/lpp_sim/lpp_sim_pkg.vhd b/lib/lpp/lpp_sim/lpp_sim_pkg.vhd --- a/lib/lpp/lpp_sim/lpp_sim_pkg.vhd +++ b/lib/lpp/lpp_sim/lpp_sim_pkg.vhd @@ -89,6 +89,9 @@ PACKAGE lpp_sim_pkg IS ); END COMPONENT; + ----------------------------------------------------------------------------- + -- SPW + ----------------------------------------------------------------------------- COMPONENT spw_sender IS GENERIC ( FNAME : STRING); @@ -116,6 +119,25 @@ PACKAGE lpp_sim_pkg IS rxvalid : in STD_LOGIC; rxhalff : out STD_LOGIC); END COMPONENT spw_receiver; + + ----------------------------------------------------------------------------- + -- LFR-I/O + ----------------------------------------------------------------------------- + COMPONENT lfr_input_gen IS + GENERIC ( + FNAME : STRING); + PORT ( + end_of_simu : OUT STD_LOGIC; + rhf1401_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); + adc_rhf1401_smp_clk : IN STD_LOGIC; + adc_rhf1401_oeb_bar_ch : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + adc_bias_fail_sel : IN STD_LOGIC; + hk_rhf1401_smp_clk : IN STD_LOGIC; + hk_rhf1401_oeb_bar_ch : IN STD_LOGIC; + hk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + error_oeb : OUT STD_LOGIC; + error_hksel : OUT STD_LOGIC); + END COMPONENT lfr_input_gen; END lpp_sim_pkg; diff --git a/lib/lpp/lpp_sim/vhdlsim.txt b/lib/lpp/lpp_sim/vhdlsim.txt --- a/lib/lpp/lpp_sim/vhdlsim.txt +++ b/lib/lpp/lpp_sim/vhdlsim.txt @@ -5,3 +5,4 @@ lpp_sim_pkg.vhd lpp_lfr_sim_pkg.vhd spw_sender.vhd spw_receiver.vhd +lfr_input_gen.vhd diff --git a/tests/Test_ADC_RHF1401/Makefile b/tests/Test_ADC_RHF1401/Makefile new file mode 100644 --- /dev/null +++ b/tests/Test_ADC_RHF1401/Makefile @@ -0,0 +1,53 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=testbench +BOARD=LFR-FM +include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF= +QSF= +EFFORT=high +XSTOPT= +SYNPOPT= +VHDLSYNFILES= +VHDLSIMFILES= tb.vhd +SIMTOP=testbench +CLEAN=soft-clean + +TECHLIBS = axcelerator + + +LIBSKIP = tmtc openchip hynix cypress ihp usbhc fmf gsi spansion eth micron + +DIRSKIP = leon2 leon2ft crypto usb satcan ddr greth grusbhc \ + leon4 leon4v0 l2cache iommu slink ascs pwm net spi can \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_uart \ + ./lpp_usb \ + ./lpp_debug_lfr \ + ./dsp/lpp_fft + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_sim_pkg.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile +################## project specific targets ########################## +distclean:myclean + +myclean: + rm -f input.txt output_fx.txt *.log + rm -rf ./2016* + +test: | ghdl ghdl-run archivate + + diff --git a/tests/Test_ADC_RHF1401/adc_input.txt b/tests/Test_ADC_RHF1401/adc_input.txt new file mode 100644 --- /dev/null +++ b/tests/Test_ADC_RHF1401/adc_input.txt @@ -0,0 +1,385 @@ +10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 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12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 +110 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 +110 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 +110 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 +110 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 +110 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 +110 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 +110 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 +110 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 +110 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 +110 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 +110 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 +110 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 +110 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +110 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 diff --git a/tests/Test_ADC_RHF1401/tb.vhd b/tests/Test_ADC_RHF1401/tb.vhd new file mode 100644 --- /dev/null +++ b/tests/Test_ADC_RHF1401/tb.vhd @@ -0,0 +1,141 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE IEEE.std_logic_signed.ALL; +USE IEEE.MATH_real.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY opencores; +USE opencores.spwpkg.ALL; +USE opencores.spwambapkg.ALL; + +LIBRARY lpp; +USE lpp.lpp_sim_pkg.ALL; +USE lpp.lpp_ad_conv.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL TSTAMP : INTEGER := 0; + + SIGNAL clk_25 : STD_LOGIC := '0'; + SIGNAL rstn_25 : STD_LOGIC; + SIGNAL clk_24 : STD_LOGIC := '0'; + SIGNAL rstn_24 : STD_LOGIC; + + SIGNAL end_of_simu : STD_LOGIC := '0'; + + SIGNAL ADC_smpclk_s : STD_LOGIC; + + SIGNAL ADC_data : Samples14; + SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL sample : Samples14v(8 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + +BEGIN + + ----------------------------------------------------------------------------- + -- CLOCK and RESET + ----------------------------------------------------------------------------- + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk_25 = '1'; + rstn_25 <= '0'; + WAIT UNTIL clk_25 = '1'; + WAIT UNTIL clk_25 = '1'; + WAIT UNTIL clk_25 = '1'; + rstn_25 <= '1'; + WAIT UNTIL end_of_simu = '1'; + WAIT FOR 10 ps; + ASSERT false REPORT "end of test" SEVERITY note; + -- Wait forever; this will finish the simulation. + WAIT; + END PROCESS; + ----------------------------------------------------------------------------- + clk_25_gen : PROCESS + BEGIN + IF end_of_simu /= '1' THEN + clk_25 <= NOT clk_25; + TSTAMP <= TSTAMP+20; + WAIT FOR 20 ns; + ELSE + WAIT FOR 20 ps; + ASSERT false REPORT "end of test" SEVERITY note; + WAIT; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- CLOCK and RESET + ----------------------------------------------------------------------------- + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk_24 = '1'; + rstn_24 <= '0'; + WAIT UNTIL clk_24 = '1'; + WAIT UNTIL clk_24 = '1'; + WAIT UNTIL clk_24 = '1'; + rstn_24 <= '1'; + WAIT UNTIL end_of_simu = '1'; + WAIT FOR 10 ps; + ASSERT false REPORT "end of test" SEVERITY note; + -- Wait forever; this will finish the simulation. + WAIT; + END PROCESS; + ----------------------------------------------------------------------------- + clk_24_gen : PROCESS + BEGIN + IF end_of_simu /= '1' THEN + clk_24 <= NOT clk_24; + WAIT FOR 20345 ps; + ELSE + WAIT FOR 20 ps; + ASSERT false REPORT "end of test" SEVERITY note; + WAIT; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter + GENERIC MAP ( + ChanelCount => 9, + ncycle_cnv_high => 12, + ncycle_cnv => 25, + FILTER_ENABLED => 16#FF#) + PORT MAP ( + cnv_clk => clk_24, + cnv_rstn => rstn_24, + cnv => ADC_smpclk_s, + clk => clk_25, + rstn => rstn_25, + ADC_data => ADC_data, + ADC_nOE => ADC_OEB_bar_CH_s, + sample => sample, + sample_val => sample_val); + + ----------------------------------------------------------------------------- + lfr_input_gen_1: lfr_input_gen + GENERIC MAP ( + FNAME => "adc_input.txt") + PORT MAP ( + end_of_simu => end_of_simu, + rhf1401_data => ADC_data, + adc_rhf1401_smp_clk => ADC_smpclk_s, + adc_rhf1401_oeb_bar_ch => ADC_OEB_bar_CH_s(7 DOWNTO 0), + adc_bias_fail_sel => '0', + hk_rhf1401_smp_clk => ADC_smpclk_s, + hk_rhf1401_oeb_bar_ch => ADC_OEB_bar_CH_s(8), + hk_sel => "00", + error_oeb => OPEN, + error_hksel => OPEN); + ----------------------------------------------------------------------------- + +END; diff --git a/tests/Test_SPW_light/Makefile b/tests/Test_SPW_light/Makefile new file mode 100644 --- /dev/null +++ b/tests/Test_SPW_light/Makefile @@ -0,0 +1,53 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=testbench +BOARD=LFR-FM +include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF= +QSF= +EFFORT=high +XSTOPT= +SYNPOPT= +VHDLSYNFILES= +VHDLSIMFILES= $(VHDLIB)/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd tb.vhd +SIMTOP=testbench +CLEAN=soft-clean + +TECHLIBS = axcelerator + + +LIBSKIP = tmtc openchip hynix cypress ihp usbhc fmf gsi spansion eth micron + +DIRSKIP = leon2 leon2ft crypto usb satcan ddr greth grusbhc \ + leon4 leon4v0 l2cache iommu slink ascs pwm net spi can \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_uart \ + ./lpp_usb \ + ./lpp_debug_lfr \ + ./dsp/lpp_fft + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_sim_pkg.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile +################## project specific targets ########################## +distclean:myclean + +myclean: + rm -f input.txt output_fx.txt *.log + rm -rf ./2016* + +test: | ghdl ghdl-run archivate + + diff --git a/tests/Test_SPW_light/spw_input.txt b/tests/Test_SPW_light/spw_input.txt new file mode 100644 --- /dev/null +++ b/tests/Test_SPW_light/spw_input.txt @@ -0,0 +1,7 @@ +20 3 +28 +14 +32 +1500 2 +18 +200 diff --git a/tests/Test_SPW_light/spw_output.txt b/tests/Test_SPW_light/spw_output.txt new file mode 100644 --- /dev/null +++ b/tests/Test_SPW_light/spw_output.txt @@ -0,0 +1,7 @@ +28 +14 +32 +TIME= 45020 +18 +200 +TIME= 47660 diff --git a/tests/Test_SPW_light/tb.vhd b/tests/Test_SPW_light/tb.vhd new file mode 100644 --- /dev/null +++ b/tests/Test_SPW_light/tb.vhd @@ -0,0 +1,213 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE IEEE.std_logic_signed.ALL; +USE IEEE.MATH_real.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY opencores; +USE opencores.spwpkg.ALL; +USE opencores.spwambapkg.ALL; + +LIBRARY lpp; +USE lpp.lpp_sim_pkg.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL TSTAMP : INTEGER := 0; + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rst : STD_LOGIC; + + SIGNAL end_of_simu : STD_LOGIC := '0'; + + SIGNAL autostart : STD_LOGIC := '1'; + SIGNAL linkstart : STD_LOGIC := '1'; + SIGNAL linkdis : STD_LOGIC := '0'; + SIGNAL ctrl_in : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL time_in : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0'); + SIGNAL txwrite : STD_LOGIC := '0'; + SIGNAL txflag : STD_LOGIC := '0'; + SIGNAL txdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL txrdy : STD_LOGIC; + SIGNAL txhalff : STD_LOGIC; + SIGNAL tick_out : STD_LOGIC; + SIGNAL ctrl_out : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL time_out : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL rxvalid : STD_LOGIC; + SIGNAL rxhalff : STD_LOGIC; + SIGNAL rxflag : STD_LOGIC; + SIGNAL rxdata : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rxread : STD_LOGIC := '0'; + SIGNAL started : STD_LOGIC; + SIGNAL connecting : STD_LOGIC; + SIGNAL running : STD_LOGIC; + SIGNAL errdisc : STD_LOGIC; + SIGNAL errpar : STD_LOGIC; + SIGNAL erresc : STD_LOGIC; + SIGNAL errcred : STD_LOGIC; + + SIGNAL spw_di : std_logic; + SIGNAL spw_si : std_logic; + SIGNAL spw_do : std_logic; + SIGNAL spw_so : std_logic; + +BEGIN + + ----------------------------------------------------------------------------- + -- CLOCK and RESET + ----------------------------------------------------------------------------- + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk = '1'; + rst <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + rst <= '0'; + WAIT UNTIL end_of_simu = '1'; + WAIT FOR 10 ps; + ASSERT false REPORT "end of test" SEVERITY note; + -- Wait forever; this will finish the simulation. + WAIT; + END PROCESS; + ----------------------------------------------------------------------------- + + clk_50M_gen : PROCESS + BEGIN + IF end_of_simu /= '1' THEN + clk <= NOT clk; + TSTAMP <= TSTAMP+20; + WAIT FOR 10 ns; + ELSE + WAIT FOR 10 ps; + ASSERT false REPORT "end of test" SEVERITY note; + WAIT; + END IF; + END PROCESS; + + + SPW : spwstream + + GENERIC MAP( + sysfreq => 50.0e6, + txclkfreq => 50.0e6, + rximpl => impl_generic, + rxchunk => 1, + tximpl => impl_generic, + rxfifosize_bits => 11, + txfifosize_bits => 11 + ) + + PORT MAP( + -- System clock. + clk => clk, + rxclk => clk, + txclk => clk, + rst => rst, + + + autostart => autostart, -- Enables automatic link start on receipt of a NULL character. + linkstart => linkstart, -- Enables link start once the Ready state is reached. Without autostart or linkstart, the link remains in state Ready. + linkdis => linkdis, -- Do not start link (overrides linkstart and autostart) and/or disconnect a running link. + + txdivcnt => X"00", + + + ------------------------------------------------------------------------- + -- TimeCode transmission + tick_in => '0', -- High for one clock cycle to request transmission of a TimeCode. The request is registered inside the entity until it can be processed. + ctrl_in => ctrl_in, -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high. + time_in => time_in, -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high. + ------------------------------------------------------------------------- + + ------------------------------------------------------------------------- + -- ### tx data ### tb -> SPW-light + txwrite => txwrite, -- Pulled high by the application to write an N-Char to the transmit queue. + -- If "txwrite" and "txrdy" are both high on the rising edge of "clk", a character is added to the transmit queue. + -- This signal has no effect if "txrdy" is low. + txflag => txflag, -- Control flag to be sent with the next N_Char. Must be valid while txwrite is high. + txdata => txdata, -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. Must be valid while txwrite is high. + txrdy => txrdy, -- High if the entity is ready to accept an N-Char for transmission. + txhalff => txhalff, -- High if the transmission queue is at least half full. + ------------------------------------------------------------------------- + + ------------------------------------------------------------------------- + -- TimeCode reception + tick_out => tick_out, -- High for one clock cycle if a TimeCode was just received. + ctrl_out => ctrl_out, -- Control bits of the last received TimeCode. + time_out => time_out, -- Counter value of the last received TimeCode. + ------------------------------------------------------------------------- + + + ------------------------------------------------------------------------- + -- ### rx data ### tb <- SPW-light + rxvalid => rxvalid, -- High if "rxflag" and "rxdata" contain valid data. This signal is high unless the receive FIFO is empty. + rxhalff => rxhalff, -- High if the receive FIFO is at least half full. + rxflag => rxflag, -- High if the received character is EOP or EEP; low if the received character is a data byte. Valid if "rxvalid" is high. + rxdata => rxdata, -- Received byte, or "00000000" for EOP or "00000001" for EEP. Valid if "rxvalid" is high. + rxread => rxread, -- Pulled high by the application to accept a received character. + -- If "rxvalid" and "rxread" are both high on the rising edge of "clk", + -- a character is removed from the receive FIFO and "rxvalid", "rxflag" and "rxdata" are updated. + -- This signal has no effect if "rxvalid" is low. + ------------------------------------------------------------------------- + + ------------------------------------------------------------------------- + -- STATUS + started => started, -- High if the link state machine is currently in the Started state. + connecting => connecting, -- High if the link state machine is currently in the Connecting state. + running => running, -- High if the link state machine is currently in the Run state, indicatin that the link is fully operational. + -- If none of started, connecting or running is high, the link is in an initial state and the transmitter is not yet enabled. + + errdisc => errdisc, -- Disconnect detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing. + errpar => errpar, -- Parity error detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing. + erresc => erresc, -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing. + errcred => errcred, -- Credit error detected. Triggers a reset and reconnect of the link. This indication is auto-clearing. + ------------------------------------------------------------------------- + + spw_di => spw_di, -- Data In signal from SpaceWire bus. + spw_si => spw_si, -- Strobe In signal from SpaceWire bus. + spw_do => spw_do, -- Data Out signal to SpaceWire bus. + spw_so => spw_so -- Strobe Out signal to SpaceWire bus. + ); + + + spw_si <= spw_so; + spw_di <= spw_do; + + spw_sender_1: spw_sender + GENERIC MAP ( + FNAME => "spw_input.txt") + PORT MAP ( + end_of_simu => OPEN, + start_of_simu => running, + clk => clk, + + txwrite => txwrite, + txflag => txflag, + txdata => txdata, + txrdy => txrdy, + txhalff => txhalff); + + spw_receiver_1: spw_receiver + GENERIC MAP ( + FNAME => "spw_output.txt") + PORT MAP ( + end_of_simu => '0', + timestamp => TSTAMP, + clk => clk, + rxread => rxread, + rxflag => rxflag, + rxdata => rxdata, + rxvalid => rxvalid, + rxhalff => rxhalff); + +END; diff --git a/tests/Validation_SPW_light/Makefile b/tests/Validation_SPW_light/Makefile deleted file mode 100644 --- a/tests/Validation_SPW_light/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=testbench -BOARD=LFR-FM -include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF= -QSF= -EFFORT=high -XSTOPT= -SYNPOPT= -VHDLSYNFILES= -VHDLSIMFILES= $(VHDLIB)/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd tb.vhd -SIMTOP=testbench -CLEAN=soft-clean - -TECHLIBS = axcelerator - - -LIBSKIP = tmtc openchip hynix cypress ihp usbhc fmf gsi spansion eth micron - -DIRSKIP = leon2 leon2ft crypto usb satcan ddr greth grusbhc \ - leon4 leon4v0 l2cache iommu slink ascs pwm net spi can \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_debug_lfr \ - ./dsp/lpp_fft - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd \ - lpp_lfr_sim_pkg.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile -################## project specific targets ########################## -distclean:myclean - -myclean: - rm -f input.txt output_fx.txt *.log - rm -rf ./2016* - -test: | ghdl ghdl-run archivate - - diff --git a/tests/Validation_SPW_light/spw_input.txt b/tests/Validation_SPW_light/spw_input.txt deleted file mode 100644 --- a/tests/Validation_SPW_light/spw_input.txt +++ /dev/null @@ -1,7 +0,0 @@ -20 3 -28 -14 -32 -1500 2 -18 -200 diff --git a/tests/Validation_SPW_light/spw_output.txt b/tests/Validation_SPW_light/spw_output.txt deleted file mode 100644 --- a/tests/Validation_SPW_light/spw_output.txt +++ /dev/null @@ -1,7 +0,0 @@ -28 -14 -32 -TIME= 45020 -18 -200 -TIME= 47660 diff --git a/tests/Validation_SPW_light/tb.vhd b/tests/Validation_SPW_light/tb.vhd deleted file mode 100644 --- a/tests/Validation_SPW_light/tb.vhd +++ /dev/null @@ -1,213 +0,0 @@ - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -USE IEEE.std_logic_signed.ALL; -USE IEEE.MATH_real.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY std; -USE std.textio.ALL; - -LIBRARY opencores; -USE opencores.spwpkg.ALL; -USE opencores.spwambapkg.ALL; - -LIBRARY lpp; -USE lpp.lpp_sim_pkg.ALL; - -ENTITY testbench IS -END; - -ARCHITECTURE behav OF testbench IS - - SIGNAL TSTAMP : INTEGER := 0; - SIGNAL clk : STD_LOGIC := '0'; - SIGNAL rst : STD_LOGIC; - - SIGNAL end_of_simu : STD_LOGIC := '0'; - - SIGNAL autostart : STD_LOGIC := '1'; - SIGNAL linkstart : STD_LOGIC := '1'; - SIGNAL linkdis : STD_LOGIC := '0'; - SIGNAL ctrl_in : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL time_in : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0'); - SIGNAL txwrite : STD_LOGIC := '0'; - SIGNAL txflag : STD_LOGIC := '0'; - SIGNAL txdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); - SIGNAL txrdy : STD_LOGIC; - SIGNAL txhalff : STD_LOGIC; - SIGNAL tick_out : STD_LOGIC; - SIGNAL ctrl_out : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL time_out : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL rxvalid : STD_LOGIC; - SIGNAL rxhalff : STD_LOGIC; - SIGNAL rxflag : STD_LOGIC; - SIGNAL rxdata : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL rxread : STD_LOGIC := '0'; - SIGNAL started : STD_LOGIC; - SIGNAL connecting : STD_LOGIC; - SIGNAL running : STD_LOGIC; - SIGNAL errdisc : STD_LOGIC; - SIGNAL errpar : STD_LOGIC; - SIGNAL erresc : STD_LOGIC; - SIGNAL errcred : STD_LOGIC; - - SIGNAL spw_di : std_logic; - SIGNAL spw_si : std_logic; - SIGNAL spw_do : std_logic; - SIGNAL spw_so : std_logic; - -BEGIN - - ----------------------------------------------------------------------------- - -- CLOCK and RESET - ----------------------------------------------------------------------------- - PROCESS - BEGIN -- PROCESS - WAIT UNTIL clk = '1'; - rst <= '1'; - WAIT UNTIL clk = '1'; - WAIT UNTIL clk = '1'; - WAIT UNTIL clk = '1'; - rst <= '0'; - WAIT UNTIL end_of_simu = '1'; - WAIT FOR 10 ps; - ASSERT false REPORT "end of test" SEVERITY note; - -- Wait forever; this will finish the simulation. - WAIT; - END PROCESS; - ----------------------------------------------------------------------------- - - clk_50M_gen : PROCESS - BEGIN - IF end_of_simu /= '1' THEN - clk <= NOT clk; - TSTAMP <= TSTAMP+20; - WAIT FOR 10 ns; - ELSE - WAIT FOR 10 ps; - ASSERT false REPORT "end of test" SEVERITY note; - WAIT; - END IF; - END PROCESS; - - - SPW : spwstream - - GENERIC MAP( - sysfreq => 50.0e6, - txclkfreq => 50.0e6, - rximpl => impl_generic, - rxchunk => 1, - tximpl => impl_generic, - rxfifosize_bits => 11, - txfifosize_bits => 11 - ) - - PORT MAP( - -- System clock. - clk => clk, - rxclk => clk, - txclk => clk, - rst => rst, - - - autostart => autostart, -- Enables automatic link start on receipt of a NULL character. - linkstart => linkstart, -- Enables link start once the Ready state is reached. Without autostart or linkstart, the link remains in state Ready. - linkdis => linkdis, -- Do not start link (overrides linkstart and autostart) and/or disconnect a running link. - - txdivcnt => X"00", - - - ------------------------------------------------------------------------- - -- TimeCode transmission - tick_in => '0', -- High for one clock cycle to request transmission of a TimeCode. The request is registered inside the entity until it can be processed. - ctrl_in => ctrl_in, -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high. - time_in => time_in, -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high. - ------------------------------------------------------------------------- - - ------------------------------------------------------------------------- - -- ### tx data ### tb -> SPW-light - txwrite => txwrite, -- Pulled high by the application to write an N-Char to the transmit queue. - -- If "txwrite" and "txrdy" are both high on the rising edge of "clk", a character is added to the transmit queue. - -- This signal has no effect if "txrdy" is low. - txflag => txflag, -- Control flag to be sent with the next N_Char. Must be valid while txwrite is high. - txdata => txdata, -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. Must be valid while txwrite is high. - txrdy => txrdy, -- High if the entity is ready to accept an N-Char for transmission. - txhalff => txhalff, -- High if the transmission queue is at least half full. - ------------------------------------------------------------------------- - - ------------------------------------------------------------------------- - -- TimeCode reception - tick_out => tick_out, -- High for one clock cycle if a TimeCode was just received. - ctrl_out => ctrl_out, -- Control bits of the last received TimeCode. - time_out => time_out, -- Counter value of the last received TimeCode. - ------------------------------------------------------------------------- - - - ------------------------------------------------------------------------- - -- ### rx data ### tb <- SPW-light - rxvalid => rxvalid, -- High if "rxflag" and "rxdata" contain valid data. This signal is high unless the receive FIFO is empty. - rxhalff => rxhalff, -- High if the receive FIFO is at least half full. - rxflag => rxflag, -- High if the received character is EOP or EEP; low if the received character is a data byte. Valid if "rxvalid" is high. - rxdata => rxdata, -- Received byte, or "00000000" for EOP or "00000001" for EEP. Valid if "rxvalid" is high. - rxread => rxread, -- Pulled high by the application to accept a received character. - -- If "rxvalid" and "rxread" are both high on the rising edge of "clk", - -- a character is removed from the receive FIFO and "rxvalid", "rxflag" and "rxdata" are updated. - -- This signal has no effect if "rxvalid" is low. - ------------------------------------------------------------------------- - - ------------------------------------------------------------------------- - -- STATUS - started => started, -- High if the link state machine is currently in the Started state. - connecting => connecting, -- High if the link state machine is currently in the Connecting state. - running => running, -- High if the link state machine is currently in the Run state, indicatin that the link is fully operational. - -- If none of started, connecting or running is high, the link is in an initial state and the transmitter is not yet enabled. - - errdisc => errdisc, -- Disconnect detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing. - errpar => errpar, -- Parity error detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing. - erresc => erresc, -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing. - errcred => errcred, -- Credit error detected. Triggers a reset and reconnect of the link. This indication is auto-clearing. - ------------------------------------------------------------------------- - - spw_di => spw_di, -- Data In signal from SpaceWire bus. - spw_si => spw_si, -- Strobe In signal from SpaceWire bus. - spw_do => spw_do, -- Data Out signal to SpaceWire bus. - spw_so => spw_so -- Strobe Out signal to SpaceWire bus. - ); - - - spw_si <= spw_so; - spw_di <= spw_do; - - spw_sender_1: spw_sender - GENERIC MAP ( - FNAME => "spw_input.txt") - PORT MAP ( - end_of_simu => OPEN, - start_of_simu => running, - clk => clk, - - txwrite => txwrite, - txflag => txflag, - txdata => txdata, - txrdy => txrdy, - txhalff => txhalff); - - spw_receiver_1: spw_receiver - GENERIC MAP ( - FNAME => "spw_output.txt") - PORT MAP ( - end_of_simu => '0', - timestamp => TSTAMP, - clk => clk, - rxread => rxread, - rxflag => rxflag, - rxdata => rxdata, - rxvalid => rxvalid, - rxhalff => rxhalff); - -END;