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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE IEEE.std_logic_signed.ALL;
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USE IEEE.MATH_real.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY std;
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USE std.textio.ALL;
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LIBRARY opencores;
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USE opencores.spwpkg.ALL;
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USE opencores.spwambapkg.ALL;
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LIBRARY lpp;
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USE lpp.lpp_sim_pkg.ALL;
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USE lpp.lpp_ad_conv.ALL;
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ENTITY testbench IS
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END;
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ARCHITECTURE behav OF testbench IS
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SIGNAL TSTAMP : INTEGER := 0;
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SIGNAL clk_25 : STD_LOGIC := '0';
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SIGNAL rstn_25 : STD_LOGIC;
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SIGNAL clk_24 : STD_LOGIC := '0';
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SIGNAL rstn_24 : STD_LOGIC;
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SIGNAL end_of_simu : STD_LOGIC := '0';
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SIGNAL ADC_smpclk_s : STD_LOGIC;
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SIGNAL ADC_data : Samples14;
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SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
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SIGNAL sample : Samples14v(8 DOWNTO 0);
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SIGNAL sample_val : STD_LOGIC;
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BEGIN
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-----------------------------------------------------------------------------
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-- CLOCK and RESET
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-----------------------------------------------------------------------------
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PROCESS
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BEGIN -- PROCESS
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WAIT UNTIL clk_25 = '1';
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rstn_25 <= '0';
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WAIT UNTIL clk_25 = '1';
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WAIT UNTIL clk_25 = '1';
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WAIT UNTIL clk_25 = '1';
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rstn_25 <= '1';
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WAIT UNTIL end_of_simu = '1';
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WAIT FOR 10 ps;
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ASSERT false REPORT "end of test" SEVERITY note;
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-- Wait forever; this will finish the simulation.
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WAIT;
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END PROCESS;
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-----------------------------------------------------------------------------
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clk_25_gen : PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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clk_25 <= NOT clk_25;
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TSTAMP <= TSTAMP+20;
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WAIT FOR 20 ns;
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ELSE
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WAIT FOR 20 ps;
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ASSERT false REPORT "end of test" SEVERITY note;
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WAIT;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- CLOCK and RESET
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-----------------------------------------------------------------------------
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PROCESS
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BEGIN -- PROCESS
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WAIT UNTIL clk_24 = '1';
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rstn_24 <= '0';
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WAIT UNTIL clk_24 = '1';
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WAIT UNTIL clk_24 = '1';
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WAIT UNTIL clk_24 = '1';
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rstn_24 <= '1';
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WAIT UNTIL end_of_simu = '1';
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WAIT FOR 10 ps;
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ASSERT false REPORT "end of test" SEVERITY note;
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-- Wait forever; this will finish the simulation.
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WAIT;
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END PROCESS;
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-----------------------------------------------------------------------------
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clk_24_gen : PROCESS
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BEGIN
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IF end_of_simu /= '1' THEN
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clk_24 <= NOT clk_24;
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WAIT FOR 20345 ps;
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ELSE
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WAIT FOR 20 ps;
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ASSERT false REPORT "end of test" SEVERITY note;
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WAIT;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
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GENERIC MAP (
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ChanelCount => 9,
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ncycle_cnv_high => 12,
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ncycle_cnv => 25,
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FILTER_ENABLED => 16#FF#)
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PORT MAP (
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cnv_clk => clk_24,
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cnv_rstn => rstn_24,
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cnv => ADC_smpclk_s,
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clk => clk_25,
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rstn => rstn_25,
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ADC_data => ADC_data,
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ADC_nOE => ADC_OEB_bar_CH_s,
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sample => sample,
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sample_val => sample_val);
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-----------------------------------------------------------------------------
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lfr_input_gen_1: lfr_input_gen
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GENERIC MAP (
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FNAME => "adc_input.txt")
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PORT MAP (
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end_of_simu => end_of_simu,
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rhf1401_data => ADC_data,
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adc_rhf1401_smp_clk => ADC_smpclk_s,
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adc_rhf1401_oeb_bar_ch => ADC_OEB_bar_CH_s(7 DOWNTO 0),
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adc_bias_fail_sel => '0',
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hk_rhf1401_smp_clk => ADC_smpclk_s,
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hk_rhf1401_oeb_bar_ch => ADC_OEB_bar_CH_s(8),
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hk_sel => "00",
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error_oeb => OPEN,
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error_hksel => OPEN);
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-----------------------------------------------------------------------------
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END;
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