HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Changelog

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HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib

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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

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	`r608:b0637f76f46e`	update LFR-em	Thu, 04 Jun 2015 14:02:38	pellion	simu_with_Leon3	0
	`r607:337372d6bbe7`	update LFR-em	Thu, 04 Jun 2015 14:02:38	pellion	simu_with_Leon3	0
	`r606:2f207df1fc75`	Hanning windows in front of FFT	Thu, 04 Jun 2015 14:00:32	pellion	simu_with_Leon3	0
	`r605:6a183ad6a08b`	Étiquette (LFR-EQM) 2-1-83 ajoutée à la révision 1b6a99d2ea09	Wed, 03 Jun 2015 08:44:32	pellion	simu_with_Leon3	0
	`r604:9d0c406efed4`	Window Function with a ROM (Hanning)	Wed, 03 Jun 2015 08:26:40	pellion	simu_with_Leon3	0
	`r603:c380a9e98a1c`	LFR-em 1.1.83 ...	Tue, 02 Jun 2015 07:38:28	pellion	simu_with_Leon3	0
	`r602:ddd72636badb`	temp	Tue, 26 May 2015 14:38:25	pellion	simu_with_Leon3	0
	`r601:1b6a99d2ea09`	LFR-EQM 2.1.83 > ad_conv_RH1401_withFilter version idem EM	Wed, 20 May 2015 10:35:37	pellion	simu_with_Leon3 (LFR-EQM) 2-1-83	0
	`r600:1d46c91bda8b`	LFR-EQM 2.1.82 - b > SMP_CLK @ 24576MHz/25 = 983.03Hz > OEn active during one cycle > sample ADC_DATA one cycle after the OEn SMP_CLK --------\|___________ CLK_25Mhz-\|_\|-\|_\|-\|_\|-\|_\|-\|_\|-\|_\|-\|_\|-\|_\|-\|_\| ADC_OEn ------------\|___\|----- ADC_DATA **************{data} ADC_DATA_reg**************{data}	Wed, 20 May 2015 09:01:18	pellion	simu_with_Leon3	0
	`r599:6aaa08019409`	LFR-EQM 2.1.82	Mon, 18 May 2015 14:44:12	pellion	simu_with_Leon3	0
	`r598:a4da461dd67d`	LFR-EQM 2.1.81 > all is ok, the ADC data are sampled at 500M.sample.Hz	Mon, 18 May 2015 12:42:37	pellion	simu_with_Leon3	0
	`r597:ec6fbc748101`	save	Mon, 18 May 2015 12:09:03	pellion	simu_with_Leon3	0
	`r596:04687799528c`	ok	Fri, 15 May 2015 07:59:58	pellion	simu_with_Leon3	0
	`r595:eb603d70d051`	register the data outputed by ADC_driver	Tue, 05 May 2015 09:12:31	pellion	simu_with_Leon3	0
	`r594:a9702b7364d2`	temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)	Mon, 04 May 2015 14:31:01	pellion	simu_with_Leon3	0
	`r593:173a643f1c9c`	temp	Thu, 30 Apr 2015 11:58:47	pellion	simu_with_Leon3	0
	`r592:7b23905bc9f6`	temp	Thu, 30 Apr 2015 09:47:15	pellion	JC	0
	`r591:e0250657227b`	ADD SDC constraint	Fri, 24 Apr 2015 14:16:40	pellion	JC	0
	`r590:f6390d699855`	merge simu_with_leon3 (add lpp_dma_SEND16B_FIFO2DMA)	Fri, 24 Apr 2015 10:31:42	pellion	JC	0
	`r589:ebd290519818`	update ok ??	Thu, 23 Apr 2015 17:11:39	pellion	simu_with_Leon3	0
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