HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r592:7b23905bc9f6

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r592:7b23905bc9f6 JC

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r592:7b23905bc9f6

designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +3 -3

               -----------------------------------------------------------------------------
               -- CLK_LOCK
               -----------------------------------------------------------------------------
-              rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
+              rst_gen_global : rstgen PORT MAP (reset, clk50MHz_int, '1', rstn_50, OPEN);
               PROCESS (clk50MHz_int, rstn_50)
               BEGIN  -- PROCESS
               rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
               rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
-              --clk_pad : clkint  port map (A => clk50MHz, Y => clk50MHz_int );
+              clk_pad : clkint  port map (A => clk50MHz, Y => clk50MHz_int );
-              clk50MHz_int <= clk50MHz;
+              --clk50MHz_int <= clk50MHz;
               PROCESS(clk50MHz_int)
               BEGIN

designs/LFR-EQM-WFP_MS/Makefile +1 -1

             #SIMTOP=testbench
             PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
             SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
-            SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
+            SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route_ALTRAN.sdc
             BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
             CLEAN=soft-clean

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