| @@ -181,7 +181,7 BEGIN -- beh | |||
|
|
181 | 181 | ----------------------------------------------------------------------------- |
|
|
182 | 182 | -- CLK_LOCK |
|
|
183 | 183 | ----------------------------------------------------------------------------- |
|
|
184 | rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); | |
|
|
184 | rst_gen_global : rstgen PORT MAP (reset, clk50MHz_int, '1', rstn_50, OPEN); | |
|
|
185 | 185 | |
|
|
186 | 186 | PROCESS (clk50MHz_int, rstn_50) |
|
|
187 | 187 | BEGIN -- PROCESS |
| @@ -207,8 +207,8 BEGIN -- beh | |||
|
|
207 | 207 | rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); |
|
|
208 | 208 | rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); |
|
|
209 | 209 | |
|
|
210 |
|
|
|
|
211 |
|
|
|
|
210 | clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); | |
|
|
211 | --clk50MHz_int <= clk50MHz; | |
|
|
212 | 212 | |
|
|
213 | 213 | PROCESS(clk50MHz_int) |
|
|
214 | 214 | BEGIN |
| @@ -18,7 +18,7 VHDLSIMFILES=testbench.vhd | |||
|
|
18 | 18 | #SIMTOP=testbench |
|
|
19 | 19 | PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc |
|
|
20 | 20 | SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc |
|
|
21 | SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc | |
|
|
21 | SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route_ALTRAN.sdc | |
|
|
22 | 22 | |
|
|
23 | 23 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut |
|
|
24 | 24 | CLEAN=soft-clean |
General Comments 0
You need to be logged in to leave comments.
Login now