# HG changeset patch # User pellion # Date 2015-04-30 09:47:15 # Node ID 7b23905bc9f6f7a1d4e9b16e9b688f06ba6d79e1 # Parent e0250657227b8f59310d93b814530abfbfb01d5c temp diff --git a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd --- a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +++ b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd @@ -181,7 +181,7 @@ BEGIN -- beh ----------------------------------------------------------------------------- -- CLK_LOCK ----------------------------------------------------------------------------- - rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); + rst_gen_global : rstgen PORT MAP (reset, clk50MHz_int, '1', rstn_50, OPEN); PROCESS (clk50MHz_int, rstn_50) BEGIN -- PROCESS @@ -207,8 +207,8 @@ BEGIN -- beh rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); - --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); - clk50MHz_int <= clk50MHz; + clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); + --clk50MHz_int <= clk50MHz; PROCESS(clk50MHz_int) BEGIN diff --git a/designs/LFR-EQM-WFP_MS/Makefile b/designs/LFR-EQM-WFP_MS/Makefile --- a/designs/LFR-EQM-WFP_MS/Makefile +++ b/designs/LFR-EQM-WFP_MS/Makefile @@ -18,7 +18,7 @@ VHDLSIMFILES=testbench.vhd #SIMTOP=testbench PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc -SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc +SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route_ALTRAN.sdc BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut CLEAN=soft-clean