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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 --library proasic3l;
48 --library proasic3l;
49 --use proasic3l.all;
49 --use proasic3l.all;
50
50
51 ENTITY LFR_EQM IS
51 ENTITY LFR_EQM IS
52 --GENERIC (
52 --GENERIC (
53 -- Mem_use : INTEGER := use_RAM);
53 -- Mem_use : INTEGER := use_RAM);
54
54
55 PORT (
55 PORT (
56 clk50MHz : IN STD_ULOGIC;
56 clk50MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
59
59
60 -- TAG --------------------------------------------------------------------
60 -- TAG --------------------------------------------------------------------
61 TAG1 : IN STD_ULOGIC; -- DSU rx data
61 TAG1 : IN STD_ULOGIC; -- DSU rx data
62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
63 -- UART APB ---------------------------------------------------------------
63 -- UART APB ---------------------------------------------------------------
64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
66 -- RAM --------------------------------------------------------------------
66 -- RAM --------------------------------------------------------------------
67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69
69
70 nSRAM_MBE : INOUT STD_LOGIC; -- new
70 nSRAM_MBE : INOUT STD_LOGIC; -- new
71 nSRAM_E1 : OUT STD_LOGIC; -- new
71 nSRAM_E1 : OUT STD_LOGIC; -- new
72 nSRAM_E2 : OUT STD_LOGIC; -- new
72 nSRAM_E2 : OUT STD_LOGIC; -- new
73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
74 nSRAM_W : OUT STD_LOGIC; -- new
74 nSRAM_W : OUT STD_LOGIC; -- new
75 nSRAM_G : OUT STD_LOGIC; -- new
75 nSRAM_G : OUT STD_LOGIC; -- new
76 nSRAM_BUSY : IN STD_LOGIC; -- new
76 nSRAM_BUSY : IN STD_LOGIC; -- new
77 -- SPW --------------------------------------------------------------------
77 -- SPW --------------------------------------------------------------------
78 spw1_en : OUT STD_LOGIC; -- new
78 spw1_en : OUT STD_LOGIC; -- new
79 spw1_din : IN STD_LOGIC;
79 spw1_din : IN STD_LOGIC;
80 spw1_sin : IN STD_LOGIC;
80 spw1_sin : IN STD_LOGIC;
81 spw1_dout : OUT STD_LOGIC;
81 spw1_dout : OUT STD_LOGIC;
82 spw1_sout : OUT STD_LOGIC;
82 spw1_sout : OUT STD_LOGIC;
83 spw2_en : OUT STD_LOGIC; -- new
83 spw2_en : OUT STD_LOGIC; -- new
84 spw2_din : IN STD_LOGIC;
84 spw2_din : IN STD_LOGIC;
85 spw2_sin : IN STD_LOGIC;
85 spw2_sin : IN STD_LOGIC;
86 spw2_dout : OUT STD_LOGIC;
86 spw2_dout : OUT STD_LOGIC;
87 spw2_sout : OUT STD_LOGIC;
87 spw2_sout : OUT STD_LOGIC;
88 -- ADC --------------------------------------------------------------------
88 -- ADC --------------------------------------------------------------------
89 bias_fail_sw : OUT STD_LOGIC;
89 bias_fail_sw : OUT STD_LOGIC;
90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
91 ADC_smpclk : OUT STD_LOGIC;
91 ADC_smpclk : OUT STD_LOGIC;
92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
93 -- DAC --------------------------------------------------------------------
93 -- DAC --------------------------------------------------------------------
94 DAC_SDO : OUT STD_LOGIC;
94 DAC_SDO : OUT STD_LOGIC;
95 DAC_SCK : OUT STD_LOGIC;
95 DAC_SCK : OUT STD_LOGIC;
96 DAC_SYNC : OUT STD_LOGIC;
96 DAC_SYNC : OUT STD_LOGIC;
97 DAC_CAL_EN : OUT STD_LOGIC;
97 DAC_CAL_EN : OUT STD_LOGIC;
98 -- HK ---------------------------------------------------------------------
98 -- HK ---------------------------------------------------------------------
99 HK_smpclk : OUT STD_LOGIC;
99 HK_smpclk : OUT STD_LOGIC;
100 ADC_OEB_bar_HK : OUT STD_LOGIC;
100 ADC_OEB_bar_HK : OUT STD_LOGIC;
101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 ---------------------------------------------------------------------------
102 ---------------------------------------------------------------------------
103 TAG8 : OUT STD_LOGIC
103 TAG8 : OUT STD_LOGIC
104 );
104 );
105
105
106 END LFR_EQM;
106 END LFR_EQM;
107
107
108
108
109 ARCHITECTURE beh OF LFR_EQM IS
109 ARCHITECTURE beh OF LFR_EQM IS
110
110
111 SIGNAL clk_25 : STD_LOGIC := '0';
111 SIGNAL clk_25 : STD_LOGIC := '0';
112 SIGNAL clk_24 : STD_LOGIC := '0';
112 SIGNAL clk_24 : STD_LOGIC := '0';
113 -----------------------------------------------------------------------------
113 -----------------------------------------------------------------------------
114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
116
116
117 -- CONSTANTS
117 -- CONSTANTS
118 CONSTANT CFG_PADTECH : INTEGER := inferred;
118 CONSTANT CFG_PADTECH : INTEGER := inferred;
119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
121 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
121 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
122
122
123 SIGNAL apbi_ext : apb_slv_in_type;
123 SIGNAL apbi_ext : apb_slv_in_type;
124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
129
129
130 -- Spacewire signals
130 -- Spacewire signals
131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 SIGNAL spw_rxtxclk : STD_ULOGIC;
134 SIGNAL spw_rxtxclk : STD_ULOGIC;
135 SIGNAL spw_rxclkn : STD_ULOGIC;
135 SIGNAL spw_rxclkn : STD_ULOGIC;
136 SIGNAL spw_clk : STD_LOGIC;
136 SIGNAL spw_clk : STD_LOGIC;
137 SIGNAL swni : grspw_in_type;
137 SIGNAL swni : grspw_in_type;
138 SIGNAL swno : grspw_out_type;
138 SIGNAL swno : grspw_out_type;
139
139
140 --GPIO
140 --GPIO
141 SIGNAL gpioi : gpio_in_type;
141 SIGNAL gpioi : gpio_in_type;
142 SIGNAL gpioo : gpio_out_type;
142 SIGNAL gpioo : gpio_out_type;
143
143
144 -- AD Converter ADS7886
144 -- AD Converter ADS7886
145 SIGNAL sample : Samples14v(8 DOWNTO 0);
145 SIGNAL sample : Samples14v(8 DOWNTO 0);
146 SIGNAL sample_s : Samples(8 DOWNTO 0);
146 SIGNAL sample_s : Samples(8 DOWNTO 0);
147 SIGNAL sample_val : STD_LOGIC;
147 SIGNAL sample_val : STD_LOGIC;
148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
149
149
150 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
152
152
153 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
154 SIGNAL rstn_25 : STD_LOGIC;
154 SIGNAL rstn_25 : STD_LOGIC;
155 SIGNAL rstn_24 : STD_LOGIC;
155 SIGNAL rstn_24 : STD_LOGIC;
156
156
157 SIGNAL LFR_soft_rstn : STD_LOGIC;
157 SIGNAL LFR_soft_rstn : STD_LOGIC;
158 SIGNAL LFR_rstn : STD_LOGIC;
158 SIGNAL LFR_rstn : STD_LOGIC;
159
159
160 SIGNAL ADC_smpclk_s : STD_LOGIC;
160 SIGNAL ADC_smpclk_s : STD_LOGIC;
161
161
162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
163
163
164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
165 SIGNAL clk_25_int : STD_LOGIC := '0';
165 SIGNAL clk_25_int : STD_LOGIC := '0';
166
166
167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
168
168
169 SIGNAL rstn_50 : STD_LOGIC;
169 SIGNAL rstn_50 : STD_LOGIC;
170 SIGNAL clk_lock : STD_LOGIC;
170 SIGNAL clk_lock : STD_LOGIC;
171 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
172 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
173
173
174 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
174 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL ahbrxd: STD_LOGIC;
175 SIGNAL ahbrxd: STD_LOGIC;
176 SIGNAL ahbtxd: STD_LOGIC;
176 SIGNAL ahbtxd: STD_LOGIC;
177 SIGNAL urxd1 : STD_LOGIC;
177 SIGNAL urxd1 : STD_LOGIC;
178 SIGNAL utxd1 : STD_LOGIC;
178 SIGNAL utxd1 : STD_LOGIC;
179 BEGIN -- beh
179 BEGIN -- beh
180
180
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- CLK_LOCK
182 -- CLK_LOCK
183 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
184 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
184 rst_gen_global : rstgen PORT MAP (reset, clk50MHz_int, '1', rstn_50, OPEN);
185
185
186 PROCESS (clk50MHz_int, rstn_50)
186 PROCESS (clk50MHz_int, rstn_50)
187 BEGIN -- PROCESS
187 BEGIN -- PROCESS
188 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
188 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
189 clk_lock <= '0';
189 clk_lock <= '0';
190 clk_busy_counter <= (OTHERS => '0');
190 clk_busy_counter <= (OTHERS => '0');
191 nSRAM_BUSY_reg <= '0';
191 nSRAM_BUSY_reg <= '0';
192 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
192 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
193 nSRAM_BUSY_reg <= nSRAM_BUSY;
193 nSRAM_BUSY_reg <= nSRAM_BUSY;
194 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
194 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
195 IF clk_busy_counter = "1111" THEN
195 IF clk_busy_counter = "1111" THEN
196 clk_lock <= '1';
196 clk_lock <= '1';
197 ELSE
197 ELSE
198 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
198 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
199 END IF;
199 END IF;
200 END IF;
200 END IF;
201 END IF;
201 END IF;
202 END PROCESS;
202 END PROCESS;
203
203
204 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
205 -- CLK
205 -- CLK
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
207 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
208 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
208 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
209
209
210 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
210 clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
211 clk50MHz_int <= clk50MHz;
211 --clk50MHz_int <= clk50MHz;
212
212
213 PROCESS(clk50MHz_int)
213 PROCESS(clk50MHz_int)
214 BEGIN
214 BEGIN
215 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
215 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
216 --clk_25_int <= NOT clk_25_int;
216 --clk_25_int <= NOT clk_25_int;
217 clk_25 <= NOT clk_25;
217 clk_25 <= NOT clk_25;
218 END IF;
218 END IF;
219 END PROCESS;
219 END PROCESS;
220 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
220 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
221
221
222 PROCESS(clk49_152MHz)
222 PROCESS(clk49_152MHz)
223 BEGIN
223 BEGIN
224 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
224 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
225 clk_24 <= NOT clk_24;
225 clk_24 <= NOT clk_24;
226 END IF;
226 END IF;
227 END PROCESS;
227 END PROCESS;
228
228
229 -----------------------------------------------------------------------------
229 -----------------------------------------------------------------------------
230 --
230 --
231 leon3_soc_1 : leon3_soc
231 leon3_soc_1 : leon3_soc
232 GENERIC MAP (
232 GENERIC MAP (
233 fabtech => apa3l,
233 fabtech => apa3l,
234 memtech => apa3l,
234 memtech => apa3l,
235 padtech => inferred,
235 padtech => inferred,
236 clktech => inferred,
236 clktech => inferred,
237 disas => 0,
237 disas => 0,
238 dbguart => 0,
238 dbguart => 0,
239 pclow => 2,
239 pclow => 2,
240 clk_freq => 25000,
240 clk_freq => 25000,
241 IS_RADHARD => 0,
241 IS_RADHARD => 0,
242 NB_CPU => 1,
242 NB_CPU => 1,
243 ENABLE_FPU => 1,
243 ENABLE_FPU => 1,
244 FPU_NETLIST => 0,
244 FPU_NETLIST => 0,
245 ENABLE_DSU => 1,
245 ENABLE_DSU => 1,
246 ENABLE_AHB_UART => 1,
246 ENABLE_AHB_UART => 1,
247 ENABLE_APB_UART => 1,
247 ENABLE_APB_UART => 1,
248 ENABLE_IRQMP => 1,
248 ENABLE_IRQMP => 1,
249 ENABLE_GPT => 1,
249 ENABLE_GPT => 1,
250 NB_AHB_MASTER => NB_AHB_MASTER,
250 NB_AHB_MASTER => NB_AHB_MASTER,
251 NB_AHB_SLAVE => NB_AHB_SLAVE,
251 NB_AHB_SLAVE => NB_AHB_SLAVE,
252 NB_APB_SLAVE => NB_APB_SLAVE,
252 NB_APB_SLAVE => NB_APB_SLAVE,
253 ADDRESS_SIZE => 19,
253 ADDRESS_SIZE => 19,
254 USES_IAP_MEMCTRLR => 1,
254 USES_IAP_MEMCTRLR => 1,
255 BYPASS_EDAC_MEMCTRLR => '0',
255 BYPASS_EDAC_MEMCTRLR => '0',
256 SRBANKSZ => 8)
256 SRBANKSZ => 8)
257 PORT MAP (
257 PORT MAP (
258 clk => clk_25,
258 clk => clk_25,
259 reset => rstn_25,
259 reset => rstn_25,
260 errorn => OPEN,
260 errorn => OPEN,
261
261
262 ahbrxd => TAG1,
262 ahbrxd => TAG1,
263 ahbtxd => TAG3,
263 ahbtxd => TAG3,
264 urxd1 => TAG2,
264 urxd1 => TAG2,
265 utxd1 => TAG4,
265 utxd1 => TAG4,
266
266
267 address => address,
267 address => address,
268 data => data,
268 data => data,
269 nSRAM_BE0 => OPEN,
269 nSRAM_BE0 => OPEN,
270 nSRAM_BE1 => OPEN,
270 nSRAM_BE1 => OPEN,
271 nSRAM_BE2 => OPEN,
271 nSRAM_BE2 => OPEN,
272 nSRAM_BE3 => OPEN,
272 nSRAM_BE3 => OPEN,
273 nSRAM_WE => nSRAM_W,
273 nSRAM_WE => nSRAM_W,
274 nSRAM_CE => nSRAM_CE,
274 nSRAM_CE => nSRAM_CE,
275 nSRAM_OE => nSRAM_G,
275 nSRAM_OE => nSRAM_G,
276 nSRAM_READY => nSRAM_BUSY,
276 nSRAM_READY => nSRAM_BUSY,
277 SRAM_MBE => nSRAM_MBE,
277 SRAM_MBE => nSRAM_MBE,
278
278
279 apbi_ext => apbi_ext,
279 apbi_ext => apbi_ext,
280 apbo_ext => apbo_ext,
280 apbo_ext => apbo_ext,
281 ahbi_s_ext => ahbi_s_ext,
281 ahbi_s_ext => ahbi_s_ext,
282 ahbo_s_ext => ahbo_s_ext,
282 ahbo_s_ext => ahbo_s_ext,
283 ahbi_m_ext => ahbi_m_ext,
283 ahbi_m_ext => ahbi_m_ext,
284 ahbo_m_ext => ahbo_m_ext);
284 ahbo_m_ext => ahbo_m_ext);
285
285
286
286
287 nSRAM_E1 <= nSRAM_CE(0);
287 nSRAM_E1 <= nSRAM_CE(0);
288 nSRAM_E2 <= nSRAM_CE(1);
288 nSRAM_E2 <= nSRAM_CE(1);
289
289
290 -------------------------------------------------------------------------------
290 -------------------------------------------------------------------------------
291 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
291 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
292 -------------------------------------------------------------------------------
292 -------------------------------------------------------------------------------
293 apb_lfr_management_1 : apb_lfr_management
293 apb_lfr_management_1 : apb_lfr_management
294 GENERIC MAP (
294 GENERIC MAP (
295 tech => apa3l,
295 tech => apa3l,
296 pindex => 6,
296 pindex => 6,
297 paddr => 6,
297 paddr => 6,
298 pmask => 16#fff#,
298 pmask => 16#fff#,
299 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
299 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
300 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
300 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
301 PORT MAP (
301 PORT MAP (
302 clk25MHz => clk_25,
302 clk25MHz => clk_25,
303 resetn_25MHz => rstn_25, -- TODO
303 resetn_25MHz => rstn_25, -- TODO
304 --clk24_576MHz => clk_24, -- 49.152MHz/2
304 --clk24_576MHz => clk_24, -- 49.152MHz/2
305 --resetn_24_576MHz => rstn_24, -- TODO
305 --resetn_24_576MHz => rstn_24, -- TODO
306
306
307 grspw_tick => swno.tickout,
307 grspw_tick => swno.tickout,
308 apbi => apbi_ext,
308 apbi => apbi_ext,
309 apbo => apbo_ext(6),
309 apbo => apbo_ext(6),
310
310
311 HK_sample => sample_s(8),
311 HK_sample => sample_s(8),
312 HK_val => sample_val,
312 HK_val => sample_val,
313 HK_sel => HK_SEL,
313 HK_sel => HK_SEL,
314
314
315 DAC_SDO => DAC_SDO,
315 DAC_SDO => DAC_SDO,
316 DAC_SCK => DAC_SCK,
316 DAC_SCK => DAC_SCK,
317 DAC_SYNC => DAC_SYNC,
317 DAC_SYNC => DAC_SYNC,
318 DAC_CAL_EN => DAC_CAL_EN,
318 DAC_CAL_EN => DAC_CAL_EN,
319
319
320 coarse_time => coarse_time,
320 coarse_time => coarse_time,
321 fine_time => fine_time,
321 fine_time => fine_time,
322 LFR_soft_rstn => LFR_soft_rstn
322 LFR_soft_rstn => LFR_soft_rstn
323 );
323 );
324
324
325 -----------------------------------------------------------------------
325 -----------------------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
327 -----------------------------------------------------------------------
327 -----------------------------------------------------------------------
328
328
329 ------------------------------------------------------------------------------
329 ------------------------------------------------------------------------------
330 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
330 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
331 ------------------------------------------------------------------------------
331 ------------------------------------------------------------------------------
332 spw1_en <= '1';
332 spw1_en <= '1';
333 spw2_en <= '1';
333 spw2_en <= '1';
334 ------------------------------------------------------------------------------
334 ------------------------------------------------------------------------------
335 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
335 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
336 ------------------------------------------------------------------------------
336 ------------------------------------------------------------------------------
337
337
338 --spw_clk <= clk50MHz;
338 --spw_clk <= clk50MHz;
339 --spw_rxtxclk <= spw_clk;
339 --spw_rxtxclk <= spw_clk;
340 --spw_rxclkn <= NOT spw_rxtxclk;
340 --spw_rxclkn <= NOT spw_rxtxclk;
341
341
342 -- PADS for SPW1
342 -- PADS for SPW1
343 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
343 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
344 PORT MAP (spw1_din, dtmp(0));
344 PORT MAP (spw1_din, dtmp(0));
345 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
345 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
346 PORT MAP (spw1_sin, stmp(0));
346 PORT MAP (spw1_sin, stmp(0));
347 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
347 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
348 PORT MAP (spw1_dout, swno.d(0));
348 PORT MAP (spw1_dout, swno.d(0));
349 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
349 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
350 PORT MAP (spw1_sout, swno.s(0));
350 PORT MAP (spw1_sout, swno.s(0));
351 -- PADS FOR SPW2
351 -- PADS FOR SPW2
352 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
352 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
353 PORT MAP (spw2_din, dtmp(1));
353 PORT MAP (spw2_din, dtmp(1));
354 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
354 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
355 PORT MAP (spw2_sin, stmp(1));
355 PORT MAP (spw2_sin, stmp(1));
356 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
356 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
357 PORT MAP (spw2_dout, swno.d(1));
357 PORT MAP (spw2_dout, swno.d(1));
358 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
358 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
359 PORT MAP (spw2_sout, swno.s(1));
359 PORT MAP (spw2_sout, swno.s(1));
360
360
361 -- GRSPW PHY
361 -- GRSPW PHY
362 --spw1_input: if CFG_SPW_GRSPW = 1 generate
362 --spw1_input: if CFG_SPW_GRSPW = 1 generate
363 spw_inputloop : FOR j IN 0 TO 1 GENERATE
363 spw_inputloop : FOR j IN 0 TO 1 GENERATE
364 spw_phy0 : grspw_phy
364 spw_phy0 : grspw_phy
365 GENERIC MAP(
365 GENERIC MAP(
366 tech => apa3l,
366 tech => apa3l,
367 rxclkbuftype => 1,
367 rxclkbuftype => 1,
368 scantest => 0)
368 scantest => 0)
369 PORT MAP(
369 PORT MAP(
370 rxrst => swno.rxrst,
370 rxrst => swno.rxrst,
371 di => dtmp(j),
371 di => dtmp(j),
372 si => stmp(j),
372 si => stmp(j),
373 rxclko => spw_rxclk(j),
373 rxclko => spw_rxclk(j),
374 do => swni.d(j),
374 do => swni.d(j),
375 ndo => swni.nd(j*5+4 DOWNTO j*5),
375 ndo => swni.nd(j*5+4 DOWNTO j*5),
376 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
376 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
377 END GENERATE spw_inputloop;
377 END GENERATE spw_inputloop;
378
378
379 -- SPW core
379 -- SPW core
380 sw0 : grspwm GENERIC MAP(
380 sw0 : grspwm GENERIC MAP(
381 tech => apa3l,
381 tech => apa3l,
382 hindex => 1,
382 hindex => 1,
383 pindex => 5,
383 pindex => 5,
384 paddr => 5,
384 paddr => 5,
385 pirq => 11,
385 pirq => 11,
386 sysfreq => 25000, -- CPU_FREQ
386 sysfreq => 25000, -- CPU_FREQ
387 rmap => 1,
387 rmap => 1,
388 rmapcrc => 1,
388 rmapcrc => 1,
389 fifosize1 => 16,
389 fifosize1 => 16,
390 fifosize2 => 16,
390 fifosize2 => 16,
391 rxclkbuftype => 1,
391 rxclkbuftype => 1,
392 rxunaligned => 0,
392 rxunaligned => 0,
393 rmapbufs => 4,
393 rmapbufs => 4,
394 ft => 0,
394 ft => 0,
395 netlist => 0,
395 netlist => 0,
396 ports => 2,
396 ports => 2,
397 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
397 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
398 memtech => apa3l,
398 memtech => apa3l,
399 destkey => 2,
399 destkey => 2,
400 spwcore => 1
400 spwcore => 1
401 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
401 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
402 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
402 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
403 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
403 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
404 )
404 )
405 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
405 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
406 spw_rxclk(1),
406 spw_rxclk(1),
407 clk50MHz_int,
407 clk50MHz_int,
408 clk50MHz_int,
408 clk50MHz_int,
409 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
409 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
410 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
410 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
411 swni, swno);
411 swni, swno);
412
412
413 swni.tickin <= '0';
413 swni.tickin <= '0';
414 swni.rmapen <= '1';
414 swni.rmapen <= '1';
415 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
415 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
416 swni.tickinraw <= '0';
416 swni.tickinraw <= '0';
417 swni.timein <= (OTHERS => '0');
417 swni.timein <= (OTHERS => '0');
418 swni.dcrstval <= (OTHERS => '0');
418 swni.dcrstval <= (OTHERS => '0');
419 swni.timerrstval <= (OTHERS => '0');
419 swni.timerrstval <= (OTHERS => '0');
420
420
421 -------------------------------------------------------------------------------
421 -------------------------------------------------------------------------------
422 -- LFR ------------------------------------------------------------------------
422 -- LFR ------------------------------------------------------------------------
423 -------------------------------------------------------------------------------
423 -------------------------------------------------------------------------------
424 LFR_rstn <= LFR_soft_rstn AND rstn_25;
424 LFR_rstn <= LFR_soft_rstn AND rstn_25;
425
425
426 lpp_lfr_1 : lpp_lfr
426 lpp_lfr_1 : lpp_lfr
427 GENERIC MAP (
427 GENERIC MAP (
428 Mem_use => use_RAM,
428 Mem_use => use_RAM,
429 nb_data_by_buffer_size => 32,
429 nb_data_by_buffer_size => 32,
430 --nb_word_by_buffer_size => 30,
430 --nb_word_by_buffer_size => 30,
431 nb_snapshot_param_size => 32,
431 nb_snapshot_param_size => 32,
432 delta_vector_size => 32,
432 delta_vector_size => 32,
433 delta_vector_size_f0_2 => 7, -- log2(96)
433 delta_vector_size_f0_2 => 7, -- log2(96)
434 pindex => 15,
434 pindex => 15,
435 paddr => 15,
435 paddr => 15,
436 pmask => 16#fff#,
436 pmask => 16#fff#,
437 pirq_ms => 6,
437 pirq_ms => 6,
438 pirq_wfp => 14,
438 pirq_wfp => 14,
439 hindex => 2,
439 hindex => 2,
440 top_lfr_version => X"020146") -- aa.bb.cc version
440 top_lfr_version => X"020146") -- aa.bb.cc version
441 -- AA : BOARD NUMBER
441 -- AA : BOARD NUMBER
442 -- 0 => MINI_LFR
442 -- 0 => MINI_LFR
443 -- 1 => EM
443 -- 1 => EM
444 -- 2 => EQM (with A3PE3000)
444 -- 2 => EQM (with A3PE3000)
445 PORT MAP (
445 PORT MAP (
446 clk => clk_25,
446 clk => clk_25,
447 rstn => LFR_rstn,
447 rstn => LFR_rstn,
448 sample_B => sample_s(2 DOWNTO 0),
448 sample_B => sample_s(2 DOWNTO 0),
449 sample_E => sample_s(7 DOWNTO 3),
449 sample_E => sample_s(7 DOWNTO 3),
450 sample_val => sample_val,
450 sample_val => sample_val,
451 apbi => apbi_ext,
451 apbi => apbi_ext,
452 apbo => apbo_ext(15),
452 apbo => apbo_ext(15),
453 ahbi => ahbi_m_ext,
453 ahbi => ahbi_m_ext,
454 ahbo => ahbo_m_ext(2),
454 ahbo => ahbo_m_ext(2),
455 coarse_time => coarse_time,
455 coarse_time => coarse_time,
456 fine_time => fine_time,
456 fine_time => fine_time,
457 data_shaping_BW => bias_fail_sw,
457 data_shaping_BW => bias_fail_sw,
458 debug_vector => OPEN,
458 debug_vector => OPEN,
459 debug_vector_ms => OPEN); --,
459 debug_vector_ms => OPEN); --,
460 --observation_vector_0 => OPEN,
460 --observation_vector_0 => OPEN,
461 --observation_vector_1 => OPEN,
461 --observation_vector_1 => OPEN,
462 --observation_reg => observation_reg);
462 --observation_reg => observation_reg);
463
463
464
464
465 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
465 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
466 sample_s(I) <= sample(I) & '0' & '0';
466 sample_s(I) <= sample(I) & '0' & '0';
467 END GENERATE all_sample;
467 END GENERATE all_sample;
468 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
468 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
469
469
470 -----------------------------------------------------------------------------
470 -----------------------------------------------------------------------------
471 --
471 --
472 -----------------------------------------------------------------------------
472 -----------------------------------------------------------------------------
473 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
473 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
474 GENERIC MAP (
474 GENERIC MAP (
475 ChanelCount => 9,
475 ChanelCount => 9,
476 ncycle_cnv_high => 13,
476 ncycle_cnv_high => 13,
477 ncycle_cnv => 25,
477 ncycle_cnv => 25,
478 FILTER_ENABLED => 16#FF#)
478 FILTER_ENABLED => 16#FF#)
479 PORT MAP (
479 PORT MAP (
480 cnv_clk => clk_24,
480 cnv_clk => clk_24,
481 cnv_rstn => rstn_24,
481 cnv_rstn => rstn_24,
482 cnv => ADC_smpclk_s,
482 cnv => ADC_smpclk_s,
483 clk => clk_25,
483 clk => clk_25,
484 rstn => rstn_25,
484 rstn => rstn_25,
485 ADC_data => ADC_data,
485 ADC_data => ADC_data,
486 ADC_nOE => ADC_OEB_bar_CH_s,
486 ADC_nOE => ADC_OEB_bar_CH_s,
487 sample => sample,
487 sample => sample,
488 sample_val => sample_val);
488 sample_val => sample_val);
489
489
490 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
490 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
491
491
492 ADC_smpclk <= ADC_smpclk_s;
492 ADC_smpclk <= ADC_smpclk_s;
493 HK_smpclk <= ADC_smpclk_s;
493 HK_smpclk <= ADC_smpclk_s;
494
494
495 TAG8 <= nSRAM_BUSY;
495 TAG8 <= nSRAM_BUSY;
496
496
497 -----------------------------------------------------------------------------
497 -----------------------------------------------------------------------------
498 -- HK
498 -- HK
499 -----------------------------------------------------------------------------
499 -----------------------------------------------------------------------------
500 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
500 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
501
501
502 END beh;
502 END beh;
Show file before | Show file after | Hide comments
@@ -1,55 +1,55
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_EQM
5 TOP=LFR_EQM
6 BOARD=LFR-EQM
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-EQM.vhd
16 VHDLSYNFILES=LFR-EQM.vhd
17 VHDLSIMFILES=testbench.vhd
17 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
18 #SIMTOP=testbench
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
20 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
20 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
21 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
21 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route_ALTRAN.sdc
22
22
23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
24 CLEAN=soft-clean
24 CLEAN=soft-clean
25
25
26 TECHLIBS = proasic3l
26 TECHLIBS = proasic3l
27
27
28 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
28 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
29 tmtc openchip hynix ihp gleichmann micron usbhc
29 tmtc openchip hynix ihp gleichmann micron usbhc
30
30
31 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
31 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
32 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
32 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
33 ./amba_lcd_16x2_ctrlr \
33 ./amba_lcd_16x2_ctrlr \
34 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_AMR \
35 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_balise \
36 ./general_purpose/lpp_delay \
36 ./general_purpose/lpp_delay \
37 ./lpp_bootloader \
37 ./lpp_bootloader \
38 ./dsp/lpp_fft_rtax \
38 ./dsp/lpp_fft_rtax \
39 ./lpp_uart \
39 ./lpp_uart \
40 ./lpp_usb \
40 ./lpp_usb \
41 ./lpp_sim/CY7C1061DV33 \
41 ./lpp_sim/CY7C1061DV33 \
42
42
43 FILESKIP = i2cmst.vhd \
43 FILESKIP = i2cmst.vhd \
44 APB_MULTI_DIODE.vhd \
44 APB_MULTI_DIODE.vhd \
45 APB_MULTI_DIODE.vhd \
45 APB_MULTI_DIODE.vhd \
46 Top_MatrixSpec.vhd \
46 Top_MatrixSpec.vhd \
47 APB_FFT.vhd\
47 APB_FFT.vhd\
48 CoreFFT_simu.vhd \
48 CoreFFT_simu.vhd \
49 lpp_lfr_apbreg_simu.vhd
49 lpp_lfr_apbreg_simu.vhd
50
50
51 include $(GRLIB)/bin/Makefile
51 include $(GRLIB)/bin/Makefile
52 include $(GRLIB)/software/leon3/Makefile
52 include $(GRLIB)/software/leon3/Makefile
53
53
54 ################## project specific targets ##########################
54 ################## project specific targets ##########################
55
55
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