HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r685:17d0356c0267

Fixed top LFR-FM for simulation.

Jean-christophe Pellion -

r685:17d0356c0267 Simu-LFR-FM

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r685:17d0356c0267

designs/SOLO_LFR_LFR-FM/LFR-FM.vhd +4 -3

             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
+            library axcelerator;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             USE techmap.axcomp.ALL;
             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
-            --library proasic3l;
-            --use proasic3l.all;
             ENTITY LFR_FM IS
               GENERIC (
               SIGNAL clk50MHz_int : STD_LOGIC := '0';
-              component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
+              --component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
+              --component hclkint port(A : in std_ulogic; Y :out std_ulogic); end component;
               SIGNAL rstn_50 : STD_LOGIC;
               SIGNAL clk_lock : STD_LOGIC;

tests/Validation_LFR/tb.vhd +14 -2

             --    nSRAM_SCRUB    : OUT   STD_LOGIC;   -- new
                 SIGNAL nSRAM_W        :     STD_LOGIC;   -- new
                 SIGNAL nSRAM_G        :     STD_LOGIC;   -- new
-                SIGNAL nSRAM_BUSY     :     STD_LOGIC;   -- new
+                SIGNAL nSRAM_BUSY     :     STD_LOGIC := '1';   -- new
                 -- SPW --------------------------------------------------------------------
                 SIGNAL spw1_en        :     STD_LOGIC;   -- new
                 SIGNAL spw1_din       :     STD_LOGIC;
               -----------------------------------------------------------------------------
               --  SRAMS Same as EM, we don't have UT8ER1M32 models
               -----------------------------------------------------------------------------
-             nSRAM_BUSY  <= '1';  -- TODO emulate scrubbing
+              buy_gen: process
+              begin
+              IF end_of_simu /= '1' THEN
+                  nSRAM_BUSY <= '0';
+                  wait for 100 ns;
+                  nSRAM_BUSY <= '1';
+                  WAIT FOR 100 us;
+                ELSE
+                  WAIT FOR 10 ps;
+                  assert false report "end of test" severity note;
+                  WAIT;
+                END IF;
+              end process;
              nSRAM_CE <= not nSRAM_E1;

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