# HG changeset patch
# User Jean-christophe Pellion <jcpellion@gmail.com>
# Date 2017-01-05 14:24:10
# Node ID 17d0356c02678606b6bfc903af05cf0ce522e55b
# Parent  892a270271d893093d7488043b767c474f2ecfee

Fixed top LFR-FM for simulation.

diff --git a/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd b/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd
--- a/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd
+++ b/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd
@@ -25,6 +25,7 @@ USE IEEE.std_logic_1164.ALL;
 LIBRARY grlib;
 USE grlib.amba.ALL;
 USE grlib.stdlib.ALL;
+library axcelerator;
 LIBRARY techmap;
 USE techmap.gencomp.ALL;
 USE techmap.axcomp.ALL;
@@ -48,8 +49,7 @@ USE lpp.general_purpose.ALL;
 USE lpp.lpp_lfr_management.ALL;
 USE lpp.lpp_leon3_soc_pkg.ALL;
 
---library proasic3l;
---use proasic3l.all;
+
 
 ENTITY LFR_FM IS
   GENERIC (
@@ -170,7 +170,8 @@ ARCHITECTURE beh OF LFR_FM IS
   
   SIGNAL clk50MHz_int : STD_LOGIC := '0';
 
-  component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
+  --component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
+  --component hclkint port(A : in std_ulogic; Y :out std_ulogic); end component;
 
   SIGNAL rstn_50 : STD_LOGIC;
   SIGNAL clk_lock : STD_LOGIC;
diff --git a/tests/Validation_LFR/tb.vhd b/tests/Validation_LFR/tb.vhd
--- a/tests/Validation_LFR/tb.vhd
+++ b/tests/Validation_LFR/tb.vhd
@@ -55,7 +55,7 @@ ARCHITECTURE behav OF testbench IS
 --    nSRAM_SCRUB    : OUT   STD_LOGIC;   -- new
     SIGNAL nSRAM_W        :     STD_LOGIC;   -- new
     SIGNAL nSRAM_G        :     STD_LOGIC;   -- new
-    SIGNAL nSRAM_BUSY     :     STD_LOGIC;   -- new
+    SIGNAL nSRAM_BUSY     :     STD_LOGIC := '1';   -- new
     -- SPW --------------------------------------------------------------------
     SIGNAL spw1_en        :     STD_LOGIC;   -- new
     SIGNAL spw1_din       :     STD_LOGIC;
@@ -293,7 +293,19 @@ spw2_sin <= '1';
   -----------------------------------------------------------------------------
   --  SRAMS Same as EM, we don't have UT8ER1M32 models
   -----------------------------------------------------------------------------
- nSRAM_BUSY  <= '1';  -- TODO emulate scrubbing
+  buy_gen: process
+  begin
+  IF end_of_simu /= '1' THEN
+      nSRAM_BUSY <= '0';
+      wait for 100 ns;
+      nSRAM_BUSY <= '1';
+      WAIT FOR 100 us;
+    ELSE
+      WAIT FOR 10 ps;
+      assert false report "end of test" severity note;
+      WAIT;
+    END IF;
+  end process;
 
  nSRAM_CE <= not nSRAM_E1;