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Fixed top LFR-FM for simulation.
Jean-christophe Pellion -
r685:17d0356c0267 Simu-LFR-FM draft
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 library axcelerator;
28 LIBRARY techmap;
29 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 USE techmap.gencomp.ALL;
30 USE techmap.axcomp.ALL;
31 USE techmap.axcomp.ALL;
31
32
32 LIBRARY gaisler;
33 LIBRARY gaisler;
33 USE gaisler.sim.ALL;
34 USE gaisler.sim.ALL;
34 USE gaisler.memctrl.ALL;
35 USE gaisler.memctrl.ALL;
35 USE gaisler.leon3.ALL;
36 USE gaisler.leon3.ALL;
36 USE gaisler.uart.ALL;
37 USE gaisler.uart.ALL;
37 USE gaisler.misc.ALL;
38 USE gaisler.misc.ALL;
38 USE gaisler.spacewire.ALL;
39 USE gaisler.spacewire.ALL;
39 LIBRARY esa;
40 LIBRARY esa;
40 USE esa.memoryctrl.ALL;
41 USE esa.memoryctrl.ALL;
41 LIBRARY lpp;
42 LIBRARY lpp;
42 USE lpp.lpp_memory.ALL;
43 USE lpp.lpp_memory.ALL;
43 USE lpp.lpp_ad_conv.ALL;
44 USE lpp.lpp_ad_conv.ALL;
44 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
45 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
45 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
46 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
46 USE lpp.iir_filter.ALL;
47 USE lpp.iir_filter.ALL;
47 USE lpp.general_purpose.ALL;
48 USE lpp.general_purpose.ALL;
48 USE lpp.lpp_lfr_management.ALL;
49 USE lpp.lpp_lfr_management.ALL;
49 USE lpp.lpp_leon3_soc_pkg.ALL;
50 USE lpp.lpp_leon3_soc_pkg.ALL;
50
51
51 --library proasic3l;
52
52 --use proasic3l.all;
53
53
54 ENTITY LFR_FM IS
54 ENTITY LFR_FM IS
55 GENERIC (
55 GENERIC (
56 Mem_use : INTEGER := use_RAM;
56 Mem_use : INTEGER := use_RAM;
57 USE_BOOTLOADER : INTEGER := 0;
57 USE_BOOTLOADER : INTEGER := 0;
58 USE_ADCDRIVER : INTEGER := 1;
58 USE_ADCDRIVER : INTEGER := 1;
59 tech : INTEGER := inferred;
59 tech : INTEGER := inferred;
60 tech_leon : INTEGER := inferred;
60 tech_leon : INTEGER := inferred;
61 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
61 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
62 USE_DEBUG_VECTOR : INTEGER := 0
62 USE_DEBUG_VECTOR : INTEGER := 0
63 );
63 );
64
64
65 PORT (
65 PORT (
66 clk50MHz : IN STD_ULOGIC;
66 clk50MHz : IN STD_ULOGIC;
67 clk49_152MHz : IN STD_ULOGIC;
67 clk49_152MHz : IN STD_ULOGIC;
68 reset : IN STD_ULOGIC;
68 reset : IN STD_ULOGIC;
69
69
70 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
70 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
71
71
72 -- TAG --------------------------------------------------------------------
72 -- TAG --------------------------------------------------------------------
73 --TAG1 : IN STD_ULOGIC; -- DSU rx data
73 --TAG1 : IN STD_ULOGIC; -- DSU rx data
74 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
74 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
75 -- UART APB ---------------------------------------------------------------
75 -- UART APB ---------------------------------------------------------------
76 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
76 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
77 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
77 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
78 -- RAM --------------------------------------------------------------------
78 -- RAM --------------------------------------------------------------------
79 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
79 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
80 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81
81
82 nSRAM_MBE : INOUT STD_LOGIC; -- new
82 nSRAM_MBE : INOUT STD_LOGIC; -- new
83 nSRAM_E1 : OUT STD_LOGIC; -- new
83 nSRAM_E1 : OUT STD_LOGIC; -- new
84 nSRAM_E2 : OUT STD_LOGIC; -- new
84 nSRAM_E2 : OUT STD_LOGIC; -- new
85 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
85 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
86 nSRAM_W : OUT STD_LOGIC; -- new
86 nSRAM_W : OUT STD_LOGIC; -- new
87 nSRAM_G : OUT STD_LOGIC; -- new
87 nSRAM_G : OUT STD_LOGIC; -- new
88 nSRAM_BUSY : IN STD_LOGIC; -- new
88 nSRAM_BUSY : IN STD_LOGIC; -- new
89 -- SPW --------------------------------------------------------------------
89 -- SPW --------------------------------------------------------------------
90 spw1_en : OUT STD_LOGIC; -- new
90 spw1_en : OUT STD_LOGIC; -- new
91 spw1_din : IN STD_LOGIC;
91 spw1_din : IN STD_LOGIC;
92 spw1_sin : IN STD_LOGIC;
92 spw1_sin : IN STD_LOGIC;
93 spw1_dout : OUT STD_LOGIC;
93 spw1_dout : OUT STD_LOGIC;
94 spw1_sout : OUT STD_LOGIC;
94 spw1_sout : OUT STD_LOGIC;
95 spw2_en : OUT STD_LOGIC; -- new
95 spw2_en : OUT STD_LOGIC; -- new
96 spw2_din : IN STD_LOGIC;
96 spw2_din : IN STD_LOGIC;
97 spw2_sin : IN STD_LOGIC;
97 spw2_sin : IN STD_LOGIC;
98 spw2_dout : OUT STD_LOGIC;
98 spw2_dout : OUT STD_LOGIC;
99 spw2_sout : OUT STD_LOGIC;
99 spw2_sout : OUT STD_LOGIC;
100 -- ADC --------------------------------------------------------------------
100 -- ADC --------------------------------------------------------------------
101 bias_fail_sw : OUT STD_LOGIC;
101 bias_fail_sw : OUT STD_LOGIC;
102 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
102 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
103 ADC_smpclk : OUT STD_LOGIC;
103 ADC_smpclk : OUT STD_LOGIC;
104 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
104 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
105 -- DAC --------------------------------------------------------------------
105 -- DAC --------------------------------------------------------------------
106 DAC_SDO : OUT STD_LOGIC;
106 DAC_SDO : OUT STD_LOGIC;
107 DAC_SCK : OUT STD_LOGIC;
107 DAC_SCK : OUT STD_LOGIC;
108 DAC_SYNC : OUT STD_LOGIC;
108 DAC_SYNC : OUT STD_LOGIC;
109 DAC_CAL_EN : OUT STD_LOGIC;
109 DAC_CAL_EN : OUT STD_LOGIC;
110 -- HK ---------------------------------------------------------------------
110 -- HK ---------------------------------------------------------------------
111 HK_smpclk : OUT STD_LOGIC;
111 HK_smpclk : OUT STD_LOGIC;
112 ADC_OEB_bar_HK : OUT STD_LOGIC;
112 ADC_OEB_bar_HK : OUT STD_LOGIC;
113 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
113 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
114 );
114 );
115
115
116 END LFR_FM;
116 END LFR_FM;
117
117
118
118
119 ARCHITECTURE beh OF LFR_FM IS
119 ARCHITECTURE beh OF LFR_FM IS
120
120
121 SIGNAL clk_25_int : STD_LOGIC := '0';
121 SIGNAL clk_25_int : STD_LOGIC := '0';
122 SIGNAL clk_25 : STD_LOGIC := '0';
122 SIGNAL clk_25 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
127
127
128 -- CONSTANTS
128 -- CONSTANTS
129 CONSTANT CFG_PADTECH : INTEGER := inferred;
129 CONSTANT CFG_PADTECH : INTEGER := inferred;
130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
133
133
134 SIGNAL apbi_ext : apb_slv_in_type;
134 SIGNAL apbi_ext : apb_slv_in_type;
135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
140
140
141 -- Spacewire signals
141 -- Spacewire signals
142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
145 SIGNAL swni : grspw_in_type;
145 SIGNAL swni : grspw_in_type;
146 SIGNAL swno : grspw_out_type;
146 SIGNAL swno : grspw_out_type;
147
147
148 --GPIO
148 --GPIO
149 SIGNAL gpioi : gpio_in_type;
149 SIGNAL gpioi : gpio_in_type;
150 SIGNAL gpioo : gpio_out_type;
150 SIGNAL gpioo : gpio_out_type;
151
151
152 -- AD Converter ADS7886
152 -- AD Converter ADS7886
153 SIGNAL sample : Samples14v(8 DOWNTO 0);
153 SIGNAL sample : Samples14v(8 DOWNTO 0);
154 SIGNAL sample_s : Samples(8 DOWNTO 0);
154 SIGNAL sample_s : Samples(8 DOWNTO 0);
155 SIGNAL sample_val : STD_LOGIC;
155 SIGNAL sample_val : STD_LOGIC;
156 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
156 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
157
157
158 -----------------------------------------------------------------------------
158 -----------------------------------------------------------------------------
159 SIGNAL LFR_rstn_int : STD_LOGIC := '0';
159 SIGNAL LFR_rstn_int : STD_LOGIC := '0';
160 SIGNAL rstn_25_int : STD_LOGIC := '0';
160 SIGNAL rstn_25_int : STD_LOGIC := '0';
161 SIGNAL rstn_25 : STD_LOGIC;
161 SIGNAL rstn_25 : STD_LOGIC;
162 SIGNAL rstn_24 : STD_LOGIC;
162 SIGNAL rstn_24 : STD_LOGIC;
163
163
164 SIGNAL LFR_soft_rstn : STD_LOGIC;
164 SIGNAL LFR_soft_rstn : STD_LOGIC;
165 SIGNAL LFR_rstn : STD_LOGIC;
165 SIGNAL LFR_rstn : STD_LOGIC;
166
166
167 SIGNAL ADC_smpclk_s : STD_LOGIC;
167 SIGNAL ADC_smpclk_s : STD_LOGIC;
168
168
169 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
169 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
170
171 SIGNAL clk50MHz_int : STD_LOGIC := '0';
171 SIGNAL clk50MHz_int : STD_LOGIC := '0';
172
172
173 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
173 --component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
174 --component hclkint port(A : in std_ulogic; Y :out std_ulogic); end component;
174
175
175 SIGNAL rstn_50 : STD_LOGIC;
176 SIGNAL rstn_50 : STD_LOGIC;
176 SIGNAL clk_lock : STD_LOGIC;
177 SIGNAL clk_lock : STD_LOGIC;
177 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
179 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
179
180
180 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
181 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
181 SIGNAL ahbrxd: STD_LOGIC;
182 SIGNAL ahbrxd: STD_LOGIC;
182 SIGNAL ahbtxd: STD_LOGIC;
183 SIGNAL ahbtxd: STD_LOGIC;
183 SIGNAL urxd1 : STD_LOGIC;
184 SIGNAL urxd1 : STD_LOGIC;
184 SIGNAL utxd1 : STD_LOGIC;
185 SIGNAL utxd1 : STD_LOGIC;
185 BEGIN -- beh
186 BEGIN -- beh
186
187
187 -----------------------------------------------------------------------------
188 -----------------------------------------------------------------------------
188 -- CLK_LOCK
189 -- CLK_LOCK
189 -----------------------------------------------------------------------------
190 -----------------------------------------------------------------------------
190 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
191 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
191
192
192 PROCESS (clk50MHz_int, rstn_50)
193 PROCESS (clk50MHz_int, rstn_50)
193 BEGIN -- PROCESS
194 BEGIN -- PROCESS
194 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
195 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
195 clk_lock <= '0';
196 clk_lock <= '0';
196 clk_busy_counter <= (OTHERS => '0');
197 clk_busy_counter <= (OTHERS => '0');
197 nSRAM_BUSY_reg <= '0';
198 nSRAM_BUSY_reg <= '0';
198 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
199 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
199 nSRAM_BUSY_reg <= nSRAM_BUSY;
200 nSRAM_BUSY_reg <= nSRAM_BUSY;
200 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
201 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
201 IF clk_busy_counter = "1111" THEN
202 IF clk_busy_counter = "1111" THEN
202 clk_lock <= '1';
203 clk_lock <= '1';
203 ELSE
204 ELSE
204 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
205 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
205 END IF;
206 END IF;
206 END IF;
207 END IF;
207 END IF;
208 END IF;
208 END PROCESS;
209 END PROCESS;
209
210
210 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
211 -- CLK
212 -- CLK
212 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
213 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25_int, OPEN);
214 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25_int, OPEN);
214 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
215 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
215
216
216 rstn_pad_25 : clkint port map (A => rstn_25_int, Y => rstn_25 );
217 rstn_pad_25 : clkint port map (A => rstn_25_int, Y => rstn_25 );
217
218
218 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
219 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
219 clk50MHz_int <= clk50MHz;
220 clk50MHz_int <= clk50MHz;
220
221
221 PROCESS(clk50MHz_int)
222 PROCESS(clk50MHz_int)
222 BEGIN
223 BEGIN
223 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
224 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
224 clk_25_int <= NOT clk_25_int;
225 clk_25_int <= NOT clk_25_int;
225 --clk_25 <= NOT clk_25;
226 --clk_25 <= NOT clk_25;
226 END IF;
227 END IF;
227 END PROCESS;
228 END PROCESS;
228 clk_pad_25 : hclkint port map (A => clk_25_int, Y => clk_25 );
229 clk_pad_25 : hclkint port map (A => clk_25_int, Y => clk_25 );
229
230
230 PROCESS(clk49_152MHz)
231 PROCESS(clk49_152MHz)
231 BEGIN
232 BEGIN
232 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
233 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
233 clk_24 <= NOT clk_24;
234 clk_24 <= NOT clk_24;
234 END IF;
235 END IF;
235 END PROCESS;
236 END PROCESS;
236 -- clk_49 <= clk49_152MHz;
237 -- clk_49 <= clk49_152MHz;
237
238
238 -----------------------------------------------------------------------------
239 -----------------------------------------------------------------------------
239 leon3_soc_1 : leon3_soc
240 leon3_soc_1 : leon3_soc
240 GENERIC MAP (
241 GENERIC MAP (
241 fabtech => axcel,--inferred,--axdsp,
242 fabtech => axcel,--inferred,--axdsp,
242 memtech => axcel,--inferred,--tech_leon,
243 memtech => axcel,--inferred,--tech_leon,
243 padtech => axcel,--inferred,
244 padtech => axcel,--inferred,
244 clktech => axcel,--inferred,
245 clktech => axcel,--inferred,
245 disas => 0,
246 disas => 0,
246 dbguart => 0,
247 dbguart => 0,
247 pclow => 2,
248 pclow => 2,
248 clk_freq => 25000,
249 clk_freq => 25000,
249 IS_RADHARD => 1,
250 IS_RADHARD => 1,
250 NB_CPU => 1,
251 NB_CPU => 1,
251 ENABLE_FPU => 1,
252 ENABLE_FPU => 1,
252 FPU_NETLIST => 0,
253 FPU_NETLIST => 0,
253 ENABLE_DSU => 1,
254 ENABLE_DSU => 1,
254 ENABLE_AHB_UART => 0,
255 ENABLE_AHB_UART => 0,
255 ENABLE_APB_UART => 1,
256 ENABLE_APB_UART => 1,
256 ENABLE_IRQMP => 1,
257 ENABLE_IRQMP => 1,
257 ENABLE_GPT => 1,
258 ENABLE_GPT => 1,
258 NB_AHB_MASTER => NB_AHB_MASTER,
259 NB_AHB_MASTER => NB_AHB_MASTER,
259 NB_AHB_SLAVE => NB_AHB_SLAVE,
260 NB_AHB_SLAVE => NB_AHB_SLAVE,
260 NB_APB_SLAVE => NB_APB_SLAVE,
261 NB_APB_SLAVE => NB_APB_SLAVE,
261 ADDRESS_SIZE => 19,
262 ADDRESS_SIZE => 19,
262 USES_IAP_MEMCTRLR => 1,
263 USES_IAP_MEMCTRLR => 1,
263 USES_MBE_PIN => 1,
264 USES_MBE_PIN => 1,
264 BYPASS_EDAC_MEMCTRLR => '0',
265 BYPASS_EDAC_MEMCTRLR => '0',
265 SRBANKSZ => 8)
266 SRBANKSZ => 8)
266 PORT MAP (
267 PORT MAP (
267 clk => clk_25,
268 clk => clk_25,
268 reset => rstn_25,
269 reset => rstn_25,
269 errorn => OPEN,
270 errorn => OPEN,
270
271
271 ahbrxd => ahbrxd, -- INPUT
272 ahbrxd => ahbrxd, -- INPUT
272 ahbtxd => ahbtxd, -- OUTPUT
273 ahbtxd => ahbtxd, -- OUTPUT
273 urxd1 => urxd1, -- INPUT
274 urxd1 => urxd1, -- INPUT
274 utxd1 => utxd1, -- OUTPUT
275 utxd1 => utxd1, -- OUTPUT
275
276
276 address => address,
277 address => address,
277 data => data,
278 data => data,
278 nSRAM_BE0 => OPEN,
279 nSRAM_BE0 => OPEN,
279 nSRAM_BE1 => OPEN,
280 nSRAM_BE1 => OPEN,
280 nSRAM_BE2 => OPEN,
281 nSRAM_BE2 => OPEN,
281 nSRAM_BE3 => OPEN,
282 nSRAM_BE3 => OPEN,
282 nSRAM_WE => nSRAM_W,
283 nSRAM_WE => nSRAM_W,
283 nSRAM_CE => nSRAM_CE,
284 nSRAM_CE => nSRAM_CE,
284 nSRAM_OE => nSRAM_G,
285 nSRAM_OE => nSRAM_G,
285 nSRAM_READY => nSRAM_BUSY,
286 nSRAM_READY => nSRAM_BUSY,
286 SRAM_MBE => nSRAM_MBE,
287 SRAM_MBE => nSRAM_MBE,
287
288
288 apbi_ext => apbi_ext,
289 apbi_ext => apbi_ext,
289 apbo_ext => apbo_ext,
290 apbo_ext => apbo_ext,
290 ahbi_s_ext => ahbi_s_ext,
291 ahbi_s_ext => ahbi_s_ext,
291 ahbo_s_ext => ahbo_s_ext,
292 ahbo_s_ext => ahbo_s_ext,
292 ahbi_m_ext => ahbi_m_ext,
293 ahbi_m_ext => ahbi_m_ext,
293 ahbo_m_ext => ahbo_m_ext);
294 ahbo_m_ext => ahbo_m_ext);
294
295
295
296
296 nSRAM_E1 <= nSRAM_CE(0);
297 nSRAM_E1 <= nSRAM_CE(0);
297 nSRAM_E2 <= nSRAM_CE(1);
298 nSRAM_E2 <= nSRAM_CE(1);
298
299
299 -------------------------------------------------------------------------------
300 -------------------------------------------------------------------------------
300 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
301 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
301 -------------------------------------------------------------------------------
302 -------------------------------------------------------------------------------
302 apb_lfr_management_1 : apb_lfr_management
303 apb_lfr_management_1 : apb_lfr_management
303 GENERIC MAP (
304 GENERIC MAP (
304 tech => tech,
305 tech => tech,
305 pindex => 6,
306 pindex => 6,
306 paddr => 6,
307 paddr => 6,
307 pmask => 16#fff#,
308 pmask => 16#fff#,
308 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
309 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
309 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
310 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
310 PORT MAP (
311 PORT MAP (
311 clk25MHz => clk_25,
312 clk25MHz => clk_25,
312 resetn_25MHz => rstn_25, -- TODO
313 resetn_25MHz => rstn_25, -- TODO
313 --clk24_576MHz => clk_24, -- 49.152MHz/2
314 --clk24_576MHz => clk_24, -- 49.152MHz/2
314 --resetn_24_576MHz => rstn_24, -- TODO
315 --resetn_24_576MHz => rstn_24, -- TODO
315
316
316 grspw_tick => swno.tickout,
317 grspw_tick => swno.tickout,
317 apbi => apbi_ext,
318 apbi => apbi_ext,
318 apbo => apbo_ext(6),
319 apbo => apbo_ext(6),
319
320
320 HK_sample => sample_s(8),
321 HK_sample => sample_s(8),
321 HK_val => sample_val,
322 HK_val => sample_val,
322 HK_sel => HK_SEL,
323 HK_sel => HK_SEL,
323
324
324 DAC_SDO => DAC_SDO,
325 DAC_SDO => DAC_SDO,
325 DAC_SCK => DAC_SCK,
326 DAC_SCK => DAC_SCK,
326 DAC_SYNC => DAC_SYNC,
327 DAC_SYNC => DAC_SYNC,
327 DAC_CAL_EN => DAC_CAL_EN,
328 DAC_CAL_EN => DAC_CAL_EN,
328
329
329 coarse_time => coarse_time,
330 coarse_time => coarse_time,
330 fine_time => fine_time,
331 fine_time => fine_time,
331 LFR_soft_rstn => LFR_soft_rstn
332 LFR_soft_rstn => LFR_soft_rstn
332 );
333 );
333
334
334 -----------------------------------------------------------------------
335 -----------------------------------------------------------------------
335 --- SpaceWire --------------------------------------------------------
336 --- SpaceWire --------------------------------------------------------
336 -----------------------------------------------------------------------
337 -----------------------------------------------------------------------
337
338
338 ------------------------------------------------------------------------------
339 ------------------------------------------------------------------------------
339 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
340 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
340 ------------------------------------------------------------------------------
341 ------------------------------------------------------------------------------
341 spw1_en <= '1';
342 spw1_en <= '1';
342 spw2_en <= '1';
343 spw2_en <= '1';
343 ------------------------------------------------------------------------------
344 ------------------------------------------------------------------------------
344 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
345 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
345 ------------------------------------------------------------------------------
346 ------------------------------------------------------------------------------
346
347
347 --spw_clk <= clk50MHz;
348 --spw_clk <= clk50MHz;
348 --spw_rxtxclk <= spw_clk;
349 --spw_rxtxclk <= spw_clk;
349 --spw_rxclkn <= NOT spw_rxtxclk;
350 --spw_rxclkn <= NOT spw_rxtxclk;
350
351
351 -- PADS for SPW1
352 -- PADS for SPW1
352 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
353 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
353 PORT MAP (spw1_din, dtmp(0));
354 PORT MAP (spw1_din, dtmp(0));
354 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
355 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
355 PORT MAP (spw1_sin, stmp(0));
356 PORT MAP (spw1_sin, stmp(0));
356 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
357 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
357 PORT MAP (spw1_dout, swno.d(0));
358 PORT MAP (spw1_dout, swno.d(0));
358 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
359 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
359 PORT MAP (spw1_sout, swno.s(0));
360 PORT MAP (spw1_sout, swno.s(0));
360 -- PADS FOR SPW2
361 -- PADS FOR SPW2
361 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
362 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
362 PORT MAP (spw2_din, dtmp(1));
363 PORT MAP (spw2_din, dtmp(1));
363 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
364 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
364 PORT MAP (spw2_sin, stmp(1));
365 PORT MAP (spw2_sin, stmp(1));
365 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
366 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
366 PORT MAP (spw2_dout, swno.d(1));
367 PORT MAP (spw2_dout, swno.d(1));
367 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
368 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
368 PORT MAP (spw2_sout, swno.s(1));
369 PORT MAP (spw2_sout, swno.s(1));
369
370
370 -- GRSPW PHY
371 -- GRSPW PHY
371 --spw1_input: if CFG_SPW_GRSPW = 1 generate
372 --spw1_input: if CFG_SPW_GRSPW = 1 generate
372 spw_inputloop : FOR j IN 0 TO 1 GENERATE
373 spw_inputloop : FOR j IN 0 TO 1 GENERATE
373 spw_phy0 : grspw_phy
374 spw_phy0 : grspw_phy
374 GENERIC MAP(
375 GENERIC MAP(
375 tech => axcel,-- inferred,--axdsp,--tech_leon,
376 tech => axcel,-- inferred,--axdsp,--tech_leon,
376 rxclkbuftype => 1,
377 rxclkbuftype => 1,
377 scantest => 0)
378 scantest => 0)
378 PORT MAP(
379 PORT MAP(
379 rxrst => swno.rxrst,
380 rxrst => swno.rxrst,
380 di => dtmp(j),
381 di => dtmp(j),
381 si => stmp(j),
382 si => stmp(j),
382 rxclko => spw_rxclk(j),
383 rxclko => spw_rxclk(j),
383 do => swni.d(j),
384 do => swni.d(j),
384 ndo => swni.nd(j*5+4 DOWNTO j*5),
385 ndo => swni.nd(j*5+4 DOWNTO j*5),
385 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
386 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
386 END GENERATE spw_inputloop;
387 END GENERATE spw_inputloop;
387
388
388 -- SPW core
389 -- SPW core
389 sw0 : grspwm GENERIC MAP(
390 sw0 : grspwm GENERIC MAP(
390 tech => axcel,--inferred,--axdsp,--tech_leon,
391 tech => axcel,--inferred,--axdsp,--tech_leon,
391 hindex => 1,
392 hindex => 1,
392 pindex => 5,
393 pindex => 5,
393 paddr => 5,
394 paddr => 5,
394 pirq => 11,
395 pirq => 11,
395 sysfreq => 25000, -- CPU_FREQ
396 sysfreq => 25000, -- CPU_FREQ
396 rmap => 1,
397 rmap => 1,
397 rmapcrc => 1,
398 rmapcrc => 1,
398 fifosize1 => 16,
399 fifosize1 => 16,
399 fifosize2 => 16,
400 fifosize2 => 16,
400 rxclkbuftype => 1,
401 rxclkbuftype => 1,
401 rxunaligned => 0,
402 rxunaligned => 0,
402 rmapbufs => 4,
403 rmapbufs => 4,
403 ft => 1,
404 ft => 1,
404 netlist => 0,
405 netlist => 0,
405 ports => 2,
406 ports => 2,
406 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
407 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
407 memtech => axcel,--inferred,--tech_leon,
408 memtech => axcel,--inferred,--tech_leon,
408 destkey => 2,
409 destkey => 2,
409 spwcore => 1
410 spwcore => 1
410 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
411 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
411 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
412 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
412 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
413 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
413 )
414 )
414 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
415 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
415 spw_rxclk(1),
416 spw_rxclk(1),
416 clk50MHz_int,
417 clk50MHz_int,
417 clk50MHz_int,
418 clk50MHz_int,
418 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
419 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
419 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
420 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
420 swni, swno);
421 swni, swno);
421
422
422 swni.tickin <= '0';
423 swni.tickin <= '0';
423 swni.rmapen <= '1';
424 swni.rmapen <= '1';
424 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
425 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
425 swni.tickinraw <= '0';
426 swni.tickinraw <= '0';
426 swni.timein <= (OTHERS => '0');
427 swni.timein <= (OTHERS => '0');
427 swni.dcrstval <= (OTHERS => '0');
428 swni.dcrstval <= (OTHERS => '0');
428 swni.timerrstval <= (OTHERS => '0');
429 swni.timerrstval <= (OTHERS => '0');
429
430
430 -------------------------------------------------------------------------------
431 -------------------------------------------------------------------------------
431 -- LFR ------------------------------------------------------------------------
432 -- LFR ------------------------------------------------------------------------
432 -------------------------------------------------------------------------------
433 -------------------------------------------------------------------------------
433 --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN);
434 --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN);
434 LFR_rstn_int <= LFR_soft_rstn AND rstn_25_int;
435 LFR_rstn_int <= LFR_soft_rstn AND rstn_25_int;
435
436
436 rstn_pad_lfr : clkint port map (A => LFR_rstn_int, Y => LFR_rstn );
437 rstn_pad_lfr : clkint port map (A => LFR_rstn_int, Y => LFR_rstn );
437
438
438 lpp_lfr_1 : lpp_lfr
439 lpp_lfr_1 : lpp_lfr
439 GENERIC MAP (
440 GENERIC MAP (
440 Mem_use => Mem_use,
441 Mem_use => Mem_use,
441 tech => inferred,--tech,
442 tech => inferred,--tech,
442 nb_data_by_buffer_size => 32,
443 nb_data_by_buffer_size => 32,
443 --nb_word_by_buffer_size => 30,
444 --nb_word_by_buffer_size => 30,
444 nb_snapshot_param_size => 32,
445 nb_snapshot_param_size => 32,
445 delta_vector_size => 32,
446 delta_vector_size => 32,
446 delta_vector_size_f0_2 => 7, -- log2(96)
447 delta_vector_size_f0_2 => 7, -- log2(96)
447 pindex => 15,
448 pindex => 15,
448 paddr => 15,
449 paddr => 15,
449 pmask => 16#fff#,
450 pmask => 16#fff#,
450 pirq_ms => 6,
451 pirq_ms => 6,
451 pirq_wfp => 14,
452 pirq_wfp => 14,
452 hindex => 2,
453 hindex => 2,
453 top_lfr_version => LPP_LFR_BOARD_LFR_FM & X"015B",
454 top_lfr_version => LPP_LFR_BOARD_LFR_FM & X"015B",
454 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA,
455 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA,
455 RTL_DESIGN_LIGHT =>0,
456 RTL_DESIGN_LIGHT =>0,
456 WINDOWS_HAANNING_PARAM_SIZE => 15,
457 WINDOWS_HAANNING_PARAM_SIZE => 15,
457 DATA_SHAPING_SATURATION => 1)
458 DATA_SHAPING_SATURATION => 1)
458 PORT MAP (
459 PORT MAP (
459 clk => clk_25,
460 clk => clk_25,
460 rstn => LFR_rstn,
461 rstn => LFR_rstn,
461 sample_B => sample_s(2 DOWNTO 0),
462 sample_B => sample_s(2 DOWNTO 0),
462 sample_E => sample_s(7 DOWNTO 3),
463 sample_E => sample_s(7 DOWNTO 3),
463 sample_val => sample_val,
464 sample_val => sample_val,
464 apbi => apbi_ext,
465 apbi => apbi_ext,
465 apbo => apbo_ext(15),
466 apbo => apbo_ext(15),
466 ahbi => ahbi_m_ext,
467 ahbi => ahbi_m_ext,
467 ahbo => ahbo_m_ext(2),
468 ahbo => ahbo_m_ext(2),
468 coarse_time => coarse_time,
469 coarse_time => coarse_time,
469 fine_time => fine_time,
470 fine_time => fine_time,
470 data_shaping_BW => bias_fail_sw,
471 data_shaping_BW => bias_fail_sw,
471 debug_vector => debug_vector,
472 debug_vector => debug_vector,
472 debug_vector_ms => OPEN); --,
473 debug_vector_ms => OPEN); --,
473 --observation_vector_0 => OPEN,
474 --observation_vector_0 => OPEN,
474 --observation_vector_1 => OPEN,
475 --observation_vector_1 => OPEN,
475 --observation_reg => observation_reg);
476 --observation_reg => observation_reg);
476
477
477
478
478 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
479 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
479 sample_s(I) <= sample(I) & '0' & '0';
480 sample_s(I) <= sample(I) & '0' & '0';
480 END GENERATE all_sample;
481 END GENERATE all_sample;
481 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
482 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
482
483
483 -----------------------------------------------------------------------------
484 -----------------------------------------------------------------------------
484 --
485 --
485 -----------------------------------------------------------------------------
486 -----------------------------------------------------------------------------
486 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
487 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
487 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
488 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
488 GENERIC MAP (
489 GENERIC MAP (
489 ChanelCount => 9,
490 ChanelCount => 9,
490 ncycle_cnv_high => 12,
491 ncycle_cnv_high => 12,
491 ncycle_cnv => 25,
492 ncycle_cnv => 25,
492 FILTER_ENABLED => 16#FF#)
493 FILTER_ENABLED => 16#FF#)
493 PORT MAP (
494 PORT MAP (
494 cnv_clk => clk_24,
495 cnv_clk => clk_24,
495 cnv_rstn => rstn_24,
496 cnv_rstn => rstn_24,
496 cnv => ADC_smpclk_s,
497 cnv => ADC_smpclk_s,
497 clk => clk_25,
498 clk => clk_25,
498 rstn => rstn_25,
499 rstn => rstn_25,
499 ADC_data => ADC_data,
500 ADC_data => ADC_data,
500 ADC_nOE => ADC_OEB_bar_CH_s,
501 ADC_nOE => ADC_OEB_bar_CH_s,
501 sample => sample,
502 sample => sample,
502 sample_val => sample_val);
503 sample_val => sample_val);
503
504
504 END GENERATE USE_ADCDRIVER_true;
505 END GENERATE USE_ADCDRIVER_true;
505
506
506 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
507 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
507 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
508 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
508 GENERIC MAP (
509 GENERIC MAP (
509 ChanelCount => 9,
510 ChanelCount => 9,
510 ncycle_cnv_high => 25,
511 ncycle_cnv_high => 25,
511 ncycle_cnv => 50,
512 ncycle_cnv => 50,
512 FILTER_ENABLED => 16#FF#)
513 FILTER_ENABLED => 16#FF#)
513 PORT MAP (
514 PORT MAP (
514 cnv_clk => clk_24,
515 cnv_clk => clk_24,
515 cnv_rstn => rstn_24,
516 cnv_rstn => rstn_24,
516 cnv => ADC_smpclk_s,
517 cnv => ADC_smpclk_s,
517 clk => clk_25,
518 clk => clk_25,
518 rstn => rstn_25,
519 rstn => rstn_25,
519 ADC_data => ADC_data,
520 ADC_data => ADC_data,
520 ADC_nOE => OPEN,
521 ADC_nOE => OPEN,
521 sample => OPEN,
522 sample => OPEN,
522 sample_val => sample_val);
523 sample_val => sample_val);
523
524
524 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
525 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
525
526
526 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
527 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
527 ramp_generator_1: ramp_generator
528 ramp_generator_1: ramp_generator
528 GENERIC MAP (
529 GENERIC MAP (
529 DATA_SIZE => 14,
530 DATA_SIZE => 14,
530 VALUE_UNSIGNED_INIT => 2**I,
531 VALUE_UNSIGNED_INIT => 2**I,
531 VALUE_UNSIGNED_INCR => 0,
532 VALUE_UNSIGNED_INCR => 0,
532 VALUE_UNSIGNED_MASK => 16#3FFF#)
533 VALUE_UNSIGNED_MASK => 16#3FFF#)
533 PORT MAP (
534 PORT MAP (
534 clk => clk_25,
535 clk => clk_25,
535 rstn => rstn_25,
536 rstn => rstn_25,
536 new_data => sample_val,
537 new_data => sample_val,
537 output_data => sample(I) );
538 output_data => sample(I) );
538 END GENERATE all_sample;
539 END GENERATE all_sample;
539
540
540
541
541 END GENERATE USE_ADCDRIVER_false;
542 END GENERATE USE_ADCDRIVER_false;
542
543
543
544
544
545
545
546
546 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
547 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
547
548
548 ADC_smpclk <= ADC_smpclk_s;
549 ADC_smpclk <= ADC_smpclk_s;
549 HK_smpclk <= ADC_smpclk_s;
550 HK_smpclk <= ADC_smpclk_s;
550
551
551
552
552 -----------------------------------------------------------------------------
553 -----------------------------------------------------------------------------
553 -- HK
554 -- HK
554 -----------------------------------------------------------------------------
555 -----------------------------------------------------------------------------
555 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
556 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
556
557
557 -----------------------------------------------------------------------------
558 -----------------------------------------------------------------------------
558 --
559 --
559 -----------------------------------------------------------------------------
560 -----------------------------------------------------------------------------
560 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
561 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
561 -- lpp_bootloader_1: lpp_bootloader
562 -- lpp_bootloader_1: lpp_bootloader
562 -- GENERIC MAP (
563 -- GENERIC MAP (
563 -- pindex => 13,
564 -- pindex => 13,
564 -- paddr => 13,
565 -- paddr => 13,
565 -- pmask => 16#fff#,
566 -- pmask => 16#fff#,
566 -- hindex => 3,
567 -- hindex => 3,
567 -- haddr => 0,
568 -- haddr => 0,
568 -- hmask => 16#fff#)
569 -- hmask => 16#fff#)
569 -- PORT MAP (
570 -- PORT MAP (
570 -- HCLK => clk_25,
571 -- HCLK => clk_25,
571 -- HRESETn => rstn_25,
572 -- HRESETn => rstn_25,
572 -- apbi => apbi_ext,
573 -- apbi => apbi_ext,
573 -- apbo => apbo_ext(13),
574 -- apbo => apbo_ext(13),
574 -- ahbsi => ahbi_s_ext,
575 -- ahbsi => ahbi_s_ext,
575 -- ahbso => ahbo_s_ext(3));
576 -- ahbso => ahbo_s_ext(3));
576 --END GENERATE inst_bootloader;
577 --END GENERATE inst_bootloader;
577
578
578 -----------------------------------------------------------------------------
579 -----------------------------------------------------------------------------
579 --
580 --
580 -----------------------------------------------------------------------------
581 -----------------------------------------------------------------------------
581 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
582 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
582 PROCESS (clk_25, rstn_25)
583 PROCESS (clk_25, rstn_25)
583 BEGIN -- PROCESS
584 BEGIN -- PROCESS
584 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
585 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
585 TAG <= (OTHERS => '0');
586 TAG <= (OTHERS => '0');
586 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
587 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
587 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
588 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
588 END IF;
589 END IF;
589 END PROCESS;
590 END PROCESS;
590
591
591
592
592 END GENERATE USE_DEBUG_VECTOR_IF;
593 END GENERATE USE_DEBUG_VECTOR_IF;
593
594
594 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
595 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
595 --ahbrxd <= TAG(1); -- AHB UART
596 --ahbrxd <= TAG(1); -- AHB UART
596 --TAG(3) <= ahbtxd;
597 --TAG(3) <= ahbtxd;
597
598
598 urxd1 <= TAG(2); -- APB UART
599 urxd1 <= TAG(2); -- APB UART
599 TAG(4) <= utxd1;
600 TAG(4) <= utxd1;
600 --TAG(8) <= nSRAM_BUSY;
601 --TAG(8) <= nSRAM_BUSY;
601 END GENERATE USE_DEBUG_VECTOR_IF2;
602 END GENERATE USE_DEBUG_VECTOR_IF2;
602
603
603 END beh;
604 END beh;
Show file before | Show file after | Hide comments
@@ -1,472 +1,484
1
1
2 LIBRARY ieee;
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
4 USE ieee.numeric_std.ALL;
5 USE IEEE.std_logic_signed.ALL;
5 USE IEEE.std_logic_signed.ALL;
6 USE IEEE.MATH_real.ALL;
6 USE IEEE.MATH_real.ALL;
7
7
8 LIBRARY techmap;
8 LIBRARY techmap;
9 USE techmap.gencomp.ALL;
9 USE techmap.gencomp.ALL;
10
10
11 LIBRARY std;
11 LIBRARY std;
12 USE std.textio.ALL;
12 USE std.textio.ALL;
13
13
14 library opencores;
14 library opencores;
15 use opencores.spwpkg.all;
15 use opencores.spwpkg.all;
16 use opencores.spwambapkg.all;
16 use opencores.spwambapkg.all;
17
17
18 LIBRARY lpp;
18 LIBRARY lpp;
19 USE lpp.iir_filter.ALL;
19 USE lpp.iir_filter.ALL;
20 USE lpp.lpp_ad_conv.ALL;
20 USE lpp.lpp_ad_conv.ALL;
21 USE lpp.FILTERcfg.ALL;
21 USE lpp.FILTERcfg.ALL;
22 USE lpp.lpp_lfr_filter_coeff.ALL;
22 USE lpp.lpp_lfr_filter_coeff.ALL;
23 USE lpp.general_purpose.ALL;
23 USE lpp.general_purpose.ALL;
24 USE lpp.data_type_pkg.ALL;
24 USE lpp.data_type_pkg.ALL;
25 USE lpp.lpp_lfr_pkg.ALL;
25 USE lpp.lpp_lfr_pkg.ALL;
26 USE lpp.general_purpose.ALL;
26 USE lpp.general_purpose.ALL;
27 USE lpp.lpp_sim_pkg.ALL;
27 USE lpp.lpp_sim_pkg.ALL;
28 USE lpp.CY7C1061DV33_pkg.ALL;
28 USE lpp.CY7C1061DV33_pkg.ALL;
29
29
30 ENTITY testbench IS
30 ENTITY testbench IS
31 GENERIC(
31 GENERIC(
32 tech : INTEGER := 0; --axcel,0
32 tech : INTEGER := 0; --axcel,0
33 Mem_use : INTEGER := use_CEL --use_RAM,use_CEL
33 Mem_use : INTEGER := use_CEL --use_RAM,use_CEL
34 );
34 );
35 END;
35 END;
36
36
37 ARCHITECTURE behav OF testbench IS
37 ARCHITECTURE behav OF testbench IS
38
38
39 SIGNAL TSTAMP : INTEGER := 0;
39 SIGNAL TSTAMP : INTEGER := 0;
40 SIGNAL clk : STD_LOGIC := '0';
40 SIGNAL clk : STD_LOGIC := '0';
41 SIGNAL clk49_152MHz : STD_LOGIC := '0';
41 SIGNAL clk49_152MHz : STD_LOGIC := '0';
42 SIGNAL rstn,rst : STD_LOGIC;
42 SIGNAL rstn,rst : STD_LOGIC;
43
43
44 SIGNAL end_of_simu : STD_LOGIC := '0';
44 SIGNAL end_of_simu : STD_LOGIC := '0';
45
45
46 -----------------------------------------------------------------------------
46 -----------------------------------------------------------------------------
47 -- LFR TOP WRAPPER SIGNALS
47 -- LFR TOP WRAPPER SIGNALS
48 -----------------------------------------------------------------------------
48 -----------------------------------------------------------------------------
49 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
49 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
50 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
50 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
51
51
52 SIGNAL nSRAM_MBE : STD_LOGIC; -- new
52 SIGNAL nSRAM_MBE : STD_LOGIC; -- new
53 SIGNAL nSRAM_E1 : STD_LOGIC; -- new
53 SIGNAL nSRAM_E1 : STD_LOGIC; -- new
54 SIGNAL nSRAM_E2 : STD_LOGIC; -- new
54 SIGNAL nSRAM_E2 : STD_LOGIC; -- new
55 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
55 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
56 SIGNAL nSRAM_W : STD_LOGIC; -- new
56 SIGNAL nSRAM_W : STD_LOGIC; -- new
57 SIGNAL nSRAM_G : STD_LOGIC; -- new
57 SIGNAL nSRAM_G : STD_LOGIC; -- new
58 SIGNAL nSRAM_BUSY : STD_LOGIC; -- new
58 SIGNAL nSRAM_BUSY : STD_LOGIC := '1'; -- new
59 -- SPW --------------------------------------------------------------------
59 -- SPW --------------------------------------------------------------------
60 SIGNAL spw1_en : STD_LOGIC; -- new
60 SIGNAL spw1_en : STD_LOGIC; -- new
61 SIGNAL spw1_din : STD_LOGIC;
61 SIGNAL spw1_din : STD_LOGIC;
62 SIGNAL spw1_sin : STD_LOGIC;
62 SIGNAL spw1_sin : STD_LOGIC;
63 SIGNAL spw1_dout : STD_LOGIC;
63 SIGNAL spw1_dout : STD_LOGIC;
64 SIGNAL spw1_sout : STD_LOGIC;
64 SIGNAL spw1_sout : STD_LOGIC;
65 SIGNAL spw2_en : STD_LOGIC; -- new
65 SIGNAL spw2_en : STD_LOGIC; -- new
66 SIGNAL spw2_din : STD_LOGIC;
66 SIGNAL spw2_din : STD_LOGIC;
67 SIGNAL spw2_sin : STD_LOGIC;
67 SIGNAL spw2_sin : STD_LOGIC;
68 SIGNAL spw2_dout : STD_LOGIC;
68 SIGNAL spw2_dout : STD_LOGIC;
69 SIGNAL spw2_sout : STD_LOGIC;
69 SIGNAL spw2_sout : STD_LOGIC;
70 -- ADC --------------------------------------------------------------------
70 -- ADC --------------------------------------------------------------------
71 SIGNAL bias_fail_sw : STD_LOGIC;
71 SIGNAL bias_fail_sw : STD_LOGIC;
72 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
72 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
73 SIGNAL ADC_smpclk : STD_LOGIC;
73 SIGNAL ADC_smpclk : STD_LOGIC;
74 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
74 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
75 -- DAC --------------------------------------------------------------------
75 -- DAC --------------------------------------------------------------------
76 SIGNAL DAC_SDO : STD_LOGIC;
76 SIGNAL DAC_SDO : STD_LOGIC;
77 SIGNAL DAC_SCK : STD_LOGIC;
77 SIGNAL DAC_SCK : STD_LOGIC;
78 SIGNAL DAC_SYNC : STD_LOGIC;
78 SIGNAL DAC_SYNC : STD_LOGIC;
79 SIGNAL DAC_CAL_EN : STD_LOGIC;
79 SIGNAL DAC_CAL_EN : STD_LOGIC;
80 -- HK ---------------------------------------------------------------------
80 -- HK ---------------------------------------------------------------------
81 SIGNAL HK_smpclk : STD_LOGIC;
81 SIGNAL HK_smpclk : STD_LOGIC;
82 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
82 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
83 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
83 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
84
84
85 SIGNAL nSRAM_CE : STD_LOGIC;
85 SIGNAL nSRAM_CE : STD_LOGIC;
86
86
87
87
88
88
89
89
90 SIGNAL autostart: std_logic := '1';
90 SIGNAL autostart: std_logic := '1';
91
91
92 -- Enables link start once the Ready state is reached.
92 -- Enables link start once the Ready state is reached.
93 -- Without autostart or linkstart, the link remains in state Ready.
93 -- Without autostart or linkstart, the link remains in state Ready.
94 SIGNAL linkstart: std_logic :='1';
94 SIGNAL linkstart: std_logic :='1';
95
95
96 -- Do not start link (overrides linkstart and autostart) and/or
96 -- Do not start link (overrides linkstart and autostart) and/or
97 -- disconnect a running link.
97 -- disconnect a running link.
98 SIGNAL linkdis: std_logic := '0';
98 SIGNAL linkdis: std_logic := '0';
99
99
100 -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
100 -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
101 SIGNAL ctrl_in: std_logic_vector(1 downto 0) :=(others => '0');
101 SIGNAL ctrl_in: std_logic_vector(1 downto 0) :=(others => '0');
102
102
103 -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
103 -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
104 SIGNAL time_in: std_logic_vector(5 downto 0):=(others => '0');
104 SIGNAL time_in: std_logic_vector(5 downto 0):=(others => '0');
105
105
106 -- Pulled high by the application to write an N-Char to the transmit
106 -- Pulled high by the application to write an N-Char to the transmit
107 -- queue. If "txwrite" and "txrdy" are both high on the rising edge
107 -- queue. If "txwrite" and "txrdy" are both high on the rising edge
108 -- of "clk", a character is added to the transmit queue.
108 -- of "clk", a character is added to the transmit queue.
109 -- This signal has no effect if "txrdy" is low.
109 -- This signal has no effect if "txrdy" is low.
110 SIGNAL txwrite: std_logic := '0';
110 SIGNAL txwrite: std_logic := '0';
111
111
112 -- Control flag to be sent with the next N_Char.
112 -- Control flag to be sent with the next N_Char.
113 -- Must be valid while txwrite is high.
113 -- Must be valid while txwrite is high.
114 SIGNAL txflag: std_logic :='0';
114 SIGNAL txflag: std_logic :='0';
115
115
116 -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
116 -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
117 -- Must be valid while txwrite is high.
117 -- Must be valid while txwrite is high.
118 SIGNAL txdata: std_logic_vector(7 downto 0):=(others => '0');
118 SIGNAL txdata: std_logic_vector(7 downto 0):=(others => '0');
119
119
120 -- High if the entity is ready to accept an N-Char for transmission.
120 -- High if the entity is ready to accept an N-Char for transmission.
121 SIGNAL txrdy: std_logic;
121 SIGNAL txrdy: std_logic;
122
122
123 -- High if the transmission queue is at least half full.
123 -- High if the transmission queue is at least half full.
124 SIGNAL txhalff: std_logic;
124 SIGNAL txhalff: std_logic;
125
125
126 -- High for one clock cycle if a TimeCode was just received.
126 -- High for one clock cycle if a TimeCode was just received.
127 SIGNAL tick_out: std_logic;
127 SIGNAL tick_out: std_logic;
128
128
129 -- Control bits of the last received TimeCode.
129 -- Control bits of the last received TimeCode.
130 SIGNAL ctrl_out: std_logic_vector(1 downto 0);
130 SIGNAL ctrl_out: std_logic_vector(1 downto 0);
131
131
132 -- Counter value of the last received TimeCode.
132 -- Counter value of the last received TimeCode.
133 SIGNAL time_out: std_logic_vector(5 downto 0);
133 SIGNAL time_out: std_logic_vector(5 downto 0);
134
134
135 -- High if "rxflag" and "rxdata" contain valid data.
135 -- High if "rxflag" and "rxdata" contain valid data.
136 -- This signal is high unless the receive FIFO is empty.
136 -- This signal is high unless the receive FIFO is empty.
137 SIGNAL rxvalid: std_logic;
137 SIGNAL rxvalid: std_logic;
138
138
139 -- High if the receive FIFO is at least half full.
139 -- High if the receive FIFO is at least half full.
140 SIGNAL rxhalff: std_logic;
140 SIGNAL rxhalff: std_logic;
141
141
142 -- High if the received character is EOP or EEP; low if the received
142 -- High if the received character is EOP or EEP; low if the received
143 -- character is a data byte. Valid if "rxvalid" is high.
143 -- character is a data byte. Valid if "rxvalid" is high.
144 SIGNAL rxflag: std_logic;
144 SIGNAL rxflag: std_logic;
145
145
146 -- Received byte, or "00000000" for EOP or "00000001" for EEP.
146 -- Received byte, or "00000000" for EOP or "00000001" for EEP.
147 -- Valid if "rxvalid" is high.
147 -- Valid if "rxvalid" is high.
148 SIGNAL rxdata: std_logic_vector(7 downto 0);
148 SIGNAL rxdata: std_logic_vector(7 downto 0);
149
149
150 -- Pulled high by the application to accept a received character.
150 -- Pulled high by the application to accept a received character.
151 -- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
151 -- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
152 -- a character is removed from the receive FIFO and "rxvalid", "rxflag"
152 -- a character is removed from the receive FIFO and "rxvalid", "rxflag"
153 -- and "rxdata" are updated.
153 -- and "rxdata" are updated.
154 -- This signal has no effect if "rxvalid" is low.
154 -- This signal has no effect if "rxvalid" is low.
155 SIGNAL rxread: std_logic:='0';
155 SIGNAL rxread: std_logic:='0';
156
156
157 -- High if the link state machine is currently in the Started state.
157 -- High if the link state machine is currently in the Started state.
158 SIGNAL started: std_logic;
158 SIGNAL started: std_logic;
159
159
160 -- High if the link state machine is currently in the Connecting state.
160 -- High if the link state machine is currently in the Connecting state.
161 SIGNAL connecting: std_logic;
161 SIGNAL connecting: std_logic;
162
162
163 -- High if the link state machine is currently in the Run state, indicating
163 -- High if the link state machine is currently in the Run state, indicating
164 -- that the link is fully operational. If none of started, connecting or running
164 -- that the link is fully operational. If none of started, connecting or running
165 -- is high, the link is in an initial state and the transmitter is not yet enabled.
165 -- is high, the link is in an initial state and the transmitter is not yet enabled.
166 SIGNAL running: std_logic;
166 SIGNAL running: std_logic;
167
167
168 -- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
168 -- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
169 -- This indication is auto-clearing.
169 -- This indication is auto-clearing.
170 SIGNAL errdisc: std_logic;
170 SIGNAL errdisc: std_logic;
171
171
172 -- Parity error detected in state Run. Triggers a reset and reconnect of the link.
172 -- Parity error detected in state Run. Triggers a reset and reconnect of the link.
173 -- This indication is auto-clearing.
173 -- This indication is auto-clearing.
174 SIGNAL errpar: std_logic;
174 SIGNAL errpar: std_logic;
175
175
176 -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
176 -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
177 -- the link. This indication is auto-clearing.
177 -- the link. This indication is auto-clearing.
178 SIGNAL erresc: std_logic;
178 SIGNAL erresc: std_logic;
179
179
180 -- Credit error detected. Triggers a reset and reconnect of the link.
180 -- Credit error detected. Triggers a reset and reconnect of the link.
181 -- This indication is auto-clearing.
181 -- This indication is auto-clearing.
182 SIGNAL errcred: std_logic;
182 SIGNAL errcred: std_logic;
183
183
184
184
185 BEGIN
185 BEGIN
186
186
187 -----------------------------------------------------------------------------
187 -----------------------------------------------------------------------------
188 -- CLOCK and RESET
188 -- CLOCK and RESET
189 -----------------------------------------------------------------------------
189 -----------------------------------------------------------------------------
190 PROCESS
190 PROCESS
191 BEGIN -- PROCESS
191 BEGIN -- PROCESS
192 WAIT UNTIL clk = '1';
192 WAIT UNTIL clk = '1';
193 rstn <= '0';
193 rstn <= '0';
194 rst <= '1';
194 rst <= '1';
195 WAIT UNTIL clk = '1';
195 WAIT UNTIL clk = '1';
196 WAIT UNTIL clk = '1';
196 WAIT UNTIL clk = '1';
197 WAIT UNTIL clk = '1';
197 WAIT UNTIL clk = '1';
198 rstn <= '1';
198 rstn <= '1';
199 rst <= '0';
199 rst <= '0';
200 WAIT UNTIL end_of_simu = '1';
200 WAIT UNTIL end_of_simu = '1';
201 WAIT FOR 10 ps;
201 WAIT FOR 10 ps;
202 assert false report "end of test" severity note;
202 assert false report "end of test" severity note;
203 -- Wait forever; this will finish the simulation.
203 -- Wait forever; this will finish the simulation.
204 wait;
204 wait;
205 END PROCESS;
205 END PROCESS;
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207
207
208
208
209 clk49_152MHz_gen:PROCESS
209 clk49_152MHz_gen:PROCESS
210 BEGIN
210 BEGIN
211 IF end_of_simu /= '1' THEN
211 IF end_of_simu /= '1' THEN
212 clk49_152MHz <= NOT clk49_152MHz;
212 clk49_152MHz <= NOT clk49_152MHz;
213 WAIT FOR 10173 ps;
213 WAIT FOR 10173 ps;
214 ELSE
214 ELSE
215 WAIT FOR 10 ps;
215 WAIT FOR 10 ps;
216 assert false report "end of test" severity note;
216 assert false report "end of test" severity note;
217 WAIT;
217 WAIT;
218 END IF;
218 END IF;
219 END PROCESS;
219 END PROCESS;
220
220
221 clk_50M_gen:PROCESS
221 clk_50M_gen:PROCESS
222 BEGIN
222 BEGIN
223 IF end_of_simu /= '1' THEN
223 IF end_of_simu /= '1' THEN
224 clk <= NOT clk;
224 clk <= NOT clk;
225 TSTAMP <= TSTAMP+20;
225 TSTAMP <= TSTAMP+20;
226 WAIT FOR 10 ns;
226 WAIT FOR 10 ns;
227 ELSE
227 ELSE
228 WAIT FOR 10 ps;
228 WAIT FOR 10 ps;
229 assert false report "end of test" severity note;
229 assert false report "end of test" severity note;
230 WAIT;
230 WAIT;
231 END IF;
231 END IF;
232 END PROCESS;
232 END PROCESS;
233
233
234
234
235 LFR: ENTITY work.LFR_FM
235 LFR: ENTITY work.LFR_FM
236 GENERIC MAP(
236 GENERIC MAP(
237 Mem_use => use_RAM,
237 Mem_use => use_RAM,
238 USE_BOOTLOADER => 0,
238 USE_BOOTLOADER => 0,
239 USE_ADCDRIVER => 1,
239 USE_ADCDRIVER => 1,
240 tech => inferred,
240 tech => inferred,
241 tech_leon => inferred,
241 tech_leon => inferred,
242 DEBUG_FORCE_DATA_DMA => 0,
242 DEBUG_FORCE_DATA_DMA => 0,
243 USE_DEBUG_VECTOR => 0
243 USE_DEBUG_VECTOR => 0
244 )
244 )
245
245
246 PORT MAP(
246 PORT MAP(
247 clk50MHz => clk,
247 clk50MHz => clk,
248 clk49_152MHz => clk49_152MHz,
248 clk49_152MHz => clk49_152MHz,
249 reset => rstn,
249 reset => rstn,
250
250
251 TAG => OPEN,
251 TAG => OPEN,
252
252
253 address => address,
253 address => address,
254 data => data,
254 data => data,
255
255
256 nSRAM_MBE => nSRAM_MBE,
256 nSRAM_MBE => nSRAM_MBE,
257 nSRAM_E1 => nSRAM_E1,
257 nSRAM_E1 => nSRAM_E1,
258 nSRAM_E2 => nSRAM_E2,
258 nSRAM_E2 => nSRAM_E2,
259 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
259 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
260 nSRAM_W => nSRAM_W,
260 nSRAM_W => nSRAM_W,
261 nSRAM_G => nSRAM_G,
261 nSRAM_G => nSRAM_G,
262 nSRAM_BUSY => nSRAM_BUSY,
262 nSRAM_BUSY => nSRAM_BUSY,
263 -- SPW --------------------------------------------------------------------
263 -- SPW --------------------------------------------------------------------
264 spw1_en => spw1_en,
264 spw1_en => spw1_en,
265 spw1_din => spw1_din,
265 spw1_din => spw1_din,
266 spw1_sin => spw1_sin,
266 spw1_sin => spw1_sin,
267 spw1_dout => spw1_dout,
267 spw1_dout => spw1_dout,
268 spw1_sout => spw1_sout,
268 spw1_sout => spw1_sout,
269 spw2_en => spw2_en,
269 spw2_en => spw2_en,
270 spw2_din => spw2_din,
270 spw2_din => spw2_din,
271 spw2_sin => spw2_sin,
271 spw2_sin => spw2_sin,
272 spw2_dout => spw2_dout,
272 spw2_dout => spw2_dout,
273 spw2_sout => spw2_sout,
273 spw2_sout => spw2_sout,
274 -- ADC --------------------------------------------------------------------
274 -- ADC --------------------------------------------------------------------
275 bias_fail_sw => bias_fail_sw,
275 bias_fail_sw => bias_fail_sw,
276 ADC_OEB_bar_CH => ADC_OEB_bar_CH,
276 ADC_OEB_bar_CH => ADC_OEB_bar_CH,
277 ADC_smpclk => ADC_smpclk,
277 ADC_smpclk => ADC_smpclk,
278 ADC_data => ADC_data,
278 ADC_data => ADC_data,
279 -- DAC --------------------------------------------------------------------
279 -- DAC --------------------------------------------------------------------
280 DAC_SDO => DAC_SDO,
280 DAC_SDO => DAC_SDO,
281 DAC_SCK => DAC_SCK,
281 DAC_SCK => DAC_SCK,
282 DAC_SYNC => DAC_SYNC,
282 DAC_SYNC => DAC_SYNC,
283 DAC_CAL_EN => DAC_CAL_EN,
283 DAC_CAL_EN => DAC_CAL_EN,
284 -- HK ---------------------------------------------------------------------
284 -- HK ---------------------------------------------------------------------
285 HK_smpclk => HK_smpclk,
285 HK_smpclk => HK_smpclk,
286 ADC_OEB_bar_HK => ADC_OEB_bar_HK,
286 ADC_OEB_bar_HK => ADC_OEB_bar_HK,
287 HK_SEL => HK_SEL
287 HK_SEL => HK_SEL
288 );
288 );
289
289
290
290
291 spw2_din <= '1';
291 spw2_din <= '1';
292 spw2_sin <= '1';
292 spw2_sin <= '1';
293 -----------------------------------------------------------------------------
293 -----------------------------------------------------------------------------
294 -- SRAMS Same as EM, we don't have UT8ER1M32 models
294 -- SRAMS Same as EM, we don't have UT8ER1M32 models
295 -----------------------------------------------------------------------------
295 -----------------------------------------------------------------------------
296 nSRAM_BUSY <= '1'; -- TODO emulate scrubbing
296 buy_gen: process
297 begin
298 IF end_of_simu /= '1' THEN
299 nSRAM_BUSY <= '0';
300 wait for 100 ns;
301 nSRAM_BUSY <= '1';
302 WAIT FOR 100 us;
303 ELSE
304 WAIT FOR 10 ps;
305 assert false report "end of test" severity note;
306 WAIT;
307 END IF;
308 end process;
297
309
298 nSRAM_CE <= not nSRAM_E1;
310 nSRAM_CE <= not nSRAM_E1;
299
311
300 async_1Mx16_0: CY7C1061DV33
312 async_1Mx16_0: CY7C1061DV33
301 GENERIC MAP (
313 GENERIC MAP (
302 ADDR_BITS => 19,
314 ADDR_BITS => 19,
303 DATA_BITS => 16,
315 DATA_BITS => 16,
304 depth => 1048576,
316 depth => 1048576,
305 MEM_ARRAY_DEBUG => 32,
317 MEM_ARRAY_DEBUG => 32,
306 TimingInfo => TRUE,
318 TimingInfo => TRUE,
307 TimingChecks => '1')
319 TimingChecks => '1')
308 PORT MAP (
320 PORT MAP (
309 CE1_b => '0',
321 CE1_b => '0',
310 CE2 => nSRAM_CE,
322 CE2 => nSRAM_CE,
311 WE_b => nSRAM_W,
323 WE_b => nSRAM_W,
312 OE_b => nSRAM_G,
324 OE_b => nSRAM_G,
313 BHE_b => '0',
325 BHE_b => '0',
314 BLE_b => '0',
326 BLE_b => '0',
315 A => address,
327 A => address,
316 DQ => data(15 DOWNTO 0));
328 DQ => data(15 DOWNTO 0));
317
329
318 async_1Mx16_1: CY7C1061DV33
330 async_1Mx16_1: CY7C1061DV33
319 GENERIC MAP (
331 GENERIC MAP (
320 ADDR_BITS => 19,
332 ADDR_BITS => 19,
321 DATA_BITS => 16,
333 DATA_BITS => 16,
322 depth => 1048576,
334 depth => 1048576,
323 MEM_ARRAY_DEBUG => 32,
335 MEM_ARRAY_DEBUG => 32,
324 TimingInfo => TRUE,
336 TimingInfo => TRUE,
325 TimingChecks => '1')
337 TimingChecks => '1')
326 PORT MAP (
338 PORT MAP (
327 CE1_b => '0',
339 CE1_b => '0',
328 CE2 => nSRAM_CE,
340 CE2 => nSRAM_CE,
329 WE_b => nSRAM_W,
341 WE_b => nSRAM_W,
330 OE_b => nSRAM_G,
342 OE_b => nSRAM_G,
331 BHE_b => '0',
343 BHE_b => '0',
332 BLE_b => '0',
344 BLE_b => '0',
333 A => address,
345 A => address,
334 DQ => data(31 DOWNTO 16));
346 DQ => data(31 DOWNTO 16));
335
347
336
348
337
349
338
350
339
351
340 SPW: spwstream
352 SPW: spwstream
341
353
342 generic map(
354 generic map(
343 sysfreq => 50.0e6,
355 sysfreq => 50.0e6,
344 txclkfreq => 50.0e6,
356 txclkfreq => 50.0e6,
345 rximpl => impl_generic,
357 rximpl => impl_generic,
346 rxchunk => 1,
358 rxchunk => 1,
347 tximpl => impl_generic,
359 tximpl => impl_generic,
348 rxfifosize_bits => 11,
360 rxfifosize_bits => 11,
349 txfifosize_bits => 11
361 txfifosize_bits => 11
350 )
362 )
351
363
352 port map(
364 port map(
353 -- System clock.
365 -- System clock.
354 clk => clk,
366 clk => clk,
355 rxclk => clk,
367 rxclk => clk,
356 txclk => clk,
368 txclk => clk,
357 rst => rst,
369 rst => rst,
358 autostart => autostart,
370 autostart => autostart,
359 linkstart => linkstart,
371 linkstart => linkstart,
360 linkdis => linkdis,
372 linkdis => linkdis,
361 txdivcnt => X"00",
373 txdivcnt => X"00",
362 tick_in => '0',
374 tick_in => '0',
363
375
364 -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
376 -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
365 ctrl_in => ctrl_in,
377 ctrl_in => ctrl_in,
366
378
367 -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
379 -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
368 time_in => time_in,
380 time_in => time_in,
369
381
370 -- Pulled high by the application to write an N-Char to the transmit
382 -- Pulled high by the application to write an N-Char to the transmit
371 -- queue. If "txwrite" and "txrdy" are both high on the rising edge
383 -- queue. If "txwrite" and "txrdy" are both high on the rising edge
372 -- of "clk", a character is added to the transmit queue.
384 -- of "clk", a character is added to the transmit queue.
373 -- This signal has no effect if "txrdy" is low.
385 -- This signal has no effect if "txrdy" is low.
374 txwrite => txwrite,
386 txwrite => txwrite,
375
387
376 -- Control flag to be sent with the next N_Char.
388 -- Control flag to be sent with the next N_Char.
377 -- Must be valid while txwrite is high.
389 -- Must be valid while txwrite is high.
378 txflag => txflag,
390 txflag => txflag,
379
391
380 -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
392 -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
381 -- Must be valid while txwrite is high.
393 -- Must be valid while txwrite is high.
382 txdata => txdata,
394 txdata => txdata,
383
395
384 -- High if the entity is ready to accept an N-Char for transmission.
396 -- High if the entity is ready to accept an N-Char for transmission.
385 txrdy => txrdy,
397 txrdy => txrdy,
386
398
387 -- High if the transmission queue is at least half full.
399 -- High if the transmission queue is at least half full.
388 txhalff => txhalff,
400 txhalff => txhalff,
389
401
390 -- High for one clock cycle if a TimeCode was just received.
402 -- High for one clock cycle if a TimeCode was just received.
391 tick_out => tick_out,
403 tick_out => tick_out,
392
404
393 -- Control bits of the last received TimeCode.
405 -- Control bits of the last received TimeCode.
394 ctrl_out => ctrl_out,
406 ctrl_out => ctrl_out,
395
407
396 -- Counter value of the last received TimeCode.
408 -- Counter value of the last received TimeCode.
397 time_out => time_out,
409 time_out => time_out,
398
410
399 -- High if "rxflag" and "rxdata" contain valid data.
411 -- High if "rxflag" and "rxdata" contain valid data.
400 -- This signal is high unless the receive FIFO is empty.
412 -- This signal is high unless the receive FIFO is empty.
401 rxvalid => rxvalid,
413 rxvalid => rxvalid,
402
414
403 -- High if the receive FIFO is at least half full.
415 -- High if the receive FIFO is at least half full.
404 rxhalff => rxhalff,
416 rxhalff => rxhalff,
405
417
406 -- High if the received character is EOP or EEP; low if the received
418 -- High if the received character is EOP or EEP; low if the received
407 -- character is a data byte. Valid if "rxvalid" is high.
419 -- character is a data byte. Valid if "rxvalid" is high.
408 rxflag => rxflag,
420 rxflag => rxflag,
409
421
410 -- Received byte, or "00000000" for EOP or "00000001" for EEP.
422 -- Received byte, or "00000000" for EOP or "00000001" for EEP.
411 -- Valid if "rxvalid" is high.
423 -- Valid if "rxvalid" is high.
412 rxdata => rxdata,
424 rxdata => rxdata,
413
425
414 -- Pulled high by the application to accept a received character.
426 -- Pulled high by the application to accept a received character.
415 -- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
427 -- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
416 -- a character is removed from the receive FIFO and "rxvalid", "rxflag"
428 -- a character is removed from the receive FIFO and "rxvalid", "rxflag"
417 -- and "rxdata" are updated.
429 -- and "rxdata" are updated.
418 -- This signal has no effect if "rxvalid" is low.
430 -- This signal has no effect if "rxvalid" is low.
419 rxread => rxread,
431 rxread => rxread,
420
432
421 -- High if the link state machine is currently in the Started state.
433 -- High if the link state machine is currently in the Started state.
422 started => started,
434 started => started,
423
435
424 -- High if the link state machine is currently in the Connecting state.
436 -- High if the link state machine is currently in the Connecting state.
425 connecting => connecting,
437 connecting => connecting,
426
438
427 -- High if the link state machine is currently in the Run state, indicating
439 -- High if the link state machine is currently in the Run state, indicating
428 -- that the link is fully operational. If none of started, connecting or running
440 -- that the link is fully operational. If none of started, connecting or running
429 -- is high, the link is in an initial state and the transmitter is not yet enabled.
441 -- is high, the link is in an initial state and the transmitter is not yet enabled.
430 running => running,
442 running => running,
431
443
432 -- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
444 -- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
433 -- This indication is auto-clearing.
445 -- This indication is auto-clearing.
434 errdisc => errdisc,
446 errdisc => errdisc,
435
447
436 -- Parity error detected in state Run. Triggers a reset and reconnect of the link.
448 -- Parity error detected in state Run. Triggers a reset and reconnect of the link.
437 -- This indication is auto-clearing.
449 -- This indication is auto-clearing.
438 errpar => errpar,
450 errpar => errpar,
439
451
440 -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
452 -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
441 -- the link. This indication is auto-clearing.
453 -- the link. This indication is auto-clearing.
442 erresc => erresc,
454 erresc => erresc,
443
455
444 -- Credit error detected. Triggers a reset and reconnect of the link.
456 -- Credit error detected. Triggers a reset and reconnect of the link.
445 -- This indication is auto-clearing.
457 -- This indication is auto-clearing.
446 errcred => errcred,
458 errcred => errcred,
447
459
448 -- Data In signal from SpaceWire bus.
460 -- Data In signal from SpaceWire bus.
449 spw_di => spw1_dout,
461 spw_di => spw1_dout,
450
462
451 -- Strobe In signal from SpaceWire bus.
463 -- Strobe In signal from SpaceWire bus.
452 spw_si => spw1_sout,
464 spw_si => spw1_sout,
453
465
454 -- Data Out signal to SpaceWire bus.
466 -- Data Out signal to SpaceWire bus.
455 spw_do => spw1_din,
467 spw_do => spw1_din,
456
468
457 -- Strobe Out signal to SpaceWire bus.
469 -- Strobe Out signal to SpaceWire bus.
458 spw_so => spw1_sin
470 spw_so => spw1_sin
459 );
471 );
460
472
461
473
462
474
463
475
464
476
465
477
466 -----------------------------------------------------------------------------
478 -----------------------------------------------------------------------------
467 -- RECORD OUTPUT SIGNALS
479 -- RECORD OUTPUT SIGNALS
468 -----------------------------------------------------------------------------
480 -----------------------------------------------------------------------------
469
481
470
482
471
483
472 END;
484 END;
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