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Cleaned EGSE_ICI design.
Alexis Jeandet -
r218:8124d5736ed6 alexis
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1 -- TOP_GSE.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5 library lpp;
6 use lpp.lpp_usb.all;
7 library techmap;
8 use techmap.gencomp.all;
9
10 entity TOP_EGSE2 is
11 generic(WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64;Simu : integer :=0);
12 port(
13 Clock : in std_logic;
14 reset : in std_logic;
15 DataRTX : in std_logic;
16 DataRTX_echo : out std_logic;
17 SCLK : out std_logic;
18 Gate : out std_logic;
19 Major_Frame : out std_logic;
20 Minor_Frame : out std_logic;
21 if_clk : out STD_LOGIC;
22 flagb : in STD_LOGIC;
23 slwr : out STD_LOGIC;
24 slrd : out std_logic;
25 pktend : out STD_LOGIC;
26 sloe : out STD_LOGIC;
27 fdbusw : out std_logic_vector (7 downto 0);
28 fifoadr : out std_logic_vector (1 downto 0)
29 );
30 end TOP_EGSE2;
31
32
33
34 architecture ar_TOP_EGSE2 of TOP_EGSE2 is
35
36 component CLKINT
37 port( A : in std_logic := 'U';
38 Y : out std_logic
39 );
40 end component;
41
42 signal clk : std_logic;
43 signal sclkint : std_logic;
44 signal RaZ : std_logic;
45 signal rstn : std_logic;
46 signal WordCount : integer range 0 to WordCnt-1;
47 signal WordClk : std_logic;
48 signal MinFCnt : integer range 0 to MinFCount-1;
49 signal MinF : std_logic;
50 signal MinFclk : std_logic;
51 signal MajF : std_logic;
52 signal GateLF : std_logic;
53 signal GateHF : std_logic;
54 signal GateDC : std_logic;
55 signal Gateint : std_logic;
56 signal GateR : std_logic;
57 signal NwDat : std_logic;
58 signal DATA : std_logic_vector(WordSize-1 downto 0);
59
60 Signal FIFODATin : std_logic_vector(7 downto 0);
61 Signal FIFODATout : std_logic_vector(7 downto 0);
62
63 Signal USB_DATA : std_logic_vector(7 downto 0);
64 Signal FIFOwe,FIFOre,FIFOfull : std_logic;
65 Signal USBwe,USBfull,USBempty : std_logic;
66
67 Signal clk80 : std_logic;
68
69
70
71 begin
72
73
74 DataRTX_echo <= DataRTX; --P48
75
76 ck_int0 : CLKINT
77 port map(Clock,clk);
78
79 DEFPLL: IF simu = 0 generate
80 PLL : entity work.PLL0
81 port map(
82 POWERDOWN => '1',
83 CLKA => clk,
84 LOCK => RaZ,
85 GLA => SCLKint,
86 GLB => clk80
87 );
88 end generate;
89
90
91 SIMPLL: IF simu = 1 generate
92 PLL : entity work.PLL0Sim
93 port map(
94 POWERDOWN => '1',
95 CLKA => clk,
96 LOCK => RaZ,
97 GLA => SCLKint,
98 GLB => clk80
99 );
100 end generate;
101
102
103 USB2: entity work.FX2_WithFIFO
104 generic map(apa3)
105 port map(
106 clk => clk,
107 if_clk => if_clk,
108 reset => rstn,
109 flagb => flagb,
110 slwr => slwr,
111 slrd => slrd,
112 pktend => pktend,
113 sloe => sloe,
114 fdbusw => fdbusw,
115 fifoadr => fifoadr,
116 FULL => USBfull,
117 Write => USBwe,
118 Data => USB_DATA
119
120 );
121
122
123 rstn <= reset and RaZ;
124
125 process(clk,rstn)
126 begin
127 if rstn = '0' then
128 USB_DATA <= (others => '0');
129 USBwe <= '0';
130 elsif clk'event and clk = '1' then
131 if USBfull = '0' then
132 USB_DATA <= std_logic_vector(unsigned(USB_DATA) + 1 );
133 USBwe <= '1';
134 else
135 USBwe <= '0';
136 end if;
137 end if;
138 end process;
139
140 end ar_TOP_EGSE2;
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1 -- FIFO_pipeline.vhd
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 ------------------------------------------------------------------------------
20 -- Author : Alexis Jeandet
21 -- Mail : alexis.jeandet@member.fsf.org
22 ------------------------------------------------------------------------------
23 library IEEE;
24 use IEEE.std_logic_1164.all;
25 use IEEE.numeric_std.all;
26 library lpp;
27 use lpp.lpp_memory.all;
28 use lpp.iir_filter.all;
29 library techmap;
30 use techmap.gencomp.all;
31
32 entity FIFO_pipeline is
33 generic(
34 tech : integer := 0;
35 Mem_use : integer := use_RAM;
36 fifoCount : integer range 2 to 32 := 8;
37 DataSz : integer range 1 to 32 := 8;
38 abits : integer range 2 to 12 := 8
39 );
40 port(
41 rstn : in std_logic;
42 ReUse : in std_logic;
43 rclk : in std_logic;
44 ren : in std_logic;
45 rdata : out std_logic_vector(DataSz-1 downto 0);
46 empty : out std_logic;
47 raddr : out std_logic_vector(abits-1 downto 0);
48 wclk : in std_logic;
49 wen : in std_logic;
50 wdata : in std_logic_vector(DataSz-1 downto 0);
51 full : out std_logic;
52 waddr : out std_logic_vector(abits-1 downto 0)
53 );
54 end entity;
55
56 architecture Ar_FIFO_pipeline of FIFO_pipeline is
57
58 type FX2State is (idle);
59
60 Signal DATA0 : std_logic_vector(DataSz-1 downto 0);
61 Signal FULL_REN0,WEN_EMPTY0 : std_logic;
62
63 begin
64
65
66 FIFO0: lpp_fifo
67 generic map(
68 tech => tech,
69 Mem_use => Mem_use,
70 Enable_ReUse => '0',
71 DataSz => DataSz,
72 abits => abits
73 )
74 port map(
75 rstn => rstn,
76 ReUse => '0',
77 rclk => rclk,
78 ren => FULL_REN0,
79 rdata => DATA0,
80 empty => WEN_EMPTY0,
81 raddr => open,
82 wclk => wclk,
83 wen => wen,
84 wdata => wdata,
85 full => full,
86 waddr => open
87 );
88
89 FIFO1: lpp_fifo
90 generic map(
91 tech => tech,
92 Mem_use => Mem_use,
93 Enable_ReUse => '0',
94 DataSz => DataSz,
95 abits => abits
96 )
97 port map(
98 rstn => rstn,
99 ReUse => '0',
100 rclk => rclk,
101 ren => ren,
102 rdata => rdata,
103 empty => empty,
104 raddr => open,
105 wclk => wclk,
106 wen => WEN_EMPTY0,
107 wdata => DATA0,
108 full => FULL_REN0,
109 waddr => open
110 );
111
112 end ar_FIFO_pipeline;
113
114
115
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@@ -1,6 +1,6
1 1 GRLIB=../..
2 2 VHDLIB=../..
3 TOP=top
3 TOP=TOP_EGSE2
4 4 BOARD=GSE_ICI
5 5 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
6 6 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
@@ -9,7 +9,7 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
9 9 EFFORT=high
10 10 XSTOPT=
11 11 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
12 VHDLSYNFILES=config.vhd EGSE_ICI.vhd
13 13 VHDLSIMFILES=testbench.vhd
14 14 SIMTOP=testbench
15 15 SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
@@ -20,9 +20,10 CLEAN=soft-clean
20 20
21 21 TECHLIBS = proasic3
22 22 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
23 tmtc openchip hynix ihp gleichmann micron usbhc
23 tmtc openchip hynix ihp gleichmann micron usbhc spw fmf gsi eth spansion esa
24 24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 spacewire leon3 leon3ft sparc can greth net gr1553b lpp_waveform \
26 lpp_dma
26 27
27 28 FILESKIP = i2cmst.vhd
28 29
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@@ -7,380 +7,314
7 7 # timing analyzer and USE_TIMEQUEST_TIMING_ANALYZER defaults to "ON"
8 8 # set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER "OFF"
9 9
10 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/version.vhd -library grlib
11 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/config.vhd -library grlib
12 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/stdlib.vhd -library grlib
13 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/sparc/sparc.vhd -library grlib
14 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/modgen/multlib.vhd -library grlib
15 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/modgen/leaves.vhd -library grlib
16 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/amba.vhd -library grlib
17 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/devices.vhd -library grlib
18 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/defmst.vhd -library grlib
19 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/apbctrl.vhd -library grlib
20 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/ahbctrl.vhd -library grlib
21 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/dma2ahb_pkg.vhd -library grlib
22 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/dma2ahb.vhd -library grlib
23 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/gencomp/gencomp.vhd -library techmap
24 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/gencomp/netcomp.vhd -library techmap
25 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/inferred/memory_inferred.vhd -library techmap
26 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/inferred/ddr_inferred.vhd -library techmap
27 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/inferred/mul_inferred.vhd -library techmap
28 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/inferred/ddr_phy_inferred.vhd -library techmap
29 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/allclkgen.vhd -library techmap
30 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/allddr.vhd -library techmap
31 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/allmem.vhd -library techmap
32 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/allmul.vhd -library techmap
33 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/allpads.vhd -library techmap
34 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/alltap.vhd -library techmap
35 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/clkgen.vhd -library techmap
36 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/clkmux.vhd -library techmap
37 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/clkand.vhd -library techmap
38 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/ddr_ireg.vhd -library techmap
39 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/ddr_oreg.vhd -library techmap
40 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/ddrphy.vhd -library techmap
41 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram.vhd -library techmap
42 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram64.vhd -library techmap
43 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram_2p.vhd -library techmap
44 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram_dp.vhd -library techmap
45 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncfifo.vhd -library techmap
46 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/regfile_3p.vhd -library techmap
47 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/tap.vhd -library techmap
48 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/techbuf.vhd -library techmap
49 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/nandtree.vhd -library techmap
50 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/clkpad.vhd -library techmap
51 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/clkpad_ds.vhd -library techmap
52 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/inpad.vhd -library techmap
53 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/inpad_ds.vhd -library techmap
54 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/iodpad.vhd -library techmap
55 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/iopad.vhd -library techmap
56 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/iopad_ds.vhd -library techmap
57 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/lvds_combo.vhd -library techmap
58 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/odpad.vhd -library techmap
59 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/outpad.vhd -library techmap
60 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/outpad_ds.vhd -library techmap
61 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/toutpad.vhd -library techmap
62 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/skew_outpad.vhd -library techmap
63 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/grspwc_net.vhd -library techmap
64 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/grspwc2_net.vhd -library techmap
65 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/grlfpw_net.vhd -library techmap
66 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/grfpw_net.vhd -library techmap
67 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/leon4_net.vhd -library techmap
68 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/mul_61x61.vhd -library techmap
69 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/cpu_disas_net.vhd -library techmap
70 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/grusbhc_net.vhd -library techmap
71 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/ringosc.vhd -library techmap
72 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/ssrctrl_net.vhd -library techmap
73 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/system_monitor.vhd -library techmap
74 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/grgates.vhd -library techmap
75 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/inpad_ddr.vhd -library techmap
76 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/outpad_ddr.vhd -library techmap
77 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/iopad_ddr.vhd -library techmap
78 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram128bw.vhd -library techmap
79 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram128.vhd -library techmap
80 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram156bw.vhd -library techmap
81 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/techmult.vhd -library techmap
82 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/spictrl_net.vhd -library techmap
83 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/scanreg.vhd -library techmap
84 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/spw/comp/spwcomp.vhd -library spw
85 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/spw/wrapper/grspw_gen.vhd -library spw
86 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/spw/wrapper/grspw2_gen.vhd -library spw
87 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/comp/ethcomp.vhd -library eth
88 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/greth_pkg.vhd -library eth
89 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/eth_rstgen.vhd -library eth
90 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/eth_edcl_ahb_mst.vhd -library eth
91 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/eth_ahb_mst.vhd -library eth
92 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/greth_tx.vhd -library eth
93 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/greth_rx.vhd -library eth
94 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/grethc.vhd -library eth
95 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/wrapper/greth_gen.vhd -library eth
96 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/wrapper/greth_gbit_gen.vhd -library eth
97 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/opencores/occomp/occomp.vhd -library opencores
98 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/opencores/can/cancomp.vhd -library opencores
99 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/opencores/can/can_top.vhd -library opencores
100 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/arith/arith.vhd -library gaisler
101 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/arith/mul32.vhd -library gaisler
102 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/arith/div32.vhd -library gaisler
103 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/memctrl.vhd -library gaisler
104 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/sdctrl.vhd -library gaisler
105 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/sdctrl64.vhd -library gaisler
106 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/sdmctrl.vhd -library gaisler
107 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/srctrl.vhd -library gaisler
108 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/spimctrl.vhd -library gaisler
109 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3.vhd -library gaisler
110 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmuconfig.vhd -library gaisler
111 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmuiface.vhd -library gaisler
112 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/libmmu.vhd -library gaisler
113 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/libiu.vhd -library gaisler
114 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/libcache.vhd -library gaisler
115 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/libproc3.vhd -library gaisler
116 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/cachemem.vhd -library gaisler
117 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_icache.vhd -library gaisler
118 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_dcache.vhd -library gaisler
119 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_acache.vhd -library gaisler
120 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmutlbcam.vhd -library gaisler
121 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmulrue.vhd -library gaisler
122 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmulru.vhd -library gaisler
123 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmutlb.vhd -library gaisler
124 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmutw.vhd -library gaisler
125 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu.vhd -library gaisler
126 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_cache.vhd -library gaisler
127 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/cpu_disasx.vhd -library gaisler
128 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/iu3.vhd -library gaisler
129 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grfpwx.vhd -library gaisler
130 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mfpwx.vhd -library gaisler
131 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grlfpwx.vhd -library gaisler
132 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/tbufmem.vhd -library gaisler
133 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/dsu3x.vhd -library gaisler
134 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/dsu3.vhd -library gaisler
135 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/proc3.vhd -library gaisler
136 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3s.vhd -library gaisler
137 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3cg.vhd -library gaisler
138 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/irqmp.vhd -library gaisler
139 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grfpwxsh.vhd -library gaisler
140 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grfpushwx.vhd -library gaisler
141 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3sh.vhd -library gaisler
142 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3ft/leon3ft.vhd -library gaisler
143 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can.vhd -library gaisler
144 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_mod.vhd -library gaisler
145 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_oc.vhd -library gaisler
146 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_mc.vhd -library gaisler
147 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/canmux.vhd -library gaisler
148 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_rd.vhd -library gaisler
149 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/misc.vhd -library gaisler
150 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/rstgen.vhd -library gaisler
151 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/gptimer.vhd -library gaisler
152 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbram.vhd -library gaisler
153 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbdpram.vhd -library gaisler
154 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace.vhd -library gaisler
155 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace_mb.vhd -library gaisler
156 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace_mmb.vhd -library gaisler
157 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbmst.vhd -library gaisler
158 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grgpio.vhd -library gaisler
159 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbstat.vhd -library gaisler
160 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/logan.vhd -library gaisler
161 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/apbps2.vhd -library gaisler
162 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/charrom_package.vhd -library gaisler
163 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/charrom.vhd -library gaisler
164 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/apbvga.vhd -library gaisler
165 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/svgactrl.vhd -library gaisler
166 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/i2cmst_gen.vhd -library gaisler
167 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/spictrlx.vhd -library gaisler
168 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/spictrl.vhd -library gaisler
169 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/i2cslv.vhd -library gaisler
170 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/wild.vhd -library gaisler
171 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/wild2ahb.vhd -library gaisler
172 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grsysmon.vhd -library gaisler
173 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/gracectrl.vhd -library gaisler
174 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grgpreg.vhd -library gaisler
175 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbmst2.vhd -library gaisler
176 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahb_mst_iface.vhd -library gaisler
177 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/net/net.vhd -library gaisler
178 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/uart.vhd -library gaisler
179 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/libdcom.vhd -library gaisler
180 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/apbuart.vhd -library gaisler
181 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/dcom.vhd -library gaisler
182 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/dcom_uart.vhd -library gaisler
183 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/ahbuart.vhd -library gaisler
184 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtag.vhd -library gaisler
185 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/libjtagcom.vhd -library gaisler
186 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtagcom.vhd -library gaisler
187 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/ahbjtag.vhd -library gaisler
188 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/ahbjtag_bsd.vhd -library gaisler
189 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/bscanregs.vhd -library gaisler
190 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/bscanregsbd.vhd -library gaisler
191 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/ethernet_mac.vhd -library gaisler
192 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth.vhd -library gaisler
193 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_mb.vhd -library gaisler
194 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_gbit.vhd -library gaisler
195 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_gbit_mb.vhd -library gaisler
196 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/grethm.vhd -library gaisler
197 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/spacewire.vhd -library gaisler
198 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspw.vhd -library gaisler
199 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspw2.vhd -library gaisler
200 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspwm.vhd -library gaisler
201 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/gr1553b/gr1553b_pkg.vhd -library gaisler
202 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/esa/memoryctrl/memoryctrl.vhd -library esa
203 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/esa/memoryctrl/mctrl.vhd -library esa
204 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd -library lpp
205 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd -library lpp
206 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd -library lpp
207 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd -library lpp
208 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd -library lpp
209 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd -library lpp
210 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd -library lpp
211 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd -library lpp
212 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd -library lpp
213 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd -library lpp
214 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/APB_IIR_Filter.vhd -library lpp
215 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTER.vhd -library lpp
216 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd -library lpp
217 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd -library lpp
218 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd -library lpp
219 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd -library lpp
220 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd -library lpp
221 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd -library lpp
222 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd -library lpp
223 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd -library lpp
224 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM.vhd -library lpp
225 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd -library lpp
226 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd -library lpp
227 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd -library lpp
228 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd -library lpp
229 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd -library lpp
230 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/Top_IIR.vhd -library lpp
231 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/iir_filter.vhd -library lpp
232 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd -library lpp
233 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/APB_FFT.vhd -library lpp
234 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/APB_FFT_half.vhd -library lpp
235 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd -library lpp
236 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd -library lpp
237 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd.bak -library lpp
238 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFTamont.vhd -library lpp
239 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFTaval.vhd -library lpp
240 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd -library lpp
241 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd.bak -library lpp
242 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd -library lpp
243 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd -library lpp
244 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/ADDRcntr.vhd -library lpp
245 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/ALU.vhd -library lpp
246 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Adder.vhd -library lpp
247 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Clk_Divider2.vhd -library lpp
248 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Clk_divider.vhd -library lpp
249 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC.vhd -library lpp
250 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd -library lpp
251 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_MUX.vhd -library lpp
252 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_MUX2.vhd -library lpp
253 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_REG.vhd -library lpp
254 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MUX2.vhd -library lpp
255 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MUXN.vhd -library lpp
256 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Multiplier.vhd -library lpp
257 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/REG.vhd -library lpp
258 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/SYNC_FF.vhd -library lpp
259 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Shifter.vhd -library lpp
260 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/TwoComplementer.vhd -library lpp
261 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/general_purpose.vhd -library lpp
262 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/APB_AMR.vhd -library lpp
263 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Clock_multi.vhd -library lpp
264 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Dephaseur.vhd -library lpp
265 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Gene_Rz.vhd -library lpp
266 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/bclk_reg.vhd -library lpp
267 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/lpp_AMR.vhd -library lpp
268 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_balise/APB_Balise.vhd -library lpp
269 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_balise/lpp_balise.vhd -library lpp
270 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/APB_Delay.vhd -library lpp
271 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/TimerDelay.vhd -library lpp
272 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/lpp_delay.vhd -library lpp
273 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lfr_time_management/apb_lfr_time_management.vhd -library lpp
274 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lfr_time_management/lfr_time_management.vhd -library lpp
275 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lfr_time_management/lpp_lfr_time_management.vhd -library lpp
276 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd -library lpp
277 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_drvr_sync.vhd -library lpp
278 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd -library lpp
279 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS1274_drvr.vhd -library lpp
280 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS1278_drvr.vhd -library lpp
281 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd -library lpp
282 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/RHF1401.vhd -library lpp
283 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/WriteGen_ADC.vhd -library lpp
284 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/dual_ADS1278_drvr.vhd -library lpp
285 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd -library lpp
286 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd -library lpp
287 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/top_ad_conv.vhd -library lpp
288 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd -library lpp
289 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd -library lpp
290 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd -library lpp
291 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_amba/apb_devices_list.vhd -library lpp
292 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_amba/lpp_amba.vhd -library lpp
293 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/bootrom.vhd -library lpp
294 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd -library lpp
295 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd -library lpp
296 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/APB_CNA.vhd -library lpp
297 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/CNA_TabloC.vhd -library lpp
298 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/Convertisseur_config.vhd -library lpp
299 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/Gene_SYNC.vhd -library lpp
300 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/Serialize.vhd -library lpp
301 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/Systeme_Clock.vhd -library lpp
302 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/lpp_cna.vhd -library lpp
303 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_demux/DEMUX.vhd -library lpp
304 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_demux/lpp_demux.vhd -library lpp
305 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd -library lpp
306 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma.vhd -library lpp
307 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_apbreg.vhd -library lpp
308 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_fsm.vhd -library lpp
309 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd -library lpp
310 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd -library lpp
311 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd -library lpp
312 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd -library lpp
313 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_Header/HeaderBuilder.vhd -library lpp
314 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_Header/lpp_Header.vhd -library lpp
315 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd -library lpp
316 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd.bak -library lpp
317 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/APB_Matrix.vhd -library lpp
318 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Dispatch.vhd -library lpp
319 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/DriveInputs.vhd -library lpp
320 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/GetResult.vhd -library lpp
321 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd -library lpp
322 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd.bak -library lpp
323 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Matrix.vhd -library lpp
324 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd -library lpp
325 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd -library lpp
326 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd.bak -library lpp
327 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Starter.vhd -library lpp
328 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopMatrix_PDR.vhd -library lpp
329 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd -library lpp
330 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Top_MatrixSpec.vhd -library lpp
331 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/lpp_matrix.vhd -library lpp
332 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/APB_FIFO.vhd -library lpp
333 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/APB_FIFO.vhd.bak -library lpp
334 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/FillFifo.vhd -library lpp
335 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/SSRAM_plugin.vhd -library lpp
336 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/SSRAM_plugin_vsim.vhd -library lpp
337 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lppFIFOxN.vhd -library lpp
338 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lppFIFOxN.vhd.bak -library lpp
339 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_FIFO.vhd -library lpp
340 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_memory.vhd -library lpp
341 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_memory.vhd.bak -library lpp
342 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd -library lpp
343 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd -library lpp
344 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd -library lpp
345 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd -library lpp
346 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd -library lpp
347 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_acq.vhd -library lpp
348 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_acq.vhd.bak -library lpp
349 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_apbreg.vhd -library lpp
350 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr.vhd -library lpp
351 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd -library lpp
352 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak -library lpp
353 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_wf_picker.vhd -library lpp
354 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd -library lpp
355 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_wf_picker_ip_whitout_filter.vhd -library lpp
356 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/top_wf_picker.vhd -library lpp
357 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/APB_UART.vhd -library lpp
358 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/BaudGen.vhd -library lpp
359 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/Shift_REG.vhd -library lpp
360 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/UART.vhd -library lpp
361 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/lpp_uart.vhd -library lpp
362 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/APB_USB.vhd -library lpp
363 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/FX2_Driver.vhd -library lpp
364 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/RWbuf.vhd -library lpp
365 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/lpp_usb.vhd -library lpp
366 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform.vhd -library lpp
367 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd -library lpp
368 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma.vhd -library lpp
369 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd -library lpp
370 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma_selectaddress.vhd -library lpp
371 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma_send_Nword.vhd -library lpp
372 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd -library lpp
373 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd -library lpp
374 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd -library lpp
375 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd -library lpp
376 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd -library lpp
377 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd -library lpp
378 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_valid_ack.vhd -library lpp
379 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/MinF_Cntr.vhd -library lpp
380 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Rocket_PCM_Encoder.vhd -library lpp
381 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Serial_Driver.vhd -library lpp
382 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Serial_Driver_Multiplexor.vhd -library lpp
383 set_global_assignment -name VHDL_FILE C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Word_Cntr.vhd -library lpp
10 set_global_assignment -name VHDL_FILE ../../lib/grlib/stdlib/version.vhd -library grlib
11 set_global_assignment -name VHDL_FILE ../../lib/grlib/stdlib/config.vhd -library grlib
12 set_global_assignment -name VHDL_FILE ../../lib/grlib/stdlib/stdlib.vhd -library grlib
13 set_global_assignment -name VHDL_FILE ../../lib/grlib/modgen/multlib.vhd -library grlib
14 set_global_assignment -name VHDL_FILE ../../lib/grlib/modgen/leaves.vhd -library grlib
15 set_global_assignment -name VHDL_FILE ../../lib/grlib/amba/amba.vhd -library grlib
16 set_global_assignment -name VHDL_FILE ../../lib/grlib/amba/devices.vhd -library grlib
17 set_global_assignment -name VHDL_FILE ../../lib/grlib/amba/defmst.vhd -library grlib
18 set_global_assignment -name VHDL_FILE ../../lib/grlib/amba/apbctrl.vhd -library grlib
19 set_global_assignment -name VHDL_FILE ../../lib/grlib/amba/ahbctrl.vhd -library grlib
20 set_global_assignment -name VHDL_FILE ../../lib/grlib/amba/dma2ahb_pkg.vhd -library grlib
21 set_global_assignment -name VHDL_FILE ../../lib/grlib/amba/dma2ahb.vhd -library grlib
22 set_global_assignment -name VHDL_FILE ../../lib/techmap/gencomp/gencomp.vhd -library techmap
23 set_global_assignment -name VHDL_FILE ../../lib/techmap/gencomp/netcomp.vhd -library techmap
24 set_global_assignment -name VHDL_FILE ../../lib/techmap/inferred/memory_inferred.vhd -library techmap
25 set_global_assignment -name VHDL_FILE ../../lib/techmap/inferred/ddr_inferred.vhd -library techmap
26 set_global_assignment -name VHDL_FILE ../../lib/techmap/inferred/mul_inferred.vhd -library techmap
27 set_global_assignment -name VHDL_FILE ../../lib/techmap/inferred/ddr_phy_inferred.vhd -library techmap
28 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/allclkgen.vhd -library techmap
29 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/allddr.vhd -library techmap
30 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/allmem.vhd -library techmap
31 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/allmul.vhd -library techmap
32 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/allpads.vhd -library techmap
33 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/alltap.vhd -library techmap
34 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/clkgen.vhd -library techmap
35 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/clkmux.vhd -library techmap
36 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/clkand.vhd -library techmap
37 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/ddr_ireg.vhd -library techmap
38 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/ddr_oreg.vhd -library techmap
39 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/ddrphy.vhd -library techmap
40 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/syncram.vhd -library techmap
41 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/syncram64.vhd -library techmap
42 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/syncram_2p.vhd -library techmap
43 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/syncram_dp.vhd -library techmap
44 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/syncfifo.vhd -library techmap
45 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/regfile_3p.vhd -library techmap
46 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/tap.vhd -library techmap
47 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/techbuf.vhd -library techmap
48 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/nandtree.vhd -library techmap
49 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/clkpad.vhd -library techmap
50 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/clkpad_ds.vhd -library techmap
51 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/inpad.vhd -library techmap
52 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/inpad_ds.vhd -library techmap
53 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/iodpad.vhd -library techmap
54 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/iopad.vhd -library techmap
55 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/iopad_ds.vhd -library techmap
56 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/lvds_combo.vhd -library techmap
57 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/odpad.vhd -library techmap
58 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/outpad.vhd -library techmap
59 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/outpad_ds.vhd -library techmap
60 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/toutpad.vhd -library techmap
61 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/skew_outpad.vhd -library techmap
62 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/grspwc_net.vhd -library techmap
63 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/grspwc2_net.vhd -library techmap
64 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/grlfpw_net.vhd -library techmap
65 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/grfpw_net.vhd -library techmap
66 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/leon4_net.vhd -library techmap
67 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/mul_61x61.vhd -library techmap
68 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/cpu_disas_net.vhd -library techmap
69 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/grusbhc_net.vhd -library techmap
70 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/ringosc.vhd -library techmap
71 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/ssrctrl_net.vhd -library techmap
72 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/system_monitor.vhd -library techmap
73 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/grgates.vhd -library techmap
74 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/inpad_ddr.vhd -library techmap
75 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/outpad_ddr.vhd -library techmap
76 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/iopad_ddr.vhd -library techmap
77 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/syncram128bw.vhd -library techmap
78 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/syncram128.vhd -library techmap
79 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/syncram156bw.vhd -library techmap
80 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/techmult.vhd -library techmap
81 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/spictrl_net.vhd -library techmap
82 set_global_assignment -name VHDL_FILE ../../lib/techmap/maps/scanreg.vhd -library techmap
83 set_global_assignment -name VHDL_FILE ../../lib/opencores/occomp/occomp.vhd -library opencores
84 set_global_assignment -name VHDL_FILE ../../lib/gaisler/arith/arith.vhd -library gaisler
85 set_global_assignment -name VHDL_FILE ../../lib/gaisler/arith/mul32.vhd -library gaisler
86 set_global_assignment -name VHDL_FILE ../../lib/gaisler/arith/div32.vhd -library gaisler
87 set_global_assignment -name VHDL_FILE ../../lib/gaisler/memctrl/memctrl.vhd -library gaisler
88 set_global_assignment -name VHDL_FILE ../../lib/gaisler/memctrl/sdctrl.vhd -library gaisler
89 set_global_assignment -name VHDL_FILE ../../lib/gaisler/memctrl/sdctrl64.vhd -library gaisler
90 set_global_assignment -name VHDL_FILE ../../lib/gaisler/memctrl/sdmctrl.vhd -library gaisler
91 set_global_assignment -name VHDL_FILE ../../lib/gaisler/memctrl/srctrl.vhd -library gaisler
92 set_global_assignment -name VHDL_FILE ../../lib/gaisler/memctrl/spimctrl.vhd -library gaisler
93 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/misc.vhd -library gaisler
94 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/rstgen.vhd -library gaisler
95 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/gptimer.vhd -library gaisler
96 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/ahbram.vhd -library gaisler
97 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/ahbdpram.vhd -library gaisler
98 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/ahbtrace.vhd -library gaisler
99 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/ahbtrace_mb.vhd -library gaisler
100 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/ahbtrace_mmb.vhd -library gaisler
101 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/ahbmst.vhd -library gaisler
102 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/grgpio.vhd -library gaisler
103 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/ahbstat.vhd -library gaisler
104 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/logan.vhd -library gaisler
105 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/apbps2.vhd -library gaisler
106 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/charrom_package.vhd -library gaisler
107 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/charrom.vhd -library gaisler
108 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/apbvga.vhd -library gaisler
109 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/svgactrl.vhd -library gaisler
110 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/i2cmst_gen.vhd -library gaisler
111 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/spictrlx.vhd -library gaisler
112 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/spictrl.vhd -library gaisler
113 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/i2cslv.vhd -library gaisler
114 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/wild.vhd -library gaisler
115 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/wild2ahb.vhd -library gaisler
116 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/grsysmon.vhd -library gaisler
117 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/gracectrl.vhd -library gaisler
118 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/grgpreg.vhd -library gaisler
119 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/ahbmst2.vhd -library gaisler
120 set_global_assignment -name VHDL_FILE ../../lib/gaisler/misc/ahb_mst_iface.vhd -library gaisler
121 set_global_assignment -name VHDL_FILE ../../lib/gaisler/net/net.vhd -library gaisler
122 set_global_assignment -name VHDL_FILE ../../lib/gaisler/uart/uart.vhd -library gaisler
123 set_global_assignment -name VHDL_FILE ../../lib/gaisler/uart/libdcom.vhd -library gaisler
124 set_global_assignment -name VHDL_FILE ../../lib/gaisler/uart/apbuart.vhd -library gaisler
125 set_global_assignment -name VHDL_FILE ../../lib/gaisler/uart/dcom.vhd -library gaisler
126 set_global_assignment -name VHDL_FILE ../../lib/gaisler/uart/dcom_uart.vhd -library gaisler
127 set_global_assignment -name VHDL_FILE ../../lib/gaisler/uart/ahbuart.vhd -library gaisler
128 set_global_assignment -name VHDL_FILE ../../lib/gaisler/jtag/jtag.vhd -library gaisler
129 set_global_assignment -name VHDL_FILE ../../lib/gaisler/jtag/libjtagcom.vhd -library gaisler
130 set_global_assignment -name VHDL_FILE ../../lib/gaisler/jtag/jtagcom.vhd -library gaisler
131 set_global_assignment -name VHDL_FILE ../../lib/gaisler/jtag/ahbjtag.vhd -library gaisler
132 set_global_assignment -name VHDL_FILE ../../lib/gaisler/jtag/ahbjtag_bsd.vhd -library gaisler
133 set_global_assignment -name VHDL_FILE ../../lib/gaisler/jtag/bscanregs.vhd -library gaisler
134 set_global_assignment -name VHDL_FILE ../../lib/gaisler/jtag/bscanregsbd.vhd -library gaisler
135 set_global_assignment -name VHDL_FILE ../../lib/gaisler/gr1553b/gr1553b_pkg.vhd -library gaisler
136 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd -library lpp
137 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd -library lpp
138 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd -library lpp
139 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd -library lpp
140 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd -library lpp
141 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd -library lpp
142 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd -library lpp
143 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd -library lpp
144 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd -library lpp
145 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd -library lpp
146 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/APB_IIR_Filter.vhd -library lpp
147 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTER.vhd -library lpp
148 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd -library lpp
149 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd -library lpp
150 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd -library lpp
151 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd -library lpp
152 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd -library lpp
153 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd -library lpp
154 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd -library lpp
155 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd -library lpp
156 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM.vhd -library lpp
157 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd -library lpp
158 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd -library lpp
159 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd -library lpp
160 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd -library lpp
161 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd -library lpp
162 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/Top_IIR.vhd -library lpp
163 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/iir_filter.vhd -library lpp
164 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd -library lpp
165 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/APB_FFT.vhd -library lpp
166 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/APB_FFT_half.vhd -library lpp
167 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd -library lpp
168 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd -library lpp
169 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd.bak -library lpp
170 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFTamont.vhd -library lpp
171 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFTaval.vhd -library lpp
172 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd -library lpp
173 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd.bak -library lpp
174 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd -library lpp
175 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd -library lpp
176 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/ADDRcntr.vhd -library lpp
177 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/ALU.vhd -library lpp
178 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/Adder.vhd -library lpp
179 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/Clk_Divider2.vhd -library lpp
180 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/Clk_divider.vhd -library lpp
181 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC.vhd -library lpp
182 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd -library lpp
183 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_MUX.vhd -library lpp
184 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_MUX2.vhd -library lpp
185 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_REG.vhd -library lpp
186 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MUX2.vhd -library lpp
187 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MUXN.vhd -library lpp
188 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/Multiplier.vhd -library lpp
189 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/REG.vhd -library lpp
190 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/SYNC_FF.vhd -library lpp
191 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/Shifter.vhd -library lpp
192 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/TwoComplementer.vhd -library lpp
193 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/general_purpose.vhd -library lpp
194 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/APB_AMR.vhd -library lpp
195 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Clock_multi.vhd -library lpp
196 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Dephaseur.vhd -library lpp
197 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Gene_Rz.vhd -library lpp
198 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/bclk_reg.vhd -library lpp
199 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/lpp_AMR.vhd -library lpp
200 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_balise/APB_Balise.vhd -library lpp
201 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_balise/lpp_balise.vhd -library lpp
202 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/APB_Delay.vhd -library lpp
203 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/TimerDelay.vhd -library lpp
204 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/lpp_delay.vhd -library lpp
205 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lfr_time_management/apb_lfr_time_management.vhd -library lpp
206 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lfr_time_management/lfr_time_management.vhd -library lpp
207 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lfr_time_management/lpp_lfr_time_management.vhd -library lpp
208 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd -library lpp
209 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_drvr_sync.vhd -library lpp
210 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd -library lpp
211 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS1274_drvr.vhd -library lpp
212 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS1278_drvr.vhd -library lpp
213 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd -library lpp
214 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/RHF1401.vhd -library lpp
215 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/WriteGen_ADC.vhd -library lpp
216 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/dual_ADS1278_drvr.vhd -library lpp
217 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd -library lpp
218 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd -library lpp
219 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/top_ad_conv.vhd -library lpp
220 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd -library lpp
221 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd -library lpp
222 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd -library lpp
223 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_amba/apb_devices_list.vhd -library lpp
224 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_amba/lpp_amba.vhd -library lpp
225 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/bootrom.vhd -library lpp
226 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd -library lpp
227 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd -library lpp
228 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/APB_CNA.vhd -library lpp
229 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/CNA_TabloC.vhd -library lpp
230 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/Convertisseur_config.vhd -library lpp
231 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/Gene_SYNC.vhd -library lpp
232 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/Serialize.vhd -library lpp
233 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/Systeme_Clock.vhd -library lpp
234 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/lpp_cna.vhd -library lpp
235 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_demux/DEMUX.vhd -library lpp
236 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_demux/lpp_demux.vhd -library lpp
237 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd -library lpp
238 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma.vhd -library lpp
239 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_apbreg.vhd -library lpp
240 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_fsm.vhd -library lpp
241 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd -library lpp
242 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd -library lpp
243 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd -library lpp
244 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd -library lpp
245 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_Header/HeaderBuilder.vhd -library lpp
246 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_Header/lpp_Header.vhd -library lpp
247 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd -library lpp
248 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd.bak -library lpp
249 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/APB_Matrix.vhd -library lpp
250 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Dispatch.vhd -library lpp
251 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/DriveInputs.vhd -library lpp
252 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/GetResult.vhd -library lpp
253 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd -library lpp
254 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd.bak -library lpp
255 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Matrix.vhd -library lpp
256 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd -library lpp
257 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd -library lpp
258 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd.bak -library lpp
259 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Starter.vhd -library lpp
260 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopMatrix_PDR.vhd -library lpp
261 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd -library lpp
262 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Top_MatrixSpec.vhd -library lpp
263 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/lpp_matrix.vhd -library lpp
264 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/APB_FIFO.vhd -library lpp
265 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/APB_FIFO.vhd.bak -library lpp
266 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/FIFO_pipeline.vhd -library lpp
267 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/FillFifo.vhd -library lpp
268 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/SSRAM_plugin.vhd -library lpp
269 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/SSRAM_plugin_vsim.vhd -library lpp
270 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/lppFIFOxN.vhd -library lpp
271 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/lppFIFOxN.vhd.bak -library lpp
272 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_FIFO.vhd -library lpp
273 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_memory.vhd -library lpp
274 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_memory.vhd.bak -library lpp
275 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd -library lpp
276 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd -library lpp
277 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd -library lpp
278 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd -library lpp
279 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd -library lpp
280 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_acq.vhd -library lpp
281 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_acq.vhd.bak -library lpp
282 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_apbreg.vhd -library lpp
283 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr.vhd -library lpp
284 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd -library lpp
285 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak -library lpp
286 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_wf_picker.vhd -library lpp
287 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd -library lpp
288 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_wf_picker_ip_whitout_filter.vhd -library lpp
289 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/top_wf_picker.vhd -library lpp
290 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_uart/APB_UART.vhd -library lpp
291 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_uart/BaudGen.vhd -library lpp
292 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_uart/Shift_REG.vhd -library lpp
293 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_uart/UART.vhd -library lpp
294 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_uart/lpp_uart.vhd -library lpp
295 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_usb/APB_USB.vhd -library lpp
296 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_usb/FX2_Driver.vhd -library lpp
297 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_usb/FX2_WithFIFO.vhd -library lpp
298 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_usb/RWbuf.vhd -library lpp
299 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_usb/lpp_usb.vhd -library lpp
300 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform.vhd -library lpp
301 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd -library lpp
302 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma.vhd -library lpp
303 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd -library lpp
304 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma_selectaddress.vhd -library lpp
305 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma_send_Nword.vhd -library lpp
306 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd -library lpp
307 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd -library lpp
308 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd -library lpp
309 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd -library lpp
310 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd -library lpp
311 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd -library lpp
312 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_valid_ack.vhd -library lpp
313 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/MinF_Cntr.vhd -library lpp
314 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Rocket_PCM_Encoder.vhd -library lpp
315 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Serial_Driver.vhd -library lpp
316 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Serial_Driver_Multiplexor.vhd -library lpp
317 set_global_assignment -name VHDL_FILE ../../lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Word_Cntr.vhd -library lpp
384 318 set_global_assignment -name VHDL_FILE config.vhd
385 319 set_global_assignment -name VHDL_FILE ahbrom.vhd
386 320 set_global_assignment -name VHDL_FILE leon3mp.vhd
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@@ -14,2056 +14,1682
14 14 <version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
15 15
16 16 <files>
17 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/boards/GSE_ICI/top.ucf" xil_pn:type="FILE_UCF">
17 <file xil_pn:name="../../boards/GSE_ICI/top.ucf" xil_pn:type="FILE_UCF">
18 18 <association xil_pn:name="Implementation"/>
19 19 </file>
20 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/version.vhd" xil_pn:type="FILE_VHDL">
20 <file xil_pn:name="../../lib/grlib/stdlib/version.vhd" xil_pn:type="FILE_VHDL">
21 21 <association xil_pn:name="BehavioralSimulation"/>
22 22 <association xil_pn:name="Implementation"/>
23 23 <library xil_pn:name="grlib"/>
24 24 </file>
25 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/config.vhd" xil_pn:type="FILE_VHDL">
25 <file xil_pn:name="../../lib/grlib/stdlib/config.vhd" xil_pn:type="FILE_VHDL">
26 26 <association xil_pn:name="BehavioralSimulation"/>
27 27 <association xil_pn:name="Implementation"/>
28 28 <library xil_pn:name="grlib"/>
29 29 </file>
30 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/stdlib.vhd" xil_pn:type="FILE_VHDL">
30 <file xil_pn:name="../../lib/grlib/stdlib/stdlib.vhd" xil_pn:type="FILE_VHDL">
31 31 <association xil_pn:name="BehavioralSimulation"/>
32 32 <association xil_pn:name="Implementation"/>
33 33 <library xil_pn:name="grlib"/>
34 34 </file>
35 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/stdio.vhd" xil_pn:type="FILE_VHDL">
35 <file xil_pn:name="../../lib/grlib/stdlib/stdio.vhd" xil_pn:type="FILE_VHDL">
36 36 <association xil_pn:name="BehavioralSimulation"/>
37 37 <library xil_pn:name="grlib"/>
38 38 </file>
39 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/testlib.vhd" xil_pn:type="FILE_VHDL">
39 <file xil_pn:name="../../lib/grlib/stdlib/testlib.vhd" xil_pn:type="FILE_VHDL">
40 40 <association xil_pn:name="BehavioralSimulation"/>
41 41 <library xil_pn:name="grlib"/>
42 42 </file>
43 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/util/util.vhd" xil_pn:type="FILE_VHDL">
43 <file xil_pn:name="../../lib/grlib/util/util.vhd" xil_pn:type="FILE_VHDL">
44 44 <association xil_pn:name="BehavioralSimulation"/>
45 45 <library xil_pn:name="grlib"/>
46 46 </file>
47 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/sparc/sparc.vhd" xil_pn:type="FILE_VHDL">
47 <file xil_pn:name="../../lib/grlib/modgen/multlib.vhd" xil_pn:type="FILE_VHDL">
48 48 <association xil_pn:name="BehavioralSimulation"/>
49 49 <association xil_pn:name="Implementation"/>
50 50 <library xil_pn:name="grlib"/>
51 51 </file>
52 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/sparc/sparc_disas.vhd" xil_pn:type="FILE_VHDL">
53 <association xil_pn:name="BehavioralSimulation"/>
54 <library xil_pn:name="grlib"/>
55 </file>
56 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/sparc/cpu_disas.vhd" xil_pn:type="FILE_VHDL">
57 <association xil_pn:name="BehavioralSimulation"/>
58 <library xil_pn:name="grlib"/>
59 </file>
60 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/modgen/multlib.vhd" xil_pn:type="FILE_VHDL">
52 <file xil_pn:name="../../lib/grlib/modgen/leaves.vhd" xil_pn:type="FILE_VHDL">
61 53 <association xil_pn:name="BehavioralSimulation"/>
62 54 <association xil_pn:name="Implementation"/>
63 55 <library xil_pn:name="grlib"/>
64 56 </file>
65 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/modgen/leaves.vhd" xil_pn:type="FILE_VHDL">
57 <file xil_pn:name="../../lib/grlib/amba/amba.vhd" xil_pn:type="FILE_VHDL">
66 58 <association xil_pn:name="BehavioralSimulation"/>
67 59 <association xil_pn:name="Implementation"/>
68 60 <library xil_pn:name="grlib"/>
69 61 </file>
70 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/amba.vhd" xil_pn:type="FILE_VHDL">
62 <file xil_pn:name="../../lib/grlib/amba/devices.vhd" xil_pn:type="FILE_VHDL">
71 63 <association xil_pn:name="BehavioralSimulation"/>
72 64 <association xil_pn:name="Implementation"/>
73 65 <library xil_pn:name="grlib"/>
74 66 </file>
75 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/devices.vhd" xil_pn:type="FILE_VHDL">
67 <file xil_pn:name="../../lib/grlib/amba/defmst.vhd" xil_pn:type="FILE_VHDL">
76 68 <association xil_pn:name="BehavioralSimulation"/>
77 69 <association xil_pn:name="Implementation"/>
78 70 <library xil_pn:name="grlib"/>
79 71 </file>
80 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/defmst.vhd" xil_pn:type="FILE_VHDL">
72 <file xil_pn:name="../../lib/grlib/amba/apbctrl.vhd" xil_pn:type="FILE_VHDL">
81 73 <association xil_pn:name="BehavioralSimulation"/>
82 74 <association xil_pn:name="Implementation"/>
83 75 <library xil_pn:name="grlib"/>
84 76 </file>
85 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/apbctrl.vhd" xil_pn:type="FILE_VHDL">
77 <file xil_pn:name="../../lib/grlib/amba/ahbctrl.vhd" xil_pn:type="FILE_VHDL">
86 78 <association xil_pn:name="BehavioralSimulation"/>
87 79 <association xil_pn:name="Implementation"/>
88 80 <library xil_pn:name="grlib"/>
89 81 </file>
90 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/ahbctrl.vhd" xil_pn:type="FILE_VHDL">
82 <file xil_pn:name="../../lib/grlib/amba/dma2ahb_pkg.vhd" xil_pn:type="FILE_VHDL">
91 83 <association xil_pn:name="BehavioralSimulation"/>
92 84 <association xil_pn:name="Implementation"/>
93 85 <library xil_pn:name="grlib"/>
94 86 </file>
95 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/dma2ahb_pkg.vhd" xil_pn:type="FILE_VHDL">
96 <association xil_pn:name="BehavioralSimulation"/>
97 <association xil_pn:name="Implementation"/>
98 <library xil_pn:name="grlib"/>
99 </file>
100 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/dma2ahb.vhd" xil_pn:type="FILE_VHDL">
87 <file xil_pn:name="../../lib/grlib/amba/dma2ahb.vhd" xil_pn:type="FILE_VHDL">
101 88 <association xil_pn:name="BehavioralSimulation"/>
102 89 <association xil_pn:name="Implementation"/>
103 90 <library xil_pn:name="grlib"/>
104 91 </file>
105 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/dma2ahb_tp.vhd" xil_pn:type="FILE_VHDL">
92 <file xil_pn:name="../../lib/grlib/amba/dma2ahb_tp.vhd" xil_pn:type="FILE_VHDL">
106 93 <association xil_pn:name="BehavioralSimulation"/>
107 94 <library xil_pn:name="grlib"/>
108 95 </file>
109 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/amba/amba_tp.vhd" xil_pn:type="FILE_VHDL">
96 <file xil_pn:name="../../lib/grlib/amba/amba_tp.vhd" xil_pn:type="FILE_VHDL">
110 97 <association xil_pn:name="BehavioralSimulation"/>
111 98 <library xil_pn:name="grlib"/>
112 99 </file>
113 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/tech/proasic3/components/proasic3.vhd" xil_pn:type="FILE_VHDL">
100 <file xil_pn:name="../../lib/tech/proasic3/components/proasic3.vhd" xil_pn:type="FILE_VHDL">
114 101 <association xil_pn:name="BehavioralSimulation"/>
115 102 <library xil_pn:name="proasic3"/>
116 103 </file>
117 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/tech/dware/simprims/DWpackages.vhd" xil_pn:type="FILE_VHDL">
104 <file xil_pn:name="../../lib/tech/dware/simprims/DWpackages.vhd" xil_pn:type="FILE_VHDL">
118 105 <association xil_pn:name="BehavioralSimulation"/>
119 106 <library xil_pn:name="dware"/>
120 107 </file>
121 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/tech/dware/simprims/DW_Foundation_arith.vhd" xil_pn:type="FILE_VHDL">
108 <file xil_pn:name="../../lib/tech/dware/simprims/DW_Foundation_arith.vhd" xil_pn:type="FILE_VHDL">
122 109 <association xil_pn:name="BehavioralSimulation"/>
123 110 <library xil_pn:name="dware"/>
124 111 </file>
125 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/tech/dware/simprims/DW_Foundation_comp.vhd" xil_pn:type="FILE_VHDL">
112 <file xil_pn:name="../../lib/tech/dware/simprims/DW_Foundation_comp.vhd" xil_pn:type="FILE_VHDL">
126 113 <association xil_pn:name="BehavioralSimulation"/>
127 114 <library xil_pn:name="dware"/>
128 115 </file>
129 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/tech/dware/simprims/DW_Foundation_comp_arith.vhd" xil_pn:type="FILE_VHDL">
116 <file xil_pn:name="../../lib/tech/dware/simprims/DW_Foundation_comp_arith.vhd" xil_pn:type="FILE_VHDL">
130 117 <association xil_pn:name="BehavioralSimulation"/>
131 118 <library xil_pn:name="dware"/>
132 119 </file>
133 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/synplify/sim/synplify.vhd" xil_pn:type="FILE_VHDL">
120 <file xil_pn:name="../../lib/synplify/sim/synplify.vhd" xil_pn:type="FILE_VHDL">
134 121 <association xil_pn:name="BehavioralSimulation"/>
135 122 <library xil_pn:name="synplify"/>
136 123 </file>
137 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/synplify/sim/synattr.vhd" xil_pn:type="FILE_VHDL">
124 <file xil_pn:name="../../lib/synplify/sim/synattr.vhd" xil_pn:type="FILE_VHDL">
138 125 <association xil_pn:name="BehavioralSimulation"/>
139 126 <library xil_pn:name="synplify"/>
140 127 </file>
141 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/gencomp/gencomp.vhd" xil_pn:type="FILE_VHDL">
128 <file xil_pn:name="../../lib/techmap/gencomp/gencomp.vhd" xil_pn:type="FILE_VHDL">
142 129 <association xil_pn:name="BehavioralSimulation"/>
143 130 <association xil_pn:name="Implementation"/>
144 131 <library xil_pn:name="techmap"/>
145 132 </file>
146 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/gencomp/netcomp.vhd" xil_pn:type="FILE_VHDL">
147 <association xil_pn:name="BehavioralSimulation"/>
148 <association xil_pn:name="Implementation"/>
149 <library xil_pn:name="techmap"/>
150 </file>
151 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/inferred/memory_inferred.vhd" xil_pn:type="FILE_VHDL">
152 <association xil_pn:name="BehavioralSimulation"/>
153 <association xil_pn:name="Implementation"/>
154 <library xil_pn:name="techmap"/>
155 </file>
156 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/inferred/ddr_inferred.vhd" xil_pn:type="FILE_VHDL">
133 <file xil_pn:name="../../lib/techmap/gencomp/netcomp.vhd" xil_pn:type="FILE_VHDL">
157 134 <association xil_pn:name="BehavioralSimulation"/>
158 135 <association xil_pn:name="Implementation"/>
159 136 <library xil_pn:name="techmap"/>
160 137 </file>
161 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/inferred/mul_inferred.vhd" xil_pn:type="FILE_VHDL">
138 <file xil_pn:name="../../lib/techmap/inferred/memory_inferred.vhd" xil_pn:type="FILE_VHDL">
162 139 <association xil_pn:name="BehavioralSimulation"/>
163 140 <association xil_pn:name="Implementation"/>
164 141 <library xil_pn:name="techmap"/>
165 142 </file>
166 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/inferred/ddr_phy_inferred.vhd" xil_pn:type="FILE_VHDL">
143 <file xil_pn:name="../../lib/techmap/inferred/ddr_inferred.vhd" xil_pn:type="FILE_VHDL">
167 144 <association xil_pn:name="BehavioralSimulation"/>
168 145 <association xil_pn:name="Implementation"/>
169 146 <library xil_pn:name="techmap"/>
170 147 </file>
171 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/allclkgen.vhd" xil_pn:type="FILE_VHDL">
172 <association xil_pn:name="BehavioralSimulation"/>
173 <association xil_pn:name="Implementation"/>
174 <library xil_pn:name="techmap"/>
175 </file>
176 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/allddr.vhd" xil_pn:type="FILE_VHDL">
148 <file xil_pn:name="../../lib/techmap/inferred/mul_inferred.vhd" xil_pn:type="FILE_VHDL">
177 149 <association xil_pn:name="BehavioralSimulation"/>
178 150 <association xil_pn:name="Implementation"/>
179 151 <library xil_pn:name="techmap"/>
180 152 </file>
181 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/allmem.vhd" xil_pn:type="FILE_VHDL">
153 <file xil_pn:name="../../lib/techmap/inferred/ddr_phy_inferred.vhd" xil_pn:type="FILE_VHDL">
182 154 <association xil_pn:name="BehavioralSimulation"/>
183 155 <association xil_pn:name="Implementation"/>
184 156 <library xil_pn:name="techmap"/>
185 157 </file>
186 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/allmul.vhd" xil_pn:type="FILE_VHDL">
187 <association xil_pn:name="BehavioralSimulation"/>
188 <association xil_pn:name="Implementation"/>
189 <library xil_pn:name="techmap"/>
190 </file>
191 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/allpads.vhd" xil_pn:type="FILE_VHDL">
158 <file xil_pn:name="../../lib/techmap/maps/allclkgen.vhd" xil_pn:type="FILE_VHDL">
192 159 <association xil_pn:name="BehavioralSimulation"/>
193 160 <association xil_pn:name="Implementation"/>
194 161 <library xil_pn:name="techmap"/>
195 162 </file>
196 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/alltap.vhd" xil_pn:type="FILE_VHDL">
197 <association xil_pn:name="BehavioralSimulation"/>
198 <association xil_pn:name="Implementation"/>
199 <library xil_pn:name="techmap"/>
200 </file>
201 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/clkgen.vhd" xil_pn:type="FILE_VHDL">
163 <file xil_pn:name="../../lib/techmap/maps/allddr.vhd" xil_pn:type="FILE_VHDL">
202 164 <association xil_pn:name="BehavioralSimulation"/>
203 165 <association xil_pn:name="Implementation"/>
204 166 <library xil_pn:name="techmap"/>
205 167 </file>
206 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/clkmux.vhd" xil_pn:type="FILE_VHDL">
168 <file xil_pn:name="../../lib/techmap/maps/allmem.vhd" xil_pn:type="FILE_VHDL">
207 169 <association xil_pn:name="BehavioralSimulation"/>
208 170 <association xil_pn:name="Implementation"/>
209 171 <library xil_pn:name="techmap"/>
210 172 </file>
211 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/clkand.vhd" xil_pn:type="FILE_VHDL">
173 <file xil_pn:name="../../lib/techmap/maps/allmul.vhd" xil_pn:type="FILE_VHDL">
212 174 <association xil_pn:name="BehavioralSimulation"/>
213 175 <association xil_pn:name="Implementation"/>
214 176 <library xil_pn:name="techmap"/>
215 177 </file>
216 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/ddr_ireg.vhd" xil_pn:type="FILE_VHDL">
178 <file xil_pn:name="../../lib/techmap/maps/allpads.vhd" xil_pn:type="FILE_VHDL">
217 179 <association xil_pn:name="BehavioralSimulation"/>
218 180 <association xil_pn:name="Implementation"/>
219 181 <library xil_pn:name="techmap"/>
220 182 </file>
221 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/ddr_oreg.vhd" xil_pn:type="FILE_VHDL">
183 <file xil_pn:name="../../lib/techmap/maps/alltap.vhd" xil_pn:type="FILE_VHDL">
222 184 <association xil_pn:name="BehavioralSimulation"/>
223 185 <association xil_pn:name="Implementation"/>
224 186 <library xil_pn:name="techmap"/>
225 187 </file>
226 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/ddrphy.vhd" xil_pn:type="FILE_VHDL">
188 <file xil_pn:name="../../lib/techmap/maps/clkgen.vhd" xil_pn:type="FILE_VHDL">
227 189 <association xil_pn:name="BehavioralSimulation"/>
228 190 <association xil_pn:name="Implementation"/>
229 191 <library xil_pn:name="techmap"/>
230 192 </file>
231 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram.vhd" xil_pn:type="FILE_VHDL">
232 <association xil_pn:name="BehavioralSimulation"/>
233 <association xil_pn:name="Implementation"/>
234 <library xil_pn:name="techmap"/>
235 </file>
236 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram64.vhd" xil_pn:type="FILE_VHDL">
193 <file xil_pn:name="../../lib/techmap/maps/clkmux.vhd" xil_pn:type="FILE_VHDL">
237 194 <association xil_pn:name="BehavioralSimulation"/>
238 195 <association xil_pn:name="Implementation"/>
239 196 <library xil_pn:name="techmap"/>
240 197 </file>
241 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram_2p.vhd" xil_pn:type="FILE_VHDL">
198 <file xil_pn:name="../../lib/techmap/maps/clkand.vhd" xil_pn:type="FILE_VHDL">
242 199 <association xil_pn:name="BehavioralSimulation"/>
243 200 <association xil_pn:name="Implementation"/>
244 201 <library xil_pn:name="techmap"/>
245 202 </file>
246 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram_dp.vhd" xil_pn:type="FILE_VHDL">
203 <file xil_pn:name="../../lib/techmap/maps/ddr_ireg.vhd" xil_pn:type="FILE_VHDL">
247 204 <association xil_pn:name="BehavioralSimulation"/>
248 205 <association xil_pn:name="Implementation"/>
249 206 <library xil_pn:name="techmap"/>
250 207 </file>
251 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncfifo.vhd" xil_pn:type="FILE_VHDL">
208 <file xil_pn:name="../../lib/techmap/maps/ddr_oreg.vhd" xil_pn:type="FILE_VHDL">
252 209 <association xil_pn:name="BehavioralSimulation"/>
253 210 <association xil_pn:name="Implementation"/>
254 211 <library xil_pn:name="techmap"/>
255 212 </file>
256 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/regfile_3p.vhd" xil_pn:type="FILE_VHDL">
213 <file xil_pn:name="../../lib/techmap/maps/ddrphy.vhd" xil_pn:type="FILE_VHDL">
257 214 <association xil_pn:name="BehavioralSimulation"/>
258 215 <association xil_pn:name="Implementation"/>
259 216 <library xil_pn:name="techmap"/>
260 217 </file>
261 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/tap.vhd" xil_pn:type="FILE_VHDL">
218 <file xil_pn:name="../../lib/techmap/maps/syncram.vhd" xil_pn:type="FILE_VHDL">
262 219 <association xil_pn:name="BehavioralSimulation"/>
263 220 <association xil_pn:name="Implementation"/>
264 221 <library xil_pn:name="techmap"/>
265 222 </file>
266 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/techbuf.vhd" xil_pn:type="FILE_VHDL">
267 <association xil_pn:name="BehavioralSimulation"/>
268 <association xil_pn:name="Implementation"/>
269 <library xil_pn:name="techmap"/>
270 </file>
271 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/nandtree.vhd" xil_pn:type="FILE_VHDL">
223 <file xil_pn:name="../../lib/techmap/maps/syncram64.vhd" xil_pn:type="FILE_VHDL">
272 224 <association xil_pn:name="BehavioralSimulation"/>
273 225 <association xil_pn:name="Implementation"/>
274 226 <library xil_pn:name="techmap"/>
275 227 </file>
276 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/clkpad.vhd" xil_pn:type="FILE_VHDL">
228 <file xil_pn:name="../../lib/techmap/maps/syncram_2p.vhd" xil_pn:type="FILE_VHDL">
277 229 <association xil_pn:name="BehavioralSimulation"/>
278 230 <association xil_pn:name="Implementation"/>
279 231 <library xil_pn:name="techmap"/>
280 232 </file>
281 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/clkpad_ds.vhd" xil_pn:type="FILE_VHDL">
233 <file xil_pn:name="../../lib/techmap/maps/syncram_dp.vhd" xil_pn:type="FILE_VHDL">
282 234 <association xil_pn:name="BehavioralSimulation"/>
283 235 <association xil_pn:name="Implementation"/>
284 236 <library xil_pn:name="techmap"/>
285 237 </file>
286 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/inpad.vhd" xil_pn:type="FILE_VHDL">
238 <file xil_pn:name="../../lib/techmap/maps/syncfifo.vhd" xil_pn:type="FILE_VHDL">
287 239 <association xil_pn:name="BehavioralSimulation"/>
288 240 <association xil_pn:name="Implementation"/>
289 241 <library xil_pn:name="techmap"/>
290 242 </file>
291 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/inpad_ds.vhd" xil_pn:type="FILE_VHDL">
243 <file xil_pn:name="../../lib/techmap/maps/regfile_3p.vhd" xil_pn:type="FILE_VHDL">
292 244 <association xil_pn:name="BehavioralSimulation"/>
293 245 <association xil_pn:name="Implementation"/>
294 246 <library xil_pn:name="techmap"/>
295 247 </file>
296 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/iodpad.vhd" xil_pn:type="FILE_VHDL">
297 <association xil_pn:name="BehavioralSimulation"/>
298 <association xil_pn:name="Implementation"/>
299 <library xil_pn:name="techmap"/>
300 </file>
301 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/iopad.vhd" xil_pn:type="FILE_VHDL">
248 <file xil_pn:name="../../lib/techmap/maps/tap.vhd" xil_pn:type="FILE_VHDL">
302 249 <association xil_pn:name="BehavioralSimulation"/>
303 250 <association xil_pn:name="Implementation"/>
304 251 <library xil_pn:name="techmap"/>
305 252 </file>
306 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/iopad_ds.vhd" xil_pn:type="FILE_VHDL">
253 <file xil_pn:name="../../lib/techmap/maps/techbuf.vhd" xil_pn:type="FILE_VHDL">
307 254 <association xil_pn:name="BehavioralSimulation"/>
308 255 <association xil_pn:name="Implementation"/>
309 256 <library xil_pn:name="techmap"/>
310 257 </file>
311 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/lvds_combo.vhd" xil_pn:type="FILE_VHDL">
258 <file xil_pn:name="../../lib/techmap/maps/nandtree.vhd" xil_pn:type="FILE_VHDL">
312 259 <association xil_pn:name="BehavioralSimulation"/>
313 260 <association xil_pn:name="Implementation"/>
314 261 <library xil_pn:name="techmap"/>
315 262 </file>
316 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/odpad.vhd" xil_pn:type="FILE_VHDL">
263 <file xil_pn:name="../../lib/techmap/maps/clkpad.vhd" xil_pn:type="FILE_VHDL">
317 264 <association xil_pn:name="BehavioralSimulation"/>
318 265 <association xil_pn:name="Implementation"/>
319 266 <library xil_pn:name="techmap"/>
320 267 </file>
321 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/outpad.vhd" xil_pn:type="FILE_VHDL">
268 <file xil_pn:name="../../lib/techmap/maps/clkpad_ds.vhd" xil_pn:type="FILE_VHDL">
322 269 <association xil_pn:name="BehavioralSimulation"/>
323 270 <association xil_pn:name="Implementation"/>
324 271 <library xil_pn:name="techmap"/>
325 272 </file>
326 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/outpad_ds.vhd" xil_pn:type="FILE_VHDL">
273 <file xil_pn:name="../../lib/techmap/maps/inpad.vhd" xil_pn:type="FILE_VHDL">
327 274 <association xil_pn:name="BehavioralSimulation"/>
328 275 <association xil_pn:name="Implementation"/>
329 276 <library xil_pn:name="techmap"/>
330 277 </file>
331 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/toutpad.vhd" xil_pn:type="FILE_VHDL">
278 <file xil_pn:name="../../lib/techmap/maps/inpad_ds.vhd" xil_pn:type="FILE_VHDL">
332 279 <association xil_pn:name="BehavioralSimulation"/>
333 280 <association xil_pn:name="Implementation"/>
334 281 <library xil_pn:name="techmap"/>
335 282 </file>
336 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/skew_outpad.vhd" xil_pn:type="FILE_VHDL">
283 <file xil_pn:name="../../lib/techmap/maps/iodpad.vhd" xil_pn:type="FILE_VHDL">
337 284 <association xil_pn:name="BehavioralSimulation"/>
338 285 <association xil_pn:name="Implementation"/>
339 286 <library xil_pn:name="techmap"/>
340 287 </file>
341 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/grspwc_net.vhd" xil_pn:type="FILE_VHDL">
288 <file xil_pn:name="../../lib/techmap/maps/iopad.vhd" xil_pn:type="FILE_VHDL">
342 289 <association xil_pn:name="BehavioralSimulation"/>
343 290 <association xil_pn:name="Implementation"/>
344 291 <library xil_pn:name="techmap"/>
345 292 </file>
346 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/grspwc2_net.vhd" xil_pn:type="FILE_VHDL">
347 <association xil_pn:name="BehavioralSimulation"/>
348 <association xil_pn:name="Implementation"/>
349 <library xil_pn:name="techmap"/>
350 </file>
351 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/grlfpw_net.vhd" xil_pn:type="FILE_VHDL">
293 <file xil_pn:name="../../lib/techmap/maps/iopad_ds.vhd" xil_pn:type="FILE_VHDL">
352 294 <association xil_pn:name="BehavioralSimulation"/>
353 295 <association xil_pn:name="Implementation"/>
354 296 <library xil_pn:name="techmap"/>
355 297 </file>
356 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/grfpw_net.vhd" xil_pn:type="FILE_VHDL">
298 <file xil_pn:name="../../lib/techmap/maps/lvds_combo.vhd" xil_pn:type="FILE_VHDL">
357 299 <association xil_pn:name="BehavioralSimulation"/>
358 300 <association xil_pn:name="Implementation"/>
359 301 <library xil_pn:name="techmap"/>
360 302 </file>
361 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/leon4_net.vhd" xil_pn:type="FILE_VHDL">
362 <association xil_pn:name="BehavioralSimulation"/>
363 <association xil_pn:name="Implementation"/>
364 <library xil_pn:name="techmap"/>
365 </file>
366 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/mul_61x61.vhd" xil_pn:type="FILE_VHDL">
303 <file xil_pn:name="../../lib/techmap/maps/odpad.vhd" xil_pn:type="FILE_VHDL">
367 304 <association xil_pn:name="BehavioralSimulation"/>
368 305 <association xil_pn:name="Implementation"/>
369 306 <library xil_pn:name="techmap"/>
370 307 </file>
371 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/cpu_disas_net.vhd" xil_pn:type="FILE_VHDL">
308 <file xil_pn:name="../../lib/techmap/maps/outpad.vhd" xil_pn:type="FILE_VHDL">
372 309 <association xil_pn:name="BehavioralSimulation"/>
373 310 <association xil_pn:name="Implementation"/>
374 311 <library xil_pn:name="techmap"/>
375 312 </file>
376 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/grusbhc_net.vhd" xil_pn:type="FILE_VHDL">
313 <file xil_pn:name="../../lib/techmap/maps/outpad_ds.vhd" xil_pn:type="FILE_VHDL">
377 314 <association xil_pn:name="BehavioralSimulation"/>
378 315 <association xil_pn:name="Implementation"/>
379 316 <library xil_pn:name="techmap"/>
380 317 </file>
381 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/ringosc.vhd" xil_pn:type="FILE_VHDL">
318 <file xil_pn:name="../../lib/techmap/maps/toutpad.vhd" xil_pn:type="FILE_VHDL">
382 319 <association xil_pn:name="BehavioralSimulation"/>
383 320 <association xil_pn:name="Implementation"/>
384 321 <library xil_pn:name="techmap"/>
385 322 </file>
386 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/ssrctrl_net.vhd" xil_pn:type="FILE_VHDL">
323 <file xil_pn:name="../../lib/techmap/maps/skew_outpad.vhd" xil_pn:type="FILE_VHDL">
387 324 <association xil_pn:name="BehavioralSimulation"/>
388 325 <association xil_pn:name="Implementation"/>
389 326 <library xil_pn:name="techmap"/>
390 327 </file>
391 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/system_monitor.vhd" xil_pn:type="FILE_VHDL">
392 <association xil_pn:name="BehavioralSimulation"/>
393 <association xil_pn:name="Implementation"/>
394 <library xil_pn:name="techmap"/>
395 </file>
396 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/grgates.vhd" xil_pn:type="FILE_VHDL">
328 <file xil_pn:name="../../lib/techmap/maps/grspwc_net.vhd" xil_pn:type="FILE_VHDL">
397 329 <association xil_pn:name="BehavioralSimulation"/>
398 330 <association xil_pn:name="Implementation"/>
399 331 <library xil_pn:name="techmap"/>
400 332 </file>
401 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/inpad_ddr.vhd" xil_pn:type="FILE_VHDL">
333 <file xil_pn:name="../../lib/techmap/maps/grspwc2_net.vhd" xil_pn:type="FILE_VHDL">
402 334 <association xil_pn:name="BehavioralSimulation"/>
403 335 <association xil_pn:name="Implementation"/>
404 336 <library xil_pn:name="techmap"/>
405 337 </file>
406 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/outpad_ddr.vhd" xil_pn:type="FILE_VHDL">
338 <file xil_pn:name="../../lib/techmap/maps/grlfpw_net.vhd" xil_pn:type="FILE_VHDL">
407 339 <association xil_pn:name="BehavioralSimulation"/>
408 340 <association xil_pn:name="Implementation"/>
409 341 <library xil_pn:name="techmap"/>
410 342 </file>
411 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/iopad_ddr.vhd" xil_pn:type="FILE_VHDL">
343 <file xil_pn:name="../../lib/techmap/maps/grfpw_net.vhd" xil_pn:type="FILE_VHDL">
412 344 <association xil_pn:name="BehavioralSimulation"/>
413 345 <association xil_pn:name="Implementation"/>
414 346 <library xil_pn:name="techmap"/>
415 347 </file>
416 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram128bw.vhd" xil_pn:type="FILE_VHDL">
348 <file xil_pn:name="../../lib/techmap/maps/leon4_net.vhd" xil_pn:type="FILE_VHDL">
417 349 <association xil_pn:name="BehavioralSimulation"/>
418 350 <association xil_pn:name="Implementation"/>
419 351 <library xil_pn:name="techmap"/>
420 352 </file>
421 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram128.vhd" xil_pn:type="FILE_VHDL">
353 <file xil_pn:name="../../lib/techmap/maps/mul_61x61.vhd" xil_pn:type="FILE_VHDL">
422 354 <association xil_pn:name="BehavioralSimulation"/>
423 355 <association xil_pn:name="Implementation"/>
424 356 <library xil_pn:name="techmap"/>
425 357 </file>
426 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram156bw.vhd" xil_pn:type="FILE_VHDL">
358 <file xil_pn:name="../../lib/techmap/maps/cpu_disas_net.vhd" xil_pn:type="FILE_VHDL">
427 359 <association xil_pn:name="BehavioralSimulation"/>
428 360 <association xil_pn:name="Implementation"/>
429 361 <library xil_pn:name="techmap"/>
430 362 </file>
431 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/techmult.vhd" xil_pn:type="FILE_VHDL">
363 <file xil_pn:name="../../lib/techmap/maps/grusbhc_net.vhd" xil_pn:type="FILE_VHDL">
432 364 <association xil_pn:name="BehavioralSimulation"/>
433 365 <association xil_pn:name="Implementation"/>
434 366 <library xil_pn:name="techmap"/>
435 367 </file>
436 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/spictrl_net.vhd" xil_pn:type="FILE_VHDL">
368 <file xil_pn:name="../../lib/techmap/maps/ringosc.vhd" xil_pn:type="FILE_VHDL">
437 369 <association xil_pn:name="BehavioralSimulation"/>
438 370 <association xil_pn:name="Implementation"/>
439 371 <library xil_pn:name="techmap"/>
440 372 </file>
441 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/scanreg.vhd" xil_pn:type="FILE_VHDL">
373 <file xil_pn:name="../../lib/techmap/maps/ssrctrl_net.vhd" xil_pn:type="FILE_VHDL">
442 374 <association xil_pn:name="BehavioralSimulation"/>
443 375 <association xil_pn:name="Implementation"/>
444 376 <library xil_pn:name="techmap"/>
445 377 </file>
446 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/spw/comp/spwcomp.vhd" xil_pn:type="FILE_VHDL">
378 <file xil_pn:name="../../lib/techmap/maps/system_monitor.vhd" xil_pn:type="FILE_VHDL">
447 379 <association xil_pn:name="BehavioralSimulation"/>
448 380 <association xil_pn:name="Implementation"/>
449 <library xil_pn:name="spw"/>
381 <library xil_pn:name="techmap"/>
450 382 </file>
451 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/spw/wrapper/grspw_gen.vhd" xil_pn:type="FILE_VHDL">
383 <file xil_pn:name="../../lib/techmap/maps/grgates.vhd" xil_pn:type="FILE_VHDL">
452 384 <association xil_pn:name="BehavioralSimulation"/>
453 385 <association xil_pn:name="Implementation"/>
454 <library xil_pn:name="spw"/>
386 <library xil_pn:name="techmap"/>
455 387 </file>
456 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/spw/wrapper/grspw2_gen.vhd" xil_pn:type="FILE_VHDL">
388 <file xil_pn:name="../../lib/techmap/maps/inpad_ddr.vhd" xil_pn:type="FILE_VHDL">
457 389 <association xil_pn:name="BehavioralSimulation"/>
458 390 <association xil_pn:name="Implementation"/>
459 <library xil_pn:name="spw"/>
391 <library xil_pn:name="techmap"/>
460 392 </file>
461 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/comp/ethcomp.vhd" xil_pn:type="FILE_VHDL">
393 <file xil_pn:name="../../lib/techmap/maps/outpad_ddr.vhd" xil_pn:type="FILE_VHDL">
462 394 <association xil_pn:name="BehavioralSimulation"/>
463 395 <association xil_pn:name="Implementation"/>
464 <library xil_pn:name="eth"/>
396 <library xil_pn:name="techmap"/>
465 397 </file>
466 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/greth_pkg.vhd" xil_pn:type="FILE_VHDL">
398 <file xil_pn:name="../../lib/techmap/maps/iopad_ddr.vhd" xil_pn:type="FILE_VHDL">
467 399 <association xil_pn:name="BehavioralSimulation"/>
468 400 <association xil_pn:name="Implementation"/>
469 <library xil_pn:name="eth"/>
401 <library xil_pn:name="techmap"/>
470 402 </file>
471 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/eth_rstgen.vhd" xil_pn:type="FILE_VHDL">
472 <association xil_pn:name="BehavioralSimulation"/>
473 <association xil_pn:name="Implementation"/>
474 <library xil_pn:name="eth"/>
475 </file>
476 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/eth_edcl_ahb_mst.vhd" xil_pn:type="FILE_VHDL">
403 <file xil_pn:name="../../lib/techmap/maps/syncram128bw.vhd" xil_pn:type="FILE_VHDL">
477 404 <association xil_pn:name="BehavioralSimulation"/>
478 405 <association xil_pn:name="Implementation"/>
479 <library xil_pn:name="eth"/>
406 <library xil_pn:name="techmap"/>
480 407 </file>
481 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/eth_ahb_mst.vhd" xil_pn:type="FILE_VHDL">
408 <file xil_pn:name="../../lib/techmap/maps/syncram128.vhd" xil_pn:type="FILE_VHDL">
482 409 <association xil_pn:name="BehavioralSimulation"/>
483 410 <association xil_pn:name="Implementation"/>
484 <library xil_pn:name="eth"/>
411 <library xil_pn:name="techmap"/>
485 412 </file>
486 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/greth_tx.vhd" xil_pn:type="FILE_VHDL">
487 <association xil_pn:name="BehavioralSimulation"/>
488 <association xil_pn:name="Implementation"/>
489 <library xil_pn:name="eth"/>
490 </file>
491 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/greth_rx.vhd" xil_pn:type="FILE_VHDL">
413 <file xil_pn:name="../../lib/techmap/maps/syncram156bw.vhd" xil_pn:type="FILE_VHDL">
492 414 <association xil_pn:name="BehavioralSimulation"/>
493 415 <association xil_pn:name="Implementation"/>
494 <library xil_pn:name="eth"/>
416 <library xil_pn:name="techmap"/>
495 417 </file>
496 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/grethc.vhd" xil_pn:type="FILE_VHDL">
497 <association xil_pn:name="BehavioralSimulation"/>
498 <association xil_pn:name="Implementation"/>
499 <library xil_pn:name="eth"/>
500 </file>
501 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/wrapper/greth_gen.vhd" xil_pn:type="FILE_VHDL">
418 <file xil_pn:name="../../lib/techmap/maps/techmult.vhd" xil_pn:type="FILE_VHDL">
502 419 <association xil_pn:name="BehavioralSimulation"/>
503 420 <association xil_pn:name="Implementation"/>
504 <library xil_pn:name="eth"/>
421 <library xil_pn:name="techmap"/>
505 422 </file>
506 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/wrapper/greth_gbit_gen.vhd" xil_pn:type="FILE_VHDL">
423 <file xil_pn:name="../../lib/techmap/maps/spictrl_net.vhd" xil_pn:type="FILE_VHDL">
507 424 <association xil_pn:name="BehavioralSimulation"/>
508 425 <association xil_pn:name="Implementation"/>
509 <library xil_pn:name="eth"/>
426 <library xil_pn:name="techmap"/>
510 427 </file>
511 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/opencores/occomp/occomp.vhd" xil_pn:type="FILE_VHDL">
428 <file xil_pn:name="../../lib/techmap/maps/scanreg.vhd" xil_pn:type="FILE_VHDL">
512 429 <association xil_pn:name="BehavioralSimulation"/>
513 430 <association xil_pn:name="Implementation"/>
514 <library xil_pn:name="opencores"/>
431 <library xil_pn:name="techmap"/>
515 432 </file>
516 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/opencores/can/cancomp.vhd" xil_pn:type="FILE_VHDL">
433 <file xil_pn:name="../../lib/opencores/occomp/occomp.vhd" xil_pn:type="FILE_VHDL">
517 434 <association xil_pn:name="BehavioralSimulation"/>
518 435 <association xil_pn:name="Implementation"/>
519 436 <library xil_pn:name="opencores"/>
520 437 </file>
521 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/opencores/can/can_top.vhd" xil_pn:type="FILE_VHDL">
522 <association xil_pn:name="BehavioralSimulation"/>
523 <association xil_pn:name="Implementation"/>
524 <library xil_pn:name="opencores"/>
525 </file>
526 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/arith/arith.vhd" xil_pn:type="FILE_VHDL">
438 <file xil_pn:name="../../lib/gaisler/arith/arith.vhd" xil_pn:type="FILE_VHDL">
527 439 <association xil_pn:name="BehavioralSimulation"/>
528 440 <association xil_pn:name="Implementation"/>
529 441 <library xil_pn:name="gaisler"/>
530 442 </file>
531 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/arith/mul32.vhd" xil_pn:type="FILE_VHDL">
443 <file xil_pn:name="../../lib/gaisler/arith/mul32.vhd" xil_pn:type="FILE_VHDL">
532 444 <association xil_pn:name="BehavioralSimulation"/>
533 445 <association xil_pn:name="Implementation"/>
534 446 <library xil_pn:name="gaisler"/>
535 447 </file>
536 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/arith/div32.vhd" xil_pn:type="FILE_VHDL">
537 <association xil_pn:name="BehavioralSimulation"/>
538 <association xil_pn:name="Implementation"/>
539 <library xil_pn:name="gaisler"/>
540 </file>
541 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/memctrl.vhd" xil_pn:type="FILE_VHDL">
448 <file xil_pn:name="../../lib/gaisler/arith/div32.vhd" xil_pn:type="FILE_VHDL">
542 449 <association xil_pn:name="BehavioralSimulation"/>
543 450 <association xil_pn:name="Implementation"/>
544 451 <library xil_pn:name="gaisler"/>
545 452 </file>
546 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/sdctrl.vhd" xil_pn:type="FILE_VHDL">
547 <association xil_pn:name="BehavioralSimulation"/>
548 <association xil_pn:name="Implementation"/>
549 <library xil_pn:name="gaisler"/>
550 </file>
551 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/sdctrl64.vhd" xil_pn:type="FILE_VHDL">
552 <association xil_pn:name="BehavioralSimulation"/>
553 <association xil_pn:name="Implementation"/>
554 <library xil_pn:name="gaisler"/>
555 </file>
556 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/sdmctrl.vhd" xil_pn:type="FILE_VHDL">
453 <file xil_pn:name="../../lib/gaisler/memctrl/memctrl.vhd" xil_pn:type="FILE_VHDL">
557 454 <association xil_pn:name="BehavioralSimulation"/>
558 455 <association xil_pn:name="Implementation"/>
559 456 <library xil_pn:name="gaisler"/>
560 457 </file>
561 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/srctrl.vhd" xil_pn:type="FILE_VHDL">
458 <file xil_pn:name="../../lib/gaisler/memctrl/sdctrl.vhd" xil_pn:type="FILE_VHDL">
562 459 <association xil_pn:name="BehavioralSimulation"/>
563 460 <association xil_pn:name="Implementation"/>
564 461 <library xil_pn:name="gaisler"/>
565 462 </file>
566 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/spimctrl.vhd" xil_pn:type="FILE_VHDL">
463 <file xil_pn:name="../../lib/gaisler/memctrl/sdctrl64.vhd" xil_pn:type="FILE_VHDL">
567 464 <association xil_pn:name="BehavioralSimulation"/>
568 465 <association xil_pn:name="Implementation"/>
569 466 <library xil_pn:name="gaisler"/>
570 467 </file>
571 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3.vhd" xil_pn:type="FILE_VHDL">
572 <association xil_pn:name="BehavioralSimulation"/>
573 <association xil_pn:name="Implementation"/>
574 <library xil_pn:name="gaisler"/>
575 </file>
576 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmuconfig.vhd" xil_pn:type="FILE_VHDL">
468 <file xil_pn:name="../../lib/gaisler/memctrl/sdmctrl.vhd" xil_pn:type="FILE_VHDL">
577 469 <association xil_pn:name="BehavioralSimulation"/>
578 470 <association xil_pn:name="Implementation"/>
579 471 <library xil_pn:name="gaisler"/>
580 472 </file>
581 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmuiface.vhd" xil_pn:type="FILE_VHDL">
582 <association xil_pn:name="BehavioralSimulation"/>
583 <association xil_pn:name="Implementation"/>
584 <library xil_pn:name="gaisler"/>
585 </file>
586 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/libmmu.vhd" xil_pn:type="FILE_VHDL">
473 <file xil_pn:name="../../lib/gaisler/memctrl/srctrl.vhd" xil_pn:type="FILE_VHDL">
587 474 <association xil_pn:name="BehavioralSimulation"/>
588 475 <association xil_pn:name="Implementation"/>
589 476 <library xil_pn:name="gaisler"/>
590 477 </file>
591 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/libiu.vhd" xil_pn:type="FILE_VHDL">
478 <file xil_pn:name="../../lib/gaisler/memctrl/spimctrl.vhd" xil_pn:type="FILE_VHDL">
592 479 <association xil_pn:name="BehavioralSimulation"/>
593 480 <association xil_pn:name="Implementation"/>
594 481 <library xil_pn:name="gaisler"/>
595 482 </file>
596 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/libcache.vhd" xil_pn:type="FILE_VHDL">
597 <association xil_pn:name="BehavioralSimulation"/>
598 <association xil_pn:name="Implementation"/>
599 <library xil_pn:name="gaisler"/>
600 </file>
601 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/libproc3.vhd" xil_pn:type="FILE_VHDL">
602 <association xil_pn:name="BehavioralSimulation"/>
603 <association xil_pn:name="Implementation"/>
604 <library xil_pn:name="gaisler"/>
605 </file>
606 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/cachemem.vhd" xil_pn:type="FILE_VHDL">
483 <file xil_pn:name="../../lib/gaisler/misc/misc.vhd" xil_pn:type="FILE_VHDL">
607 484 <association xil_pn:name="BehavioralSimulation"/>
608 485 <association xil_pn:name="Implementation"/>
609 486 <library xil_pn:name="gaisler"/>
610 487 </file>
611 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_icache.vhd" xil_pn:type="FILE_VHDL">
488 <file xil_pn:name="../../lib/gaisler/misc/rstgen.vhd" xil_pn:type="FILE_VHDL">
612 489 <association xil_pn:name="BehavioralSimulation"/>
613 490 <association xil_pn:name="Implementation"/>
614 491 <library xil_pn:name="gaisler"/>
615 492 </file>
616 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_dcache.vhd" xil_pn:type="FILE_VHDL">
617 <association xil_pn:name="BehavioralSimulation"/>
618 <association xil_pn:name="Implementation"/>
619 <library xil_pn:name="gaisler"/>
620 </file>
621 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_acache.vhd" xil_pn:type="FILE_VHDL">
493 <file xil_pn:name="../../lib/gaisler/misc/gptimer.vhd" xil_pn:type="FILE_VHDL">
622 494 <association xil_pn:name="BehavioralSimulation"/>
623 495 <association xil_pn:name="Implementation"/>
624 496 <library xil_pn:name="gaisler"/>
625 497 </file>
626 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmutlbcam.vhd" xil_pn:type="FILE_VHDL">
498 <file xil_pn:name="../../lib/gaisler/misc/ahbram.vhd" xil_pn:type="FILE_VHDL">
627 499 <association xil_pn:name="BehavioralSimulation"/>
628 500 <association xil_pn:name="Implementation"/>
629 501 <library xil_pn:name="gaisler"/>
630 502 </file>
631 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmulrue.vhd" xil_pn:type="FILE_VHDL">
503 <file xil_pn:name="../../lib/gaisler/misc/ahbdpram.vhd" xil_pn:type="FILE_VHDL">
632 504 <association xil_pn:name="BehavioralSimulation"/>
633 505 <association xil_pn:name="Implementation"/>
634 506 <library xil_pn:name="gaisler"/>
635 507 </file>
636 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmulru.vhd" xil_pn:type="FILE_VHDL">
637 <association xil_pn:name="BehavioralSimulation"/>
638 <association xil_pn:name="Implementation"/>
639 <library xil_pn:name="gaisler"/>
640 </file>
641 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmutlb.vhd" xil_pn:type="FILE_VHDL">
508 <file xil_pn:name="../../lib/gaisler/misc/ahbtrace.vhd" xil_pn:type="FILE_VHDL">
642 509 <association xil_pn:name="BehavioralSimulation"/>
643 510 <association xil_pn:name="Implementation"/>
644 511 <library xil_pn:name="gaisler"/>
645 512 </file>
646 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmutw.vhd" xil_pn:type="FILE_VHDL">
647 <association xil_pn:name="BehavioralSimulation"/>
648 <association xil_pn:name="Implementation"/>
649 <library xil_pn:name="gaisler"/>
650 </file>
651 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu.vhd" xil_pn:type="FILE_VHDL">
513 <file xil_pn:name="../../lib/gaisler/misc/ahbtrace_mb.vhd" xil_pn:type="FILE_VHDL">
652 514 <association xil_pn:name="BehavioralSimulation"/>
653 515 <association xil_pn:name="Implementation"/>
654 516 <library xil_pn:name="gaisler"/>
655 517 </file>
656 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_cache.vhd" xil_pn:type="FILE_VHDL">
518 <file xil_pn:name="../../lib/gaisler/misc/ahbtrace_mmb.vhd" xil_pn:type="FILE_VHDL">
657 519 <association xil_pn:name="BehavioralSimulation"/>
658 520 <association xil_pn:name="Implementation"/>
659 521 <library xil_pn:name="gaisler"/>
660 522 </file>
661 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/cpu_disasx.vhd" xil_pn:type="FILE_VHDL">
662 <association xil_pn:name="BehavioralSimulation"/>
663 <association xil_pn:name="Implementation"/>
664 <library xil_pn:name="gaisler"/>
665 </file>
666 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/iu3.vhd" xil_pn:type="FILE_VHDL">
523 <file xil_pn:name="../../lib/gaisler/misc/ahbmst.vhd" xil_pn:type="FILE_VHDL">
667 524 <association xil_pn:name="BehavioralSimulation"/>
668 525 <association xil_pn:name="Implementation"/>
669 526 <library xil_pn:name="gaisler"/>
670 527 </file>
671 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grfpwx.vhd" xil_pn:type="FILE_VHDL">
672 <association xil_pn:name="BehavioralSimulation"/>
673 <association xil_pn:name="Implementation"/>
674 <library xil_pn:name="gaisler"/>
675 </file>
676 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mfpwx.vhd" xil_pn:type="FILE_VHDL">
677 <association xil_pn:name="BehavioralSimulation"/>
678 <association xil_pn:name="Implementation"/>
679 <library xil_pn:name="gaisler"/>
680 </file>
681 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grlfpwx.vhd" xil_pn:type="FILE_VHDL">
528 <file xil_pn:name="../../lib/gaisler/misc/grgpio.vhd" xil_pn:type="FILE_VHDL">
682 529 <association xil_pn:name="BehavioralSimulation"/>
683 530 <association xil_pn:name="Implementation"/>
684 531 <library xil_pn:name="gaisler"/>
685 532 </file>
686 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/tbufmem.vhd" xil_pn:type="FILE_VHDL">
533 <file xil_pn:name="../../lib/gaisler/misc/ahbstat.vhd" xil_pn:type="FILE_VHDL">
687 534 <association xil_pn:name="BehavioralSimulation"/>
688 535 <association xil_pn:name="Implementation"/>
689 536 <library xil_pn:name="gaisler"/>
690 537 </file>
691 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/dsu3x.vhd" xil_pn:type="FILE_VHDL">
538 <file xil_pn:name="../../lib/gaisler/misc/logan.vhd" xil_pn:type="FILE_VHDL">
692 539 <association xil_pn:name="BehavioralSimulation"/>
693 540 <association xil_pn:name="Implementation"/>
694 541 <library xil_pn:name="gaisler"/>
695 542 </file>
696 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/dsu3.vhd" xil_pn:type="FILE_VHDL">
697 <association xil_pn:name="BehavioralSimulation"/>
698 <association xil_pn:name="Implementation"/>
699 <library xil_pn:name="gaisler"/>
700 </file>
701 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/proc3.vhd" xil_pn:type="FILE_VHDL">
543 <file xil_pn:name="../../lib/gaisler/misc/apbps2.vhd" xil_pn:type="FILE_VHDL">
702 544 <association xil_pn:name="BehavioralSimulation"/>
703 545 <association xil_pn:name="Implementation"/>
704 546 <library xil_pn:name="gaisler"/>
705 547 </file>
706 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3s.vhd" xil_pn:type="FILE_VHDL">
707 <association xil_pn:name="BehavioralSimulation"/>
708 <association xil_pn:name="Implementation"/>
709 <library xil_pn:name="gaisler"/>
710 </file>
711 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3cg.vhd" xil_pn:type="FILE_VHDL">
548 <file xil_pn:name="../../lib/gaisler/misc/charrom_package.vhd" xil_pn:type="FILE_VHDL">
712 549 <association xil_pn:name="BehavioralSimulation"/>
713 550 <association xil_pn:name="Implementation"/>
714 551 <library xil_pn:name="gaisler"/>
715 552 </file>
716 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/irqmp.vhd" xil_pn:type="FILE_VHDL">
553 <file xil_pn:name="../../lib/gaisler/misc/charrom.vhd" xil_pn:type="FILE_VHDL">
717 554 <association xil_pn:name="BehavioralSimulation"/>
718 555 <association xil_pn:name="Implementation"/>
719 556 <library xil_pn:name="gaisler"/>
720 557 </file>
721 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grfpwxsh.vhd" xil_pn:type="FILE_VHDL">
558 <file xil_pn:name="../../lib/gaisler/misc/apbvga.vhd" xil_pn:type="FILE_VHDL">
722 559 <association xil_pn:name="BehavioralSimulation"/>
723 560 <association xil_pn:name="Implementation"/>
724 561 <library xil_pn:name="gaisler"/>
725 562 </file>
726 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grfpushwx.vhd" xil_pn:type="FILE_VHDL">
727 <association xil_pn:name="BehavioralSimulation"/>
728 <association xil_pn:name="Implementation"/>
729 <library xil_pn:name="gaisler"/>
730 </file>
731 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3sh.vhd" xil_pn:type="FILE_VHDL">
563 <file xil_pn:name="../../lib/gaisler/misc/svgactrl.vhd" xil_pn:type="FILE_VHDL">
732 564 <association xil_pn:name="BehavioralSimulation"/>
733 565 <association xil_pn:name="Implementation"/>
734 566 <library xil_pn:name="gaisler"/>
735 567 </file>
736 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3ft/leon3ft.vhd" xil_pn:type="FILE_VHDL">
568 <file xil_pn:name="../../lib/gaisler/misc/i2cmst_gen.vhd" xil_pn:type="FILE_VHDL">
737 569 <association xil_pn:name="BehavioralSimulation"/>
738 570 <association xil_pn:name="Implementation"/>
739 571 <library xil_pn:name="gaisler"/>
740 572 </file>
741 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can.vhd" xil_pn:type="FILE_VHDL">
742 <association xil_pn:name="BehavioralSimulation"/>
743 <association xil_pn:name="Implementation"/>
744 <library xil_pn:name="gaisler"/>
745 </file>
746 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_mod.vhd" xil_pn:type="FILE_VHDL">
573 <file xil_pn:name="../../lib/gaisler/misc/spictrlx.vhd" xil_pn:type="FILE_VHDL">
747 574 <association xil_pn:name="BehavioralSimulation"/>
748 575 <association xil_pn:name="Implementation"/>
749 576 <library xil_pn:name="gaisler"/>
750 577 </file>
751 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_oc.vhd" xil_pn:type="FILE_VHDL">
752 <association xil_pn:name="BehavioralSimulation"/>
753 <association xil_pn:name="Implementation"/>
754 <library xil_pn:name="gaisler"/>
755 </file>
756 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_mc.vhd" xil_pn:type="FILE_VHDL">
578 <file xil_pn:name="../../lib/gaisler/misc/spictrl.vhd" xil_pn:type="FILE_VHDL">
757 579 <association xil_pn:name="BehavioralSimulation"/>
758 580 <association xil_pn:name="Implementation"/>
759 581 <library xil_pn:name="gaisler"/>
760 582 </file>
761 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/canmux.vhd" xil_pn:type="FILE_VHDL">
583 <file xil_pn:name="../../lib/gaisler/misc/i2cslv.vhd" xil_pn:type="FILE_VHDL">
762 584 <association xil_pn:name="BehavioralSimulation"/>
763 585 <association xil_pn:name="Implementation"/>
764 586 <library xil_pn:name="gaisler"/>
765 587 </file>
766 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_rd.vhd" xil_pn:type="FILE_VHDL">
767 <association xil_pn:name="BehavioralSimulation"/>
768 <association xil_pn:name="Implementation"/>
769 <library xil_pn:name="gaisler"/>
770 </file>
771 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/misc.vhd" xil_pn:type="FILE_VHDL">
588 <file xil_pn:name="../../lib/gaisler/misc/wild.vhd" xil_pn:type="FILE_VHDL">
772 589 <association xil_pn:name="BehavioralSimulation"/>
773 590 <association xil_pn:name="Implementation"/>
774 591 <library xil_pn:name="gaisler"/>
775 592 </file>
776 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/rstgen.vhd" xil_pn:type="FILE_VHDL">
777 <association xil_pn:name="BehavioralSimulation"/>
778 <association xil_pn:name="Implementation"/>
779 <library xil_pn:name="gaisler"/>
780 </file>
781 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/gptimer.vhd" xil_pn:type="FILE_VHDL">
593 <file xil_pn:name="../../lib/gaisler/misc/wild2ahb.vhd" xil_pn:type="FILE_VHDL">
782 594 <association xil_pn:name="BehavioralSimulation"/>
783 595 <association xil_pn:name="Implementation"/>
784 596 <library xil_pn:name="gaisler"/>
785 597 </file>
786 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbram.vhd" xil_pn:type="FILE_VHDL">
787 <association xil_pn:name="BehavioralSimulation"/>
788 <association xil_pn:name="Implementation"/>
789 <library xil_pn:name="gaisler"/>
790 </file>
791 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbdpram.vhd" xil_pn:type="FILE_VHDL">
792 <association xil_pn:name="BehavioralSimulation"/>
793 <association xil_pn:name="Implementation"/>
794 <library xil_pn:name="gaisler"/>
795 </file>
796 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace.vhd" xil_pn:type="FILE_VHDL">
598 <file xil_pn:name="../../lib/gaisler/misc/grsysmon.vhd" xil_pn:type="FILE_VHDL">
797 599 <association xil_pn:name="BehavioralSimulation"/>
798 600 <association xil_pn:name="Implementation"/>
799 601 <library xil_pn:name="gaisler"/>
800 602 </file>
801 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace_mb.vhd" xil_pn:type="FILE_VHDL">
802 <association xil_pn:name="BehavioralSimulation"/>
803 <association xil_pn:name="Implementation"/>
804 <library xil_pn:name="gaisler"/>
805 </file>
806 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace_mmb.vhd" xil_pn:type="FILE_VHDL">
807 <association xil_pn:name="BehavioralSimulation"/>
808 <association xil_pn:name="Implementation"/>
809 <library xil_pn:name="gaisler"/>
810 </file>
811 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbmst.vhd" xil_pn:type="FILE_VHDL">
603 <file xil_pn:name="../../lib/gaisler/misc/gracectrl.vhd" xil_pn:type="FILE_VHDL">
812 604 <association xil_pn:name="BehavioralSimulation"/>
813 605 <association xil_pn:name="Implementation"/>
814 606 <library xil_pn:name="gaisler"/>
815 607 </file>
816 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grgpio.vhd" xil_pn:type="FILE_VHDL">
608 <file xil_pn:name="../../lib/gaisler/misc/grgpreg.vhd" xil_pn:type="FILE_VHDL">
817 609 <association xil_pn:name="BehavioralSimulation"/>
818 610 <association xil_pn:name="Implementation"/>
819 611 <library xil_pn:name="gaisler"/>
820 612 </file>
821 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbstat.vhd" xil_pn:type="FILE_VHDL">
613 <file xil_pn:name="../../lib/gaisler/misc/ahbmst2.vhd" xil_pn:type="FILE_VHDL">
822 614 <association xil_pn:name="BehavioralSimulation"/>
823 615 <association xil_pn:name="Implementation"/>
824 616 <library xil_pn:name="gaisler"/>
825 617 </file>
826 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/logan.vhd" xil_pn:type="FILE_VHDL">
827 <association xil_pn:name="BehavioralSimulation"/>
828 <association xil_pn:name="Implementation"/>
829 <library xil_pn:name="gaisler"/>
830 </file>
831 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/apbps2.vhd" xil_pn:type="FILE_VHDL">
618 <file xil_pn:name="../../lib/gaisler/misc/ahb_mst_iface.vhd" xil_pn:type="FILE_VHDL">
832 619 <association xil_pn:name="BehavioralSimulation"/>
833 620 <association xil_pn:name="Implementation"/>
834 621 <library xil_pn:name="gaisler"/>
835 622 </file>
836 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/charrom_package.vhd" xil_pn:type="FILE_VHDL">
623 <file xil_pn:name="../../lib/gaisler/ambatest/ahbtbp.vhd" xil_pn:type="FILE_VHDL">
837 624 <association xil_pn:name="BehavioralSimulation"/>
838 <association xil_pn:name="Implementation"/>
839 625 <library xil_pn:name="gaisler"/>
840 626 </file>
841 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/charrom.vhd" xil_pn:type="FILE_VHDL">
627 <file xil_pn:name="../../lib/gaisler/ambatest/ahbtbm.vhd" xil_pn:type="FILE_VHDL">
628 <association xil_pn:name="BehavioralSimulation"/>
629 <library xil_pn:name="gaisler"/>
630 </file>
631 <file xil_pn:name="../../lib/gaisler/net/net.vhd" xil_pn:type="FILE_VHDL">
842 632 <association xil_pn:name="BehavioralSimulation"/>
843 633 <association xil_pn:name="Implementation"/>
844 634 <library xil_pn:name="gaisler"/>
845 635 </file>
846 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/apbvga.vhd" xil_pn:type="FILE_VHDL">
847 <association xil_pn:name="BehavioralSimulation"/>
848 <association xil_pn:name="Implementation"/>
849 <library xil_pn:name="gaisler"/>
850 </file>
851 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/svgactrl.vhd" xil_pn:type="FILE_VHDL">
852 <association xil_pn:name="BehavioralSimulation"/>
853 <association xil_pn:name="Implementation"/>
854 <library xil_pn:name="gaisler"/>
855 </file>
856 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/i2cmst_gen.vhd" xil_pn:type="FILE_VHDL">
857 <association xil_pn:name="BehavioralSimulation"/>
858 <association xil_pn:name="Implementation"/>
859 <library xil_pn:name="gaisler"/>
860 </file>
861 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/spictrlx.vhd" xil_pn:type="FILE_VHDL">
636 <file xil_pn:name="../../lib/gaisler/uart/uart.vhd" xil_pn:type="FILE_VHDL">
862 637 <association xil_pn:name="BehavioralSimulation"/>
863 638 <association xil_pn:name="Implementation"/>
864 639 <library xil_pn:name="gaisler"/>
865 640 </file>
866 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/spictrl.vhd" xil_pn:type="FILE_VHDL">
641 <file xil_pn:name="../../lib/gaisler/uart/libdcom.vhd" xil_pn:type="FILE_VHDL">
867 642 <association xil_pn:name="BehavioralSimulation"/>
868 643 <association xil_pn:name="Implementation"/>
869 644 <library xil_pn:name="gaisler"/>
870 645 </file>
871 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/i2cslv.vhd" xil_pn:type="FILE_VHDL">
872 <association xil_pn:name="BehavioralSimulation"/>
873 <association xil_pn:name="Implementation"/>
874 <library xil_pn:name="gaisler"/>
875 </file>
876 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/wild.vhd" xil_pn:type="FILE_VHDL">
646 <file xil_pn:name="../../lib/gaisler/uart/apbuart.vhd" xil_pn:type="FILE_VHDL">
877 647 <association xil_pn:name="BehavioralSimulation"/>
878 648 <association xil_pn:name="Implementation"/>
879 649 <library xil_pn:name="gaisler"/>
880 650 </file>
881 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/wild2ahb.vhd" xil_pn:type="FILE_VHDL">
651 <file xil_pn:name="../../lib/gaisler/uart/dcom.vhd" xil_pn:type="FILE_VHDL">
882 652 <association xil_pn:name="BehavioralSimulation"/>
883 653 <association xil_pn:name="Implementation"/>
884 654 <library xil_pn:name="gaisler"/>
885 655 </file>
886 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grsysmon.vhd" xil_pn:type="FILE_VHDL">
656 <file xil_pn:name="../../lib/gaisler/uart/dcom_uart.vhd" xil_pn:type="FILE_VHDL">
887 657 <association xil_pn:name="BehavioralSimulation"/>
888 658 <association xil_pn:name="Implementation"/>
889 659 <library xil_pn:name="gaisler"/>
890 660 </file>
891 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/gracectrl.vhd" xil_pn:type="FILE_VHDL">
892 <association xil_pn:name="BehavioralSimulation"/>
893 <association xil_pn:name="Implementation"/>
894 <library xil_pn:name="gaisler"/>
895 </file>
896 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grgpreg.vhd" xil_pn:type="FILE_VHDL">
661 <file xil_pn:name="../../lib/gaisler/uart/ahbuart.vhd" xil_pn:type="FILE_VHDL">
897 662 <association xil_pn:name="BehavioralSimulation"/>
898 663 <association xil_pn:name="Implementation"/>
899 664 <library xil_pn:name="gaisler"/>
900 665 </file>
901 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbmst2.vhd" xil_pn:type="FILE_VHDL">
666 <file xil_pn:name="../../lib/gaisler/sim/sim.vhd" xil_pn:type="FILE_VHDL">
902 667 <association xil_pn:name="BehavioralSimulation"/>
903 <association xil_pn:name="Implementation"/>
904 668 <library xil_pn:name="gaisler"/>
905 669 </file>
906 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahb_mst_iface.vhd" xil_pn:type="FILE_VHDL">
907 <association xil_pn:name="BehavioralSimulation"/>
908 <association xil_pn:name="Implementation"/>
909 <library xil_pn:name="gaisler"/>
910 </file>
911 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/ambatest/ahbtbp.vhd" xil_pn:type="FILE_VHDL">
670 <file xil_pn:name="../../lib/gaisler/sim/sram.vhd" xil_pn:type="FILE_VHDL">
912 671 <association xil_pn:name="BehavioralSimulation"/>
913 672 <library xil_pn:name="gaisler"/>
914 673 </file>
915 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/ambatest/ahbtbm.vhd" xil_pn:type="FILE_VHDL">
674 <file xil_pn:name="../../lib/gaisler/sim/ata_device.vhd" xil_pn:type="FILE_VHDL">
675 <association xil_pn:name="BehavioralSimulation"/>
676 <library xil_pn:name="gaisler"/>
677 </file>
678 <file xil_pn:name="../../lib/gaisler/sim/sram16.vhd" xil_pn:type="FILE_VHDL">
679 <association xil_pn:name="BehavioralSimulation"/>
680 <library xil_pn:name="gaisler"/>
681 </file>
682 <file xil_pn:name="../../lib/gaisler/sim/phy.vhd" xil_pn:type="FILE_VHDL">
683 <association xil_pn:name="BehavioralSimulation"/>
684 <library xil_pn:name="gaisler"/>
685 </file>
686 <file xil_pn:name="../../lib/gaisler/sim/ahbrep.vhd" xil_pn:type="FILE_VHDL">
916 687 <association xil_pn:name="BehavioralSimulation"/>
917 688 <library xil_pn:name="gaisler"/>
918 689 </file>
919 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/net/net.vhd" xil_pn:type="FILE_VHDL">
690 <file xil_pn:name="../../lib/gaisler/sim/delay_wire.vhd" xil_pn:type="FILE_VHDL">
920 691 <association xil_pn:name="BehavioralSimulation"/>
921 <association xil_pn:name="Implementation"/>
922 692 <library xil_pn:name="gaisler"/>
923 693 </file>
924 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/uart.vhd" xil_pn:type="FILE_VHDL">
694 <file xil_pn:name="../../lib/gaisler/sim/spi_flash.vhd" xil_pn:type="FILE_VHDL">
925 695 <association xil_pn:name="BehavioralSimulation"/>
926 <association xil_pn:name="Implementation"/>
927 696 <library xil_pn:name="gaisler"/>
928 697 </file>
929 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/libdcom.vhd" xil_pn:type="FILE_VHDL">
698 <file xil_pn:name="../../lib/gaisler/sim/pwm_check.vhd" xil_pn:type="FILE_VHDL">
930 699 <association xil_pn:name="BehavioralSimulation"/>
931 <association xil_pn:name="Implementation"/>
932 700 <library xil_pn:name="gaisler"/>
933 701 </file>
934 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/apbuart.vhd" xil_pn:type="FILE_VHDL">
702 <file xil_pn:name="../../lib/gaisler/sim/usbsim.vhd" xil_pn:type="FILE_VHDL">
935 703 <association xil_pn:name="BehavioralSimulation"/>
936 <association xil_pn:name="Implementation"/>
937 704 <library xil_pn:name="gaisler"/>
938 705 </file>
939 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/dcom.vhd" xil_pn:type="FILE_VHDL">
706 <file xil_pn:name="../../lib/gaisler/sim/grusbdcsim.vhd" xil_pn:type="FILE_VHDL">
940 707 <association xil_pn:name="BehavioralSimulation"/>
941 <association xil_pn:name="Implementation"/>
942 708 <library xil_pn:name="gaisler"/>
943 709 </file>
944 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/dcom_uart.vhd" xil_pn:type="FILE_VHDL">
710 <file xil_pn:name="../../lib/gaisler/sim/grusb_dclsim.vhd" xil_pn:type="FILE_VHDL">
945 711 <association xil_pn:name="BehavioralSimulation"/>
946 <association xil_pn:name="Implementation"/>
947 712 <library xil_pn:name="gaisler"/>
948 713 </file>
949 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/ahbuart.vhd" xil_pn:type="FILE_VHDL">
714 <file xil_pn:name="../../lib/gaisler/jtag/jtag.vhd" xil_pn:type="FILE_VHDL">
950 715 <association xil_pn:name="BehavioralSimulation"/>
951 716 <association xil_pn:name="Implementation"/>
952 717 <library xil_pn:name="gaisler"/>
953 718 </file>
954 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/sim.vhd" xil_pn:type="FILE_VHDL">
955 <association xil_pn:name="BehavioralSimulation"/>
956 <library xil_pn:name="gaisler"/>
957 </file>
958 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/sram.vhd" xil_pn:type="FILE_VHDL">
959 <association xil_pn:name="BehavioralSimulation"/>
960 <library xil_pn:name="gaisler"/>
961 </file>
962 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/ata_device.vhd" xil_pn:type="FILE_VHDL">
719 <file xil_pn:name="../../lib/gaisler/jtag/libjtagcom.vhd" xil_pn:type="FILE_VHDL">
963 720 <association xil_pn:name="BehavioralSimulation"/>
964 <library xil_pn:name="gaisler"/>
965 </file>
966 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/sram16.vhd" xil_pn:type="FILE_VHDL">
967 <association xil_pn:name="BehavioralSimulation"/>
968 <library xil_pn:name="gaisler"/>
969 </file>
970 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/phy.vhd" xil_pn:type="FILE_VHDL">
971 <association xil_pn:name="BehavioralSimulation"/>
972 <library xil_pn:name="gaisler"/>
973 </file>
974 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/ahbrep.vhd" xil_pn:type="FILE_VHDL">
975 <association xil_pn:name="BehavioralSimulation"/>
721 <association xil_pn:name="Implementation"/>
976 722 <library xil_pn:name="gaisler"/>
977 723 </file>
978 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/delay_wire.vhd" xil_pn:type="FILE_VHDL">
724 <file xil_pn:name="../../lib/gaisler/jtag/jtagcom.vhd" xil_pn:type="FILE_VHDL">
979 725 <association xil_pn:name="BehavioralSimulation"/>
980 <library xil_pn:name="gaisler"/>
981 </file>
982 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/spi_flash.vhd" xil_pn:type="FILE_VHDL">
983 <association xil_pn:name="BehavioralSimulation"/>
984 <library xil_pn:name="gaisler"/>
985 </file>
986 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/pwm_check.vhd" xil_pn:type="FILE_VHDL">
987 <association xil_pn:name="BehavioralSimulation"/>
726 <association xil_pn:name="Implementation"/>
988 727 <library xil_pn:name="gaisler"/>
989 728 </file>
990 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/usbsim.vhd" xil_pn:type="FILE_VHDL">
991 <association xil_pn:name="BehavioralSimulation"/>
992 <library xil_pn:name="gaisler"/>
993 </file>
994 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/grusbdcsim.vhd" xil_pn:type="FILE_VHDL">
995 <association xil_pn:name="BehavioralSimulation"/>
996 <library xil_pn:name="gaisler"/>
997 </file>
998 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/grusb_dclsim.vhd" xil_pn:type="FILE_VHDL">
999 <association xil_pn:name="BehavioralSimulation"/>
1000 <library xil_pn:name="gaisler"/>
1001 </file>
1002 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtag.vhd" xil_pn:type="FILE_VHDL">
729 <file xil_pn:name="../../lib/gaisler/jtag/ahbjtag.vhd" xil_pn:type="FILE_VHDL">
1003 730 <association xil_pn:name="BehavioralSimulation"/>
1004 731 <association xil_pn:name="Implementation"/>
1005 732 <library xil_pn:name="gaisler"/>
1006 733 </file>
1007 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/libjtagcom.vhd" xil_pn:type="FILE_VHDL">
734 <file xil_pn:name="../../lib/gaisler/jtag/ahbjtag_bsd.vhd" xil_pn:type="FILE_VHDL">
1008 735 <association xil_pn:name="BehavioralSimulation"/>
1009 736 <association xil_pn:name="Implementation"/>
1010 737 <library xil_pn:name="gaisler"/>
1011 738 </file>
1012 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtagcom.vhd" xil_pn:type="FILE_VHDL">
739 <file xil_pn:name="../../lib/gaisler/jtag/bscanregs.vhd" xil_pn:type="FILE_VHDL">
1013 740 <association xil_pn:name="BehavioralSimulation"/>
1014 741 <association xil_pn:name="Implementation"/>
1015 742 <library xil_pn:name="gaisler"/>
1016 743 </file>
1017 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/ahbjtag.vhd" xil_pn:type="FILE_VHDL">
744 <file xil_pn:name="../../lib/gaisler/jtag/bscanregsbd.vhd" xil_pn:type="FILE_VHDL">
1018 745 <association xil_pn:name="BehavioralSimulation"/>
1019 746 <association xil_pn:name="Implementation"/>
1020 747 <library xil_pn:name="gaisler"/>
1021 748 </file>
1022 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/ahbjtag_bsd.vhd" xil_pn:type="FILE_VHDL">
749 <file xil_pn:name="../../lib/gaisler/jtag/jtagtst.vhd" xil_pn:type="FILE_VHDL">
1023 750 <association xil_pn:name="BehavioralSimulation"/>
1024 <association xil_pn:name="Implementation"/>
1025 751 <library xil_pn:name="gaisler"/>
1026 752 </file>
1027 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/bscanregs.vhd" xil_pn:type="FILE_VHDL">
1028 <association xil_pn:name="BehavioralSimulation"/>
1029 <association xil_pn:name="Implementation"/>
1030 <library xil_pn:name="gaisler"/>
1031 </file>
1032 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/bscanregsbd.vhd" xil_pn:type="FILE_VHDL">
753 <file xil_pn:name="../../lib/gaisler/gr1553b/gr1553b_pkg.vhd" xil_pn:type="FILE_VHDL">
1033 754 <association xil_pn:name="BehavioralSimulation"/>
1034 755 <association xil_pn:name="Implementation"/>
1035 756 <library xil_pn:name="gaisler"/>
1036 757 </file>
1037 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtagtst.vhd" xil_pn:type="FILE_VHDL">
1038 <association xil_pn:name="BehavioralSimulation"/>
1039 <library xil_pn:name="gaisler"/>
1040 </file>
1041 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/ethernet_mac.vhd" xil_pn:type="FILE_VHDL">
758 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd" xil_pn:type="FILE_VHDL">
1042 759 <association xil_pn:name="BehavioralSimulation"/>
1043 760 <association xil_pn:name="Implementation"/>
1044 <library xil_pn:name="gaisler"/>
1045 </file>
1046 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth.vhd" xil_pn:type="FILE_VHDL">
1047 <association xil_pn:name="BehavioralSimulation"/>
1048 <association xil_pn:name="Implementation"/>
1049 <library xil_pn:name="gaisler"/>
761 <library xil_pn:name="lpp"/>
1050 762 </file>
1051 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_mb.vhd" xil_pn:type="FILE_VHDL">
1052 <association xil_pn:name="BehavioralSimulation"/>
1053 <association xil_pn:name="Implementation"/>
1054 <library xil_pn:name="gaisler"/>
1055 </file>
1056 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_gbit.vhd" xil_pn:type="FILE_VHDL">
763 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd" xil_pn:type="FILE_VHDL">
1057 764 <association xil_pn:name="BehavioralSimulation"/>
1058 765 <association xil_pn:name="Implementation"/>
1059 <library xil_pn:name="gaisler"/>
766 <library xil_pn:name="lpp"/>
1060 767 </file>
1061 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_gbit_mb.vhd" xil_pn:type="FILE_VHDL">
1062 <association xil_pn:name="BehavioralSimulation"/>
1063 <association xil_pn:name="Implementation"/>
1064 <library xil_pn:name="gaisler"/>
1065 </file>
1066 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/grethm.vhd" xil_pn:type="FILE_VHDL">
768 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd" xil_pn:type="FILE_VHDL">
1067 769 <association xil_pn:name="BehavioralSimulation"/>
1068 770 <association xil_pn:name="Implementation"/>
1069 <library xil_pn:name="gaisler"/>
771 <library xil_pn:name="lpp"/>
1070 772 </file>
1071 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/spacewire.vhd" xil_pn:type="FILE_VHDL">
773 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd" xil_pn:type="FILE_VHDL">
1072 774 <association xil_pn:name="BehavioralSimulation"/>
1073 775 <association xil_pn:name="Implementation"/>
1074 <library xil_pn:name="gaisler"/>
1075 </file>
1076 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspw.vhd" xil_pn:type="FILE_VHDL">
1077 <association xil_pn:name="BehavioralSimulation"/>
1078 <association xil_pn:name="Implementation"/>
1079 <library xil_pn:name="gaisler"/>
776 <library xil_pn:name="lpp"/>
1080 777 </file>
1081 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspw2.vhd" xil_pn:type="FILE_VHDL">
1082 <association xil_pn:name="BehavioralSimulation"/>
1083 <association xil_pn:name="Implementation"/>
1084 <library xil_pn:name="gaisler"/>
1085 </file>
1086 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspwm.vhd" xil_pn:type="FILE_VHDL">
778 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd" xil_pn:type="FILE_VHDL">
1087 779 <association xil_pn:name="BehavioralSimulation"/>
1088 780 <association xil_pn:name="Implementation"/>
1089 <library xil_pn:name="gaisler"/>
781 <library xil_pn:name="lpp"/>
1090 782 </file>
1091 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/gr1553b/gr1553b_pkg.vhd" xil_pn:type="FILE_VHDL">
783 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd" xil_pn:type="FILE_VHDL">
1092 784 <association xil_pn:name="BehavioralSimulation"/>
1093 785 <association xil_pn:name="Implementation"/>
1094 <library xil_pn:name="gaisler"/>
786 <library xil_pn:name="lpp"/>
1095 787 </file>
1096 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/esa/memoryctrl/memoryctrl.vhd" xil_pn:type="FILE_VHDL">
1097 <association xil_pn:name="BehavioralSimulation"/>
1098 <association xil_pn:name="Implementation"/>
1099 <library xil_pn:name="esa"/>
1100 </file>
1101 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/esa/memoryctrl/mctrl.vhd" xil_pn:type="FILE_VHDL">
788 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd" xil_pn:type="FILE_VHDL">
1102 789 <association xil_pn:name="BehavioralSimulation"/>
1103 790 <association xil_pn:name="Implementation"/>
1104 <library xil_pn:name="esa"/>
1105 </file>
1106 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/utilities/conversions.vhd" xil_pn:type="FILE_VHDL">
1107 <association xil_pn:name="BehavioralSimulation"/>
1108 <library xil_pn:name="fmf"/>
1109 </file>
1110 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/utilities/gen_utils.vhd" xil_pn:type="FILE_VHDL">
1111 <association xil_pn:name="BehavioralSimulation"/>
1112 <library xil_pn:name="fmf"/>
791 <library xil_pn:name="lpp"/>
1113 792 </file>
1114 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/flash/flash.vhd" xil_pn:type="FILE_VHDL">
1115 <association xil_pn:name="BehavioralSimulation"/>
1116 <library xil_pn:name="fmf"/>
1117 </file>
1118 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/flash/s25fl064a.vhd" xil_pn:type="FILE_VHDL">
1119 <association xil_pn:name="BehavioralSimulation"/>
1120 <library xil_pn:name="fmf"/>
1121 </file>
1122 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/flash/m25p80.vhd" xil_pn:type="FILE_VHDL">
793 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd" xil_pn:type="FILE_VHDL">
1123 794 <association xil_pn:name="BehavioralSimulation"/>
1124 <library xil_pn:name="fmf"/>
1125 </file>
1126 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/fifo/idt7202.vhd" xil_pn:type="FILE_VHDL">
1127 <association xil_pn:name="BehavioralSimulation"/>
1128 <library xil_pn:name="fmf"/>
1129 </file>
1130 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gsi/ssram/functions.vhd" xil_pn:type="FILE_VHDL">
1131 <association xil_pn:name="BehavioralSimulation"/>
1132 <library xil_pn:name="gsi"/>
795 <association xil_pn:name="Implementation"/>
796 <library xil_pn:name="lpp"/>
1133 797 </file>
1134 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gsi/ssram/core_burst.vhd" xil_pn:type="FILE_VHDL">
798 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd" xil_pn:type="FILE_VHDL">
1135 799 <association xil_pn:name="BehavioralSimulation"/>
1136 <library xil_pn:name="gsi"/>
800 <association xil_pn:name="Implementation"/>
801 <library xil_pn:name="lpp"/>
1137 802 </file>
1138 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/gsi/ssram/g880e18bt.vhd" xil_pn:type="FILE_VHDL">
1139 <association xil_pn:name="BehavioralSimulation"/>
1140 <library xil_pn:name="gsi"/>
1141 </file>
1142 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd" xil_pn:type="FILE_VHDL">
803 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd" xil_pn:type="FILE_VHDL">
1143 804 <association xil_pn:name="BehavioralSimulation"/>
1144 805 <association xil_pn:name="Implementation"/>
1145 806 <library xil_pn:name="lpp"/>
1146 807 </file>
1147 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd" xil_pn:type="FILE_VHDL">
808 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/APB_IIR_Filter.vhd" xil_pn:type="FILE_VHDL">
809 <association xil_pn:name="BehavioralSimulation"/>
810 <association xil_pn:name="Implementation"/>
811 <library xil_pn:name="lpp"/>
812 </file>
813 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTER.vhd" xil_pn:type="FILE_VHDL">
814 <association xil_pn:name="BehavioralSimulation"/>
815 <association xil_pn:name="Implementation"/>
816 <library xil_pn:name="lpp"/>
817 </file>
818 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd" xil_pn:type="FILE_VHDL">
819 <association xil_pn:name="BehavioralSimulation"/>
820 <association xil_pn:name="Implementation"/>
821 <library xil_pn:name="lpp"/>
822 </file>
823 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd" xil_pn:type="FILE_VHDL">
824 <association xil_pn:name="BehavioralSimulation"/>
825 <association xil_pn:name="Implementation"/>
826 <library xil_pn:name="lpp"/>
827 </file>
828 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd" xil_pn:type="FILE_VHDL">
1148 829 <association xil_pn:name="BehavioralSimulation"/>
1149 830 <association xil_pn:name="Implementation"/>
1150 831 <library xil_pn:name="lpp"/>
1151 832 </file>
1152 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd" xil_pn:type="FILE_VHDL">
833 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd" xil_pn:type="FILE_VHDL">
834 <association xil_pn:name="BehavioralSimulation"/>
835 <association xil_pn:name="Implementation"/>
836 <library xil_pn:name="lpp"/>
837 </file>
838 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd" xil_pn:type="FILE_VHDL">
839 <association xil_pn:name="BehavioralSimulation"/>
840 <association xil_pn:name="Implementation"/>
841 <library xil_pn:name="lpp"/>
842 </file>
843 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd" xil_pn:type="FILE_VHDL">
1153 844 <association xil_pn:name="BehavioralSimulation"/>
1154 845 <association xil_pn:name="Implementation"/>
1155 846 <library xil_pn:name="lpp"/>
1156 847 </file>
1157 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd" xil_pn:type="FILE_VHDL">
848 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd" xil_pn:type="FILE_VHDL">
849 <association xil_pn:name="BehavioralSimulation"/>
850 <association xil_pn:name="Implementation"/>
851 <library xil_pn:name="lpp"/>
852 </file>
853 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd" xil_pn:type="FILE_VHDL">
854 <association xil_pn:name="BehavioralSimulation"/>
855 <association xil_pn:name="Implementation"/>
856 <library xil_pn:name="lpp"/>
857 </file>
858 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM.vhd" xil_pn:type="FILE_VHDL">
859 <association xil_pn:name="BehavioralSimulation"/>
860 <association xil_pn:name="Implementation"/>
861 <library xil_pn:name="lpp"/>
862 </file>
863 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd" xil_pn:type="FILE_VHDL">
1158 864 <association xil_pn:name="BehavioralSimulation"/>
1159 865 <association xil_pn:name="Implementation"/>
1160 866 <library xil_pn:name="lpp"/>
1161 867 </file>
1162 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd" xil_pn:type="FILE_VHDL">
868 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd" xil_pn:type="FILE_VHDL">
1163 869 <association xil_pn:name="BehavioralSimulation"/>
1164 870 <association xil_pn:name="Implementation"/>
1165 871 <library xil_pn:name="lpp"/>
1166 872 </file>
1167 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd" xil_pn:type="FILE_VHDL">
873 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd" xil_pn:type="FILE_VHDL">
1168 874 <association xil_pn:name="BehavioralSimulation"/>
1169 875 <association xil_pn:name="Implementation"/>
1170 876 <library xil_pn:name="lpp"/>
1171 877 </file>
1172 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd" xil_pn:type="FILE_VHDL">
878 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd" xil_pn:type="FILE_VHDL">
1173 879 <association xil_pn:name="BehavioralSimulation"/>
1174 880 <association xil_pn:name="Implementation"/>
1175 881 <library xil_pn:name="lpp"/>
1176 882 </file>
1177 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd" xil_pn:type="FILE_VHDL">
883 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd" xil_pn:type="FILE_VHDL">
1178 884 <association xil_pn:name="BehavioralSimulation"/>
1179 885 <association xil_pn:name="Implementation"/>
1180 886 <library xil_pn:name="lpp"/>
1181 887 </file>
1182 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd" xil_pn:type="FILE_VHDL">
888 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/Top_IIR.vhd" xil_pn:type="FILE_VHDL">
1183 889 <association xil_pn:name="BehavioralSimulation"/>
1184 890 <association xil_pn:name="Implementation"/>
1185 891 <library xil_pn:name="lpp"/>
1186 892 </file>
1187 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd" xil_pn:type="FILE_VHDL">
893 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/iir_filter.vhd" xil_pn:type="FILE_VHDL">
1188 894 <association xil_pn:name="BehavioralSimulation"/>
1189 895 <association xil_pn:name="Implementation"/>
1190 896 <library xil_pn:name="lpp"/>
1191 897 </file>
1192 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/APB_IIR_Filter.vhd" xil_pn:type="FILE_VHDL">
1193 <association xil_pn:name="BehavioralSimulation"/>
1194 <association xil_pn:name="Implementation"/>
1195 <library xil_pn:name="lpp"/>
1196 </file>
1197 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTER.vhd" xil_pn:type="FILE_VHDL">
898 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd" xil_pn:type="FILE_VHDL">
1198 899 <association xil_pn:name="BehavioralSimulation"/>
1199 900 <association xil_pn:name="Implementation"/>
1200 901 <library xil_pn:name="lpp"/>
1201 902 </file>
1202 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd" xil_pn:type="FILE_VHDL">
903 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/APB_FFT.vhd" xil_pn:type="FILE_VHDL">
1203 904 <association xil_pn:name="BehavioralSimulation"/>
1204 905 <association xil_pn:name="Implementation"/>
1205 906 <library xil_pn:name="lpp"/>
1206 907 </file>
1207 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd" xil_pn:type="FILE_VHDL">
908 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/APB_FFT_half.vhd" xil_pn:type="FILE_VHDL">
1208 909 <association xil_pn:name="BehavioralSimulation"/>
1209 910 <association xil_pn:name="Implementation"/>
1210 911 <library xil_pn:name="lpp"/>
1211 912 </file>
1212 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd" xil_pn:type="FILE_VHDL">
913 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd" xil_pn:type="FILE_VHDL">
1213 914 <association xil_pn:name="BehavioralSimulation"/>
1214 915 <association xil_pn:name="Implementation"/>
1215 916 <library xil_pn:name="lpp"/>
1216 917 </file>
1217 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd" xil_pn:type="FILE_VHDL">
918 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd" xil_pn:type="FILE_VHDL">
1218 919 <association xil_pn:name="BehavioralSimulation"/>
1219 920 <association xil_pn:name="Implementation"/>
1220 921 <library xil_pn:name="lpp"/>
1221 922 </file>
1222 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd" xil_pn:type="FILE_VHDL">
923 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd.bak" xil_pn:type="FILE_VHDL">
1223 924 <association xil_pn:name="BehavioralSimulation"/>
1224 925 <association xil_pn:name="Implementation"/>
1225 926 <library xil_pn:name="lpp"/>
1226 927 </file>
1227 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd" xil_pn:type="FILE_VHDL">
928 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFTamont.vhd" xil_pn:type="FILE_VHDL">
1228 929 <association xil_pn:name="BehavioralSimulation"/>
1229 930 <association xil_pn:name="Implementation"/>
1230 931 <library xil_pn:name="lpp"/>
1231 932 </file>
1232 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd" xil_pn:type="FILE_VHDL">
933 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFTaval.vhd" xil_pn:type="FILE_VHDL">
1233 934 <association xil_pn:name="BehavioralSimulation"/>
1234 935 <association xil_pn:name="Implementation"/>
1235 936 <library xil_pn:name="lpp"/>
1236 937 </file>
1237 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd" xil_pn:type="FILE_VHDL">
938 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd" xil_pn:type="FILE_VHDL">
1238 939 <association xil_pn:name="BehavioralSimulation"/>
1239 940 <association xil_pn:name="Implementation"/>
1240 941 <library xil_pn:name="lpp"/>
1241 942 </file>
1242 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM.vhd" xil_pn:type="FILE_VHDL">
943 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd.bak" xil_pn:type="FILE_VHDL">
1243 944 <association xil_pn:name="BehavioralSimulation"/>
1244 945 <association xil_pn:name="Implementation"/>
1245 946 <library xil_pn:name="lpp"/>
1246 947 </file>
1247 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd" xil_pn:type="FILE_VHDL">
948 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd" xil_pn:type="FILE_VHDL">
1248 949 <association xil_pn:name="BehavioralSimulation"/>
1249 950 <association xil_pn:name="Implementation"/>
1250 951 <library xil_pn:name="lpp"/>
1251 952 </file>
1252 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd" xil_pn:type="FILE_VHDL">
953 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd" xil_pn:type="FILE_VHDL">
1253 954 <association xil_pn:name="BehavioralSimulation"/>
1254 955 <association xil_pn:name="Implementation"/>
1255 956 <library xil_pn:name="lpp"/>
1256 957 </file>
1257 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd" xil_pn:type="FILE_VHDL">
958 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/ADDRcntr.vhd" xil_pn:type="FILE_VHDL">
1258 959 <association xil_pn:name="BehavioralSimulation"/>
1259 960 <association xil_pn:name="Implementation"/>
1260 961 <library xil_pn:name="lpp"/>
1261 962 </file>
1262 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd" xil_pn:type="FILE_VHDL">
963 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/ALU.vhd" xil_pn:type="FILE_VHDL">
1263 964 <association xil_pn:name="BehavioralSimulation"/>
1264 965 <association xil_pn:name="Implementation"/>
1265 966 <library xil_pn:name="lpp"/>
1266 967 </file>
1267 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd" xil_pn:type="FILE_VHDL">
1268 <association xil_pn:name="BehavioralSimulation"/>
1269 <association xil_pn:name="Implementation"/>
1270 <library xil_pn:name="lpp"/>
1271 </file>
1272 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/Top_IIR.vhd" xil_pn:type="FILE_VHDL">
968 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/Adder.vhd" xil_pn:type="FILE_VHDL">
1273 969 <association xil_pn:name="BehavioralSimulation"/>
1274 970 <association xil_pn:name="Implementation"/>
1275 971 <library xil_pn:name="lpp"/>
1276 972 </file>
1277 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/iir_filter.vhd" xil_pn:type="FILE_VHDL">
973 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/Clk_Divider2.vhd" xil_pn:type="FILE_VHDL">
1278 974 <association xil_pn:name="BehavioralSimulation"/>
1279 975 <association xil_pn:name="Implementation"/>
1280 976 <library xil_pn:name="lpp"/>
1281 977 </file>
1282 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd" xil_pn:type="FILE_VHDL">
978 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/Clk_divider.vhd" xil_pn:type="FILE_VHDL">
1283 979 <association xil_pn:name="BehavioralSimulation"/>
1284 980 <association xil_pn:name="Implementation"/>
1285 981 <library xil_pn:name="lpp"/>
1286 982 </file>
1287 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/APB_FFT.vhd" xil_pn:type="FILE_VHDL">
983 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC.vhd" xil_pn:type="FILE_VHDL">
1288 984 <association xil_pn:name="BehavioralSimulation"/>
1289 985 <association xil_pn:name="Implementation"/>
1290 986 <library xil_pn:name="lpp"/>
1291 987 </file>
1292 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/APB_FFT_half.vhd" xil_pn:type="FILE_VHDL">
988 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd" xil_pn:type="FILE_VHDL">
1293 989 <association xil_pn:name="BehavioralSimulation"/>
1294 990 <association xil_pn:name="Implementation"/>
1295 991 <library xil_pn:name="lpp"/>
1296 992 </file>
1297 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd" xil_pn:type="FILE_VHDL">
993 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_MUX.vhd" xil_pn:type="FILE_VHDL">
1298 994 <association xil_pn:name="BehavioralSimulation"/>
1299 995 <association xil_pn:name="Implementation"/>
1300 996 <library xil_pn:name="lpp"/>
1301 997 </file>
1302 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd" xil_pn:type="FILE_VHDL">
998 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_MUX2.vhd" xil_pn:type="FILE_VHDL">
1303 999 <association xil_pn:name="BehavioralSimulation"/>
1304 1000 <association xil_pn:name="Implementation"/>
1305 1001 <library xil_pn:name="lpp"/>
1306 1002 </file>
1307 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd.bak" xil_pn:type="FILE_VHDL">
1003 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_REG.vhd" xil_pn:type="FILE_VHDL">
1308 1004 <association xil_pn:name="BehavioralSimulation"/>
1309 1005 <association xil_pn:name="Implementation"/>
1310 1006 <library xil_pn:name="lpp"/>
1311 1007 </file>
1312 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFTamont.vhd" xil_pn:type="FILE_VHDL">
1008 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MUX2.vhd" xil_pn:type="FILE_VHDL">
1313 1009 <association xil_pn:name="BehavioralSimulation"/>
1314 1010 <association xil_pn:name="Implementation"/>
1315 1011 <library xil_pn:name="lpp"/>
1316 1012 </file>
1317 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFTaval.vhd" xil_pn:type="FILE_VHDL">
1013 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/MUXN.vhd" xil_pn:type="FILE_VHDL">
1318 1014 <association xil_pn:name="BehavioralSimulation"/>
1319 1015 <association xil_pn:name="Implementation"/>
1320 1016 <library xil_pn:name="lpp"/>
1321 1017 </file>
1322 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd" xil_pn:type="FILE_VHDL">
1323 <association xil_pn:name="BehavioralSimulation"/>
1324 <association xil_pn:name="Implementation"/>
1325 <library xil_pn:name="lpp"/>
1326 </file>
1327 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd.bak" xil_pn:type="FILE_VHDL">
1018 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/Multiplier.vhd" xil_pn:type="FILE_VHDL">
1328 1019 <association xil_pn:name="BehavioralSimulation"/>
1329 1020 <association xil_pn:name="Implementation"/>
1330 1021 <library xil_pn:name="lpp"/>
1331 1022 </file>
1332 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd" xil_pn:type="FILE_VHDL">
1023 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/REG.vhd" xil_pn:type="FILE_VHDL">
1333 1024 <association xil_pn:name="BehavioralSimulation"/>
1334 1025 <association xil_pn:name="Implementation"/>
1335 1026 <library xil_pn:name="lpp"/>
1336 1027 </file>
1337 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd" xil_pn:type="FILE_VHDL">
1028 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/SYNC_FF.vhd" xil_pn:type="FILE_VHDL">
1338 1029 <association xil_pn:name="BehavioralSimulation"/>
1339 1030 <association xil_pn:name="Implementation"/>
1340 1031 <library xil_pn:name="lpp"/>
1341 1032 </file>
1342 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/ADDRcntr.vhd" xil_pn:type="FILE_VHDL">
1033 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/Shifter.vhd" xil_pn:type="FILE_VHDL">
1343 1034 <association xil_pn:name="BehavioralSimulation"/>
1344 1035 <association xil_pn:name="Implementation"/>
1345 1036 <library xil_pn:name="lpp"/>
1346 1037 </file>
1347 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/ALU.vhd" xil_pn:type="FILE_VHDL">
1038 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/TwoComplementer.vhd" xil_pn:type="FILE_VHDL">
1348 1039 <association xil_pn:name="BehavioralSimulation"/>
1349 1040 <association xil_pn:name="Implementation"/>
1350 1041 <library xil_pn:name="lpp"/>
1351 1042 </file>
1352 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Adder.vhd" xil_pn:type="FILE_VHDL">
1043 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/general_purpose.vhd" xil_pn:type="FILE_VHDL">
1353 1044 <association xil_pn:name="BehavioralSimulation"/>
1354 1045 <association xil_pn:name="Implementation"/>
1355 1046 <library xil_pn:name="lpp"/>
1356 1047 </file>
1357 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Clk_Divider2.vhd" xil_pn:type="FILE_VHDL">
1048 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/APB_AMR.vhd" xil_pn:type="FILE_VHDL">
1358 1049 <association xil_pn:name="BehavioralSimulation"/>
1359 1050 <association xil_pn:name="Implementation"/>
1360 1051 <library xil_pn:name="lpp"/>
1361 1052 </file>
1362 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Clk_divider.vhd" xil_pn:type="FILE_VHDL">
1053 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Clock_multi.vhd" xil_pn:type="FILE_VHDL">
1363 1054 <association xil_pn:name="BehavioralSimulation"/>
1364 1055 <association xil_pn:name="Implementation"/>
1365 1056 <library xil_pn:name="lpp"/>
1366 1057 </file>
1367 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC.vhd" xil_pn:type="FILE_VHDL">
1058 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Dephaseur.vhd" xil_pn:type="FILE_VHDL">
1368 1059 <association xil_pn:name="BehavioralSimulation"/>
1369 1060 <association xil_pn:name="Implementation"/>
1370 1061 <library xil_pn:name="lpp"/>
1371 1062 </file>
1372 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd" xil_pn:type="FILE_VHDL">
1373 <association xil_pn:name="BehavioralSimulation"/>
1374 <association xil_pn:name="Implementation"/>
1375 <library xil_pn:name="lpp"/>
1376 </file>
1377 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_MUX.vhd" xil_pn:type="FILE_VHDL">
1063 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Gene_Rz.vhd" xil_pn:type="FILE_VHDL">
1378 1064 <association xil_pn:name="BehavioralSimulation"/>
1379 1065 <association xil_pn:name="Implementation"/>
1380 1066 <library xil_pn:name="lpp"/>
1381 1067 </file>
1382 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_MUX2.vhd" xil_pn:type="FILE_VHDL">
1068 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/bclk_reg.vhd" xil_pn:type="FILE_VHDL">
1383 1069 <association xil_pn:name="BehavioralSimulation"/>
1384 1070 <association xil_pn:name="Implementation"/>
1385 1071 <library xil_pn:name="lpp"/>
1386 1072 </file>
1387 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_REG.vhd" xil_pn:type="FILE_VHDL">
1073 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/lpp_AMR.vhd" xil_pn:type="FILE_VHDL">
1388 1074 <association xil_pn:name="BehavioralSimulation"/>
1389 1075 <association xil_pn:name="Implementation"/>
1390 1076 <library xil_pn:name="lpp"/>
1391 1077 </file>
1392 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MUX2.vhd" xil_pn:type="FILE_VHDL">
1078 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_balise/APB_Balise.vhd" xil_pn:type="FILE_VHDL">
1393 1079 <association xil_pn:name="BehavioralSimulation"/>
1394 1080 <association xil_pn:name="Implementation"/>
1395 1081 <library xil_pn:name="lpp"/>
1396 1082 </file>
1397 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MUXN.vhd" xil_pn:type="FILE_VHDL">
1083 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_balise/lpp_balise.vhd" xil_pn:type="FILE_VHDL">
1398 1084 <association xil_pn:name="BehavioralSimulation"/>
1399 1085 <association xil_pn:name="Implementation"/>
1400 1086 <library xil_pn:name="lpp"/>
1401 1087 </file>
1402 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Multiplier.vhd" xil_pn:type="FILE_VHDL">
1088 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/APB_Delay.vhd" xil_pn:type="FILE_VHDL">
1403 1089 <association xil_pn:name="BehavioralSimulation"/>
1404 1090 <association xil_pn:name="Implementation"/>
1405 1091 <library xil_pn:name="lpp"/>
1406 1092 </file>
1407 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/REG.vhd" xil_pn:type="FILE_VHDL">
1093 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/TimerDelay.vhd" xil_pn:type="FILE_VHDL">
1408 1094 <association xil_pn:name="BehavioralSimulation"/>
1409 1095 <association xil_pn:name="Implementation"/>
1410 1096 <library xil_pn:name="lpp"/>
1411 1097 </file>
1412 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/SYNC_FF.vhd" xil_pn:type="FILE_VHDL">
1098 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/lpp_delay.vhd" xil_pn:type="FILE_VHDL">
1413 1099 <association xil_pn:name="BehavioralSimulation"/>
1414 1100 <association xil_pn:name="Implementation"/>
1415 1101 <library xil_pn:name="lpp"/>
1416 1102 </file>
1417 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Shifter.vhd" xil_pn:type="FILE_VHDL">
1103 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lfr_time_management/apb_lfr_time_management.vhd" xil_pn:type="FILE_VHDL">
1418 1104 <association xil_pn:name="BehavioralSimulation"/>
1419 1105 <association xil_pn:name="Implementation"/>
1420 1106 <library xil_pn:name="lpp"/>
1421 1107 </file>
1422 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/TwoComplementer.vhd" xil_pn:type="FILE_VHDL">
1108 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lfr_time_management/lfr_time_management.vhd" xil_pn:type="FILE_VHDL">
1423 1109 <association xil_pn:name="BehavioralSimulation"/>
1424 1110 <association xil_pn:name="Implementation"/>
1425 1111 <library xil_pn:name="lpp"/>
1426 1112 </file>
1427 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/general_purpose.vhd" xil_pn:type="FILE_VHDL">
1113 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lfr_time_management/lpp_lfr_time_management.vhd" xil_pn:type="FILE_VHDL">
1428 1114 <association xil_pn:name="BehavioralSimulation"/>
1429 1115 <association xil_pn:name="Implementation"/>
1430 1116 <library xil_pn:name="lpp"/>
1431 1117 </file>
1432 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/APB_AMR.vhd" xil_pn:type="FILE_VHDL">
1118 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd" xil_pn:type="FILE_VHDL">
1433 1119 <association xil_pn:name="BehavioralSimulation"/>
1434 1120 <association xil_pn:name="Implementation"/>
1435 1121 <library xil_pn:name="lpp"/>
1436 1122 </file>
1437 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Clock_multi.vhd" xil_pn:type="FILE_VHDL">
1438 <association xil_pn:name="BehavioralSimulation"/>
1439 <association xil_pn:name="Implementation"/>
1440 <library xil_pn:name="lpp"/>
1441 </file>
1442 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Dephaseur.vhd" xil_pn:type="FILE_VHDL">
1123 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_drvr_sync.vhd" xil_pn:type="FILE_VHDL">
1443 1124 <association xil_pn:name="BehavioralSimulation"/>
1444 1125 <association xil_pn:name="Implementation"/>
1445 1126 <library xil_pn:name="lpp"/>
1446 1127 </file>
1447 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Gene_Rz.vhd" xil_pn:type="FILE_VHDL">
1128 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd" xil_pn:type="FILE_VHDL">
1448 1129 <association xil_pn:name="BehavioralSimulation"/>
1449 1130 <association xil_pn:name="Implementation"/>
1450 1131 <library xil_pn:name="lpp"/>
1451 1132 </file>
1452 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/bclk_reg.vhd" xil_pn:type="FILE_VHDL">
1453 <association xil_pn:name="BehavioralSimulation"/>
1454 <association xil_pn:name="Implementation"/>
1455 <library xil_pn:name="lpp"/>
1456 </file>
1457 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/lpp_AMR.vhd" xil_pn:type="FILE_VHDL">
1133 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS1274_drvr.vhd" xil_pn:type="FILE_VHDL">
1458 1134 <association xil_pn:name="BehavioralSimulation"/>
1459 1135 <association xil_pn:name="Implementation"/>
1460 1136 <library xil_pn:name="lpp"/>
1461 1137 </file>
1462 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_balise/APB_Balise.vhd" xil_pn:type="FILE_VHDL">
1138 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS1278_drvr.vhd" xil_pn:type="FILE_VHDL">
1463 1139 <association xil_pn:name="BehavioralSimulation"/>
1464 1140 <association xil_pn:name="Implementation"/>
1465 1141 <library xil_pn:name="lpp"/>
1466 1142 </file>
1467 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_balise/lpp_balise.vhd" xil_pn:type="FILE_VHDL">
1143 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd" xil_pn:type="FILE_VHDL">
1468 1144 <association xil_pn:name="BehavioralSimulation"/>
1469 1145 <association xil_pn:name="Implementation"/>
1470 1146 <library xil_pn:name="lpp"/>
1471 1147 </file>
1472 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/APB_Delay.vhd" xil_pn:type="FILE_VHDL">
1148 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/RHF1401.vhd" xil_pn:type="FILE_VHDL">
1473 1149 <association xil_pn:name="BehavioralSimulation"/>
1474 1150 <association xil_pn:name="Implementation"/>
1475 1151 <library xil_pn:name="lpp"/>
1476 1152 </file>
1477 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/TimerDelay.vhd" xil_pn:type="FILE_VHDL">
1153 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/WriteGen_ADC.vhd" xil_pn:type="FILE_VHDL">
1478 1154 <association xil_pn:name="BehavioralSimulation"/>
1479 1155 <association xil_pn:name="Implementation"/>
1480 1156 <library xil_pn:name="lpp"/>
1481 1157 </file>
1482 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/lpp_delay.vhd" xil_pn:type="FILE_VHDL">
1158 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/dual_ADS1278_drvr.vhd" xil_pn:type="FILE_VHDL">
1483 1159 <association xil_pn:name="BehavioralSimulation"/>
1484 1160 <association xil_pn:name="Implementation"/>
1485 1161 <library xil_pn:name="lpp"/>
1486 1162 </file>
1487 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lfr_time_management/apb_lfr_time_management.vhd" xil_pn:type="FILE_VHDL">
1163 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd" xil_pn:type="FILE_VHDL">
1488 1164 <association xil_pn:name="BehavioralSimulation"/>
1489 1165 <association xil_pn:name="Implementation"/>
1490 1166 <library xil_pn:name="lpp"/>
1491 1167 </file>
1492 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lfr_time_management/lfr_time_management.vhd" xil_pn:type="FILE_VHDL">
1168 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd" xil_pn:type="FILE_VHDL">
1493 1169 <association xil_pn:name="BehavioralSimulation"/>
1494 1170 <association xil_pn:name="Implementation"/>
1495 1171 <library xil_pn:name="lpp"/>
1496 1172 </file>
1497 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lfr_time_management/lpp_lfr_time_management.vhd" xil_pn:type="FILE_VHDL">
1173 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/top_ad_conv.vhd" xil_pn:type="FILE_VHDL">
1498 1174 <association xil_pn:name="BehavioralSimulation"/>
1499 1175 <association xil_pn:name="Implementation"/>
1500 1176 <library xil_pn:name="lpp"/>
1501 1177 </file>
1502 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd" xil_pn:type="FILE_VHDL">
1178 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd" xil_pn:type="FILE_VHDL">
1503 1179 <association xil_pn:name="BehavioralSimulation"/>
1504 1180 <association xil_pn:name="Implementation"/>
1505 1181 <library xil_pn:name="lpp"/>
1506 1182 </file>
1507 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_drvr_sync.vhd" xil_pn:type="FILE_VHDL">
1183 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd" xil_pn:type="FILE_VHDL">
1508 1184 <association xil_pn:name="BehavioralSimulation"/>
1509 1185 <association xil_pn:name="Implementation"/>
1510 1186 <library xil_pn:name="lpp"/>
1511 1187 </file>
1512 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd" xil_pn:type="FILE_VHDL">
1188 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd" xil_pn:type="FILE_VHDL">
1513 1189 <association xil_pn:name="BehavioralSimulation"/>
1514 1190 <association xil_pn:name="Implementation"/>
1515 1191 <library xil_pn:name="lpp"/>
1516 1192 </file>
1517 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS1274_drvr.vhd" xil_pn:type="FILE_VHDL">
1193 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_amba/apb_devices_list.vhd" xil_pn:type="FILE_VHDL">
1518 1194 <association xil_pn:name="BehavioralSimulation"/>
1519 1195 <association xil_pn:name="Implementation"/>
1520 1196 <library xil_pn:name="lpp"/>
1521 1197 </file>
1522 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS1278_drvr.vhd" xil_pn:type="FILE_VHDL">
1198 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_amba/lpp_amba.vhd" xil_pn:type="FILE_VHDL">
1523 1199 <association xil_pn:name="BehavioralSimulation"/>
1524 1200 <association xil_pn:name="Implementation"/>
1525 1201 <library xil_pn:name="lpp"/>
1526 1202 </file>
1527 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd" xil_pn:type="FILE_VHDL">
1528 <association xil_pn:name="BehavioralSimulation"/>
1529 <association xil_pn:name="Implementation"/>
1530 <library xil_pn:name="lpp"/>
1531 </file>
1532 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/RHF1401.vhd" xil_pn:type="FILE_VHDL">
1203 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/bootrom.vhd" xil_pn:type="FILE_VHDL">
1533 1204 <association xil_pn:name="BehavioralSimulation"/>
1534 1205 <association xil_pn:name="Implementation"/>
1535 1206 <library xil_pn:name="lpp"/>
1536 1207 </file>
1537 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/WriteGen_ADC.vhd" xil_pn:type="FILE_VHDL">
1208 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd" xil_pn:type="FILE_VHDL">
1538 1209 <association xil_pn:name="BehavioralSimulation"/>
1539 1210 <association xil_pn:name="Implementation"/>
1540 1211 <library xil_pn:name="lpp"/>
1541 1212 </file>
1542 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/dual_ADS1278_drvr.vhd" xil_pn:type="FILE_VHDL">
1213 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd" xil_pn:type="FILE_VHDL">
1543 1214 <association xil_pn:name="BehavioralSimulation"/>
1544 1215 <association xil_pn:name="Implementation"/>
1545 1216 <library xil_pn:name="lpp"/>
1546 1217 </file>
1547 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd" xil_pn:type="FILE_VHDL">
1218 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/APB_CNA.vhd" xil_pn:type="FILE_VHDL">
1548 1219 <association xil_pn:name="BehavioralSimulation"/>
1549 1220 <association xil_pn:name="Implementation"/>
1550 1221 <library xil_pn:name="lpp"/>
1551 1222 </file>
1552 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd" xil_pn:type="FILE_VHDL">
1223 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/CNA_TabloC.vhd" xil_pn:type="FILE_VHDL">
1553 1224 <association xil_pn:name="BehavioralSimulation"/>
1554 1225 <association xil_pn:name="Implementation"/>
1555 1226 <library xil_pn:name="lpp"/>
1556 1227 </file>
1557 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/top_ad_conv.vhd" xil_pn:type="FILE_VHDL">
1228 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/Convertisseur_config.vhd" xil_pn:type="FILE_VHDL">
1558 1229 <association xil_pn:name="BehavioralSimulation"/>
1559 1230 <association xil_pn:name="Implementation"/>
1560 1231 <library xil_pn:name="lpp"/>
1561 1232 </file>
1562 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd" xil_pn:type="FILE_VHDL">
1233 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/Gene_SYNC.vhd" xil_pn:type="FILE_VHDL">
1563 1234 <association xil_pn:name="BehavioralSimulation"/>
1564 1235 <association xil_pn:name="Implementation"/>
1565 1236 <library xil_pn:name="lpp"/>
1566 1237 </file>
1567 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd" xil_pn:type="FILE_VHDL">
1238 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/Serialize.vhd" xil_pn:type="FILE_VHDL">
1568 1239 <association xil_pn:name="BehavioralSimulation"/>
1569 1240 <association xil_pn:name="Implementation"/>
1570 1241 <library xil_pn:name="lpp"/>
1571 1242 </file>
1572 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd" xil_pn:type="FILE_VHDL">
1243 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/Systeme_Clock.vhd" xil_pn:type="FILE_VHDL">
1573 1244 <association xil_pn:name="BehavioralSimulation"/>
1574 1245 <association xil_pn:name="Implementation"/>
1575 1246 <library xil_pn:name="lpp"/>
1576 1247 </file>
1577 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_amba/apb_devices_list.vhd" xil_pn:type="FILE_VHDL">
1248 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_cna/lpp_cna.vhd" xil_pn:type="FILE_VHDL">
1578 1249 <association xil_pn:name="BehavioralSimulation"/>
1579 1250 <association xil_pn:name="Implementation"/>
1580 1251 <library xil_pn:name="lpp"/>
1581 1252 </file>
1582 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_amba/lpp_amba.vhd" xil_pn:type="FILE_VHDL">
1583 <association xil_pn:name="BehavioralSimulation"/>
1584 <association xil_pn:name="Implementation"/>
1585 <library xil_pn:name="lpp"/>
1586 </file>
1587 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/bootrom.vhd" xil_pn:type="FILE_VHDL">
1253 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_demux/DEMUX.vhd" xil_pn:type="FILE_VHDL">
1588 1254 <association xil_pn:name="BehavioralSimulation"/>
1589 1255 <association xil_pn:name="Implementation"/>
1590 1256 <library xil_pn:name="lpp"/>
1591 1257 </file>
1592 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd" xil_pn:type="FILE_VHDL">
1258 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_demux/lpp_demux.vhd" xil_pn:type="FILE_VHDL">
1593 1259 <association xil_pn:name="BehavioralSimulation"/>
1594 1260 <association xil_pn:name="Implementation"/>
1595 1261 <library xil_pn:name="lpp"/>
1596 1262 </file>
1597 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd" xil_pn:type="FILE_VHDL">
1263 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd" xil_pn:type="FILE_VHDL">
1598 1264 <association xil_pn:name="BehavioralSimulation"/>
1599 1265 <association xil_pn:name="Implementation"/>
1600 1266 <library xil_pn:name="lpp"/>
1601 1267 </file>
1602 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/APB_CNA.vhd" xil_pn:type="FILE_VHDL">
1268 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma.vhd" xil_pn:type="FILE_VHDL">
1603 1269 <association xil_pn:name="BehavioralSimulation"/>
1604 1270 <association xil_pn:name="Implementation"/>
1605 1271 <library xil_pn:name="lpp"/>
1606 1272 </file>
1607 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/CNA_TabloC.vhd" xil_pn:type="FILE_VHDL">
1273 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_apbreg.vhd" xil_pn:type="FILE_VHDL">
1608 1274 <association xil_pn:name="BehavioralSimulation"/>
1609 1275 <association xil_pn:name="Implementation"/>
1610 1276 <library xil_pn:name="lpp"/>
1611 1277 </file>
1612 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/Convertisseur_config.vhd" xil_pn:type="FILE_VHDL">
1278 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_fsm.vhd" xil_pn:type="FILE_VHDL">
1613 1279 <association xil_pn:name="BehavioralSimulation"/>
1614 1280 <association xil_pn:name="Implementation"/>
1615 1281 <library xil_pn:name="lpp"/>
1616 1282 </file>
1617 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/Gene_SYNC.vhd" xil_pn:type="FILE_VHDL">
1283 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd" xil_pn:type="FILE_VHDL">
1618 1284 <association xil_pn:name="BehavioralSimulation"/>
1619 1285 <association xil_pn:name="Implementation"/>
1620 1286 <library xil_pn:name="lpp"/>
1621 1287 </file>
1622 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/Serialize.vhd" xil_pn:type="FILE_VHDL">
1288 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd" xil_pn:type="FILE_VHDL">
1623 1289 <association xil_pn:name="BehavioralSimulation"/>
1624 1290 <association xil_pn:name="Implementation"/>
1625 1291 <library xil_pn:name="lpp"/>
1626 1292 </file>
1627 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/Systeme_Clock.vhd" xil_pn:type="FILE_VHDL">
1293 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd" xil_pn:type="FILE_VHDL">
1628 1294 <association xil_pn:name="BehavioralSimulation"/>
1629 1295 <association xil_pn:name="Implementation"/>
1630 1296 <library xil_pn:name="lpp"/>
1631 1297 </file>
1632 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/lpp_cna.vhd" xil_pn:type="FILE_VHDL">
1633 <association xil_pn:name="BehavioralSimulation"/>
1634 <association xil_pn:name="Implementation"/>
1635 <library xil_pn:name="lpp"/>
1636 </file>
1637 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_demux/DEMUX.vhd" xil_pn:type="FILE_VHDL">
1298 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd" xil_pn:type="FILE_VHDL">
1638 1299 <association xil_pn:name="BehavioralSimulation"/>
1639 1300 <association xil_pn:name="Implementation"/>
1640 1301 <library xil_pn:name="lpp"/>
1641 1302 </file>
1642 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_demux/lpp_demux.vhd" xil_pn:type="FILE_VHDL">
1303 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_Header/HeaderBuilder.vhd" xil_pn:type="FILE_VHDL">
1643 1304 <association xil_pn:name="BehavioralSimulation"/>
1644 1305 <association xil_pn:name="Implementation"/>
1645 1306 <library xil_pn:name="lpp"/>
1646 1307 </file>
1647 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd" xil_pn:type="FILE_VHDL">
1308 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_Header/lpp_Header.vhd" xil_pn:type="FILE_VHDL">
1648 1309 <association xil_pn:name="BehavioralSimulation"/>
1649 1310 <association xil_pn:name="Implementation"/>
1650 1311 <library xil_pn:name="lpp"/>
1651 1312 </file>
1652 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma.vhd" xil_pn:type="FILE_VHDL">
1313 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd" xil_pn:type="FILE_VHDL">
1653 1314 <association xil_pn:name="BehavioralSimulation"/>
1654 1315 <association xil_pn:name="Implementation"/>
1655 1316 <library xil_pn:name="lpp"/>
1656 1317 </file>
1657 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_apbreg.vhd" xil_pn:type="FILE_VHDL">
1318 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd.bak" xil_pn:type="FILE_VHDL">
1658 1319 <association xil_pn:name="BehavioralSimulation"/>
1659 1320 <association xil_pn:name="Implementation"/>
1660 1321 <library xil_pn:name="lpp"/>
1661 1322 </file>
1662 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_fsm.vhd" xil_pn:type="FILE_VHDL">
1323 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/APB_Matrix.vhd" xil_pn:type="FILE_VHDL">
1663 1324 <association xil_pn:name="BehavioralSimulation"/>
1664 1325 <association xil_pn:name="Implementation"/>
1665 1326 <library xil_pn:name="lpp"/>
1666 1327 </file>
1667 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd" xil_pn:type="FILE_VHDL">
1328 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Dispatch.vhd" xil_pn:type="FILE_VHDL">
1668 1329 <association xil_pn:name="BehavioralSimulation"/>
1669 1330 <association xil_pn:name="Implementation"/>
1670 1331 <library xil_pn:name="lpp"/>
1671 1332 </file>
1672 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd" xil_pn:type="FILE_VHDL">
1333 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/DriveInputs.vhd" xil_pn:type="FILE_VHDL">
1673 1334 <association xil_pn:name="BehavioralSimulation"/>
1674 1335 <association xil_pn:name="Implementation"/>
1675 1336 <library xil_pn:name="lpp"/>
1676 1337 </file>
1677 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd" xil_pn:type="FILE_VHDL">
1338 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/GetResult.vhd" xil_pn:type="FILE_VHDL">
1678 1339 <association xil_pn:name="BehavioralSimulation"/>
1679 1340 <association xil_pn:name="Implementation"/>
1680 1341 <library xil_pn:name="lpp"/>
1681 1342 </file>
1682 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd" xil_pn:type="FILE_VHDL">
1343 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd" xil_pn:type="FILE_VHDL">
1683 1344 <association xil_pn:name="BehavioralSimulation"/>
1684 1345 <association xil_pn:name="Implementation"/>
1685 1346 <library xil_pn:name="lpp"/>
1686 1347 </file>
1687 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_Header/HeaderBuilder.vhd" xil_pn:type="FILE_VHDL">
1348 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd.bak" xil_pn:type="FILE_VHDL">
1688 1349 <association xil_pn:name="BehavioralSimulation"/>
1689 1350 <association xil_pn:name="Implementation"/>
1690 1351 <library xil_pn:name="lpp"/>
1691 1352 </file>
1692 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_Header/lpp_Header.vhd" xil_pn:type="FILE_VHDL">
1353 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Matrix.vhd" xil_pn:type="FILE_VHDL">
1693 1354 <association xil_pn:name="BehavioralSimulation"/>
1694 1355 <association xil_pn:name="Implementation"/>
1695 1356 <library xil_pn:name="lpp"/>
1696 1357 </file>
1697 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd" xil_pn:type="FILE_VHDL">
1358 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd" xil_pn:type="FILE_VHDL">
1698 1359 <association xil_pn:name="BehavioralSimulation"/>
1699 1360 <association xil_pn:name="Implementation"/>
1700 1361 <library xil_pn:name="lpp"/>
1701 1362 </file>
1702 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd.bak" xil_pn:type="FILE_VHDL">
1363 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd" xil_pn:type="FILE_VHDL">
1703 1364 <association xil_pn:name="BehavioralSimulation"/>
1704 1365 <association xil_pn:name="Implementation"/>
1705 1366 <library xil_pn:name="lpp"/>
1706 1367 </file>
1707 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/APB_Matrix.vhd" xil_pn:type="FILE_VHDL">
1708 <association xil_pn:name="BehavioralSimulation"/>
1709 <association xil_pn:name="Implementation"/>
1710 <library xil_pn:name="lpp"/>
1711 </file>
1712 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Dispatch.vhd" xil_pn:type="FILE_VHDL">
1368 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd.bak" xil_pn:type="FILE_VHDL">
1713 1369 <association xil_pn:name="BehavioralSimulation"/>
1714 1370 <association xil_pn:name="Implementation"/>
1715 1371 <library xil_pn:name="lpp"/>
1716 1372 </file>
1717 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/DriveInputs.vhd" xil_pn:type="FILE_VHDL">
1373 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Starter.vhd" xil_pn:type="FILE_VHDL">
1718 1374 <association xil_pn:name="BehavioralSimulation"/>
1719 1375 <association xil_pn:name="Implementation"/>
1720 1376 <library xil_pn:name="lpp"/>
1721 1377 </file>
1722 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/GetResult.vhd" xil_pn:type="FILE_VHDL">
1378 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopMatrix_PDR.vhd" xil_pn:type="FILE_VHDL">
1723 1379 <association xil_pn:name="BehavioralSimulation"/>
1724 1380 <association xil_pn:name="Implementation"/>
1725 1381 <library xil_pn:name="lpp"/>
1726 1382 </file>
1727 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd" xil_pn:type="FILE_VHDL">
1383 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd" xil_pn:type="FILE_VHDL">
1728 1384 <association xil_pn:name="BehavioralSimulation"/>
1729 1385 <association xil_pn:name="Implementation"/>
1730 1386 <library xil_pn:name="lpp"/>
1731 1387 </file>
1732 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd.bak" xil_pn:type="FILE_VHDL">
1388 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Top_MatrixSpec.vhd" xil_pn:type="FILE_VHDL">
1733 1389 <association xil_pn:name="BehavioralSimulation"/>
1734 1390 <association xil_pn:name="Implementation"/>
1735 1391 <library xil_pn:name="lpp"/>
1736 1392 </file>
1737 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Matrix.vhd" xil_pn:type="FILE_VHDL">
1393 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/lpp_matrix.vhd" xil_pn:type="FILE_VHDL">
1738 1394 <association xil_pn:name="BehavioralSimulation"/>
1739 1395 <association xil_pn:name="Implementation"/>
1740 1396 <library xil_pn:name="lpp"/>
1741 1397 </file>
1742 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd" xil_pn:type="FILE_VHDL">
1398 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/APB_FIFO.vhd" xil_pn:type="FILE_VHDL">
1743 1399 <association xil_pn:name="BehavioralSimulation"/>
1744 1400 <association xil_pn:name="Implementation"/>
1745 1401 <library xil_pn:name="lpp"/>
1746 1402 </file>
1747 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd" xil_pn:type="FILE_VHDL">
1403 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/APB_FIFO.vhd.bak" xil_pn:type="FILE_VHDL">
1748 1404 <association xil_pn:name="BehavioralSimulation"/>
1749 1405 <association xil_pn:name="Implementation"/>
1750 1406 <library xil_pn:name="lpp"/>
1751 1407 </file>
1752 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd.bak" xil_pn:type="FILE_VHDL">
1408 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/FIFO_pipeline.vhd" xil_pn:type="FILE_VHDL">
1753 1409 <association xil_pn:name="BehavioralSimulation"/>
1754 1410 <association xil_pn:name="Implementation"/>
1755 1411 <library xil_pn:name="lpp"/>
1756 1412 </file>
1757 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Starter.vhd" xil_pn:type="FILE_VHDL">
1413 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/FillFifo.vhd" xil_pn:type="FILE_VHDL">
1758 1414 <association xil_pn:name="BehavioralSimulation"/>
1759 1415 <association xil_pn:name="Implementation"/>
1760 1416 <library xil_pn:name="lpp"/>
1761 1417 </file>
1762 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopMatrix_PDR.vhd" xil_pn:type="FILE_VHDL">
1418 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/SSRAM_plugin.vhd" xil_pn:type="FILE_VHDL">
1763 1419 <association xil_pn:name="BehavioralSimulation"/>
1764 1420 <association xil_pn:name="Implementation"/>
1765 1421 <library xil_pn:name="lpp"/>
1766 1422 </file>
1767 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd" xil_pn:type="FILE_VHDL">
1423 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/SSRAM_plugin_vsim.vhd" xil_pn:type="FILE_VHDL">
1768 1424 <association xil_pn:name="BehavioralSimulation"/>
1769 1425 <association xil_pn:name="Implementation"/>
1770 1426 <library xil_pn:name="lpp"/>
1771 1427 </file>
1772 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Top_MatrixSpec.vhd" xil_pn:type="FILE_VHDL">
1428 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/lppFIFOxN.vhd" xil_pn:type="FILE_VHDL">
1773 1429 <association xil_pn:name="BehavioralSimulation"/>
1774 1430 <association xil_pn:name="Implementation"/>
1775 1431 <library xil_pn:name="lpp"/>
1776 1432 </file>
1777 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/lpp_matrix.vhd" xil_pn:type="FILE_VHDL">
1433 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/lppFIFOxN.vhd.bak" xil_pn:type="FILE_VHDL">
1778 1434 <association xil_pn:name="BehavioralSimulation"/>
1779 1435 <association xil_pn:name="Implementation"/>
1780 1436 <library xil_pn:name="lpp"/>
1781 1437 </file>
1782 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/APB_FIFO.vhd" xil_pn:type="FILE_VHDL">
1783 <association xil_pn:name="BehavioralSimulation"/>
1784 <association xil_pn:name="Implementation"/>
1785 <library xil_pn:name="lpp"/>
1786 </file>
1787 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/APB_FIFO.vhd.bak" xil_pn:type="FILE_VHDL">
1438 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_FIFO.vhd" xil_pn:type="FILE_VHDL">
1788 1439 <association xil_pn:name="BehavioralSimulation"/>
1789 1440 <association xil_pn:name="Implementation"/>
1790 1441 <library xil_pn:name="lpp"/>
1791 1442 </file>
1792 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/FillFifo.vhd" xil_pn:type="FILE_VHDL">
1443 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_memory.vhd" xil_pn:type="FILE_VHDL">
1793 1444 <association xil_pn:name="BehavioralSimulation"/>
1794 1445 <association xil_pn:name="Implementation"/>
1795 1446 <library xil_pn:name="lpp"/>
1796 1447 </file>
1797 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/SSRAM_plugin.vhd" xil_pn:type="FILE_VHDL">
1448 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_memory.vhd.bak" xil_pn:type="FILE_VHDL">
1798 1449 <association xil_pn:name="BehavioralSimulation"/>
1799 1450 <association xil_pn:name="Implementation"/>
1800 1451 <library xil_pn:name="lpp"/>
1801 1452 </file>
1802 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/SSRAM_plugin_vsim.vhd" xil_pn:type="FILE_VHDL">
1453 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd" xil_pn:type="FILE_VHDL">
1803 1454 <association xil_pn:name="BehavioralSimulation"/>
1804 1455 <association xil_pn:name="Implementation"/>
1805 1456 <library xil_pn:name="lpp"/>
1806 1457 </file>
1807 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lppFIFOxN.vhd" xil_pn:type="FILE_VHDL">
1458 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd" xil_pn:type="FILE_VHDL">
1808 1459 <association xil_pn:name="BehavioralSimulation"/>
1809 1460 <association xil_pn:name="Implementation"/>
1810 1461 <library xil_pn:name="lpp"/>
1811 1462 </file>
1812 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lppFIFOxN.vhd.bak" xil_pn:type="FILE_VHDL">
1463 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd" xil_pn:type="FILE_VHDL">
1813 1464 <association xil_pn:name="BehavioralSimulation"/>
1814 1465 <association xil_pn:name="Implementation"/>
1815 1466 <library xil_pn:name="lpp"/>
1816 1467 </file>
1817 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_FIFO.vhd" xil_pn:type="FILE_VHDL">
1468 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd" xil_pn:type="FILE_VHDL">
1818 1469 <association xil_pn:name="BehavioralSimulation"/>
1819 1470 <association xil_pn:name="Implementation"/>
1820 1471 <library xil_pn:name="lpp"/>
1821 1472 </file>
1822 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_memory.vhd" xil_pn:type="FILE_VHDL">
1473 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd" xil_pn:type="FILE_VHDL">
1823 1474 <association xil_pn:name="BehavioralSimulation"/>
1824 1475 <association xil_pn:name="Implementation"/>
1825 1476 <library xil_pn:name="lpp"/>
1826 1477 </file>
1827 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_memory.vhd.bak" xil_pn:type="FILE_VHDL">
1478 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_acq.vhd" xil_pn:type="FILE_VHDL">
1828 1479 <association xil_pn:name="BehavioralSimulation"/>
1829 1480 <association xil_pn:name="Implementation"/>
1830 1481 <library xil_pn:name="lpp"/>
1831 1482 </file>
1832 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd" xil_pn:type="FILE_VHDL">
1483 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_acq.vhd.bak" xil_pn:type="FILE_VHDL">
1833 1484 <association xil_pn:name="BehavioralSimulation"/>
1834 1485 <association xil_pn:name="Implementation"/>
1835 1486 <library xil_pn:name="lpp"/>
1836 1487 </file>
1837 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd" xil_pn:type="FILE_VHDL">
1838 <association xil_pn:name="BehavioralSimulation"/>
1839 <association xil_pn:name="Implementation"/>
1840 <library xil_pn:name="lpp"/>
1841 </file>
1842 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd" xil_pn:type="FILE_VHDL">
1488 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_apbreg.vhd" xil_pn:type="FILE_VHDL">
1843 1489 <association xil_pn:name="BehavioralSimulation"/>
1844 1490 <association xil_pn:name="Implementation"/>
1845 1491 <library xil_pn:name="lpp"/>
1846 1492 </file>
1847 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd" xil_pn:type="FILE_VHDL">
1493 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr.vhd" xil_pn:type="FILE_VHDL">
1848 1494 <association xil_pn:name="BehavioralSimulation"/>
1849 1495 <association xil_pn:name="Implementation"/>
1850 1496 <library xil_pn:name="lpp"/>
1851 1497 </file>
1852 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd" xil_pn:type="FILE_VHDL">
1498 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd" xil_pn:type="FILE_VHDL">
1853 1499 <association xil_pn:name="BehavioralSimulation"/>
1854 1500 <association xil_pn:name="Implementation"/>
1855 1501 <library xil_pn:name="lpp"/>
1856 1502 </file>
1857 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_acq.vhd" xil_pn:type="FILE_VHDL">
1503 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak" xil_pn:type="FILE_VHDL">
1858 1504 <association xil_pn:name="BehavioralSimulation"/>
1859 1505 <association xil_pn:name="Implementation"/>
1860 1506 <library xil_pn:name="lpp"/>
1861 1507 </file>
1862 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_acq.vhd.bak" xil_pn:type="FILE_VHDL">
1508 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_wf_picker.vhd" xil_pn:type="FILE_VHDL">
1863 1509 <association xil_pn:name="BehavioralSimulation"/>
1864 1510 <association xil_pn:name="Implementation"/>
1865 1511 <library xil_pn:name="lpp"/>
1866 1512 </file>
1867 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_apbreg.vhd" xil_pn:type="FILE_VHDL">
1513 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd" xil_pn:type="FILE_VHDL">
1868 1514 <association xil_pn:name="BehavioralSimulation"/>
1869 1515 <association xil_pn:name="Implementation"/>
1870 1516 <library xil_pn:name="lpp"/>
1871 1517 </file>
1872 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr.vhd" xil_pn:type="FILE_VHDL">
1518 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_wf_picker_ip_whitout_filter.vhd" xil_pn:type="FILE_VHDL">
1873 1519 <association xil_pn:name="BehavioralSimulation"/>
1874 1520 <association xil_pn:name="Implementation"/>
1875 1521 <library xil_pn:name="lpp"/>
1876 1522 </file>
1877 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd" xil_pn:type="FILE_VHDL">
1523 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/top_wf_picker.vhd" xil_pn:type="FILE_VHDL">
1878 1524 <association xil_pn:name="BehavioralSimulation"/>
1879 1525 <association xil_pn:name="Implementation"/>
1880 1526 <library xil_pn:name="lpp"/>
1881 1527 </file>
1882 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak" xil_pn:type="FILE_VHDL">
1528 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_uart/APB_UART.vhd" xil_pn:type="FILE_VHDL">
1883 1529 <association xil_pn:name="BehavioralSimulation"/>
1884 1530 <association xil_pn:name="Implementation"/>
1885 1531 <library xil_pn:name="lpp"/>
1886 1532 </file>
1887 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_wf_picker.vhd" xil_pn:type="FILE_VHDL">
1888 <association xil_pn:name="BehavioralSimulation"/>
1889 <association xil_pn:name="Implementation"/>
1890 <library xil_pn:name="lpp"/>
1891 </file>
1892 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd" xil_pn:type="FILE_VHDL">
1533 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_uart/BaudGen.vhd" xil_pn:type="FILE_VHDL">
1893 1534 <association xil_pn:name="BehavioralSimulation"/>
1894 1535 <association xil_pn:name="Implementation"/>
1895 1536 <library xil_pn:name="lpp"/>
1896 1537 </file>
1897 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_wf_picker_ip_whitout_filter.vhd" xil_pn:type="FILE_VHDL">
1538 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_uart/Shift_REG.vhd" xil_pn:type="FILE_VHDL">
1898 1539 <association xil_pn:name="BehavioralSimulation"/>
1899 1540 <association xil_pn:name="Implementation"/>
1900 1541 <library xil_pn:name="lpp"/>
1901 1542 </file>
1902 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_top_lfr/top_wf_picker.vhd" xil_pn:type="FILE_VHDL">
1543 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_uart/UART.vhd" xil_pn:type="FILE_VHDL">
1903 1544 <association xil_pn:name="BehavioralSimulation"/>
1904 1545 <association xil_pn:name="Implementation"/>
1905 1546 <library xil_pn:name="lpp"/>
1906 1547 </file>
1907 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/APB_UART.vhd" xil_pn:type="FILE_VHDL">
1548 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_uart/lpp_uart.vhd" xil_pn:type="FILE_VHDL">
1908 1549 <association xil_pn:name="BehavioralSimulation"/>
1909 1550 <association xil_pn:name="Implementation"/>
1910 1551 <library xil_pn:name="lpp"/>
1911 1552 </file>
1912 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/BaudGen.vhd" xil_pn:type="FILE_VHDL">
1913 <association xil_pn:name="BehavioralSimulation"/>
1914 <association xil_pn:name="Implementation"/>
1915 <library xil_pn:name="lpp"/>
1916 </file>
1917 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/Shift_REG.vhd" xil_pn:type="FILE_VHDL">
1553 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_usb/APB_USB.vhd" xil_pn:type="FILE_VHDL">
1918 1554 <association xil_pn:name="BehavioralSimulation"/>
1919 1555 <association xil_pn:name="Implementation"/>
1920 1556 <library xil_pn:name="lpp"/>
1921 1557 </file>
1922 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/UART.vhd" xil_pn:type="FILE_VHDL">
1558 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_usb/FX2_Driver.vhd" xil_pn:type="FILE_VHDL">
1923 1559 <association xil_pn:name="BehavioralSimulation"/>
1924 1560 <association xil_pn:name="Implementation"/>
1925 1561 <library xil_pn:name="lpp"/>
1926 1562 </file>
1927 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/lpp_uart.vhd" xil_pn:type="FILE_VHDL">
1563 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_usb/FX2_WithFIFO.vhd" xil_pn:type="FILE_VHDL">
1928 1564 <association xil_pn:name="BehavioralSimulation"/>
1929 1565 <association xil_pn:name="Implementation"/>
1930 1566 <library xil_pn:name="lpp"/>
1931 1567 </file>
1932 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/APB_USB.vhd" xil_pn:type="FILE_VHDL">
1568 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_usb/RWbuf.vhd" xil_pn:type="FILE_VHDL">
1933 1569 <association xil_pn:name="BehavioralSimulation"/>
1934 1570 <association xil_pn:name="Implementation"/>
1935 1571 <library xil_pn:name="lpp"/>
1936 1572 </file>
1937 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/FX2_Driver.vhd" xil_pn:type="FILE_VHDL">
1573 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_usb/lpp_usb.vhd" xil_pn:type="FILE_VHDL">
1938 1574 <association xil_pn:name="BehavioralSimulation"/>
1939 1575 <association xil_pn:name="Implementation"/>
1940 1576 <library xil_pn:name="lpp"/>
1941 1577 </file>
1942 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/RWbuf.vhd" xil_pn:type="FILE_VHDL">
1578 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform.vhd" xil_pn:type="FILE_VHDL">
1943 1579 <association xil_pn:name="BehavioralSimulation"/>
1944 1580 <association xil_pn:name="Implementation"/>
1945 1581 <library xil_pn:name="lpp"/>
1946 1582 </file>
1947 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/lpp_usb.vhd" xil_pn:type="FILE_VHDL">
1583 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd" xil_pn:type="FILE_VHDL">
1948 1584 <association xil_pn:name="BehavioralSimulation"/>
1949 1585 <association xil_pn:name="Implementation"/>
1950 1586 <library xil_pn:name="lpp"/>
1951 1587 </file>
1952 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform.vhd" xil_pn:type="FILE_VHDL">
1588 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma.vhd" xil_pn:type="FILE_VHDL">
1953 1589 <association xil_pn:name="BehavioralSimulation"/>
1954 1590 <association xil_pn:name="Implementation"/>
1955 1591 <library xil_pn:name="lpp"/>
1956 1592 </file>
1957 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd" xil_pn:type="FILE_VHDL">
1958 <association xil_pn:name="BehavioralSimulation"/>
1959 <association xil_pn:name="Implementation"/>
1960 <library xil_pn:name="lpp"/>
1961 </file>
1962 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma.vhd" xil_pn:type="FILE_VHDL">
1593 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd" xil_pn:type="FILE_VHDL">
1963 1594 <association xil_pn:name="BehavioralSimulation"/>
1964 1595 <association xil_pn:name="Implementation"/>
1965 1596 <library xil_pn:name="lpp"/>
1966 1597 </file>
1967 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd" xil_pn:type="FILE_VHDL">
1598 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma_selectaddress.vhd" xil_pn:type="FILE_VHDL">
1968 1599 <association xil_pn:name="BehavioralSimulation"/>
1969 1600 <association xil_pn:name="Implementation"/>
1970 1601 <library xil_pn:name="lpp"/>
1971 1602 </file>
1972 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma_selectaddress.vhd" xil_pn:type="FILE_VHDL">
1603 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma_send_Nword.vhd" xil_pn:type="FILE_VHDL">
1973 1604 <association xil_pn:name="BehavioralSimulation"/>
1974 1605 <association xil_pn:name="Implementation"/>
1975 1606 <library xil_pn:name="lpp"/>
1976 1607 </file>
1977 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_dma_send_Nword.vhd" xil_pn:type="FILE_VHDL">
1608 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd" xil_pn:type="FILE_VHDL">
1978 1609 <association xil_pn:name="BehavioralSimulation"/>
1979 1610 <association xil_pn:name="Implementation"/>
1980 1611 <library xil_pn:name="lpp"/>
1981 1612 </file>
1982 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd" xil_pn:type="FILE_VHDL">
1613 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd" xil_pn:type="FILE_VHDL">
1983 1614 <association xil_pn:name="BehavioralSimulation"/>
1984 1615 <association xil_pn:name="Implementation"/>
1985 1616 <library xil_pn:name="lpp"/>
1986 1617 </file>
1987 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd" xil_pn:type="FILE_VHDL">
1618 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd" xil_pn:type="FILE_VHDL">
1988 1619 <association xil_pn:name="BehavioralSimulation"/>
1989 1620 <association xil_pn:name="Implementation"/>
1990 1621 <library xil_pn:name="lpp"/>
1991 1622 </file>
1992 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd" xil_pn:type="FILE_VHDL">
1623 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd" xil_pn:type="FILE_VHDL">
1993 1624 <association xil_pn:name="BehavioralSimulation"/>
1994 1625 <association xil_pn:name="Implementation"/>
1995 1626 <library xil_pn:name="lpp"/>
1996 1627 </file>
1997 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd" xil_pn:type="FILE_VHDL">
1628 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd" xil_pn:type="FILE_VHDL">
1998 1629 <association xil_pn:name="BehavioralSimulation"/>
1999 1630 <association xil_pn:name="Implementation"/>
2000 1631 <library xil_pn:name="lpp"/>
2001 1632 </file>
2002 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd" xil_pn:type="FILE_VHDL">
1633 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd" xil_pn:type="FILE_VHDL">
2003 1634 <association xil_pn:name="BehavioralSimulation"/>
2004 1635 <association xil_pn:name="Implementation"/>
2005 1636 <library xil_pn:name="lpp"/>
2006 1637 </file>
2007 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd" xil_pn:type="FILE_VHDL">
1638 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_valid_ack.vhd" xil_pn:type="FILE_VHDL">
2008 1639 <association xil_pn:name="BehavioralSimulation"/>
2009 1640 <association xil_pn:name="Implementation"/>
2010 1641 <library xil_pn:name="lpp"/>
2011 1642 </file>
2012 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_waveform/lpp_waveform_valid_ack.vhd" xil_pn:type="FILE_VHDL">
1643 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/MinF_Cntr.vhd" xil_pn:type="FILE_VHDL">
2013 1644 <association xil_pn:name="BehavioralSimulation"/>
2014 1645 <association xil_pn:name="Implementation"/>
2015 1646 <library xil_pn:name="lpp"/>
2016 1647 </file>
2017 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/MinF_Cntr.vhd" xil_pn:type="FILE_VHDL">
1648 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Rocket_PCM_Encoder.vhd" xil_pn:type="FILE_VHDL">
2018 1649 <association xil_pn:name="BehavioralSimulation"/>
2019 1650 <association xil_pn:name="Implementation"/>
2020 1651 <library xil_pn:name="lpp"/>
2021 1652 </file>
2022 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Rocket_PCM_Encoder.vhd" xil_pn:type="FILE_VHDL">
1653 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Serial_Driver.vhd" xil_pn:type="FILE_VHDL">
2023 1654 <association xil_pn:name="BehavioralSimulation"/>
2024 1655 <association xil_pn:name="Implementation"/>
2025 1656 <library xil_pn:name="lpp"/>
2026 1657 </file>
2027 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Serial_Driver.vhd" xil_pn:type="FILE_VHDL">
1658 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Serial_Driver_Multiplexor.vhd" xil_pn:type="FILE_VHDL">
2028 1659 <association xil_pn:name="BehavioralSimulation"/>
2029 1660 <association xil_pn:name="Implementation"/>
2030 1661 <library xil_pn:name="lpp"/>
2031 1662 </file>
2032 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Serial_Driver_Multiplexor.vhd" xil_pn:type="FILE_VHDL">
2033 <association xil_pn:name="BehavioralSimulation"/>
2034 <association xil_pn:name="Implementation"/>
2035 <library xil_pn:name="lpp"/>
2036 </file>
2037 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Word_Cntr.vhd" xil_pn:type="FILE_VHDL">
1663 <file xil_pn:name="../../lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Word_Cntr.vhd" xil_pn:type="FILE_VHDL">
2038 1664 <association xil_pn:name="BehavioralSimulation"/>
2039 1665 <association xil_pn:name="Implementation"/>
2040 1666 <library xil_pn:name="lpp"/>
2041 1667 </file>
2042 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/cypress/ssram/components.vhd" xil_pn:type="FILE_VHDL">
1668 <file xil_pn:name="../../lib/cypress/ssram/components.vhd" xil_pn:type="FILE_VHDL">
2043 1669 <association xil_pn:name="BehavioralSimulation"/>
2044 1670 <library xil_pn:name="cypress"/>
2045 1671 </file>
2046 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/cypress/ssram/package_utility.vhd" xil_pn:type="FILE_VHDL">
1672 <file xil_pn:name="../../lib/cypress/ssram/package_utility.vhd" xil_pn:type="FILE_VHDL">
2047 1673 <association xil_pn:name="BehavioralSimulation"/>
2048 1674 <library xil_pn:name="cypress"/>
2049 1675 </file>
2050 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/cypress/ssram/cy7c1354b.vhd" xil_pn:type="FILE_VHDL">
1676 <file xil_pn:name="../../lib/cypress/ssram/cy7c1354b.vhd" xil_pn:type="FILE_VHDL">
2051 1677 <association xil_pn:name="BehavioralSimulation"/>
2052 1678 <library xil_pn:name="cypress"/>
2053 1679 </file>
2054 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/cypress/ssram/cy7c1380d.vhd" xil_pn:type="FILE_VHDL">
1680 <file xil_pn:name="../../lib/cypress/ssram/cy7c1380d.vhd" xil_pn:type="FILE_VHDL">
2055 1681 <association xil_pn:name="BehavioralSimulation"/>
2056 1682 <library xil_pn:name="cypress"/>
2057 1683 </file>
2058 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/work/debug/debug.vhd" xil_pn:type="FILE_VHDL">
1684 <file xil_pn:name="../../lib/work/debug/debug.vhd" xil_pn:type="FILE_VHDL">
2059 1685 <association xil_pn:name="BehavioralSimulation"/>
2060 1686 <library xil_pn:name="work"/>
2061 1687 </file>
2062 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/work/debug/grtestmod.vhd" xil_pn:type="FILE_VHDL">
1688 <file xil_pn:name="../../lib/work/debug/grtestmod.vhd" xil_pn:type="FILE_VHDL">
2063 1689 <association xil_pn:name="BehavioralSimulation"/>
2064 1690 <library xil_pn:name="work"/>
2065 1691 </file>
2066 <file xil_pn:name="C:/opt/grlib-gpl-1.1.0-b4108/lib/work/debug/cpu_disas.vhd" xil_pn:type="FILE_VHDL">
1692 <file xil_pn:name="../../lib/work/debug/cpu_disas.vhd" xil_pn:type="FILE_VHDL">
2067 1693 <association xil_pn:name="BehavioralSimulation"/>
2068 1694 <library xil_pn:name="work"/>
2069 1695 </file>
@@ -2096,7 +1722,7
2096 1722 <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="None"/>
2097 1723 <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|rtl"/>
2098 1724 <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top"/>
2099 <property xil_pn:name="Macro Search Path" xil_pn:value="C:/opt/grlib-gpl-1.1.0-b4108/netlists/xilinx/PROASIC3"/>
1725 <property xil_pn:name="Macro Search Path" xil_pn:value="../../netlists/xilinx/PROASIC3"/>
2100 1726 <property xil_pn:name="Other Map Command Line Options" xil_pn:value=""/>
2101 1727 <property xil_pn:name="Other XST Command Line Options" xil_pn:value=""/>
2102 1728 <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="high"/>
@@ -2121,14 +1747,8
2121 1747 <library xil_pn:name="dware"/>
2122 1748 <library xil_pn:name="synplify"/>
2123 1749 <library xil_pn:name="techmap"/>
2124 <library xil_pn:name="spw"/>
2125 <library xil_pn:name="eth"/>
2126 1750 <library xil_pn:name="opencores"/>
2127 1751 <library xil_pn:name="gaisler"/>
2128 <library xil_pn:name="esa"/>
2129 <library xil_pn:name="fmf"/>
2130 <library xil_pn:name="spansion"/>
2131 <library xil_pn:name="gsi"/>
2132 1752 <library xil_pn:name="lpp"/>
2133 1753 <library xil_pn:name="cypress"/>
2134 1754 <library xil_pn:name="work"/>
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@@ -72,6 +72,29 generic (
72 72 );
73 73 end component;
74 74
75 component FIFO_pipeline is
76 generic(
77 tech : integer := 0;
78 Mem_use : integer := use_RAM;
79 fifoCount : integer range 2 to 32 := 8;
80 DataSz : integer range 1 to 32 := 8;
81 abits : integer range 2 to 12 := 8
82 );
83 port(
84 rstn : in std_logic;
85 ReUse : in std_logic;
86 rclk : in std_logic;
87 ren : in std_logic;
88 rdata : out std_logic_vector(DataSz-1 downto 0);
89 empty : out std_logic;
90 raddr : out std_logic_vector(abits-1 downto 0);
91 wclk : in std_logic;
92 wen : in std_logic;
93 wdata : in std_logic_vector(DataSz-1 downto 0);
94 full : out std_logic;
95 waddr : out std_logic_vector(abits-1 downto 0)
96 );
97 end component;
75 98
76 99 component lpp_fifo is
77 100 generic(
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@@ -1,5 +1,6
1 1 APB_FIFO.vhd
2 2 APB_FIFO.vhd.bak
3 FIFO_pipeline.vhd
3 4 FillFifo.vhd
4 5 SSRAM_plugin.vhd
5 6 SSRAM_plugin_vsim.vhd
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@@ -53,7 +53,7 end component;
53 53 component FX2_WithFIFO is
54 54 generic(
55 55 tech : integer := 0;
56 Mem_use : integer := use_RAM;
56 Mem_use : integer := 0;
57 57 Enable_ReUse : std_logic := '0'
58 58 );
59 59 port(
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