HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/EGSE_ICI/top_synplify.npl

Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.

Alexis Jeandet - - Load All Authors

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/ designs / EGSE_ICI / top_synplify.npl

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				JDF G
				PROJECT top
				DESIGN top
				DEVFAM PROASIC3
				DEVICE A3PE1500
				DEVSPEED Std
				DEVPKG ""
				DEVTOPLEVELMODULETYPE EDIF
				DEVSIMULATOR Modelsim
				DEVGENERATEDSIMULATIONMODEL VHDL
				SOURCE synplify\top.edf
				DEPASSOC top C:\opt\grlib-gpl-1.1.0-b4108\boards\GSE_ICI\top.ucf
				[Normal]
				xilxMapAllowLogicOpt=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True
				xilxMapCoverMode=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Speed
				xilxNgdbld_AUL=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True
				xilxPAReffortLevel=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Medium
				xilxNgdbldMacro=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1105378344, C:\opt\grlib-gpl-1.1.0-b4108\netlists\xilinx\PROASIC3
				[STRATEGY-LIST]
				Normal=True

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