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-- TOP_GSE.vhd
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library lpp;
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use lpp.lpp_usb.all;
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library techmap;
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use techmap.gencomp.all;
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entity TOP_EGSE2 is
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generic(WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64;Simu : integer :=0);
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port(
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Clock : in std_logic;
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reset : in std_logic;
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DataRTX : in std_logic;
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DataRTX_echo : out std_logic;
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SCLK : out std_logic;
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Gate : out std_logic;
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Major_Frame : out std_logic;
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Minor_Frame : out std_logic;
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if_clk : out STD_LOGIC;
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flagb : in STD_LOGIC;
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slwr : out STD_LOGIC;
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slrd : out std_logic;
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pktend : out STD_LOGIC;
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sloe : out STD_LOGIC;
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fdbusw : out std_logic_vector (7 downto 0);
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fifoadr : out std_logic_vector (1 downto 0)
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);
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end TOP_EGSE2;
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architecture ar_TOP_EGSE2 of TOP_EGSE2 is
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component CLKINT
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port( A : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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signal clk : std_logic;
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signal sclkint : std_logic;
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signal RaZ : std_logic;
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signal rstn : std_logic;
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signal WordCount : integer range 0 to WordCnt-1;
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signal WordClk : std_logic;
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signal MinFCnt : integer range 0 to MinFCount-1;
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signal MinF : std_logic;
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signal MinFclk : std_logic;
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signal MajF : std_logic;
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signal GateLF : std_logic;
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signal GateHF : std_logic;
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signal GateDC : std_logic;
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signal Gateint : std_logic;
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signal GateR : std_logic;
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signal NwDat : std_logic;
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signal DATA : std_logic_vector(WordSize-1 downto 0);
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Signal FIFODATin : std_logic_vector(7 downto 0);
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Signal FIFODATout : std_logic_vector(7 downto 0);
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Signal USB_DATA : std_logic_vector(7 downto 0);
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Signal FIFOwe,FIFOre,FIFOfull : std_logic;
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Signal USBwe,USBfull,USBempty : std_logic;
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Signal clk80 : std_logic;
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begin
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DataRTX_echo <= DataRTX; --P48
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ck_int0 : CLKINT
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port map(Clock,clk);
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DEFPLL: IF simu = 0 generate
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PLL : entity work.PLL0
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port map(
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POWERDOWN => '1',
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CLKA => clk,
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LOCK => RaZ,
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GLA => SCLKint,
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GLB => clk80
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);
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end generate;
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SIMPLL: IF simu = 1 generate
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PLL : entity work.PLL0Sim
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port map(
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POWERDOWN => '1',
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CLKA => clk,
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LOCK => RaZ,
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GLA => SCLKint,
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GLB => clk80
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);
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end generate;
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USB2: entity work.FX2_WithFIFO
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generic map(apa3)
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port map(
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clk => clk,
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if_clk => if_clk,
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reset => rstn,
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flagb => flagb,
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slwr => slwr,
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slrd => slrd,
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pktend => pktend,
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sloe => sloe,
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fdbusw => fdbusw,
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fifoadr => fifoadr,
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FULL => USBfull,
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Write => USBwe,
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Data => USB_DATA
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);
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rstn <= reset and RaZ;
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process(clk,rstn)
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begin
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if rstn = '0' then
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USB_DATA <= (others => '0');
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USBwe <= '0';
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elsif clk'event and clk = '1' then
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if USBfull = '0' then
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USB_DATA <= std_logic_vector(unsigned(USB_DATA) + 1 );
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USBwe <= '1';
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else
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USBwe <= '0';
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end if;
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end if;
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end process;
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end ar_TOP_EGSE2;
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