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modif APB_fifo
martin -
r91:0d940e249f25 martin
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, Write_int to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity LocalReset is
27 port(
28 clk : in std_logic;
29 raz : in std_logic;
30 Rz : in std_logic;
31 rstf : out std_logic
32 );
33 end LocalReset;
34
35
36 architecture ar_LocalReset of LocalReset is
37
38 signal Rz_reg : std_logic;
39
40 type state is (st0);
41 signal ect : state;
42
43 begin
44 process(clk,raz)
45 begin
46
47 if(raz='0')then
48 rstf <= '0';
49 ect <= st0;
50
51 elsif(clk'event and clk='1')then
52 Rz_reg <= Rz;
53
54 case ect is
55
56 when st0 =>
57 rstf <= '1';
58 if(Rz_reg='0' and Rz='1')then
59 rstf <= '0';
60 ect <= st0;
61 elsif(Rz_reg='1' and Rz='0')then
62 rstf <= '0';
63 ect <= st0;
64 end if;
65
66 end case;
67 end if;
68 end process;
69
70 end ar_LocalReset; No newline at end of file
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_matrix.all;
31 use lpp.lpp_matrix.all;
32
32
33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
34
34
35 entity APB_Matrix is
35 entity APB_Matrix is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0;
41 abits : integer := 8;
41 abits : integer := 8;
42 Input_SZ : integer := 16;
42 Input_SZ : integer := 16;
43 Result_SZ : integer := 32);
43 Result_SZ : integer := 32);
44 port (
44 port (
45 clk : in std_logic; --! Horloge du composant
45 clk : in std_logic; --! Horloge du composant
46 rst : in std_logic; --! Reset general du composant
46 rst : in std_logic; --! Reset general du composant
47 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
48 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
49 Full : in std_logic_vector(1 downto 0);
49 Full : in std_logic_vector(1 downto 0);
50 Empty : in std_logic_vector(1 downto 0);
50 Empty : in std_logic_vector(1 downto 0);
51 ReadFIFO : out std_logic_vector(1 downto 0);
51 ReadFIFO : out std_logic_vector(1 downto 0);
52 WriteFIFO : out std_logic;
52 WriteFIFO : out std_logic;
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 Start : out std_logic;
54 Start : out std_logic;
55 -- Read : out std_logic;
55 Read : out std_logic;
56 -- Take : out std_logic;
56 Take : out std_logic;
57 -- Valid : out std_logic;
57 Valid : out std_logic;
58 Received : out std_logic;
58 Res : out std_logic_vector(Result_SZ-1 downto 0);
59 Res : out std_logic_vector(Result_SZ-1 downto 0);
59 -- Conjugate : out std_logic;
60 -- Conjugate : out std_logic;
60 -- OP1 : out std_logic_vector(3 downto 0);
61 OP1 : out std_logic_vector(3 downto 0);
61 -- OP2 : out std_logic_vector(3 downto 0);
62 OP2 : out std_logic_vector(3 downto 0);
62 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
63 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
63 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
64 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
64 );
65 );
65 end APB_Matrix;
66 end APB_Matrix;
66
67
67
68
68 architecture ar_APB_Matrix of APB_Matrix is
69 architecture ar_APB_Matrix of APB_Matrix is
69
70
70 constant REVISION : integer := 1;
71 constant REVISION : integer := 1;
71
72
72 constant pconfig : apb_config_type := (
73 constant pconfig : apb_config_type := (
73 0 => ahb_device_reg (VENDOR_LPP, LPP_MATRIX, 0, REVISION, 0),
74 0 => ahb_device_reg (VENDOR_LPP, LPP_MATRIX, 0, REVISION, 0),
74 1 => apb_iobar(paddr, pmask));
75 1 => apb_iobar(paddr, pmask));
75
76
76 type MATRIX_ctrlr_Reg is record
77 type MATRIX_ctrlr_Reg is record
77 MATRIX_Statu : std_logic_vector(3 downto 0);
78 MATRIX_Statu : std_logic_vector(3 downto 0);
78 end record;
79 end record;
79
80
80 signal Rec : MATRIX_ctrlr_Reg;
81 signal Rec : MATRIX_ctrlr_Reg;
81 signal Rdata : std_logic_vector(31 downto 0);
82 signal Rdata : std_logic_vector(31 downto 0);
82
83
83 begin
84 begin
84
85
85 Mspec0 : SpectralMatrix
86 Mspec0 : SpectralMatrix
86 generic map (Input_SZ,Result_SZ)
87 generic map (Input_SZ,Result_SZ)
87 port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Res,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
88 port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Read,Take,Valid,Received,Res,OP1,OP2,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
88
89
89 process(rst,clk)
90 process(rst,clk)
90 begin
91 begin
91 if(rst='0')then
92 if(rst='0')then
92 Rec.MATRIX_Statu <= (others => '0');
93 Rec.MATRIX_Statu <= (others => '0');
93
94
94 elsif(clk'event and clk='1')then
95 elsif(clk'event and clk='1')then
95
96
96 --APB Write OP
97 --APB Write OP
97 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
98 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
98 case apbi.paddr(abits-1 downto 2) is
99 case apbi.paddr(abits-1 downto 2) is
99 when "000000" =>
100 when "000000" =>
100 Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0);
101 Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0);
101 when others =>
102 when others =>
102 null;
103 null;
103 end case;
104 end case;
104 end if;
105 end if;
105
106
106 --APB READ OP
107 --APB READ OP
107 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
108 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
108 case apbi.paddr(abits-1 downto 2) is
109 case apbi.paddr(abits-1 downto 2) is
109 when "000000" =>
110 when "000000" =>
110 Rdata(31 downto 4) <= (others => '0');
111 Rdata(31 downto 4) <= (others => '0');
111 Rdata(3 downto 0) <= Rec.MATRIX_Statu;
112 Rdata(3 downto 0) <= Rec.MATRIX_Statu;
112 --when "000001" =>
113 --when "000001" =>
113 -- Rdata(3 downto 0) <= "000" & Rec.MATRIX_Cfg(0);
114 -- Rdata(3 downto 0) <= "000" & Rec.MATRIX_Cfg(0);
114 -- Rdata(7 downto 4) <= "000" & Rec.MATRIX_Cfg(1);
115 -- Rdata(7 downto 4) <= "000" & Rec.MATRIX_Cfg(1);
115 -- Rdata(11 downto 8) <= "000" & Rec.MATRIX_Cfg(2);
116 -- Rdata(11 downto 8) <= "000" & Rec.MATRIX_Cfg(2);
116 -- Rdata(15 downto 12) <= "000" & Rec.MATRIX_Cfg(3);
117 -- Rdata(15 downto 12) <= "000" & Rec.MATRIX_Cfg(3);
117 -- Rdata(19 downto 16) <= "000" & Rec.MATRIX_Cfg(4);
118 -- Rdata(19 downto 16) <= "000" & Rec.MATRIX_Cfg(4);
118 -- Rdata(23 downto 20) <= "000" & Rec.MATRIX_Cfg(5);
119 -- Rdata(23 downto 20) <= "000" & Rec.MATRIX_Cfg(5);
119 -- Rdata(31 downto 24) <= X"CC";
120 -- Rdata(31 downto 24) <= X"CC";
120 when others =>
121 when others =>
121 Rdata <= (others => '0');
122 Rdata <= (others => '0');
122 end case;
123 end case;
123 end if;
124 end if;
124
125
125 end if;
126 end if;
126 apbo.pconfig <= pconfig;
127 apbo.pconfig <= pconfig;
127 end process;
128 end process;
128
129
129 apbo.prdata <= Rdata when apbi.penable = '1';
130 apbo.prdata <= Rdata when apbi.penable = '1';
130
131
131 end ar_APB_MATRIX; No newline at end of file
132 end ar_APB_MATRIX;
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@@ -1,71 +1,71
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
25 use lpp.lpp_matrix.all;
26
26
27 --! Programme de calcule de Matrice Spectral, composοΏ½ d'une ALU et de son Driver
27 --! Programme de calcule de Matrice Spectral, composοΏ½ d'une ALU et de son Driver
28
28
29 entity Matrix is
29 entity Matrix is
30 generic(
30 generic(
31 Input_SZ : integer := 16);
31 Input_SZ : integer := 16);
32 port(
32 port(
33 clk : in std_logic; --! Horloge du composant
33 clk : in std_logic; --! Horloge du composant
34 raz : in std_logic; --! Reset general du composant
34 raz : in std_logic; --! Reset general du composant
35 IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
35 IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
36 IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
36 IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
37 Take : in std_logic; --! Flag, opοΏ½rande rοΏ½cupοΏ½rοΏ½
37 Take : in std_logic; --! Flag, opοΏ½rande rοΏ½cupοΏ½rοΏ½
38 Received : in std_logic; --! Flag, RοΏ½sultat bien ressu
38 Received : in std_logic; --! Flag, RοΏ½sultat bien ressu
39 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjuguοΏ½
39 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjuguοΏ½
40 Valid : out std_logic; --! Flag, RοΏ½sultat disponible
40 Valid : out std_logic; --! Flag, RοΏ½sultat disponible
41 Read : out std_logic; --! Flag, opοΏ½rande disponible
41 Read : out std_logic; --! Flag, opοΏ½rande disponible
42 -- OPin1 : out std_logic_vector(3 downto 0);
42 OPin1 : out std_logic_vector(3 downto 0);
43 -- OPin2 : out std_logic_vector(3 downto 0);
43 OPin2 : out std_logic_vector(3 downto 0);
44 Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! RοΏ½sultat du calcul
44 Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! RοΏ½sultat du calcul
45 );
45 );
46 end Matrix;
46 end Matrix;
47
47
48
48
49 architecture ar_Matrix of Matrix is
49 architecture ar_Matrix of Matrix is
50
50
51 signal CTRL : std_logic_vector(4 downto 0);
51 signal CTRL : std_logic_vector(4 downto 0);
52 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
52 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
53 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
53 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
54
54
55 begin
55 begin
56 --OPin1 <= OP1(3 downto 0);
56 OPin1 <= OP1(3 downto 0);
57 --OPin2 <= OP1(3 downto 0);
57 OPin2 <= OP1(3 downto 0);
58
58
59
59
60 DRIVE : ALU_Driver
60 DRIVE : ALU_Driver
61 generic map(Input_SZ,Input_SZ)
61 generic map(Input_SZ,Input_SZ)
62 port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,OP1,OP2);
62 port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,OP1,OP2);
63
63
64
64
65 ALU : ALU_v2
65 ALU : ALU_v2
66 generic map(1,0,Input_SZ,Input_SZ)
66 generic map(1,0,Input_SZ,Input_SZ)
67 port map(clk,raz,CTRL,OP1,OP2,Result);
67 port map(clk,raz,CTRL,OP1,OP2,Result);
68
68
69
69
70 end ar_Matrix;
70 end ar_Matrix;
71
71
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@@ -1,109 +1,109
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
25 use lpp.lpp_matrix.all;
26
26
27 entity SpectralMatrix is
27 entity SpectralMatrix is
28 generic(
28 generic(
29 Input_SZ : integer := 16;
29 Input_SZ : integer := 16;
30 Result_SZ : integer := 32);
30 Result_SZ : integer := 32);
31 port(
31 port(
32 clk : in std_logic;
32 clk : in std_logic;
33 reset : in std_logic;
33 reset : in std_logic;
34 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
34 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
35 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
35 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
36 Full : in std_logic_vector(1 downto 0);
36 Full : in std_logic_vector(1 downto 0);
37 Empty : in std_logic_vector(1 downto 0);
37 Empty : in std_logic_vector(1 downto 0);
38 Statu : in std_logic_vector(3 downto 0);
38 Statu : in std_logic_vector(3 downto 0);
39 ReadFIFO : out std_logic_vector(1 downto 0);
39 ReadFIFO : out std_logic_vector(1 downto 0);
40 WriteFIFO : out std_logic;
40 WriteFIFO : out std_logic;
41 Start : out std_logic;
41 Start : out std_logic;
42 -- Read : out std_logic;
42 Read : out std_logic;
43 -- Take : out std_logic;
43 Take : out std_logic;
44 -- Valid : out std_logic;
44 Valid : out std_logic;
45 Res : out std_logic_vector(Result_SZ-1 downto 0);
45 Received : out std_logic;
46 -- Received : out std_logic;
46 Res : out std_logic_vector(Result_SZ-1 downto 0);
47 -- Conjugate : out std_logic;
47 -- Conjugate : out std_logic;
48 -- OP1 : out std_logic_vector(3 downto 0);
48 OP1 : out std_logic_vector(3 downto 0);
49 -- OP2 : out std_logic_vector(3 downto 0);
49 OP2 : out std_logic_vector(3 downto 0);
50 Result : out std_logic_vector(Result_SZ-1 downto 0)
50 Result : out std_logic_vector(Result_SZ-1 downto 0)
51 );
51 );
52 end SpectralMatrix;
52 end SpectralMatrix;
53
53
54
54
55 architecture ar_SpectralMatrix of SpectralMatrix is
55 architecture ar_SpectralMatrix of SpectralMatrix is
56
56
57 signal Start_int : std_logic;
57 signal Start_int : std_logic;
58 signal Read_int : std_logic;
58 signal Read_int : std_logic;
59 signal Take_int : std_logic;
59 signal Take_int : std_logic;
60 signal Received_int : std_logic;
60 signal Received_int : std_logic;
61 signal Valid_int : std_logic;
61 signal Valid_int : std_logic;
62 signal Conjugate_int : std_logic;
62 signal Conjugate_int : std_logic;
63
63
64 --signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
64 --signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
65 --signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
65 --signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
66 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
66 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
67 --signal Res : std_logic_vector(Result_SZ-1 downto 0);
67 --signal Res : std_logic_vector(Result_SZ-1 downto 0);
68
68
69
69
70 begin
70 begin
71
71
72 ST0 : Starter
72 ST0 : Starter
73 port map(clk,reset,Full,Empty,Conjugate_int,Received_int,Start_int);
73 port map(clk,reset,Full,Empty,Conjugate_int,Received_int,Start_int);
74
74
75 --IN0 : SelectInputs
75 --IN0 : SelectInputs
76 -- generic map(Input_SZ)
76 -- generic map(Input_SZ)
77 -- port map(clk,Start,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,Statu,OP1,OP2);
77 -- port map(clk,Start,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,Statu,OP1,OP2);
78
78
79 IN1 : DriveInputs
79 IN1 : DriveInputs
80 port map(clk,Start_int,Read_int,Conjugate_int,Take_int,ReadFIFO);
80 port map(clk,Start_int,Read_int,Conjugate_int,Take_int,ReadFIFO);
81
81
82
82
83 CALC0 : Matrix
83 CALC0 : Matrix
84 generic map(Input_SZ)
84 generic map(Input_SZ)
85 port map(clk,Start_int,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
85 port map(clk,Start_int,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,OP1,OP2,Resultat);
86
86
87
87
88 RES0 : GetResult
88 RES0 : GetResult
89 generic map(Result_SZ)
89 generic map(Result_SZ)
90 port map(clk,Start_int,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);
90 port map(clk,Start_int,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);
91
91
92
92
93 With Statu select
93 With Statu select
94 Conjugate_int <= '1' when "0001",
94 Conjugate_int <= '1' when "0001",
95 '1' when "0011",
95 '1' when "0011",
96 '1' when "0110",
96 '1' when "0110",
97 '1' when "1010",
97 '1' when "1010",
98 '1' when "1111",
98 '1' when "1111",
99 '0' when others;
99 '0' when others;
100
100
101 Start <= Start_int;
101 Start <= Start_int;
102 --Read <= Read_int;
102 Read <= Read_int;
103 --Take <= Take_int;
103 Take <= Take_int;
104 --Received <= Received_int;
104 Received <= Received_int;
105 --Valid <= Valid_int;
105 Valid <= Valid_int;
106 --Conjugate <= Conjugate_int;
106 --Conjugate <= Conjugate_int;
107 Res <= Resultat;
107 Res <= Resultat;
108
108
109 end ar_SpectralMatrix; No newline at end of file
109 end ar_SpectralMatrix;
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@@ -1,233 +1,249
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31
31
32 package lpp_matrix is
32 package lpp_matrix is
33
33
34 component APB_Matrix is
34 component APB_Matrix is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8;
40 abits : integer := 8;
41 Input_SZ : integer := 16;
41 Input_SZ : integer := 16;
42 Result_SZ : integer := 32);
42 Result_SZ : integer := 32);
43 port (
43 port (
44 clk : in std_logic; --! Horloge du composant
44 clk : in std_logic; --! Horloge du composant
45 rst : in std_logic; --! Reset general du composant
45 rst : in std_logic; --! Reset general du composant
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
51 WriteFIFO : out std_logic;
51 WriteFIFO : out std_logic;
52 Result : out std_logic_vector(Result_SZ-1 downto 0);
52 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Start : out std_logic;
53 Start : out std_logic;
54 Res : out std_logic_vector(Result_SZ-1 downto 0);
54 Read : out std_logic;
55 Take : out std_logic;
56 Valid : out std_logic;
57 Received : out std_logic;
58 Res : out std_logic_vector(Result_SZ-1 downto 0);
59 -- Conjugate : out std_logic;
60 OP1 : out std_logic_vector(3 downto 0);
61 OP2 : out std_logic_vector(3 downto 0);
55 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
62 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
56 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
63 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
57 );
64 );
58 end component;
65 end component;
59
66
60
67
61 component SpectralMatrix is
68 component SpectralMatrix is
62 generic(
69 generic(
63 Input_SZ : integer := 16;
70 Input_SZ : integer := 16;
64 Result_SZ : integer := 32);
71 Result_SZ : integer := 32);
65 port(
72 port(
66 clk : in std_logic;
73 clk : in std_logic;
67 reset : in std_logic;
74 reset : in std_logic;
68 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
75 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
69 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
76 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
70 Full : in std_logic_vector(1 downto 0);
77 Full : in std_logic_vector(1 downto 0);
71 Empty : in std_logic_vector(1 downto 0);
78 Empty : in std_logic_vector(1 downto 0);
72 Statu : in std_logic_vector(3 downto 0);
79 Statu : in std_logic_vector(3 downto 0);
73 ReadFIFO : out std_logic_vector(1 downto 0);
80 ReadFIFO : out std_logic_vector(1 downto 0);
74 WriteFIFO : out std_logic;
81 WriteFIFO : out std_logic;
75 Start : out std_logic;
82 Start : out std_logic;
83 Read : out std_logic;
84 Take : out std_logic;
85 Valid : out std_logic;
86 Received : out std_logic;
76 Res : out std_logic_vector(Result_SZ-1 downto 0);
87 Res : out std_logic_vector(Result_SZ-1 downto 0);
88 -- Conjugate : out std_logic;
89 OP1 : out std_logic_vector(3 downto 0);
90 OP2 : out std_logic_vector(3 downto 0);
77 Result : out std_logic_vector(Result_SZ-1 downto 0)
91 Result : out std_logic_vector(Result_SZ-1 downto 0)
78 );
92 );
79 end component;
93 end component;
80
94
81
95
82 component Matrix is
96 component Matrix is
83 generic(
97 generic(
84 Input_SZ : integer := 16);
98 Input_SZ : integer := 16);
85 port(
99 port(
86 clk : in std_logic;
100 clk : in std_logic;
87 raz : in std_logic;
101 raz : in std_logic;
88 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
102 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
89 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
103 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
90 Take : in std_logic;
104 Take : in std_logic;
91 Received : in std_logic;
105 Received : in std_logic;
92 Conjugate : in std_logic;
106 Conjugate : in std_logic;
93 Valid : out std_logic;
107 Valid : out std_logic;
94 Read : out std_logic;
108 Read : out std_logic;
109 OPin1 : out std_logic_vector(3 downto 0);
110 OPin2 : out std_logic_vector(3 downto 0);
95 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
111 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
96 );
112 );
97 end component;
113 end component;
98
114
99
115
100 component ALU_Driver is
116 component ALU_Driver is
101 generic(
117 generic(
102 Input_SZ_1 : integer := 16;
118 Input_SZ_1 : integer := 16;
103 Input_SZ_2 : integer := 16);
119 Input_SZ_2 : integer := 16);
104 port(
120 port(
105 clk : in std_logic;
121 clk : in std_logic;
106 reset : in std_logic;
122 reset : in std_logic;
107 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
123 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
108 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
124 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
109 Take : in std_logic;
125 Take : in std_logic;
110 Received : in std_logic;
126 Received : in std_logic;
111 Conjugate : in std_logic;
127 Conjugate : in std_logic;
112 Valid : out std_logic;
128 Valid : out std_logic;
113 Read : out std_logic;
129 Read : out std_logic;
114 CTRL : out std_logic_vector(4 downto 0);
130 CTRL : out std_logic_vector(4 downto 0);
115 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
131 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
116 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
132 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
117 );
133 );
118 end component;
134 end component;
119
135
120
136
121 component ALU_v2 is
137 component ALU_v2 is
122 generic(
138 generic(
123 Arith_en : integer := 1;
139 Arith_en : integer := 1;
124 Logic_en : integer := 1;
140 Logic_en : integer := 1;
125 Input_SZ_1 : integer := 16;
141 Input_SZ_1 : integer := 16;
126 Input_SZ_2 : integer := 9);
142 Input_SZ_2 : integer := 9);
127 port(
143 port(
128 clk : in std_logic;
144 clk : in std_logic;
129 reset : in std_logic;
145 reset : in std_logic;
130 ctrl : in std_logic_vector(4 downto 0);
146 ctrl : in std_logic_vector(4 downto 0);
131 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
147 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
132 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
148 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
133 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
149 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
134 );
150 );
135 end component;
151 end component;
136
152
137
153
138 component MAC_v2 is
154 component MAC_v2 is
139 generic(
155 generic(
140 Input_SZ_A : integer := 8;
156 Input_SZ_A : integer := 8;
141 Input_SZ_B : integer := 8);
157 Input_SZ_B : integer := 8);
142 port(
158 port(
143 clk : in std_logic;
159 clk : in std_logic;
144 reset : in std_logic;
160 reset : in std_logic;
145 clr_MAC : in std_logic;
161 clr_MAC : in std_logic;
146 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
162 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
147 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
163 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
148 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
164 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
149 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
165 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
150 );
166 );
151 end component;
167 end component;
152
168
153
169
154 component TwoComplementer is
170 component TwoComplementer is
155 generic(
171 generic(
156 Input_SZ : integer := 16);
172 Input_SZ : integer := 16);
157 port(
173 port(
158 clk : in std_logic;
174 clk : in std_logic;
159 reset : in std_logic;
175 reset : in std_logic;
160 clr : in std_logic;
176 clr : in std_logic;
161 TwoComp : in std_logic;
177 TwoComp : in std_logic;
162 OP : in std_logic_vector(Input_SZ-1 downto 0);
178 OP : in std_logic_vector(Input_SZ-1 downto 0);
163 RES : out std_logic_vector(Input_SZ-1 downto 0)
179 RES : out std_logic_vector(Input_SZ-1 downto 0)
164 );
180 );
165 end component;
181 end component;
166
182
167
183
168 component GetResult is
184 component GetResult is
169 generic(
185 generic(
170 Result_SZ : integer := 32);
186 Result_SZ : integer := 32);
171 port(
187 port(
172 clk : in std_logic;
188 clk : in std_logic;
173 raz : in std_logic;
189 raz : in std_logic;
174 Valid : in std_logic;
190 Valid : in std_logic;
175 Conjugate : in std_logic;
191 Conjugate : in std_logic;
176 Res : in std_logic_vector(Result_SZ-1 downto 0);
192 Res : in std_logic_vector(Result_SZ-1 downto 0);
177 WriteFIFO : out std_logic;
193 WriteFIFO : out std_logic;
178 Received : out std_logic;
194 Received : out std_logic;
179 Result : out std_logic_vector(Result_SZ-1 downto 0)
195 Result : out std_logic_vector(Result_SZ-1 downto 0)
180 );
196 );
181 end component;
197 end component;
182
198
183
199
184 component SelectInputs is
200 component SelectInputs is
185 generic(
201 generic(
186 Input_SZ : integer := 16);
202 Input_SZ : integer := 16);
187 port(
203 port(
188 clk : in std_logic;
204 clk : in std_logic;
189 raz : in std_logic;
205 raz : in std_logic;
190 Read : in std_logic;
206 Read : in std_logic;
191 B1 : in std_logic_vector(Input_SZ-1 downto 0);
207 B1 : in std_logic_vector(Input_SZ-1 downto 0);
192 B2 : in std_logic_vector(Input_SZ-1 downto 0);
208 B2 : in std_logic_vector(Input_SZ-1 downto 0);
193 B3 : in std_logic_vector(Input_SZ-1 downto 0);
209 B3 : in std_logic_vector(Input_SZ-1 downto 0);
194 E1 : in std_logic_vector(Input_SZ-1 downto 0);
210 E1 : in std_logic_vector(Input_SZ-1 downto 0);
195 E2 : in std_logic_vector(Input_SZ-1 downto 0);
211 E2 : in std_logic_vector(Input_SZ-1 downto 0);
196 Conjugate : out std_logic;
212 Conjugate : out std_logic;
197 Take : out std_logic;
213 Take : out std_logic;
198 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
214 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
199 Statu : out std_logic_vector(3 downto 0);
215 Statu : out std_logic_vector(3 downto 0);
200 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
216 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
201 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
217 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
202 );
218 );
203 end component;
219 end component;
204 ---------------------------------------------------------------------------
220 ---------------------------------------------------------------------------
205 component DriveInputs is
221 component DriveInputs is
206 port(
222 port(
207 clk : in std_logic;
223 clk : in std_logic;
208 raz : in std_logic;
224 raz : in std_logic;
209 Read : in std_logic;
225 Read : in std_logic;
210 -- FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
226 -- FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
211 -- FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
227 -- FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
212 -- Statu : in std_logic_vector(3 downto 0);
228 -- Statu : in std_logic_vector(3 downto 0);
213 Conjugate : in std_logic;
229 Conjugate : in std_logic;
214 Take : out std_logic;
230 Take : out std_logic;
215 ReadFIFO : out std_logic_vector(1 downto 0)
231 ReadFIFO : out std_logic_vector(1 downto 0)
216 -- OP1 : out std_logic_vector(Input_SZ-1 downto 0);
232 -- OP1 : out std_logic_vector(Input_SZ-1 downto 0);
217 -- OP2 : out std_logic_vector(Input_SZ-1 downto 0)
233 -- OP2 : out std_logic_vector(Input_SZ-1 downto 0)
218 );
234 );
219 end component;
235 end component;
220
236
221 component Starter is
237 component Starter is
222 port(
238 port(
223 clk : in std_logic;
239 clk : in std_logic;
224 raz : in std_logic;
240 raz : in std_logic;
225 Full : in std_logic_vector(1 downto 0);
241 Full : in std_logic_vector(1 downto 0);
226 Empty : in std_logic_vector(1 downto 0);
242 Empty : in std_logic_vector(1 downto 0);
227 Conjugate : in std_logic;
243 Conjugate : in std_logic;
228 received : in std_logic;
244 received : in std_logic;
229 Start : out std_logic
245 Start : out std_logic
230 );
246 );
231 end component;
247 end component;
232
248
233 end; No newline at end of file
249 end;
Show file before | Show file after | Hide comments
@@ -1,88 +1,88
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_memory.all;
31 use lpp.lpp_memory.all;
32
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
34
35 entity APB_FIFO is
35 entity APB_FIFO is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0;
41 abits : integer := 8;
41 abits : integer := 8;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
48 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
49 Full : out std_logic;
49 Full : out std_logic;
50 Empty : out std_logic;
50 Empty : out std_logic;
51 WR : out std_logic;
51 WR : out std_logic;
52 RE : out std_logic;
52 RE : out std_logic;
53 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
53 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
54 );
54 );
55 end APB_FIFO;
55 end APB_FIFO;
56
56
57
57
58 architecture ar_APB_FIFO of APB_FIFO is
58 architecture ar_APB_FIFO of APB_FIFO is
59
59
60 signal ReadEnable : std_logic;
60 signal ReadEnable : std_logic;
61 signal WriteEnable : std_logic;
61 signal WriteEnable : std_logic;
62 signal FlagEmpty : std_logic;
62 signal FlagEmpty : std_logic;
63 signal FlagFull : std_logic;
63 signal FlagFull : std_logic;
64 --signal ReUse : std_logic;
64 --signal ReUse : std_logic;
65 --signal Lock : std_logic;
65 --signal Lock : std_logic;
66 --signal RstMem : std_logic;
66 signal RstMem : std_logic;
67 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
67 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
68 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
68 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
69 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
69 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
70 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
70 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
71
71
72 begin
72 begin
73
73
74 APB : ApbDriver
74 APB : ApbDriver
75 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
75 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
76 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
76 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77
77
78
78
79 DEVICE : Top_FIFO
79 DEVICE : Top_FIFO
80 generic map(Data_sz,Addr_sz,addr_max_int)
80 generic map(Data_sz,Addr_sz,addr_max_int)
81 port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
81 port map(clk,rst,ReadEnable,WriteEnable,RstMem,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
82
82
83 Empty <= FlagEmpty;
83 Empty <= FlagEmpty;
84 Full <= FlagFull;
84 Full <= FlagFull;
85 WR <= WriteEnable;
85 WR <= WriteEnable;
86 RE <= ReadEnable;
86 RE <= ReadEnable;
87
87
88 end ar_APB_FIFO; No newline at end of file
88 end ar_APB_FIFO;
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@@ -1,89 +1,91
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_memory.all;
31 use lpp.lpp_memory.all;
32
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
34
35 entity APB_FifoRead is
35 entity APB_FifoRead is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0;
41 abits : integer := 8;
41 abits : integer := 8;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
48 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
49 WriteEnable : in std_logic; --! Demande d'οΏ½criture dans la mοΏ½moire, gοΏ½rοΏ½ hors de l'IP
49 WriteEnable : in std_logic; --! Demande d'οΏ½criture dans la mοΏ½moire, gοΏ½rοΏ½ hors de l'IP
50 RE : out std_logic;
50 RE : out std_logic;
51 Full : out std_logic; --! Flag, Memoire pleine
51 Full : out std_logic; --! Flag, Memoire pleine
52 Empty : out std_logic; --! Flag, Memoire vide
52 Empty : out std_logic; --! Flag, Memoire vide
53 DATA : in std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½es en entrοΏ½e de la mοΏ½moire
53 DATA : in std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½es en entrοΏ½e de la mοΏ½moire
54 dataTEST : out std_logic_vector(Data_sz-1 downto 0);
54 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 );
56 );
56 end APB_FifoRead;
57 end APB_FifoRead;
57
58
58 --! @details Gestion de la FIFO, οΏ½criture via le bus APB, lecture interne au FPGA
59 --! @details Gestion de la FIFO, οΏ½criture via le bus APB, lecture interne au FPGA
59
60
60 architecture ar_APB_FifoRead of APB_FifoRead is
61 architecture ar_APB_FifoRead of APB_FifoRead is
61
62
62 signal Low : std_logic:='0';
63 signal Low : std_logic:='0';
63 signal ReadEnable : std_logic;
64 signal ReadEnable : std_logic;
64 signal FlagEmpty : std_logic;
65 signal FlagEmpty : std_logic;
65 signal FlagFull : std_logic;
66 signal FlagFull : std_logic;
66 --signal ReUse : std_logic;
67 --signal ReUse : std_logic;
67 --signal Lock : std_logic;
68 --signal Lock : std_logic;
68 --signal RstMem : std_logic;
69 signal RstMem : std_logic;
69 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
70 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
70 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
71 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
71 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
72 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
72 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
73 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
73
74
74 begin
75 begin
75
76
76 APB : ApbDriver
77 APB : ApbDriver
77 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
78 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
78 port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
79 port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
79
80
80
81
81 FIFO : Top_FIFO
82 FIFO : Top_FIFO
82 generic map(Data_sz,Addr_sz,addr_max_int)
83 generic map(Data_sz,Addr_sz,addr_max_int)
83 port map(clk,rst,ReadEnable,WriteEnable,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
84 port map(clk,rst,ReadEnable,WriteEnable,RstMem,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
84
85
85 Empty <= FlagEmpty;
86 Empty <= FlagEmpty;
86 Full <= FlagFull;
87 Full <= FlagFull;
87 RE <= ReadEnable;
88 RE <= ReadEnable;
89 dataTEST <= DataOut;
88
90
89 end ar_APB_FifoRead; No newline at end of file
91 end ar_APB_FifoRead;
Show file before | Show file after | Hide comments
@@ -1,88 +1,88
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_memory.all;
31 use lpp.lpp_memory.all;
32
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
34
35 entity APB_FifoWrite is
35 entity APB_FifoWrite is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0;
41 abits : integer := 8;
41 abits : integer := 8;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
48 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
49 ReadEnable : in std_logic; --! Demande de lecture de la mοΏ½moire, gοΏ½rοΏ½ hors de l'IP
49 ReadEnable : in std_logic; --! Demande de lecture de la mοΏ½moire, gοΏ½rοΏ½ hors de l'IP
50 Empty : out std_logic; --! Flag, Memoire vide
50 Empty : out std_logic; --! Flag, Memoire vide
51 Full : out std_logic; --! Flag, Memoire pleine
51 Full : out std_logic; --! Flag, Memoire pleine
52 DATA : out std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½es en sortie de la mοΏ½moire
52 DATA : out std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½es en sortie de la mοΏ½moire
53 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
53 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
54 );
54 );
55 end APB_FifoWrite;
55 end APB_FifoWrite;
56
56
57 --! @details Gestion de la FIFO, οΏ½criture via le bus APB, lecture interne au FPGA
57 --! @details Gestion de la FIFO, οΏ½criture via le bus APB, lecture interne au FPGA
58
58
59 architecture ar_APB_FifoWrite of APB_FifoWrite is
59 architecture ar_APB_FifoWrite of APB_FifoWrite is
60
60
61 signal Low : std_logic:='0';
61 signal Low : std_logic:='0';
62 signal WriteEnable : std_logic;
62 signal WriteEnable : std_logic;
63 signal FlagEmpty : std_logic;
63 signal FlagEmpty : std_logic;
64 signal FlagFull : std_logic;
64 signal FlagFull : std_logic;
65 --signal ReUse : std_logic;
65 --signal ReUse : std_logic;
66 --signal Lock : std_logic;
66 --signal Lock : std_logic;
67 --signal RstMem : std_logic;
67 signal RstMem : std_logic;
68 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
68 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
69 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
69 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
70 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
70 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
71 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
71 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
72
72
73 begin
73 begin
74
74
75 APB : ApbDriver
75 APB : ApbDriver
76 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
76 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
77 port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77 port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
78
78
79
79
80 FIFO : Top_FIFO
80 FIFO : Top_FIFO
81 generic map(Data_sz,Addr_sz,addr_max_int)
81 generic map(Data_sz,Addr_sz,addr_max_int)
82 port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
82 port map(clk,rst,ReadEnable,WriteEnable,RstMem,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
83
83
84 DATA <= DataOut;
84 DATA <= DataOut;
85 Empty <= FlagEmpty;
85 Empty <= FlagEmpty;
86 Full <= FlagFull;
86 Full <= FlagFull;
87
87
88 end ar_APB_FifoWrite; No newline at end of file
88 end ar_APB_FifoWrite;
Show file before | Show file after | Hide comments
@@ -1,173 +1,173
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31
31
32 --! Driver APB "GοΏ½nοΏ½rique" qui va faire le lien entre le bus Amba et la FIFO
32 --! Driver APB "GοΏ½nοΏ½rique" qui va faire le lien entre le bus Amba et la FIFO
33
33
34 entity ApbDriver is
34 entity ApbDriver is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8;
40 abits : integer := 8;
41 LPP_DEVICE : integer;
41 LPP_DEVICE : integer;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 ReadEnable : out std_logic; --! Instruction de lecture en mοΏ½moire
48 ReadEnable : out std_logic; --! Instruction de lecture en mοΏ½moire
49 WriteEnable : out std_logic; --! Instruction d'οΏ½criture en mοΏ½moire
49 WriteEnable : out std_logic; --! Instruction d'οΏ½criture en mοΏ½moire
50 FlagEmpty : in std_logic; --! Flag, MοΏ½moire vide
50 FlagEmpty : in std_logic; --! Flag, MοΏ½moire vide
51 FlagFull : in std_logic; --! Flag, MοΏ½moire pleine
51 FlagFull : in std_logic; --! Flag, MοΏ½moire pleine
52 -- ReUse : out std_logic; --! Flag, Permet de relire la mοΏ½moire en boucle sans nouvelle donnοΏ½es
52 -- ReUse : out std_logic; --! Flag, Permet de relire la mοΏ½moire en boucle sans nouvelle donnοΏ½es
53 -- Lock : out std_logic; --! Flag, Permet de bloquer l'οΏ½criture dans la mοΏ½moire
53 -- Lock : out std_logic; --! Flag, Permet de bloquer l'οΏ½criture dans la mοΏ½moire
54 -- RstMem : out std_logic; --! Flag, Reset "manuel" spοΏ½cifique au composant
54 RstMem : out std_logic; --! Flag, Reset "manuel" spοΏ½cifique au composant
55 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
55 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
56 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en sortie
56 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en sortie
57 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (οΏ½criture)
57 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (οΏ½criture)
58 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
58 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
59 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
59 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
60 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
60 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
61 );
61 );
62 end ApbDriver;
62 end ApbDriver;
63
63
64 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
64 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
65
65
66 architecture ar_ApbDriver of ApbDriver is
66 architecture ar_ApbDriver of ApbDriver is
67
67
68 constant REVISION : integer := 1;
68 constant REVISION : integer := 1;
69
69
70 constant pconfig : apb_config_type := (
70 constant pconfig : apb_config_type := (
71 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
71 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
72 1 => apb_iobar(paddr, pmask));
72 1 => apb_iobar(paddr, pmask));
73
73
74 type DEVICE_ctrlr_Reg is record
74 type DEVICE_ctrlr_Reg is record
75 DEVICE_Cfg : std_logic_vector(3 downto 0);
75 DEVICE_Cfg : std_logic_vector(4 downto 0);
76 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
76 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
77 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
77 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
78 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
78 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
79 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
79 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
80 end record;
80 end record;
81
81
82 signal Rec : DEVICE_ctrlr_Reg;
82 signal Rec : DEVICE_ctrlr_Reg;
83 signal Rdata : std_logic_vector(31 downto 0);
83 signal Rdata : std_logic_vector(31 downto 0);
84
84
85 signal FlagRE : std_logic;
85 signal FlagRE : std_logic;
86 signal FlagWR : std_logic;
86 signal FlagWR : std_logic;
87
87
88 begin
88 begin
89
89
90 Rec.DEVICE_Cfg(0) <= FlagRE;
90 Rec.DEVICE_Cfg(2) <= FlagRE;
91 Rec.DEVICE_Cfg(1) <= FlagWR;
91 Rec.DEVICE_Cfg(1) <= FlagWR;
92 Rec.DEVICE_Cfg(2) <= FlagEmpty;
92 Rec.DEVICE_Cfg(3) <= FlagEmpty;
93 Rec.DEVICE_Cfg(3) <= FlagFull;
93 Rec.DEVICE_Cfg(4) <= FlagFull;
94 --ReUse <= Rec.DEVICE_Cfg(4);
94 --ReUse <= Rec.DEVICE_Cfg(4);
95 --Lock <= Rec.DEVICE_Cfg(5);
95 --Lock <= Rec.DEVICE_Cfg(5);
96 --RstMem <= Rec.DEVICE_Cfg(7);
96 RstMem <= Rec.DEVICE_Cfg(0);
97
97
98 DataIn <= Rec.DEVICE_DataW;
98 DataIn <= Rec.DEVICE_DataW;
99 Rec.DEVICE_DataR <= DataOut;
99 Rec.DEVICE_DataR <= DataOut;
100 Rec.DEVICE_AddrW <= AddrIn;
100 Rec.DEVICE_AddrW <= AddrIn;
101 Rec.DEVICE_AddrR <= AddrOut;
101 Rec.DEVICE_AddrR <= AddrOut;
102
102
103
103
104
104
105 process(rst,clk)
105 process(rst,clk)
106 begin
106 begin
107 if(rst='0')then
107 if(rst='0')then
108 Rec.DEVICE_DataW <= (others => '0');
108 Rec.DEVICE_DataW <= (others => '0');
109 FlagWR <= '0';
109 FlagWR <= '0';
110 FlagRE <= '0';
110 FlagRE <= '0';
111 -- Rec.DEVICE_Cfg(4) <= '0';
111 Rec.DEVICE_Cfg(0) <= '0';
112 -- Rec.DEVICE_Cfg(5) <= '0';
112 -- Rec.DEVICE_Cfg(5) <= '0';
113 -- Rec.DEVICE_Cfg(7) <= '0';
113 -- Rec.DEVICE_Cfg(7) <= '0';
114
114
115 elsif(clk'event and clk='1')then
115 elsif(clk'event and clk='1')then
116
116
117 --APB Write OP
117 --APB Write OP
118 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
118 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
119 case apbi.paddr(abits-1 downto 2) is
119 case apbi.paddr(abits-1 downto 2) is
120 when "000000" =>
120 when "000000" =>
121 FlagWR <= '1';
121 FlagWR <= '1';
122 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
122 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
123 -- when "000010" =>
123 when "000010" =>
124 -- Rec.DEVICE_Cfg(7) <= apbi.pwdata(28);
124 Rec.DEVICE_Cfg(0) <= apbi.pwdata(0);
125 -- Rec.DEVICE_Cfg(5) <= apbi.pwdata(20);
125 -- Rec.DEVICE_Cfg(5) <= apbi.pwdata(20);
126 -- Rec.DEVICE_Cfg(6) <= apbi.pwdata(24);
126 -- Rec.DEVICE_Cfg(6) <= apbi.pwdata(24);
127 when others =>
127 when others =>
128 null;
128 null;
129 end case;
129 end case;
130 else
130 else
131 FlagWR <= '0';
131 FlagWR <= '0';
132 end if;
132 end if;
133
133
134 --APB Read OP
134 --APB Read OP
135 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
135 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
136 case apbi.paddr(abits-1 downto 2) is
136 case apbi.paddr(abits-1 downto 2) is
137 when "000000" =>
137 when "000000" =>
138 if(apbi.penable = '1')then
138 if(apbi.penable = '1')then
139 FlagRE <= '1';
139 FlagRE <= '1';
140 end if;
140 end if;
141 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
141 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
142 when "000001" =>
142 when "000001" =>
143 -- Rdata(31 downto 8) <= X"AAAAAA";
143 -- Rdata(31 downto 8) <= X"AAAAAA";
144 Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrR;
144 Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrR;
145 when "000101" =>
145 when "000101" =>
146 -- Rdata(31 downto 8) <= X"AAAAAA";
146 -- Rdata(31 downto 8) <= X"AAAAAA";
147 Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrW;
147 Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrW;
148 when "000010" =>
148 when "000010" =>
149 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
149 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
150 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
150 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
151 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
151 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
152 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
152 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
153 -- Rdata(27 downto 16) <= X"000";
153 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
154 -- Rdata(31 downto 28) <= "000" & Rec.DEVICE_Cfg(7);
154 -- Rdata(31 downto 28) <= "000" & Rec.DEVICE_Cfg(7);
155 -- Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5);
155 -- Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5);
156 -- Rdata(27 downto 24) <= "000" & Rec.DEVICE_Cfg(6);
156 -- Rdata(27 downto 24) <= "000" & Rec.DEVICE_Cfg(6);
157 Rdata(31 downto 16) <= X"CCCC";
157 Rdata(31 downto 20) <= X"CCC";
158 when others =>
158 when others =>
159 Rdata <= (others => '0');
159 Rdata <= (others => '0');
160 end case;
160 end case;
161 else
161 else
162 FlagRE <= '0';
162 FlagRE <= '0';
163 end if;
163 end if;
164
164
165 end if;
165 end if;
166 apbo.pconfig <= pconfig;
166 apbo.pconfig <= pconfig;
167 end process;
167 end process;
168
168
169 apbo.prdata <= Rdata when apbi.penable = '1';
169 apbo.prdata <= Rdata when apbi.penable = '1';
170 WriteEnable <= FlagWR;
170 WriteEnable <= FlagWR;
171 ReadEnable <= FlagRE; --when apbi.penable = '1';
171 ReadEnable <= FlagRE; --when apbi.penable = '1';
172
172
173 end ar_ApbDriver; No newline at end of file
173 end ar_ApbDriver;
Show file before | Show file after | Hide comments
@@ -1,94 +1,101
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25
25
26 --! Programme de la FIFO de lecture
26 --! Programme de la FIFO de lecture
27
27
28 entity Fifo_Read is
28 entity Fifo_Read is
29 generic(
29 generic(
30 Addr_sz : integer := 8;
30 Addr_sz : integer := 8;
31 addr_max_int : integer := 256);
31 addr_max_int : integer := 256);
32 port(
32 port(
33 clk,raz : in std_logic; --! Horloge et reset general du composant
33 clk,raz : in std_logic; --! Horloge et reset general du composant
34 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
34 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
35 -- flag_WR : in std_logic;
35 -- ReUse : in std_logic; --! Flag, Permet de relire la mοΏ½moire du dοΏ½but
36 -- ReUse : in std_logic; --! Flag, Permet de relire la mοΏ½moire du dοΏ½but
36 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'οΏ½criture dans la mοΏ½moire
37 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'οΏ½criture dans la mοΏ½moire
37 empty : out std_logic; --! Flag, MοΏ½moire vide
38 empty : out std_logic; --! Flag, MοΏ½moire vide
38 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la mοΏ½moire
39 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la mοΏ½moire
39 );
40 );
40 end Fifo_Read;
41 end Fifo_Read;
41
42
42 --! @details En aval de la SRAM Gaisler
43 --! @details En aval de la SRAM Gaisler
43
44
44 architecture ar_Fifo_Read of Fifo_Read is
45 architecture ar_Fifo_Read of Fifo_Read is
45
46
46 signal Rad_int : integer range 0 to addr_max_int;
47 signal Rad_int : integer range 0 to addr_max_int;
47 signal Rad_int_reg : integer range 0 to addr_max_int;
48 signal Rad_int_reg : integer range 0 to addr_max_int;
48 signal Wad_int : integer range 0 to addr_max_int;
49 signal Wad_int : integer range 0 to addr_max_int;
49 signal Wad_int_reg : integer range 0 to addr_max_int;
50 signal Wad_int_reg : integer range 0 to addr_max_int;
50 signal flag_reg : std_logic;
51 signal s_empty : std_logic;
51
52
52 begin
53 begin
53 process (clk,raz)
54 process (clk,raz)
54 begin
55 begin
55 if(raz='0')then
56 if(raz='0')then
56 Rad_int <= 0;
57 Rad_int <= 0;
57 empty <= '1';
58 s_empty <= '1';
58 flag_reg <= '0';
59
59
60 elsif(clk' event and clk='1')then
60 elsif(clk' event and clk='1')then
61 Wad_int_reg <= Wad_int;
61 Wad_int_reg <= Wad_int;
62 Rad_int_reg <= Rad_int;
62 Rad_int_reg <= Rad_int;
63 flag_reg <= flag_RE;
64
63
65
64
66 if(flag_reg ='0' and flag_RE='1')then
65 if(flag_RE='1')then
67 if(Rad_int=addr_max_int-1)then
66
68 Rad_int <= 0;
67 if(s_empty = '0')then
69 else
68 if(Rad_int=addr_max_int-1)then
70 Rad_int <= Rad_int+1;
69 Rad_int <= 0;
70 -- elsif(Rad_int=Wad_int-1)then
71 -- Rad_int <= Rad_int+1;
72 -- s_empty <= '1';
73 else
74 Rad_int <= Rad_int+1;
75 end if;
76 end if;
77
78 if(Rad_int=Wad_int-1)then
79 s_empty <= '1';
80 elsif(Rad_int=addr_max_int-1 and Wad_int=0)then
81 s_empty <= '1';
82 end if;
83
84 end if;
85
86
87 if(Wad_int_reg /= Wad_int)then
88 if(s_empty='1')then
89 s_empty <= '0';
71 end if;
90 end if;
72 end if;
91 end if;
92
93 end if;
73
94
74 -- if(ReUse='1')then
75 -- empty <= '0';
76 -- else
77 if(Rad_int_reg /= Rad_int)then
78 if(Rad_int=Wad_int)then
79 empty <= '1';
80 else
81 empty <= '0';
82 end if;
83 elsif(Wad_int_reg /= Wad_int)then
84 empty <= '0';
85 end if;
86 end if;
87
88 -- end if;
89 end process;
95 end process;
90
96
91 Wad_int <= to_integer(unsigned(Waddr));
97 Wad_int <= to_integer(unsigned(Waddr));
92 Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz));
98 Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz));
99 empty <= s_empty;
93
100
94 end ar_Fifo_Read; No newline at end of file
101 end ar_Fifo_Read;
Show file before | Show file after | Hide comments
@@ -1,89 +1,97
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25
25
26 --! Programme de la FIFO d'οΏ½criture
26 --! Programme de la FIFO d'οΏ½criture
27
27
28 entity Fifo_Write is
28 entity Fifo_Write is
29 generic(
29 generic(
30 Addr_sz : integer := 8;
30 Addr_sz : integer := 8;
31 addr_max_int : integer := 256);
31 addr_max_int : integer := 256);
32 port(
32 port(
33 clk,raz : in std_logic; --! Horloge et reset general du composant
33 clk,raz : in std_logic; --! Horloge et reset general du composant
34 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
34 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
35 -- flag_RE : in std_logic;
35 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la mοΏ½moire
36 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la mοΏ½moire
36 full : out std_logic; --! Flag, MοΏ½moire pleine
37 full : out std_logic; --! Flag, MοΏ½moire pleine
37 Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'οΏ½criture dans la mοΏ½moire
38 Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'οΏ½criture dans la mοΏ½moire
38 );
39 );
39 end Fifo_Write;
40 end Fifo_Write;
40
41
41 --! @details En amont de la SRAM Gaisler
42 --! @details En amont de la SRAM Gaisler
42
43
43 architecture ar_Fifo_Write of Fifo_Write is
44 architecture ar_Fifo_Write of Fifo_Write is
44
45
45 signal Wad_int : integer range 0 to addr_max_int;
46 signal Wad_int : integer range 0 to addr_max_int;
46 signal Wad_int_reg : integer range 0 to addr_max_int;
47 signal Wad_int_reg : integer range 0 to addr_max_int;
47 signal Rad_int : integer range 0 to addr_max_int;
48 signal Rad_int : integer range 0 to addr_max_int;
48 signal Rad_int_reg : integer range 0 to addr_max_int;
49 signal Rad_int_reg : integer range 0 to addr_max_int;
49 signal flag_reg : std_logic;
50 signal s_full : std_logic;
50
51
51 begin
52 begin
52 process (clk,raz)
53 process (clk,raz)
53 begin
54 begin
54 if(raz='0')then
55 if(raz='0')then
55 Wad_int <= 0;
56 Wad_int <= 0;
56 full <= '0';
57 s_full <= '0';
57 flag_reg <= '0';
58
58
59 elsif(clk' event and clk='1')then
59 elsif(clk' event and clk='1')then
60 Wad_int_reg <= Wad_int;
60 Wad_int_reg <= Wad_int;
61 Rad_int_reg <= Rad_int;
61 Rad_int_reg <= Rad_int;
62 flag_reg <= flag_WR;
62
63
63 if(flag_WR='1')then
64
64
65 if(flag_reg ='0' and flag_WR='1')then
65 if(s_full = '0')then
66 if(Wad_int=addr_max_int-1)then
66 if(Wad_int=addr_max_int-1)then
67 Wad_int <= 0;
67 Wad_int <= 0;
68 else
68 -- elsif(Wad_int=Rad_int-1)then
69 Wad_int <= Wad_int+1;
69 -- Wad_int <= Wad_int+1;
70 -- s_full <= '1';
71 else
72 Wad_int <= Wad_int+1;
73 end if;
70 end if;
74 end if;
75
76 if(Wad_int=Rad_int-1)then
77 s_full <= '1';
78 elsif(Wad_int=addr_max_int-1 and Rad_int=0)then
79 s_full <= '1';
80 end if;
81
71 end if;
82 end if;
72
83
73 if(Wad_int_reg /= Wad_int)then
84 if(Rad_int_reg /= Rad_int)then
74 if(Wad_int=Rad_int)then
85 if(s_full='1')then
75 full <= '1';
86 s_full <= '0';
76 else
77 full <= '0';
78 end if;
87 end if;
79 elsif(Rad_int_reg /= Rad_int)then
80 full <= '0';
81 end if;
88 end if;
82
89
83 end if;
90 end if;
84 end process;
91 end process;
85
92
86 Rad_int <= to_integer(unsigned(Raddr));
93 Rad_int <= to_integer(unsigned(Raddr));
87 Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz));
94 Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz));
95 full <= s_full;
88
96
89 end ar_Fifo_Write; No newline at end of file
97 end ar_Fifo_Write;
Show file before | Show file after | Hide comments
@@ -1,108 +1,115
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use work.FIFO_Config.all;
25
26
26 --! Programme qui va permettre de "pipeliner" la FIFO, donnοΏ½e disponible en sortie dοΏ½ son οΏ½criture en entrοΏ½e de la FIFO
27 --! Programme qui va permettre de "pipeliner" la FIFO, donnοΏ½e disponible en sortie dοΏ½ son οΏ½criture en entrοΏ½e de la FIFO
27
28
28 entity Pipeline is
29 entity PipeLine is
29 generic(Data_sz : integer := 16);
30 generic(Data_sz : integer := 16);
30 port(
31 port(
31 clk,raz : in std_logic; --! Horloge et reset general du composant
32 clk,raz : in std_logic; --! Horloge et reset general du composant
32 Data_one : in std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½e en entrοΏ½e de la FIFO, cotοΏ½ οΏ½criture
33 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½e en entrοΏ½e de la FIFO, cotοΏ½ οΏ½criture
33 Data_two : in std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½e en sortie de la FIFO, cotοΏ½ lecture
34 -- ReUse : in std_logic; --! Flag, Permet de relire la mοΏ½moire du dοΏ½but
35 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
34 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
36 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
35 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
37 empty : in std_logic; --! Flag, MοΏ½moire vide
36 empty : in std_logic; --! Flag, MοΏ½moire vide
38 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! DonnοΏ½e en sortie, pipelinοΏ½e
37 Data_svg : out std_logic_vector(Data_sz-1 downto 0);
38 Data1 : out std_logic;
39 Data2 : out std_logic
39 );
40 );
40 end Pipeline;
41 end PipeLine;
41
42
42 architecture ar_Pipeline of Pipeline is
43 architecture ar_PipeLine of PipeLine is
43
44
44 type etat is (e0,e1,e2,eX);
45 type etat is (e0,e1,e2,st0,st1,st2);
45 signal ect : etat;
46 signal ect : etat;
46
47
47 begin
48 begin
48 process (clk,raz)
49 process (clk,raz)
49 begin
50 begin
50 if(raz='0')then
51 if(raz='0')then
51 Data_out <= (others => 'X');
52 Data1 <= '0';
53 Data2 <= '0';
52 ect <= e0;
54 ect <= e0;
53
55
54 elsif(clk' event and clk='1')then
56 elsif(clk' event and clk='1')then
57 Data_svg <= Data_in;
58
55 case ect is
59 case ect is
56 when e0 =>
60 when e0 =>
61 Data2 <= '0';
57 if(flag_WR='1')then
62 if(flag_WR='1')then
58 Data_out <= Data_one;
63 Data1 <= '1';
59 ect <= e1;
64 ect <= st2;
60 -- elsif(ReUse='1')then
61 -- ect <= e1;
62 end if;
65 end if;
63
66
64 when e1 =>
67 when st2 =>
68 Data1 <= '0';
69 ect <= e1;
70
71 when e1 =>
65 if(flag_RE='1')then
72 if(flag_RE='1')then
66 --Data_out <= Data_two;
73 ect <= st0;
67 ect <= eX;
74 end if;
68 end if;
69
75
70 when eX =>
76 when st0 =>
71 --Data_out <= Data_two;
77 ect <= st1;
72 ect <= e2;
73
78
74 when e2 =>
79 when st1 =>
75 Data_out <= Data_two;
80 Data2 <= '1';
81 ect <= e2;
82
83
84 when e2 =>
76 if(empty='1')then
85 if(empty='1')then
77 ect <= e0;
86 ect <= e0;
78 else
87 else
79 --Data_out <= Data_two;
80 ect <= e2;
88 ect <= e2;
81 end if;
89 end if;
82
90
83
91
84
85 end case;
92 end case;
86 end if;
93 end if;
87 end process;
94 end process;
88
95
89 end ar_Pipeline;
96 end ar_PipeLine;
90
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@@ -1,149 +1,118
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library techmap;
25 library techmap;
26 use techmap.gencomp.all;
26 use techmap.gencomp.all;
27 use work.config.all;
27 use work.config.all;
28 use lpp.lpp_memory.all;
28 use lpp.lpp_memory.all;
29
29
30 --! Programme de la FIFO
30 --! Programme de la FIFO
31
31
32 entity Top_FIFO is
32 entity Top_FIFO is
33 generic(
33 generic(
34 Data_sz : integer := 16;
34 Data_sz : integer := 16;
35 Addr_sz : integer := 8;
35 Addr_sz : integer := 8;
36 addr_max_int : integer := 256
36 addr_max_int : integer := 256
37 );
37 );
38 port(
38 port(
39 clk,raz : in std_logic; --! Horloge et reset general du composant
39 clk,raz : in std_logic; --! Horloge et reset general du composant
40 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
40 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
41 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
41 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
42 -- ReUse : in std_logic; --! Flag, Permet de relire la mοΏ½moire en boucle sans nouvelle donnοΏ½es
42 RstMem : in std_logic;
43 -- Lock : in std_logic; --! Permet de bloquer l'οΏ½criture dans la mοΏ½moire
44 -- RstMem : in std_logic; --! Flag, Reset "manuel" spοΏ½cifique au composant
45 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrοΏ½e du composant
43 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrοΏ½e du composant
46 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'οΏ½criture
44 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'οΏ½criture
47 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
45 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
48 full : out std_logic; --! Flag, MοΏ½moire pleine
46 full : out std_logic; --! Flag, MοΏ½moire pleine
49 empty : out std_logic; --! Flag, MοΏ½moire vide
47 empty : out std_logic; --! Flag, MοΏ½moire vide
50 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
48 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
51 );
49 );
52 end Top_FIFO;
50 end Top_FIFO;
53
51
54 --! @details Une mοΏ½moire SRAM de chez Gaisler est utilisοΏ½e,
52 --! @details Une mοΏ½moire SRAM de chez Gaisler est utilisοΏ½e,
55 --! associοΏ½e a deux Drivers, un pour οΏ½crire l'autre pour lire cette mοΏ½moire
53 --! associοΏ½e a deux Drivers, un pour οΏ½crire l'autre pour lire cette mοΏ½moire
56
54
57 architecture ar_Top_FIFO of Top_FIFO is
55 architecture ar_Top_FIFO of Top_FIFO is
58
56
59 component syncram_2p
57 component syncram_2p
60 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
58 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
61 port (
59 port (
62 rclk : in std_ulogic;
60 rclk : in std_ulogic;
63 renable : in std_ulogic;
61 renable : in std_ulogic;
64 raddress : in std_logic_vector((abits -1) downto 0);
62 raddress : in std_logic_vector((abits -1) downto 0);
65 dataout : out std_logic_vector((dbits -1) downto 0);
63 dataout : out std_logic_vector((dbits -1) downto 0);
66 wclk : in std_ulogic;
64 wclk : in std_ulogic;
67 write : in std_ulogic;
65 write : in std_ulogic;
68 waddress : in std_logic_vector((abits -1) downto 0);
66 waddress : in std_logic_vector((abits -1) downto 0);
69 datain : in std_logic_vector((dbits -1) downto 0));
67 datain : in std_logic_vector((dbits -1) downto 0));
70 end component;
68 end component;
71
69
72 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
70 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
73 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
71 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
74 signal Data_int : std_logic_vector(Data_sz-1 downto 0);
72 signal Data_int : std_logic_vector(Data_sz-1 downto 0);
73 signal Data_svg : std_logic_vector(Data_sz-1 downto 0);
75 signal s_empty : std_logic;
74 signal s_empty : std_logic;
76 signal s_full : std_logic;
75 signal s_full : std_logic;
77 --signal s_full2 : std_logic;
76 signal Data1 : std_logic;
77 signal Data2 : std_logic;
78 signal s_flag_RE : std_logic;
78 signal s_flag_RE : std_logic;
79 signal s_flag_WR : std_logic;
79 signal s_flag_WR : std_logic;
80 signal Flag_WR_reg : std_logic;
80 signal rstf : std_logic;
81 --signal rst : std_logic;
82 --signal RstMem_inv : std_logic;
83
81
84 begin
82 begin
85
83
86 --RstMem_inv <= not RstMem;
84 Reset : entity LocalReset
87 --rst <= raz and RstMem_inv;
85 port map(clk,raz,RstMem,rstf);
88
86
89 WR : Fifo_Write
87 WR : entity Fifo_Write
90 generic map(Addr_sz,addr_max_int)
88 generic map(Addr_sz,addr_max_int)
91 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr);
89 port map(clk,rstf,s_flag_WR,Raddr,s_full,Waddr);
92
93
90
94 SRAM : syncram_2p
91 SRAM : syncram_2p
95 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
92 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
96 port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in);
93 port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in);
97
94
95 RE : entity Fifo_Read
96 generic map(Addr_sz,addr_max_int)
97 port map(clk,rstf,s_flag_RE,Waddr,s_empty,Raddr);
98
98
99 Pipe : Pipeline
99 PIPE : entity PipeLine
100 generic map(Data_sz)
100 generic map(Data_sz)
101 port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
101 port map(clk,rstf,Data_in,s_flag_RE,s_flag_WR,s_empty,Data_svg,Data1,Data2);
102
102
103
103
104 RE : Fifo_Read
104 Data_out <= Data_svg when Data1='1' else
105 generic map(Addr_sz,addr_max_int)
105 Data_int when Data2='1';
106 port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr);
107
108 process(clk,raz)
109 begin
110 if(raz='0')then
111 s_flag_RE <= '0';
112 s_flag_WR <= '0';
113 -- s_full2 <= s_full;
114 Flag_WR_reg <= '0';
115
116 elsif(clk'event and clk='1')then
117 Flag_WR_reg <= Flag_WR;
118
106
119 if(s_full='0')then --2
107 full <= s_full;
120 if(s_empty='1')then
121 s_flag_WR <= Flag_WR_reg;
122 else
123 s_flag_WR <= Flag_WR;
124 end if;
125 else
126 s_flag_WR <= '0';
127 end if;
128
129 if(s_empty='0')then
130 s_flag_RE <= Flag_RE;
131 else
132 s_flag_RE <= '0';
133 end if;
134
135 -- if(Lock='1')then
136 -- s_full2 <= '1';
137 -- else
138 -- s_full2 <= s_full;
139 -- end if;
140
141 end if;
142 end process;
143
144 full <= s_full; --2
145 empty <= s_empty;
108 empty <= s_empty;
146 Addr_RE <= Raddr;
109 Addr_RE <= Raddr;
147 Addr_WR <= Waddr;
110 Addr_WR <= Waddr;
148
111
112 s_flag_WR <= Flag_WR when s_full='0' else
113 '0';
114
115 s_flag_RE <= Flag_RE when s_empty='0' else
116 '0';
117
149 end ar_Top_FIFO; No newline at end of file
118 end ar_Top_FIFO;
Show file before | Show file after | Hide comments
@@ -1,253 +1,262
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31
31
32 package lpp_memory is
32 package lpp_memory is
33
33
34 --===========================================================|
34 --===========================================================|
35 --=================== FIFO ComplοΏ½te =========================|
35 --=================== FIFO ComplοΏ½te =========================|
36 --===========================================================|
36 --===========================================================|
37
37
38 component APB_FIFO is
38 component APB_FIFO is
39 generic (
39 generic (
40 pindex : integer := 0;
40 pindex : integer := 0;
41 paddr : integer := 0;
41 paddr : integer := 0;
42 pmask : integer := 16#fff#;
42 pmask : integer := 16#fff#;
43 pirq : integer := 0;
43 pirq : integer := 0;
44 abits : integer := 8;
44 abits : integer := 8;
45 Data_sz : integer := 16;
45 Data_sz : integer := 16;
46 Addr_sz : integer := 8;
46 Addr_sz : integer := 8;
47 addr_max_int : integer := 256);
47 addr_max_int : integer := 256);
48 port (
48 port (
49 clk : in std_logic;
49 clk : in std_logic;
50 rst : in std_logic;
50 rst : in std_logic;
51 apbi : in apb_slv_in_type;
51 apbi : in apb_slv_in_type;
52 Full : out std_logic;
52 Full : out std_logic;
53 Empty : out std_logic;
53 Empty : out std_logic;
54 WR : out std_logic;
54 WR : out std_logic;
55 RE : out std_logic;
55 RE : out std_logic;
56 apbo : out apb_slv_out_type
56 apbo : out apb_slv_out_type
57 );
57 );
58 end component;
58 end component;
59
59
60
60
61 component ApbDriver is
61 component ApbDriver is
62 generic (
62 generic (
63 pindex : integer := 0;
63 pindex : integer := 0;
64 paddr : integer := 0;
64 paddr : integer := 0;
65 pmask : integer := 16#fff#;
65 pmask : integer := 16#fff#;
66 pirq : integer := 0;
66 pirq : integer := 0;
67 abits : integer := 8;
67 abits : integer := 8;
68 LPP_DEVICE : integer;
68 LPP_DEVICE : integer;
69 Data_sz : integer := 16;
69 Data_sz : integer := 16;
70 Addr_sz : integer := 8;
70 Addr_sz : integer := 8;
71 addr_max_int : integer := 256);
71 addr_max_int : integer := 256);
72 port (
72 port (
73 clk : in std_logic;
73 clk : in std_logic;
74 rst : in std_logic;
74 rst : in std_logic;
75 ReadEnable : out std_logic;
75 ReadEnable : out std_logic;
76 WriteEnable : out std_logic;
76 WriteEnable : out std_logic;
77 FlagEmpty : in std_logic;
77 FlagEmpty : in std_logic;
78 FlagFull : in std_logic;
78 FlagFull : in std_logic;
79 -- ReUse : out std_logic;
79 -- ReUse : out std_logic;
80 -- Lock : out std_logic;
80 -- Lock : out std_logic;
81 -- RstMem : out std_logic;
81 RstMem : out std_logic;
82 DataIn : out std_logic_vector(Data_sz-1 downto 0);
82 DataIn : out std_logic_vector(Data_sz-1 downto 0);
83 DataOut : in std_logic_vector(Data_sz-1 downto 0);
83 DataOut : in std_logic_vector(Data_sz-1 downto 0);
84 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
84 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
85 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
85 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
86 apbi : in apb_slv_in_type;
86 apbi : in apb_slv_in_type;
87 apbo : out apb_slv_out_type
87 apbo : out apb_slv_out_type
88 );
88 );
89 end component;
89 end component;
90
90
91
91
92 component Top_FIFO is
92 component Top_FIFO is
93 generic(
93 generic(
94 Data_sz : integer := 16;
94 Data_sz : integer := 16;
95 Addr_sz : integer := 8;
95 Addr_sz : integer := 8;
96 addr_max_int : integer := 256
96 addr_max_int : integer := 256
97 );
97 );
98 port(
98 port(
99 clk,raz : in std_logic;
99 clk,raz : in std_logic;
100 flag_RE : in std_logic;
100 flag_RE : in std_logic;
101 flag_WR : in std_logic;
101 flag_WR : in std_logic;
102 -- ReUse : in std_logic;
102 -- ReUse : in std_logic;
103 -- Lock : in std_logic;
103 -- Lock : in std_logic;
104 -- RstMem : in std_logic;
104 RstMem : in std_logic;
105 Data_in : in std_logic_vector(Data_sz-1 downto 0);
105 Data_in : in std_logic_vector(Data_sz-1 downto 0);
106 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
106 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
107 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
107 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
108 full : out std_logic;
108 full : out std_logic;
109 empty : out std_logic;
109 empty : out std_logic;
110 Data_out : out std_logic_vector(Data_sz-1 downto 0)
110 Data_out : out std_logic_vector(Data_sz-1 downto 0)
111 );
111 );
112 end component;
112 end component;
113
113
114
114
115 component Fifo_Read is
115 component Fifo_Read is
116 generic(
116 generic(
117 Addr_sz : integer := 8;
117 Addr_sz : integer := 8;
118 addr_max_int : integer := 256);
118 addr_max_int : integer := 256);
119 port(
119 port(
120 clk : in std_logic;
120 clk : in std_logic;
121 raz : in std_logic;
121 raz : in std_logic;
122 flag_RE : in std_logic;
122 flag_RE : in std_logic;
123 -- ReUse : in std_logic;
124 Waddr : in std_logic_vector(addr_sz-1 downto 0);
123 Waddr : in std_logic_vector(addr_sz-1 downto 0);
125 empty : out std_logic;
124 empty : out std_logic;
126 Raddr : out std_logic_vector(addr_sz-1 downto 0)
125 Raddr : out std_logic_vector(addr_sz-1 downto 0)
127 );
126 );
128 end component;
127 end component;
129
128
130
129
131 component Fifo_Write is
130 component Fifo_Write is
132 generic(
131 generic(
133 Addr_sz : integer := 8;
132 Addr_sz : integer := 8;
134 addr_max_int : integer := 256);
133 addr_max_int : integer := 256);
135 port(
134 port(
136 clk : in std_logic;
135 clk : in std_logic;
137 raz : in std_logic;
136 raz : in std_logic;
138 flag_WR : in std_logic;
137 flag_WR : in std_logic;
139 Raddr : in std_logic_vector(addr_sz-1 downto 0);
138 Raddr : in std_logic_vector(addr_sz-1 downto 0);
140 full : out std_logic;
139 full : out std_logic;
141 Waddr : out std_logic_vector(addr_sz-1 downto 0)
140 Waddr : out std_logic_vector(addr_sz-1 downto 0)
142 );
141 );
143 end component;
142 end component;
144
143
145
144
146 component Pipeline is
145 component PipeLine is
147 generic(Data_sz : integer := 16);
146 generic(Data_sz : integer := 16);
148 port(
147 port(
149 clk,raz : in std_logic;
148 clk,raz : in std_logic; --! Horloge et reset general du composant
150 Data_one : in std_logic_vector(Data_sz-1 downto 0);
149 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½e en entrοΏ½e de la FIFO, cotοΏ½ οΏ½criture
151 Data_two : in std_logic_vector(Data_sz-1 downto 0);
150 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
152 -- ReUse : in std_logic;
151 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
153 flag_RE : in std_logic;
152 empty : in std_logic; --! Flag, MοΏ½moire vide
154 flag_WR : in std_logic;
153 Data_svg : out std_logic_vector(Data_sz-1 downto 0);
155 empty : in std_logic;
154 Data1 : out std_logic;
156 Data_out : out std_logic_vector(Data_sz-1 downto 0)
155 Data2 : out std_logic
157 );
156 );
158 end component;
157 end component;
159
158
159
160 component LocalReset is
161 port(
162 clk : in std_logic;
163 raz : in std_logic;
164 Rz : in std_logic;
165 rstf : out std_logic
166 );
167 end component;
160 --===========================================================|
168 --===========================================================|
161 --================= Demi FIFO Ecriture ======================|
169 --================= Demi FIFO Ecriture ======================|
162 --===========================================================|
170 --===========================================================|
163
171
164 component APB_FifoWrite is
172 component APB_FifoWrite is
165 generic (
173 generic (
166 pindex : integer := 0;
174 pindex : integer := 0;
167 paddr : integer := 0;
175 paddr : integer := 0;
168 pmask : integer := 16#fff#;
176 pmask : integer := 16#fff#;
169 pirq : integer := 0;
177 pirq : integer := 0;
170 abits : integer := 8;
178 abits : integer := 8;
171 Data_sz : integer := 16;
179 Data_sz : integer := 16;
172 Addr_sz : integer := 8;
180 Addr_sz : integer := 8;
173 addr_max_int : integer := 256);
181 addr_max_int : integer := 256);
174 port (
182 port (
175 clk : in std_logic;
183 clk : in std_logic;
176 rst : in std_logic;
184 rst : in std_logic;
177 apbi : in apb_slv_in_type;
185 apbi : in apb_slv_in_type;
178 ReadEnable : in std_logic;
186 ReadEnable : in std_logic;
179 Empty : out std_logic;
187 Empty : out std_logic;
180 Full : out std_logic;
188 Full : out std_logic;
181 DATA : out std_logic_vector(Data_sz-1 downto 0);
189 DATA : out std_logic_vector(Data_sz-1 downto 0);
182 apbo : out apb_slv_out_type
190 apbo : out apb_slv_out_type
183 );
191 );
184 end component;
192 end component;
185
193
186
194
187 --component Top_FifoWrite is
195 --component Top_FifoWrite is
188 -- generic(
196 -- generic(
189 -- Data_sz : integer := 16;
197 -- Data_sz : integer := 16;
190 -- Addr_sz : integer := 8;
198 -- Addr_sz : integer := 8;
191 -- addr_max_int : integer := 256);
199 -- addr_max_int : integer := 256);
192 -- port(
200 -- port(
193 -- clk : in std_logic;
201 -- clk : in std_logic;
194 -- raz : in std_logic;
202 -- raz : in std_logic;
195 -- flag_RE : in std_logic;
203 -- flag_RE : in std_logic;
196 -- flag_WR : in std_logic;
204 -- flag_WR : in std_logic;
197 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
205 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
198 -- Raddr : in std_logic_vector(addr_sz-1 downto 0);
206 -- Raddr : in std_logic_vector(addr_sz-1 downto 0);
199 -- full : out std_logic;
207 -- full : out std_logic;
200 -- empty : out std_logic;
208 -- empty : out std_logic;
201 -- Waddr : out std_logic_vector(addr_sz-1 downto 0);
209 -- Waddr : out std_logic_vector(addr_sz-1 downto 0);
202 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
210 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
203 -- );
211 -- );
204 --end component;
212 --end component;
205
213
206 --===========================================================|
214 --===========================================================|
207 --================== Demi FIFO Lecture ======================|
215 --================== Demi FIFO Lecture ======================|
208 --===========================================================|
216 --===========================================================|
209
217
210 component APB_FifoRead is
218 component APB_FifoRead is
211 generic (
219 generic (
212 pindex : integer := 0;
220 pindex : integer := 0;
213 paddr : integer := 0;
221 paddr : integer := 0;
214 pmask : integer := 16#fff#;
222 pmask : integer := 16#fff#;
215 pirq : integer := 0;
223 pirq : integer := 0;
216 abits : integer := 8;
224 abits : integer := 8;
217 Data_sz : integer := 16;
225 Data_sz : integer := 16;
218 Addr_sz : integer := 8;
226 Addr_sz : integer := 8;
219 addr_max_int : integer := 256);
227 addr_max_int : integer := 256);
220 port (
228 port (
221 clk : in std_logic;
229 clk : in std_logic;
222 rst : in std_logic;
230 rst : in std_logic;
223 apbi : in apb_slv_in_type;
231 apbi : in apb_slv_in_type;
224 WriteEnable : in std_logic;
232 WriteEnable : in std_logic;
225 RE : out std_logic;
233 RE : out std_logic;
226 Full : out std_logic;
234 Full : out std_logic;
227 Empty : out std_logic;
235 Empty : out std_logic;
228 DATA : in std_logic_vector(Data_sz-1 downto 0);
236 DATA : in std_logic_vector(Data_sz-1 downto 0);
237 dataTEST : out std_logic_vector(Data_sz-1 downto 0);
229 apbo : out apb_slv_out_type
238 apbo : out apb_slv_out_type
230 );
239 );
231 end component;
240 end component;
232
241
233
242
234 --component Top_FifoRead is
243 --component Top_FifoRead is
235 -- generic(
244 -- generic(
236 -- Data_sz : integer := 16;
245 -- Data_sz : integer := 16;
237 -- Addr_sz : integer := 8;
246 -- Addr_sz : integer := 8;
238 -- addr_max_int : integer := 256);
247 -- addr_max_int : integer := 256);
239 -- port(
248 -- port(
240 -- clk : in std_logic;
249 -- clk : in std_logic;
241 -- raz : in std_logic;
250 -- raz : in std_logic;
242 -- flag_RE : in std_logic;
251 -- flag_RE : in std_logic;
243 -- flag_WR : in std_logic;
252 -- flag_WR : in std_logic;
244 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
253 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
245 -- Waddr : in std_logic_vector(addr_sz-1 downto 0);
254 -- Waddr : in std_logic_vector(addr_sz-1 downto 0);
246 -- full : out std_logic;
255 -- full : out std_logic;
247 -- empty : out std_logic;
256 -- empty : out std_logic;
248 -- Raddr : out std_logic_vector(addr_sz-1 downto 0);
257 -- Raddr : out std_logic_vector(addr_sz-1 downto 0);
249 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
258 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
250 -- );
259 -- );
251 --end component;
260 --end component;
252
261
253 end;
262 end;
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