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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library lpp;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.lpp_memory.all;
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--! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
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entity APB_FifoWrite is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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Data_sz : integer := 16;
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Addr_sz : integer := 8;
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addr_max_int : integer := 256);
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port (
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clk : in std_logic; --! Horloge du composant
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rst : in std_logic; --! Reset general du composant
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apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
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ReadEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
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Empty : out std_logic; --! Flag, Memoire vide
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Full : out std_logic; --! Flag, Memoire pleine
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DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire
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apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
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);
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end APB_FifoWrite;
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--! @details Gestion de la FIFO, �criture via le bus APB, lecture interne au FPGA
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architecture ar_APB_FifoWrite of APB_FifoWrite is
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signal Low : std_logic:='0';
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signal WriteEnable : std_logic;
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signal FlagEmpty : std_logic;
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signal FlagFull : std_logic;
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--signal ReUse : std_logic;
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--signal Lock : std_logic;
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--signal RstMem : std_logic;
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signal DataIn : std_logic_vector(Data_sz-1 downto 0);
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signal DataOut : std_logic_vector(Data_sz-1 downto 0);
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signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
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signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
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begin
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APB : ApbDriver
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generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
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port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
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FIFO : Top_FIFO
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generic map(Data_sz,Addr_sz,addr_max_int)
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port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
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DATA <= DataOut;
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Empty <= FlagEmpty;
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Full <= FlagFull;
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end ar_APB_FifoWrite;
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