APB_FifoWrite.vhd
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| 3.7 KiB
| text/x-vhdl
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VhdlLexer
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r53 | ------------------------------------------------------------------------------ | |
-- This file is a part of the LPP VHDL IP LIBRARY | |||
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
-- | |||
-- This program is free software; you can redistribute it and/or modify | |||
-- it under the terms of the GNU General Public License as published by | |||
-- the Free Software Foundation; either version 3 of the License, or | |||
-- (at your option) any later version. | |||
-- | |||
-- This program is distributed in the hope that it will be useful, | |||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
-- GNU General Public License for more details. | |||
-- | |||
-- You should have received a copy of the GNU General Public License | |||
-- along with this program; if not, write to the Free Software | |||
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
------------------------------------------------------------------------------ | |||
-- Author : Martin Morlot | |||
-- Mail : martin.morlot@lpp.polytechnique.fr | |||
------------------------------------------------------------------------------ | |||
library ieee; | |||
use ieee.std_logic_1164.all; | |||
library grlib; | |||
use grlib.amba.all; | |||
use grlib.stdlib.all; | |||
use grlib.devices.all; | |||
library lpp; | |||
use lpp.lpp_amba.all; | |||
use lpp.apb_devices_list.all; | |||
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r75 | use lpp.lpp_memory.all; | |
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r53 | ||
--! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba | |||
entity APB_FifoWrite is | |||
generic ( | |||
pindex : integer := 0; | |||
paddr : integer := 0; | |||
pmask : integer := 16#fff#; | |||
pirq : integer := 0; | |||
abits : integer := 8; | |||
Data_sz : integer := 16; | |||
Addr_sz : integer := 8; | |||
addr_max_int : integer := 256); | |||
port ( | |||
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r75 | clk : in std_logic; --! Horloge du composant | |
rst : in std_logic; --! Reset general du composant | |||
apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |||
ReadEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP | |||
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r87 | Empty : out std_logic; --! Flag, Memoire vide | |
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r79 | Full : out std_logic; --! Flag, Memoire pleine | |
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r75 | DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire | |
apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |||
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r53 | ); | |
end APB_FifoWrite; | |||
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r75 | --! @details Gestion de la FIFO, �criture via le bus APB, lecture interne au FPGA | |
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r53 | ||
architecture ar_APB_FifoWrite of APB_FifoWrite is | |||
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r75 | signal Low : std_logic:='0'; | |
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r62 | signal WriteEnable : std_logic; | |
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r75 | signal FlagEmpty : std_logic; | |
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r62 | signal FlagFull : std_logic; | |
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r87 | --signal ReUse : std_logic; | |
--signal Lock : std_logic; | |||
--signal RstMem : std_logic; | |||
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r62 | signal DataIn : std_logic_vector(Data_sz-1 downto 0); | |
signal DataOut : std_logic_vector(Data_sz-1 downto 0); | |||
signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); | |||
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r75 | signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); | |
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r53 | ||
begin | |||
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r62 | APB : ApbDriver | |
generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) | |||
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r87 | port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); | |
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r53 | ||
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r75 | FIFO : Top_FIFO | |
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r62 | generic map(Data_sz,Addr_sz,addr_max_int) | |
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r87 | port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); | |
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r53 | ||
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r75 | DATA <= DataOut; | |
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r77 | Empty <= FlagEmpty; | |
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r79 | Full <= FlagFull; | |
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r53 | ||
end ar_APB_FifoWrite; |