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Spectral Matrix Okai, with 5 input fifo
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r77:5e578edcbc3c martin
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@@ -0,0 +1,85
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity Starter is
27 port(
28 clk : in std_logic;
29 raz : in std_logic;
30 empty1 : in std_logic;
31 empty2 : in std_logic;
32 Conjugate : in std_logic;
33 Start : out std_logic
34 );
35 end Starter;
36
37
38 architecture ar_Starter of Starter is
39
40 begin
41 process(clk,raz)
42 begin
43
44 if(raz='0')then
45 Start <= '0';
46
47 elsif(clk'event and clk='1')then
48
49 if(Conjugate='1')then
50 if(empty1='1')then
51 Start <= '0';
52 else
53 Start <= '1';
54 end if;
55 else
56 if(empty1='1' or empty2='1')then
57 Start <= '0';
58 else
59 Start <= '1';
60 end if;
61
62 end if;
63 end if;
64 end process;
65
66 end ar_Starter;
67
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@@ -1,34 +1,34
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25
25
26 entity SelectInputs is
26 entity SelectInputs is
27 generic(
27 generic(
28 Input_SZ : integer := 16);
28 Input_SZ : integer := 16);
29 port(
29 port(
30 clk : in std_logic;
30 clk : in std_logic;
31 raz : in std_logic;
31 raz : in std_logic;
32 Read : in std_logic;
32 Read : in std_logic;
33 B1 : in std_logic_vector(Input_SZ-1 downto 0);
33 B1 : in std_logic_vector(Input_SZ-1 downto 0);
34 B2 : in std_logic_vector(Input_SZ-1 downto 0);
34 B2 : in std_logic_vector(Input_SZ-1 downto 0);
@@ -37,21 +37,24 port(
37 E2 : in std_logic_vector(Input_SZ-1 downto 0);
37 E2 : in std_logic_vector(Input_SZ-1 downto 0);
38 Conjugate : out std_logic;
38 Conjugate : out std_logic;
39 Take : out std_logic;
39 Take : out std_logic;
40 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
40 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
41 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
41 Statu : out std_logic_vector(3 downto 0);
42 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
42 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
43 );
43 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
44 end SelectInputs;
44 );
45
45 end SelectInputs;
46
46
47 architecture ar_SelectInputs of SelectInputs is
47
48 architecture ar_SelectInputs of SelectInputs is
48
49
49 signal Read_reg : std_logic;
50 signal Read_reg : std_logic;
50 signal i : integer range 1 to 15;
51 signal i : integer range 0 to 128;
52 signal j : integer range 0 to 15;
53 signal Read_int : std_logic_vector(4 downto 0);
51
54
52 type state is (stX,st1a,st1b);
55 type state is (stX,sta,stb,st1,st2,idl1,idl2);
53 signal ect : state;
56 signal ect : state;
54
57
55 begin
58 begin
56 process(clk,raz)
59 process(clk,raz)
57 begin
60 begin
@@ -59,6 +62,7 begin
59 if(raz='0')then
62 if(raz='0')then
60 Take <= '0';
63 Take <= '0';
61 i <= 0;
64 i <= 0;
65 j <= 0;
62 Read_reg <= '0';
66 Read_reg <= '0';
63 ect <= stX;
67 ect <= stX;
64
68
@@ -66,202 +70,53 begin
66 Read_reg <= Read;
70 Read_reg <= Read;
67
71
68 case ect is
72 case ect is
73
69 when stX =>
74 when stX =>
70 i <= 1;
75 i <= 1;
71 if(Read_reg='0' and Read='1')then
76 if(Read_reg='0' and Read='1')then
72 ect <= st1a;
77 if(j=15)then
78 j <= 1;
79 else
80 j<= j+1;
81 end if;
82 ect <= idl1;
73 end if;
83 end if;
74 -------------------------------------------------------------------------------
84
75 when st1a =>
85 when idl1 =>
76 Take <= '1';
86 ect <= st1;
87
88 when st1 =>
89 Take <= '1';
90 ect <= sta;
91
92 when sta =>
77 if(Read_reg='0' and Read='1')then
93 if(Read_reg='0' and Read='1')then
78 ect <= st1b;
94 ect <= idl2;
79 end if;
95 end if;
80
96
81 when st1b =>
97 when idl2 =>
98 ect <= st2;
99
100 when st2 =>
82 Take <= '0';
101 Take <= '0';
83 if(i=15)then
102 ect <= stb;
103
104 when stb =>
105 if(i=128)then
84 ect <= stX;
106 ect <= stX;
85 elsif(Read_reg='0' and Read='1')then
107 elsif(Read_reg='0' and Read='1')then
86 i <= i+1;
108 i <= i+1;
87 ect <= st1a;
109 ect <= idl1;
88 end if;
110 end if;
89 -------------------------------------------------------------------------------
111
90 -- when st2a =>
91 -- Take <= '1';
92 -- if(Read_reg='0' and Read='1')then
93 -- ect <= st2b;
94 -- end if;
95 --
96 -- when st2b =>
97 -- Take <= '0';
98 -- if(Read_reg='0' and Read='1')then
99 -- ect <= st3a;
100 -- end if;
101 ---------------------------------------------------------------------------------
102 -- when st3a =>
103 -- Take <= '1';
104 -- if(Read_reg='0' and Read='1')then
105 -- ect <= st3b;
106 -- end if;
107 --
108 -- when st3b =>
109 -- Take <= '0';
110 -- if(Read_reg='0' and Read='1')then
111 -- ect <= st4a;
112 -- end if;
113 ---------------------------------------------------------------------------------
114 -- when st4a =>
115 -- Take <= '1';
116 -- if(Read_reg='0' and Read='1')then
117 -- ect <= st4b;
118 -- end if;
119 --
120 -- when st4b =>
121 -- Take <= '0';
122 -- if(Read_reg='0' and Read='1')then
123 -- ect <= st5a;
124 -- end if;
125 ---------------------------------------------------------------------------------
126 --
127 -- when st5a =>
128 -- Take <= '1';
129 -- if(Read_reg='0' and Read='1')then
130 -- ect <= st5b;
131 -- end if;
132 --
133 -- when st5b =>
134 -- Take <= '0';
135 -- if(Read_reg='0' and Read='1')then
136 -- ect <= st6a;
137 -- end if;
138 ---------------------------------------------------------------------------------
139 -- when st6a =>
140 -- Take <= '1';
141 -- if(Read_reg='0' and Read='1')then
142 -- ect <= st6b;
143 -- end if;
144 --
145 -- when st6b =>
146 -- Take <= '0';
147 -- if(Read_reg='0' and Read='1')then
148 -- ect <= st7a;
149 -- end if;
150 ---------------------------------------------------------------------------------
151 -- when st7a =>
152 -- Take <= '1';
153 -- if(Read_reg='0' and Read='1')then
154 -- ect <= st7b;
155 -- end if;
156 --
157 -- when st7b =>
158 -- Take <= '0';
159 -- if(Read_reg='0' and Read='1')then
160 -- ect <= st8a;
161 -- end if;
162 ---------------------------------------------------------------------------------
163 -- when st8a =>
164 -- Take <= '1';
165 -- if(Read_reg='0' and Read='1')then
166 -- ect <= st8b;
167 -- end if;
168 --
169 -- when st8b =>
170 -- Take <= '0';
171 -- if(Read_reg='0' and Read='1')then
172 -- ect <= st9a;
173 -- end if;
174 ---------------------------------------------------------------------------------
175 -- when st9a =>
176 -- Take <= '1';
177 -- if(Read_reg='0' and Read='1')then
178 -- ect <= st9b;
179 -- end if;
180 --
181 -- when st9b =>
182 -- Take <= '0';
183 -- if(Read_reg='0' and Read='1')then
184 -- ect <= st10a;
185 -- end if;
186 ---------------------------------------------------------------------------------
187 -- when st10a =>
188 -- Take <= '1';
189 -- if(Read_reg='0' and Read='1')then
190 -- ect <= st10b;
191 -- end if;
192 --
193 -- when st10b =>
194 -- Take <= '0';
195 -- if(Read_reg='0' and Read='1')then
196 -- ect <= st11a;
197 -- end if;
198 ---------------------------------------------------------------------------------
199 -- when st11a =>
200 -- Take <= '1';
201 -- if(Read_reg='0' and Read='1')then
202 -- ect <= st11b;
203 -- end if;
204 --
205 -- when st11b =>
206 -- Take <= '0';
207 -- if(Read_reg='0' and Read='1')then
208 -- ect <= st12a;
209 -- end if;
210 ---------------------------------------------------------------------------------
211 -- when st12a =>
212 -- Take <= '1';
213 -- if(Read_reg='0' and Read='1')then
214 -- ect <= st12b;
215 -- end if;
216 --
217 -- when st12b =>
218 -- Take <= '0';
219 -- if(Read_reg='0' and Read='1')then
220 -- ect <= st13a;
221 -- end if;
222 ---------------------------------------------------------------------------------
223 -- when st13a =>
224 -- Take <= '1';
225 -- if(Read_reg='0' and Read='1')then
226 -- ect <= st13b;
227 -- end if;
228 --
229 -- when st13b =>
230 -- Take <= '0';
231 -- if(Read_reg='0' and Read='1')then
232 -- ect <= st14a;
233 -- end if;
234 ---------------------------------------------------------------------------------
235 -- when st14a =>
236 -- Take <= '1';
237 -- if(Read_reg='0' and Read='1')then
238 -- ect <= st14b;
239 -- end if;
240 --
241 -- when st14b =>
242 -- Take <= '0';
243 -- if(Read_reg='0' and Read='1')then
244 -- ect <= st15a;
245 -- end if;
246 ---------------------------------------------------------------------------------
247 -- when st15a =>
248 -- Take <= '1';
249 -- if(Read_reg='0' and Read='1')then
250 -- ect <= st7_b;
251 -- end if;
252 --
253 -- when st15b =>
254 -- Take <= '0';
255 -- if(Read_reg='0' and Read='1')then
256 -- ect <= stX;
257 -- end if;
258 -------------------------------------------------------------------------------
259 end case;
112 end case;
260 end if;
113 end if;
261 end process;
114 end process;
262
115
263 with i select
116 Statu <= std_logic_vector(to_unsigned(j,4));
264 ReadFIFO <= "10000" when 1,
117
118 with j select
119 Read_int <= "10000" when 1,
265 "11000" when 2,
120 "11000" when 2,
266 "01000" when 3,
121 "01000" when 3,
267 "10100" when 4,
122 "10100" when 4,
@@ -276,41 +131,15 with i select
276 "00101" when 13,
131 "00101" when 13,
277 "00011" when 14,
132 "00011" when 14,
278 "00001" when 15,
133 "00001" when 15,
279 "00000" when others;
134 "00000" when others;
280
135
281 --with ect select
136 with ect select
282 -- ReadB2 <= Read when st1,
137 ReadFIFO <= Read_int when idl1,
283 -- Read when st2,
138 Read_int when idl2,
284 -- Read when st4,
139 "00000" when others;
285 -- Read when st7,
286 -- Read when st11,
287 -- '0' when others;
288 --
289 --with ect select
290 -- ReadB3 <= Read when st3,
291 -- Read when st4,
292 -- Read when st5,
293 -- Read when st8,
294 -- Read when st12,
295 -- '0' when others;
296 --
297 --with ect select
298 -- ReadE1 <= Read when st6,
299 -- Read when st7,
300 -- Read when st8,
301 -- Read when st9,
302 -- Read when st13,
303 -- '0' when others;
304 --
305 --with ect select
306 -- ReadE2 <= Read when st10,
307 -- Read when st11,
308 -- Read when st12,
309 -- Read when st13,
310 -- Read when st14,
311 -- '0' when others;
312
140
313 with i select
141
142 with j select
314 OP1 <= B1 when 1,
143 OP1 <= B1 when 1,
315 B1 when 2,
144 B1 when 2,
316 B1 when 4,
145 B1 when 4,
@@ -328,7 +157,8 with i select
328 E2 when 15,
157 E2 when 15,
329 X"FFFF" when others;
158 X"FFFF" when others;
330
159
331 with i select
160
161 with j select
332 OP2 <= B1 when 1,
162 OP2 <= B1 when 1,
333 B2 when 2,
163 B2 when 2,
334 B2 when 3,
164 B2 when 3,
@@ -346,14 +176,14 with i select
346 E2 when 15,
176 E2 when 15,
347 X"FFFF" when others;
177 X"FFFF" when others;
348
178
349 with i select
179
180 with j select
350 Conjugate <= '1' when 1,
181 Conjugate <= '1' when 1,
351 '1' when 3,
182 '1' when 3,
352 '1' when 6,
183 '1' when 6,
353 '1' when 10,
184 '1' when 10,
354 '1' when 15,
185 '1' when 15,
355 '0' when others;
186 '0' when others;
356
187
357
188
358 --RE_FIFO <= ReadE2 & ReadE1 & ReadB3 & ReadB2 & ReadB1;
359 end ar_SelectInputs; No newline at end of file
189 end ar_SelectInputs;
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@@ -36,8 +36,13 port(
36 B3 : in std_logic_vector(Input_SZ-1 downto 0);
36 B3 : in std_logic_vector(Input_SZ-1 downto 0);
37 E1 : in std_logic_vector(Input_SZ-1 downto 0);
37 E1 : in std_logic_vector(Input_SZ-1 downto 0);
38 E2 : in std_logic_vector(Input_SZ-1 downto 0);
38 E2 : in std_logic_vector(Input_SZ-1 downto 0);
39 Empty : in std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
40 Statu : out std_logic_vector(3 downto 0);
39 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
41 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
40 Result : out std_logic_vector(Result_SZ-1 downto 0)
42 OP11 : out std_logic_vector(Input_SZ-1 downto 0);
43 starting : out std_logic;
44 Conj : out std_logic;
45 Result : out std_logic_vector(Result_SZ-1 downto 0)
41 );
46 );
42 end SpectralMatrix;
47 end SpectralMatrix;
43
48
@@ -49,26 +54,33 signal Take : std_logic;
49 signal Received : std_logic;
54 signal Received : std_logic;
50 signal Valid : std_logic;
55 signal Valid : std_logic;
51 signal Conjugate : std_logic;
56 signal Conjugate : std_logic;
57 signal Start : std_logic;
52 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
58 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
53 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
59 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
54 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
60 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
55
61
62
56 begin
63 begin
64 OP11 <= OP1;
65 starting <= Start;
66 conj <= Conjugate;
57
67
68 ST0 : Starter
69 port map(clk,reset,Empty(4),Empty(3),Conjugate,Start);
58
70
59 IN0 : SelectInputs
71 IN0 : SelectInputs
60 generic map(Input_SZ)
72 generic map(Input_SZ)
61 port map(clk,reset,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,OP1,OP2);
73 port map(clk,Start,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,Statu,OP1,OP2);
62
74
63
75
64 CALC0 : Matrix
76 CALC0 : Matrix
65 generic map(Input_SZ)
77 generic map(Input_SZ)
66 port map(clk,reset,OP1,OP2,Take,Received,Conjugate,Valid,Read,Resultat);
78 port map(clk,Start,OP1,OP2,Take,Received,Conjugate,Valid,Read,Resultat);
67
79
68
80
69 RES0 : GetResult
81 RES0 : GetResult
70 generic map(Result_SZ)
82 generic map(Result_SZ)
71 port map(clk,reset,Valid,Conjugate,Resultat,Received,Result);
83 port map(clk,Start,Valid,Conjugate,Resultat,Received,Result);
72
84
73
85
74 end ar_SpectralMatrix; No newline at end of file
86 end ar_SpectralMatrix;
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@@ -59,7 +59,12 port(
59 B3 : in std_logic_vector(Input_SZ-1 downto 0);
59 B3 : in std_logic_vector(Input_SZ-1 downto 0);
60 E1 : in std_logic_vector(Input_SZ-1 downto 0);
60 E1 : in std_logic_vector(Input_SZ-1 downto 0);
61 E2 : in std_logic_vector(Input_SZ-1 downto 0);
61 E2 : in std_logic_vector(Input_SZ-1 downto 0);
62 Empty : in std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
63 Statu : out std_logic_vector(3 downto 0);
62 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
64 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
65 OP11 : out std_logic_vector(Input_SZ-1 downto 0);
66 starting : out std_logic;
67 Conj : out std_logic;
63 Result : out std_logic_vector(Result_SZ-1 downto 0)
68 Result : out std_logic_vector(Result_SZ-1 downto 0)
64 );
69 );
65 end component;
70 end component;
@@ -181,9 +186,22 port(
181 Conjugate : out std_logic;
186 Conjugate : out std_logic;
182 Take : out std_logic;
187 Take : out std_logic;
183 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
188 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
189 Statu : out std_logic_vector(3 downto 0);
184 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
190 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
185 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
191 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
186 );
192 );
187 end component;
193 end component;
188
194
195
196 component Starter is
197 port(
198 clk : in std_logic;
199 raz : in std_logic;
200 empty1 : in std_logic;
201 empty2 : in std_logic;
202 Conjugate : in std_logic;
203 Start : out std_logic
204 );
205 end component;
206
189 end; No newline at end of file
207 end;
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@@ -47,6 +47,7 entity APB_FifoWrite is
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 ReadEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
49 ReadEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
50 Empty : out std_logic; --! Flag, Memoire vide
50 DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire
51 DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 );
53 );
@@ -79,5 +80,6 begin
79 port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
80 port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
80
81
81 DATA <= DataOut;
82 DATA <= DataOut;
83 Empty <= FlagEmpty;
82
84
83 end ar_APB_FifoWrite; No newline at end of file
85 end ar_APB_FifoWrite;
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@@ -64,14 +64,13 begin
64
64
65 if(flag_reg ='0' and flag_RE='1')then
65 if(flag_reg ='0' and flag_RE='1')then
66 if(Rad_int=addr_max_int-1)then
66 if(Rad_int=addr_max_int-1)then
67 Rad_int <= 0;
67 Rad_int <= 0;
68 else
68 else
69 Rad_int <= Rad_int+1;
69 Rad_int <= Rad_int+1;
70 end if;
70 end if;
71 end if;
71 end if;
72
72
73 if(ReUse='1')then
73 if(ReUse='1')then
74 Rad_int <= 0;
75 empty <= '0';
74 empty <= '0';
76 else
75 else
77 if(Rad_int_reg /= Rad_int)then
76 if(Rad_int_reg /= Rad_int)then
@@ -82,7 +81,7 begin
82 end if;
81 end if;
83 elsif(Wad_int_reg /= Wad_int)then
82 elsif(Wad_int_reg /= Wad_int)then
84 empty <= '0';
83 empty <= '0';
85 end if;
84 end if;
86 end if;
85 end if;
87
86
88 end if;
87 end if;
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@@ -40,6 +40,7 entity Top_FIFO is
40 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
40 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
41 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
41 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
42 ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but
42 ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but
43 Lock : in std_logic; --! Permet de bloquer l'�criture dans la m�moire
43 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
44 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
44 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
45 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
45 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
46 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
@@ -69,9 +70,10 end component;
69
70
70 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
71 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
71 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
72 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
72 signal Data_int : std_logic_vector(Data_sz-1 downto 0);
73 --signal Data_int : std_logic_vector(Data_sz-1 downto 0);
73 signal s_empty : std_logic;
74 signal s_empty : std_logic;
74 signal s_full : std_logic;
75 signal s_full : std_logic;
76 signal s_full2 : std_logic;
75 signal s_flag_RE : std_logic;
77 signal s_flag_RE : std_logic;
76 signal s_flag_WR : std_logic;
78 signal s_flag_WR : std_logic;
77
79
@@ -84,12 +86,13 begin
84
86
85 SRAM : syncram_2p
87 SRAM : syncram_2p
86 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
88 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
87 port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in);
89 port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in);
88
90
89
91
90 link : Link_Reg
92 -- link : Link_Reg
91 generic map(Data_sz)
93 -- generic map(Data_sz)
92 port map(clk,raz,Data_in,Data_int,ReUse,s_flag_RE,s_flag_WR,s_empty,Data_out);
94 -- port map(clk,raz,Data_in,Data_int,ReUse,s_flag_RE,s_flag_WR,s_empty,Data_out);
95
93
96
94 RE : Fifo_Read
97 RE : Fifo_Read
95 generic map(Addr_sz,addr_max_int)
98 generic map(Addr_sz,addr_max_int)
@@ -100,10 +103,11 begin
100 if(raz='0')then
103 if(raz='0')then
101 s_flag_RE <= '0';
104 s_flag_RE <= '0';
102 s_flag_WR <= '0';
105 s_flag_WR <= '0';
106 s_full2 <= s_full;
103
107
104 elsif(clk'event and clk='1')then
108 elsif(clk'event and clk='1')then
105 if(s_full='0')then
109 if(s_full2='0')then
106 s_flag_WR <= Flag_WR;
110 s_flag_WR <= Flag_WR;
107 else
111 else
108 s_flag_WR <= '0';
112 s_flag_WR <= '0';
109 end if;
113 end if;
@@ -113,11 +117,17 begin
113 else
117 else
114 s_flag_RE <= '0';
118 s_flag_RE <= '0';
115 end if;
119 end if;
116
120
121 if(Lock='1')then
122 s_full2 <= '1';
123 else
124 s_full2 <= s_full;
125 end if;
126
117 end if;
127 end if;
118 end process;
128 end process;
119
129
120 full <= s_full;
130 full <= s_full2;
121 empty <= s_empty;
131 empty <= s_empty;
122 Addr_RE <= Raddr;
132 Addr_RE <= Raddr;
123 Addr_WR <= Waddr;
133 Addr_WR <= Waddr;
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@@ -170,6 +170,7 component APB_FifoWrite is
170 rst : in std_logic;
170 rst : in std_logic;
171 apbi : in apb_slv_in_type;
171 apbi : in apb_slv_in_type;
172 ReadEnable : in std_logic;
172 ReadEnable : in std_logic;
173 Empty : out std_logic;
173 DATA : out std_logic_vector(Data_sz-1 downto 0);
174 DATA : out std_logic_vector(Data_sz-1 downto 0);
174 apbo : out apb_slv_out_type
175 apbo : out apb_slv_out_type
175 );
176 );
@@ -213,7 +214,7 component APB_FifoRead is
213 clk : in std_logic;
214 clk : in std_logic;
214 rst : in std_logic;
215 rst : in std_logic;
215 apbi : in apb_slv_in_type;
216 apbi : in apb_slv_in_type;
216 WriteEnable : in std_logic;
217 WriteEnable : in std_logic;
217 DATA : out std_logic_vector(Data_sz-1 downto 0);
218 DATA : out std_logic_vector(Data_sz-1 downto 0);
218 apbo : out apb_slv_out_type
219 apbo : out apb_slv_out_type
219 );
220 );
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@@ -1,1 +1,1
1 touch test11
1 touch test1
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