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APB interface modified (FIFO,FFT)
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fft.all;
32 use work.fft_components.all;
33
34 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
35
36 entity APB_FFT is
37 generic (
38 pindex : integer := 0;
39 paddr : integer := 0;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
42 abits : integer := 8;
43 Data_sz : integer := 16;
44 Addr_sz : integer := 8;
45 addr_max_int : integer := 256);
46 port (
47 clk : in std_logic; --! Horloge du composant
48 rst : in std_logic; --! Reset general du composant
49 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
50 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
51 );
52 end APB_FFT;
53
54
55 architecture ar_APB_FFT of APB_FFT is
56
57 signal ReadEnable : std_logic;
58 signal WriteEnable : std_logic;
59 signal FlagEmpty : std_logic;
60 signal FlagFull : std_logic;
61 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
62 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
63 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
64 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
65
66 signal X,Y,Z : std_logic;
67 --signal Pong : std_logic;
68 --signal Valid : std_logic;
69 signal DummyIn : std_logic_vector(Data_sz-1 downto 0);
70 --signal DummyOut : std_logic_vector(Data_sz-1 downto 0);
71
72 begin
73
74 APB : entity work.ApbDriver
75 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
76 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77
78
79 DEVICE : entity work.CoreFFT
80 generic map(
81 LOGPTS => gLOGPTS,
82 LOGLOGPTS => gLOGLOGPTS,
83 WSIZE => gWSIZE,
84 TWIDTH => gTWIDTH,
85 DWIDTH => gDWIDTH,
86 TDWIDTH => gTDWIDTH,
87 RND_MODE => gRND_MODE,
88 SCALE_MODE => gSCALE_MODE,
89 PTS => gPTS,
90 HALFPTS => gHALFPTS,
91 inBuf_RWDLY => gInBuf_RWDLY)
92 port map(clk,X,rst,WriteEnable,ReadEnable,DummyIn,DataIn,Y,open,open,DataOut,open,Z);
93
94 X <= not rst;
95 Y <= not FlagFull;
96 Z <= not FlagEmpty;
97 DummyIn <= (others => '0');
98
99 end ar_APB_FFT; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29 use lpp.lpp_memory.all;
30 use work.fft_components.all;
31
32
33 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
34
35 package lpp_fft is
36
37 component APB_FFT is
38 generic (
39 pindex : integer := 0;
40 paddr : integer := 0;
41 pmask : integer := 16#fff#;
42 pirq : integer := 0;
43 abits : integer := 8;
44 Data_sz : integer := 16;
45 Addr_sz : integer := 8;
46 addr_max_int : integer := 256);
47 port (
48 clk : in std_logic;
49 rst : in std_logic;
50 apbi : in apb_slv_in_type;
51 apbo : out apb_slv_out_type
52 );
53 end component;
54
55
56 component CoreFFT IS
57 GENERIC (
58 LOGPTS : integer := gLOGPTS;
59 LOGLOGPTS : integer := gLOGLOGPTS;
60 WSIZE : integer := gWSIZE;
61 TWIDTH : integer := gTWIDTH;
62 DWIDTH : integer := gDWIDTH;
63 TDWIDTH : integer := gTDWIDTH;
64 RND_MODE : integer := gRND_MODE;
65 SCALE_MODE : integer := gSCALE_MODE;
66 PTS : integer := gPTS;
67 HALFPTS : integer := gHALFPTS;
68 inBuf_RWDLY : integer := gInBuf_RWDLY );
69 PORT (
70 clk,ifiStart,ifiNreset : IN std_logic;
71 ifiD_valid, ifiRead_y : IN std_logic;
72 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
73 ifoLoad, ifoPong : OUT std_logic;
74 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
75 ifoY_valid, ifoY_rdy : OUT std_logic);
76 END component;
77
78
79 component actar is
80 port( DataA : in std_logic_vector(15 downto 0); DataB : in
81 std_logic_vector(15 downto 0); Mult : out
82 std_logic_vector(31 downto 0);Clock : in std_logic) ;
83 end component;
84
85 component actram is
86 port( DI : in std_logic_vector(31 downto 0); DO : out
87 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
88 WADDR : in std_logic_vector(6 downto 0); RADDR : in
89 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
90 std_logic) ;
91 end component;
92
93 component switch IS
94 GENERIC ( DWIDTH : integer := 32 );
95 PORT (
96 clk, sel, validIn : IN std_logic;
97 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
98 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
99 validOut : OUT std_logic);
100 END component;
101
102 component twid_rA IS
103 GENERIC (LOGPTS : integer := 8;
104 LOGLOGPTS : integer := 3 );
105 PORT (clk : IN std_logic;
106 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
107 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
108 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
109 END component;
110
111 component counter IS
112 GENERIC (
113 WIDTH : integer := 7;
114 TERMCOUNT : integer := 127 );
115 PORT (
116 clk, nGrst, rst, cntEn : IN std_logic;
117 tc : OUT std_logic;
118 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
119 END component;
120
121
122 component twiddle IS
123 PORT (
124 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
125 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
126 END component;
127
128
129 end; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
35 entity APB_FIFO is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
45 port (
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
50 );
51 end APB_FIFO;
52
53
54 architecture ar_APB_FIFO of APB_FIFO is
55
56 signal ReadEnable : std_logic;
57 signal WriteEnable : std_logic;
58 signal FlagEmpty : std_logic;
59 signal FlagFull : std_logic;
60 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
61 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
62 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
63 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
64
65 begin
66
67 APB : entity work.ApbDriver
68 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
69 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
70
71
72 DEVICE : entity work.Top_FIFO
73 generic map(Data_sz,Addr_sz,addr_max_int)
74 port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
75
76
77 end ar_APB_FIFO; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
35 entity APB_FifoRead is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
45 port (
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 Flag_WR : in std_logic; --! Demande l'�criture dans la m�moire, g�r� hors de l'IP
50 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 );
53 end APB_FifoRead;
54
55
56 architecture ar_APB_FifoRead of APB_FifoRead is
57
58 constant REVISION : integer := 1;
59
60 constant pconfig : apb_config_type := (
61 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0),
62 1 => apb_iobar(paddr, pmask));
63
64 type FIFO_ctrlr_Reg is record
65 FIFO_Cfg : std_logic_vector(1 downto 0);
66 FIFO_DataW : std_logic_vector(15 downto 0);
67 FIFO_DataR : std_logic_vector(15 downto 0);
68 FIFO_AddrR : std_logic_vector(7 downto 0);
69 end record;
70
71 signal Rec : FIFO_ctrlr_Reg;
72 signal Rdata : std_logic_vector(31 downto 0);
73
74 signal flag_RE : std_logic;
75 signal empty : std_logic;
76
77 begin
78
79 Rec.FIFO_Cfg(0) <= flag_RE;
80 Rec.FIFO_Cfg(2) <= empty;
81
82
83 MEMORY_READ : entity Work.Top_FifoRead
84 generic map(Data_sz,Addr_sz,addr_max_int)
85 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,Rec.FIFO_AddrR,full,Waddr,Rec.FIFO_DataR);
86
87
88 process(rst,clk)
89 begin
90 if(rst='0')then
91 Rec.FIFO_AddrR <= (others => '0');
92
93 elsif(clk'event and clk='1')then
94
95 --APB Write OP
96 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
97 case apbi.paddr(abits-1 downto 2) is
98 when others =>
99 null;
100 end case;
101 end if;
102
103 --APB Read OP
104 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
105 case apbi.paddr(abits-1 downto 2) is
106 when "000000" =>
107 Rdata(31 downto 16) <= X"DDDD";
108 Rdata(15 downto 0) <= Rec.FIFO_DataR;
109 when "000001" =>
110 Rdata(31 downto 8) <= X"AAAAAA";
111 Rdata(7 downto 0) <= Rec.FIFO_AddrR;
112 when "000010" =>
113 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
114 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
115 Rdata(31 downto 8) <= X"CCCCCC";
116 when others =>
117 Rdata <= (others => '0');
118 end case;
119 end if;
120
121 end if;
122 apbo.pconfig <= pconfig;
123 end process;
124
125 apbo.prdata <= Rdata when apbi.penable = '1';
126
127 end ar_APB_FifoReade; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
35 entity APB_FifoWrite is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
45 port (
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 Flag_RE : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
50 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture dans la m�moire
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 );
53 end APB_FifoWrite;
54
55
56 architecture ar_APB_FifoWrite of APB_FifoWrite is
57
58 constant REVISION : integer := 1;
59
60 constant pconfig : apb_config_type := (
61 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0),
62 1 => apb_iobar(paddr, pmask));
63
64 type FIFO_ctrlr_Reg is record
65 FIFO_Cfg : std_logic_vector(1 downto 0);
66 FIFO_DataW : std_logic_vector(15 downto 0);
67 FIFO_DataR : std_logic_vector(15 downto 0);
68 FIFO_AddrW : std_logic_vector(7 downto 0);
69 end record;
70
71 signal Rec : FIFO_ctrlr_Reg;
72 signal Rdata : std_logic_vector(31 downto 0);
73
74 signal flag_WR : std_logic;
75 signal full : std_logic;
76
77 begin
78
79 Rec.FIFO_Cfg(0) <= flag_WR;
80 Rec.FIFO_Cfg(1) <= full;
81
82 MEMORY_WRITE : entity Work.Top_FifoWrite
83 generic map(Data_sz,Addr_sz,addr_max_int)
84 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,Raddr,full,Rec.FIFO_AddrW,Rec.FIFO_DataR);
85
86
87 process(rst,clk)
88 begin
89 if(rst='0')then
90 Rec.FIFO_DataW <= (others => '0');
91
92 elsif(clk'event and clk='1')then
93
94 --APB Write OP
95 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
96 case apbi.paddr(abits-1 downto 2) is
97 when "000000" =>
98 flag_WR <= '1';
99 Rec.FIFO_DataW <= apbi.pwdata(15 downto 0);
100 when others =>
101 null;
102 end case;
103 else
104 flag_WR <= '0';
105 end if;
106
107 --APB Read OP
108 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
109 case apbi.paddr(abits-1 downto 2) is
110 when "000000" =>
111 Rdata(31 downto 16) <= X"DDDD";
112 Rdata(15 downto 0) <= Rec.FIFO_DataR;
113 when "000001" =>
114 Rdata(31 downto 8) <= X"AAAAAA";
115 Rdata(7 downto 0) <= Rec.FIFO_AddrW;
116 when "000010" =>
117 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
118 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
119 Rdata(31 downto 8) <= X"CCCCCC";
120 when others =>
121 Rdata <= (others => '0');
122 end case;
123 end if;
124
125 end if;
126 apbo.pconfig <= pconfig;
127 end process;
128
129 apbo.prdata <= Rdata when apbi.penable = '1';
130
131 end ar_APB_FifoWrite; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31
32
33 entity ApbDriver is
34 generic (
35 pindex : integer := 0;
36 paddr : integer := 0;
37 pmask : integer := 16#fff#;
38 pirq : integer := 0;
39 abits : integer := 8;
40 LPP_DEVICE : integer;
41 Data_sz : integer := 16;
42 Addr_sz : integer := 8;
43 addr_max_int : integer := 256);
44 port (
45 clk : in std_logic; --! Horloge du composant
46 rst : in std_logic; --! Reset general du composant
47 ReadEnable : out std_logic;
48 WriteEnable : out std_logic;
49 FlagEmpty : in std_logic;
50 FlagFull : in std_logic;
51 DataIn : out std_logic_vector(Data_sz-1 downto 0);
52 DataOut : in std_logic_vector(Data_sz-1 downto 0);
53 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
54 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
55 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
56 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
57 );
58 end ApbDriver;
59
60
61 architecture ar_ApbDriver of ApbDriver is
62
63 constant REVISION : integer := 1;
64
65 constant pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
68
69 type DEVICE_ctrlr_Reg is record
70 DEVICE_Cfg : std_logic_vector(3 downto 0);
71 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
72 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
73 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
74 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
75 end record;
76
77 signal Rec : DEVICE_ctrlr_Reg;
78 signal Rdata : std_logic_vector(31 downto 0);
79
80 signal FlagRE : std_logic;
81 signal FlagWR : std_logic;
82 begin
83
84 Rec.DEVICE_Cfg(0) <= FlagRE;
85 Rec.DEVICE_Cfg(1) <= FlagWR;
86 Rec.DEVICE_Cfg(2) <= FlagEmpty;
87 Rec.DEVICE_Cfg(3) <= FlagFull;
88
89 DataIn <= Rec.DEVICE_DataW;
90 Rec.DEVICE_DataR <= DataOut;
91 Rec.DEVICE_AddrW <= AddrIn;
92 Rec.DEVICE_AddrR <= AddrOut;
93
94
95
96 process(rst,clk)
97 begin
98 if(rst='0')then
99 Rec.DEVICE_DataW <= (others => '0');
100 FlagWR <= '0';
101 FlagRE <= '0';
102
103 elsif(clk'event and clk='1')then
104
105 --APB Write OP
106 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
107 case apbi.paddr(abits-1 downto 2) is
108 when "000000" =>
109 FlagWR <= '1';
110 Rec.DEVICE_DataW <= apbi.pwdata(15 downto 0);
111 when others =>
112 null;
113 end case;
114 else
115 FlagWR <= '0';
116 end if;
117
118 --APB Read OP
119 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
120 case apbi.paddr(abits-1 downto 2) is
121 when "000000" =>
122 FlagRE <= '1';
123 Rdata(31 downto 16) <= X"DDDD";
124 Rdata(15 downto 0) <= Rec.DEVICE_DataR;
125 when "000001" =>
126 Rdata(31 downto 8) <= X"AAAAAA";
127 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
128 when "000101" =>
129 Rdata(31 downto 8) <= X"AAAAAA";
130 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
131 when "000010" =>
132 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
133 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
134 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
135 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
136 Rdata(31 downto 16) <= X"CCCC";
137 when others =>
138 Rdata <= (others => '0');
139 end case;
140 else
141 FlagRE <= '0';
142 end if;
143
144 end if;
145 apbo.pconfig <= pconfig;
146 end process;
147
148 apbo.prdata <= Rdata when apbi.penable = '1';
149 WriteEnable <= FlagWR;
150 ReadEnable <= FlagRE;
151
152 end ar_ApbDriver; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 --! Programme de la FIFO de lecture
27
28 entity Fifo_Read is
29 generic(
30 Addr_sz : integer := 8;
31 addr_max_int : integer := 256);
32 port(
33 clk,raz : in std_logic; --! Horloge et reset general du composant
34 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
35 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
36 empty : out std_logic; --! Flag, M�moire vide
37 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la m�moire
38 );
39 end Fifo_Read;
40
41 --! @details En aval de la SRAM Gaisler
42
43 architecture ar_Fifo_Read of Fifo_Read is
44
45 signal Rad_int : integer range 0 to addr_max_int;
46 signal Rad_int_reg : integer range 0 to addr_max_int;
47 signal Wad_int : integer range 0 to addr_max_int;
48 signal Wad_int_reg : integer range 0 to addr_max_int;
49 signal flag_reg : std_logic;
50
51 begin
52 process (clk,raz)
53 begin
54 if(raz='0')then
55 Rad_int <= 0;
56 empty <= '1';
57
58 elsif(clk' event and clk='1')then
59 Wad_int_reg <= Wad_int;
60 Rad_int_reg <= Rad_int;
61 flag_reg <= flag_RE;
62
63 if(flag_reg ='0' and flag_RE='1')then
64 if(Rad_int=addr_max_int-1)then
65 Rad_int <= 0;
66 else
67 Rad_int <= Rad_int+1;
68 end if;
69 end if;
70
71 if(Rad_int_reg /= Rad_int)then
72 if(Rad_int=Wad_int)then
73 empty <= '1';
74 else
75 empty <= '0';
76 end if;
77 elsif(Wad_int_reg /= Wad_int)then
78 empty <= '0';
79 end if;
80 end if;
81 end process;
82
83 Wad_int <= to_integer(unsigned(Waddr));
84 Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz));
85
86 end ar_Fifo_Read; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 --! Programme de la FIFO d'�criture
27
28 entity Fifo_Write is
29 generic(
30 Addr_sz : integer := 8;
31 addr_max_int : integer := 256);
32 port(
33 clk,raz : in std_logic; --! Horloge et reset general du composant
34 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
35 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la m�moire
36 full : out std_logic; --! Flag, M�moire pleine
37 Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'�criture dans la m�moire
38 );
39 end Fifo_Write;
40
41 --! @details En amont de la SRAM Gaisler
42
43 architecture ar_Fifo_Write of Fifo_Write is
44
45 signal Wad_int : integer range 0 to addr_max_int;
46 signal Wad_int_reg : integer range 0 to addr_max_int;
47 signal Rad_int : integer range 0 to addr_max_int;
48 signal Rad_int_reg : integer range 0 to addr_max_int;
49
50 begin
51 process (clk,raz)
52 begin
53 if(raz='0')then
54 Wad_int <= 0;
55 full <= '0';
56
57 elsif(clk' event and clk='1')then
58 Wad_int_reg <= Wad_int;
59 Rad_int_reg <= Rad_int;
60
61
62 if(flag_WR='1')then
63 if(Wad_int=addr_max_int-1)then
64 Wad_int <= 0;
65 else
66 Wad_int <= Wad_int+1;
67 end if;
68 end if;
69
70 if(Wad_int_reg /= Wad_int)then
71 if(Wad_int=Rad_int)then
72 full <= '1';
73 else
74 full <= '0';
75 end if;
76 elsif(Rad_int_reg /= Rad_int)then
77 full <= '0';
78 end if;
79
80 end if;
81 end process;
82
83 Rad_int <= to_integer(unsigned(Raddr));
84 Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz));
85
86 end ar_Fifo_Write; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FIFO_Config.all;
26
27 --! Programme qui va permettre de "pipeliner" la FIFO, donn�e disponible en sortie d� son �criture en entr�e de la FIFO
28
29 entity Link_Reg is
30 generic(Data_sz : integer := 16);
31 port(
32 clk,raz : in std_logic; --! Horloge et reset general du composant
33 Data_one : in std_logic_vector(Data_sz-1 downto 0); --! Donn�e en entr�e de la FIFO, cot� �criture
34 Data_two : in std_logic_vector(Data_sz-1 downto 0); --! Donn�e en sortie de la FIFO, cot� lecture
35 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
36 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
37 empty : in std_logic; --! Flag, M�moire vide
38 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Donn�e en sortie, pipelin�e
39 );
40 end Link_Reg;
41
42 architecture ar_Link_Reg of Link_Reg is
43
44 type etat is (e0,e1,e2,e3);
45 signal ect : etat;
46
47 begin
48 process (clk,raz)
49 begin
50 if(raz='0')then
51 Data_out <= (others => 'X');
52 ect <= e0;
53
54 elsif(clk' event and clk='1')then
55 case ect is
56 when e0 =>
57 if(flag_WR='1')then
58 Data_out <= Data_one;
59 ect <= e1;
60 end if;
61
62 when e1 =>
63 if(flag_RE='1')then
64 Data_out <= Data_two;
65 ect <= e2;
66 end if;
67
68 when e2 =>
69 if(empty='1')then
70 ect <= e3;
71 else
72 Data_out <= Data_two;
73 ect <= e2;
74 end if;
75
76 when e3 =>
77 Data_out <= Data_two;
78 ect <= e0;
79
80 end case;
81 end if;
82 end process;
83
84 end ar_Link_Reg;
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library techmap;
26 use techmap.gencomp.all;
27 use work.config.all;
28
29 --! Programme de la FIFO
30
31 entity Top_FIFO is
32 generic(
33 Data_sz : integer := 16;
34 Addr_sz : integer := 8;
35 addr_max_int : integer := 256
36 );
37 port(
38 clk,raz : in std_logic; --! Horloge et reset general du composant
39 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
40 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
41 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
42 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
43 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
44 full : out std_logic; --! Flag, M�moire pleine
45 empty : out std_logic; --! Flag, M�moire vide
46 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
47 );
48 end Top_FIFO;
49
50 --! @details Une m�moire SRAM de chez Gaisler est utilis�e,
51 --! associ�e a deux Drivers, un pour �crire l'autre pour lire cette m�moire
52
53 architecture ar_Top_FIFO of Top_FIFO is
54
55 component syncram_2p
56 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
57 port (
58 rclk : in std_ulogic;
59 renable : in std_ulogic;
60 raddress : in std_logic_vector((abits -1) downto 0);
61 dataout : out std_logic_vector((dbits -1) downto 0);
62 wclk : in std_ulogic;
63 write : in std_ulogic;
64 waddress : in std_logic_vector((abits -1) downto 0);
65 datain : in std_logic_vector((dbits -1) downto 0));
66 end component;
67
68 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
69 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
70 signal Data_int : std_logic_vector(Data_sz-1 downto 0);
71 signal s_empty : std_logic;
72 signal s_full : std_logic;
73 signal s_flag_RE : std_logic;
74 signal s_flag_WR : std_logic;
75
76 begin
77
78 WR : entity work.Fifo_Write
79 generic map(Addr_sz,addr_max_int)
80 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr);
81
82
83 SRAM : syncram_2p
84 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
85 port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in);
86
87
88 link : entity work.Link_Reg
89 generic map(Data_sz)
90 port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
91
92 RE : entity work.Fifo_Read
93 generic map(Addr_sz,addr_max_int)
94 port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr);
95
96 process(clk,raz)
97 begin
98 if(raz='0')then
99 s_flag_RE <= '0';
100 s_flag_WR <= '0';
101
102 elsif(clk'event and clk='1')then
103 if(s_full='0')then
104 s_flag_WR <= Flag_WR;
105 else
106 s_flag_WR <= '0';
107 end if;
108
109 if(s_empty='0')then
110 s_flag_RE <= Flag_RE;
111 else
112 s_flag_RE <= '0';
113 end if;
114
115 end if;
116 end process;
117
118 full <= s_full;
119 empty <= s_empty;
120 Addr_RE <= Raddr;
121 Addr_WR <= Waddr;
122
123 end ar_Top_FIFO; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library techmap;
26 use techmap.gencomp.all;
27 use work.config.all;
28
29 --! Programme de la FIFO
30
31 entity Top_FifoRead is
32 generic(
33 Data_sz : integer := 16;
34 Addr_sz : integer := 8;
35 addr_max_int : integer := 256);
36 port(
37 clk,raz : in std_logic; --! Horloge et reset general du composant
38 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
39 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
40 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
41 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
42 full : out std_logic; --! Flag, M�moire pleine
43 empty : out std_logic; --! Flag, M�moire vide
44 Raddr : out std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la m�moire
45 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
46 );
47 end Top_FifoRead;
48
49 --! @details Une m�moire SRAM de chez Gaisler est utilis�e,
50 --! associ�e a une fifo, utilis� pour la lecture
51
52 architecture ar_Top_FifoRead of Top_FifoRead is
53
54 component syncram_2p
55 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
56 port (
57 rclk : in std_ulogic;
58 renable : in std_ulogic;
59 raddress : in std_logic_vector((abits -1) downto 0);
60 dataout : out std_logic_vector((dbits -1) downto 0);
61 wclk : in std_ulogic;
62 write : in std_ulogic;
63 waddress : in std_logic_vector((abits -1) downto 0);
64 datain : in std_logic_vector((dbits -1) downto 0));
65 end component;
66
67 signal Raddr_int : std_logic_vector(addr_sz-1 downto 0);
68 signal s_flag_RE : std_logic;
69 signal s_empty : std_logic;
70
71 begin
72
73 SRAM : syncram_2p
74 generic map(CFG_MEMTECH,addr_sz,Data_sz)
75 port map(clk,s_flag_RE,Waddr,Data_int,clk,flag_WR,Raddr_int,Data_in);
76
77
78 RE : entity work.Fifo_Read
79 generic map(Addr_sz,addr_max_int)
80 port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr_int);
81
82 link : entity work.Link_Reg
83 generic map(Data_sz)
84 port map(clk,raz,Data_in,Data_int,s_flag_RE,flag_WR,s_empty,Data_out);
85
86 process(clk,raz)
87 begin
88 if(raz='0')then
89 s_flag_RE <= '0';
90
91 elsif(clk'event and clk='1')then
92 if(s_empty='0')then
93 s_flag_RE <= Flag_RE;
94 else
95 s_flag_RE <= '0';
96 end if;
97
98 end if;
99 end process;
100
101 empty <= s_empty;
102 Raddr <= Raddr_int;
103
104 end ar_Top_FifoRead; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library techmap;
26 use techmap.gencomp.all;
27 use work.config.all;
28
29 --! Programme de la FIFO
30
31 entity Top_FifoWrite is
32 generic(
33 Data_sz : integer := 16;
34 Addr_sz : integer := 8;
35 addr_max_int : integer := 256);
36 port(
37 clk,raz : in std_logic; --! Horloge et reset general du composant
38 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
39 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
40 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
41 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
42 full : out std_logic; --! Flag, M�moire pleine
43 Waddr : out std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la m�moire
44 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
45 );
46 end Top_FifoWrite;
47
48 --! @details Une m�moire SRAM de chez Gaisler est utilis�e,
49 --! associ�e a un Driver, utilis�e pour �crire dans celle-ci
50
51 architecture ar_Top_FifoWrite of Top_FifoWrite is
52
53 component syncram_2p
54 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
55 port (
56 rclk : in std_ulogic;
57 renable : in std_ulogic;
58 raddress : in std_logic_vector((abits -1) downto 0);
59 dataout : out std_logic_vector((dbits -1) downto 0);
60 wclk : in std_ulogic;
61 write : in std_ulogic;
62 waddress : in std_logic_vector((abits -1) downto 0);
63 datain : in std_logic_vector((dbits -1) downto 0));
64 end component;
65
66 signal Waddr_int : std_logic_vector(addr_sz-1 downto 0);
67 signal s_flag_WR : std_logic;
68 signal s_full : std_logic;
69
70 begin
71
72
73 WR : entity work.Fifo_Write
74 generic map(Addr_sz,addr_max_int)
75 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr_int);
76
77
78 SRAM : syncram_2p
79 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
80 port map(clk,flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr_int,Data_in);
81
82
83 process(clk,raz)
84 begin
85 if(raz='0')then
86 s_flag_WR <= '0';
87
88 elsif(clk'event and clk='1')then
89 if(s_full='0')then
90 s_flag_WR <= Flag_WR;
91 else
92 s_flag_WR <= '0';
93 end if;
94
95 end if;
96 end process;
97
98 Waddr <= Waddr_int;
99 full <= s_full;
100
101 end ar_Top_FifoWrite; No newline at end of file
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@@ -0,0 +1,233
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29
30
31 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
32
33 package lpp_memory is
34
35 --===========================================================|
36 --================= FIFOW SRAM FIFOR ========================|
37 --===========================================================|
38
39 component APB_FIFO is
40 generic (
41 pindex : integer := 0;
42 paddr : integer := 0;
43 pmask : integer := 16#fff#;
44 pirq : integer := 0;
45 abits : integer := 8;
46 Data_sz : integer := 16;
47 Addr_sz : integer := 8;
48 addr_max_int : integer := 256);
49 port (
50 clk : in std_logic;
51 rst : in std_logic;
52 apbi : in apb_slv_in_type;
53 apbo : out apb_slv_out_type
54 );
55 end component;
56
57
58 component ApbDriver is
59 generic (
60 pindex : integer := 0;
61 paddr : integer := 0;
62 pmask : integer := 16#fff#;
63 pirq : integer := 0;
64 abits : integer := 8;
65 LPP_DEVICE : integer;
66 Data_sz : integer := 16;
67 Addr_sz : integer := 8;
68 addr_max_int : integer := 256);
69 port (
70 clk : in std_logic;
71 rst : in std_logic;
72 ReadEnable : in std_logic;
73 WriteEnable : in std_logic;
74 FlagEmpty : in std_logic;
75 FlagFull : in std_logic;
76 DataIn : out std_logic_vector(Data_sz-1 downto 0);
77 DataOut : in std_logic_vector(Data_sz-1 downto 0);
78 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
79 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
80 apbi : in apb_slv_in_type;
81 apbo : out apb_slv_out_type
82 );
83 end component;
84
85
86 component Top_FIFO is
87 generic(
88 Addr_sz : integer := 8;
89 Data_sz : integer := 16;
90 addr_max_int : integer := 256);
91 port(
92 clk : in std_logic;
93 raz : in std_logic;
94 Send_RE : in std_logic;
95 Send_WR : in std_logic;
96 Data_in : in std_logic_vector(Data_sz-1 downto 0);
97 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
98 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
99 full : out std_logic;
100 empty : out std_logic;
101 Data_out : out std_logic_vector(Data_sz-1 downto 0)
102 );
103 end component;
104
105
106 component Fifo_Read is
107 generic(
108 Addr_sz : integer := 8;
109 addr_max_int : integer := 256);
110 port(
111 clk : in std_logic;
112 raz : in std_logic;
113 flag_RE : in std_logic;
114 Waddr : in std_logic_vector(addr_sz-1 downto 0);
115 empty : out std_logic;
116 Raddr : out std_logic_vector(addr_sz-1 downto 0)
117 );
118 end component;
119
120
121 component Fifo_Write is
122 generic(
123 Addr_sz : integer := 8;
124 addr_max_int : integer := 256);
125 port(
126 clk : in std_logic;
127 raz : in std_logic;
128 flag_WR : in std_logic;
129 Raddr : in std_logic_vector(addr_sz-1 downto 0);
130 full : out std_logic;
131 Waddr : out std_logic_vector(addr_sz-1 downto 0)
132 );
133 end component;
134
135
136 component Link_Reg is
137 generic(Data_sz : integer := 16);
138 port(
139 clk,raz : in std_logic;
140 Data_one : in std_logic_vector(Data_sz-1 downto 0);
141 Data_two : in std_logic_vector(Data_sz-1 downto 0);
142 flag_RE : in std_logic;
143 flag_WR : in std_logic;
144 empty : in std_logic;
145 Data_out : out std_logic_vector(Data_sz-1 downto 0)
146 );
147 end component;
148
149 --===========================================================|
150 --===================== FIFOW SRAM ==========================|
151 --===========================================================|
152
153 component APB_FifoWrite is
154 generic (
155 pindex : integer := 0;
156 paddr : integer := 0;
157 pmask : integer := 16#fff#;
158 pirq : integer := 0;
159 abits : integer := 8;
160 Data_sz : integer := 16;
161 Addr_sz : integer := 8;
162 addr_max_int : integer := 256);
163 port (
164 clk : in std_logic;
165 rst : in std_logic;
166 apbi : in apb_slv_in_type;
167 apbo : out apb_slv_out_type
168 );
169 end component;
170
171
172 component Top_FifoWrite is
173 generic(
174 Data_sz : integer := 16;
175 Addr_sz : integer := 8;
176 addr_max_int : integer := 256);
177 port(
178 clk : in std_logic;
179 raz : in std_logic;
180 flag_RE : in std_logic;
181 flag_WR : in std_logic;
182 Data_in : in std_logic_vector(Data_sz-1 downto 0);
183 Raddr : in std_logic_vector(addr_sz-1 downto 0);
184 full : out std_logic;
185 empty : out std_logic;
186 Waddr : out std_logic_vector(addr_sz-1 downto 0);
187 Data_out : out std_logic_vector(Data_sz-1 downto 0)
188 );
189 end component;
190
191 --===========================================================|
192 --===================== SRAM FIFOR ==========================|
193 --===========================================================|
194
195 component APB_FifoRead is
196 generic (
197 pindex : integer := 0;
198 paddr : integer := 0;
199 pmask : integer := 16#fff#;
200 pirq : integer := 0;
201 abits : integer := 8;
202 Data_sz : integer := 16;
203 Addr_sz : integer := 8;
204 addr_max_int : integer := 256);
205 port (
206 clk : in std_logic;
207 rst : in std_logic;
208 apbi : in apb_slv_in_type;
209 apbo : out apb_slv_out_type
210 );
211 end component;
212
213
214 component Top_FifoRead is
215 generic(
216 Data_sz : integer := 16;
217 Addr_sz : integer := 8;
218 addr_max_int : integer := 256);
219 port(
220 clk : in std_logic;
221 raz : in std_logic;
222 flag_RE : in std_logic;
223 flag_WR : in std_logic;
224 Data_in : in std_logic_vector(Data_sz-1 downto 0);
225 Waddr : in std_logic_vector(addr_sz-1 downto 0);
226 full : out std_logic;
227 empty : out std_logic;
228 Raddr : out std_logic_vector(addr_sz-1 downto 0);
229 Data_out : out std_logic_vector(Data_sz-1 downto 0)
230 );
231 end component;
232
233 end;
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@@ -28,5 +28,11 syntax: glob
28 *~
28 *~
29 apb_devices_list.h
29 apb_devices_list.h
30 apb_devices_list.vhd
30 apb_devices_list.vhd
31
31 twiddle.vhd
32
32 primitives.vhd
33 fftSm.vhd
34 fftDp.vhd
35 fft_components.vhd
36 CoreFFT.vhd
37 actram.vhd
38 actar.vhd No newline at end of file
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