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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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USE work.fft_components.all;
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entity Top_FFT is
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port(
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clk,raz : in std_logic;
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data : in std_logic_vector(15 downto 0);
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y_valid : out std_logic;
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d_valid : out std_logic;
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y_re : out std_logic_vector(15 downto 0);
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y_im : out std_logic_vector(15 downto 0)
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);
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end Top_FFT;
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architecture ar_Top_FFT of Top_FFT is
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signal load : std_logic;
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signal start : std_logic;
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signal read_y : std_logic;
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signal val : std_logic;
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signal d_re : std_logic_vector(15 downto 0);
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signal d_im : std_logic_vector(15 downto 0);
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begin
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FFT : entity work.CoreFFT
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GENERIC map(
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LOGPTS => gLOGPTS,
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LOGLOGPTS => gLOGLOGPTS,
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WSIZE => gWSIZE,
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TWIDTH => gTWIDTH,
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DWIDTH => gDWIDTH,
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TDWIDTH => gTDWIDTH,
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RND_MODE => gRND_MODE,
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SCALE_MODE => gSCALE_MODE,
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PTS => gPTS,
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HALFPTS => gHALFPTS,
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inBuf_RWDLY => gInBuf_RWDLY)
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port map(clk,start,raz,val,read_y,d_im,d_re,load,open,y_im,y_re,y_valid,open);
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Input : entity work.Driver_IN
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port map(clk,raz,load,data,start,read_y,val,d_re,d_im);
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d_valid <= val;
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end ar_Top_FFT;
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