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APB_FIFO updated and APBs added to lpp_FIFO
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1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19
20 include ../../rules.mk
21 LIBDIR = ../../lib
22 INCPATH = ../../includes
23 SCRIPTDIR=../../scripts/
24 LIBS=-lapb_fifo_Driver -llpp_apb_functions
25 INPUTFILE=main.c
26 EXEC=BenchFIFO.bin
27 OUTBINDIR=bin/
28
29
30 .PHONY:bin
31
32 all:bin
33 @echo $(EXEC)" file created"
34
35 clean:
36 rm -f *.{o,a}
37
38
39
40 help:ruleshelp
41 @echo " all : makes an executable file called "$(EXEC)
42 @echo " in "$(OUTBINDIR)
43 @echo " clean : removes temporary files"
44
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
19 #include "stdio.h"
20 #include "lpp_apb_functions.h"
21 #include "apb_fifo_Driver.h"
22
23
24
25 int main()
26 {
27 int d=0;
28 int i=0;
29 APB_FIFO_Device* FIFO0;
30 FIFO0 = apbfifoOpen(0);
31
32 for(i=0;i<1024;i++)
33 {
34 FIFO0->rwdata = i;
35 }
36
37 for(i=0;i<1024;i++)
38 {
39 printf("%x",FIFO0->rwdata);
40 }
41
42
43 return 0;
44 }
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_FIFO_DRIVER_H
23 #define APB_FIFO_DRIVER_H
24
25
26
27 /*===================================================
28 T Y P E S D E F
29 ====================================================*/
30
31 /** Structure reprοΏ½sentant le registre du FIFO */
32 struct APB_FIFO_REG
33 {
34 int rwdata; /**< Registre de configuration: Flag Ready [1] ; Flag Enable [0] */
35 int raddr; /**< Registre de donnοΏ½e sur 16 bits */
36 int cfgreg;
37 int dummy0;
38 int dummy1;
39 int waddr;
40 };
41
42 typedef struct APB_FIFO_REG APB_FIFO_Device;
43
44 /*===================================================
45 F U N C T I O N S
46 ====================================================*/
47
48 /** Ouvre l'accοΏ½ au FIFO */
49 APB_FIFO_Device* apbfifoOpen(int count);
50
51
52
53
54 #endif
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1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19 FILE = apb_fifo_Driver
20 LIB = liblpp_fifo_Driver.a
21
22 include ../../rules.mk
23
24 all: $(FILE).a
25 @echo $(FILE)".a created"
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #include "lpp_apb_functions.h"
23 #include "apb_fifo_Driver.h"
24 #include <stdio.h>
25
26
27 APB_FIFO_Device* apbfifoOpen(int count)
28 {
29 APB_FIFO_Device* fifo0;
30 fifo0 = (APB_FIFO_Device*) apbgetdevice(LPP_FIFO,VENDOR_LPP,count);
31 return fifo0;
32 }
33
34
35
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_FIFO_DRIVER_H
23 #define APB_FIFO_DRIVER_H
24
25
26
27 /*===================================================
28 T Y P E S D E F
29 ====================================================*/
30
31 /** Structure reprοΏ½sentant le registre du FIFO */
32 struct APB_FIFO_REG
33 {
34 int rwdata; /**< Registre de configuration: Flag Ready [1] ; Flag Enable [0] */
35 int raddr; /**< Registre de donnοΏ½e sur 16 bits */
36 int cfgreg;
37 int dummy0;
38 int dummy1;
39 int waddr;
40 };
41
42 typedef struct APB_FIFO_REG APB_FIFO_Device;
43
44 /*===================================================
45 F U N C T I O N S
46 ====================================================*/
47
48 /** Ouvre l'accοΏ½ au FIFO */
49 APB_FIFO_Device* apbfifoOpen(int count);
50
51
52
53
54 #endif
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fft.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
35 entity APB_FFT is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 clk : in std_logic; --! Horloge du composant
44 rst : in std_logic; --! Reset general du composant
45 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
46 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
47 );
48 end APB_FFT;
49
50
51 architecture ar_APB_FFT of APB_FFT is
52
53 constant REVISION : integer := 1;
54
55 constant pconfig : apb_config_type := (
56 0 => ahb_device_reg (VENDOR_LPP, LPP_FFT, 0, REVISION, 0),
57 1 => apb_iobar(paddr, pmask));
58
59 type FFT_ctrlr_Reg is record
60 FFT_Cfg : std_logic_vector(1 downto 0);
61 FFT_Data : std_logic_vector(15 downto 0);
62 FFT_Reel : std_logic_vector(15 downto 0);
63 FFT_Img : std_logic_vector(15 downto 0);
64 end record;
65
66 signal Rec : FFT_ctrlr_Reg;
67 signal Rdata : std_logic_vector(31 downto 0);
68
69 signal y_valid : std_logic;
70 signal d_valid : std_logic;
71 begin
72
73
74 Rec.FFT_Cfg(0) <= d_valid;
75 Rec.FFT_Cfg(1) <= y_valid;
76
77 CONVERTER : entity Work.Top_FFT
78 port map(clk,rst,Rec.FFT_Data,y_valid,d_valid,Rec.FFT_Reel,Rec.FFT_Img);
79
80
81 process(rst,clk)
82 begin
83 if(rst='0')then
84 Rec.FFT_Data <= (others => '0');
85
86 elsif(clk'event and clk='1')then
87
88 --APB Write OP
89 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
90 case apbi.paddr(abits-1 downto 2) is
91 when "000001" =>
92 Rec.FFT_Data <= apbi.pwdata(15 downto 0);
93 when others =>
94 null;
95 end case;
96 end if;
97
98 --APB Read OP
99 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
100 case apbi.paddr(abits-1 downto 2) is
101 when "000000" =>
102 Rdata(3 downto 0) <= "000" & Rec.FFT_Cfg(0);
103 Rdata(7 downto 4) <= "000" & Rec.FFT_Cfg(1);
104 Rdata(31 downto 8) <= X"CCCCCC";
105 when "000001" =>
106 Rdata(31 downto 16) <= X"FFFF";
107 Rdata(15 downto 0) <= Rec.FFT_Data;
108 when "000010" =>
109 Rdata(31 downto 16) <= X"FFFF";
110 Rdata(15 downto 0) <= Rec.FFT_Reel;
111 when "000011" =>
112 Rdata(31 downto 16) <= X"FFFF";
113 Rdata(15 downto 0) <= Rec.FFT_Img;
114 when others =>
115 Rdata <= (others => '0');
116 end case;
117 end if;
118
119 end if;
120 apbo.pconfig <= pconfig;
121 end process;
122
123 apbo.prdata <= Rdata when apbi.penable = '1';
124
125 end ar_APB_FFT; No newline at end of file
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1 -- APB_FFTexp.vhd
2 library ieee;
3 use ieee.std_logic_1164.all;
4 library grlib;
5 use grlib.amba.all;
6 use grlib.stdlib.all;
7 use grlib.devices.all;
8 library lpp;
9 use lpp.lpp_amba.all;
10 use lpp.apb_devices_list.all;
11 use lpp.lpp_fft.all;
12
13 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
14
15 entity APB_FFTexp is
16 generic (
17 pindex : integer := 0;
18 paddr : integer := 0;
19 pmask : integer := 16#fff#;
20 pirq : integer := 0;
21 abits : integer := 8);
22 port (
23 clk : in std_logic; --! Horloge du composant
24 rst : in std_logic; --! Reset general du composant
25 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
26 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
27 );
28 end APB_FFTexp;
29
30
31 architecture ar_APB_FFTexp of APB_FFTexp is
32
33 constant REVISION : integer := 1;
34
35 constant pconfig : apb_config_type := (
36 0 => ahb_device_reg (VENDOR_LPP, LPP_FFT, 0, REVISION, 0),
37 1 => apb_iobar(paddr, pmask));
38
39 type FFT_ctrlr_Reg is record
40 FFT_Cfg : std_logic_vector(1 downto 0);
41 FFT_Reel : std_logic_vector(15 downto 0);
42 FFT_Img : std_logic_vector(15 downto 0);
43 end record;
44
45 signal Rec : FFT_ctrlr_Reg;
46 signal Rdata : std_logic_vector(31 downto 0);
47
48 signal y_valid : std_logic;
49 signal y_rdy : std_logic;
50 begin
51
52
53 Rec.FFT_Cfg(0) <= y_rdy;
54 Rec.FFT_Cfg(1) <= y_valid;
55
56 CONVERTER : entity work.topFFTbis
57 port map (clk,raz,y_valid,y_rdy,Rec.FFT_Reel,Rec.FFT_Img);
58
59
60 process(rst,clk)
61 begin
62 -- if(rst='0')then
63
64 if(clk'event and clk='1')then
65
66 --APB Write OP
67 -- if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
68 -- case apbi.paddr(abits-1 downto 2) is
69 -- when "000001" =>
70 -- Rec.FFT_Data <= apbi.pwdata(15 downto 0);
71 -- when others =>
72 -- null;
73 -- end case;
74 -- end if;
75
76 --APB Read OP
77 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
78 case apbi.paddr(abits-1 downto 2) is
79 when "000000" =>
80 Rdata(3 downto 0) <= "000" & Rec.FFT_Cfg(0);
81 Rdata(7 downto 4) <= "000" & Rec.FFT_Cfg(1);
82 Rdata(31 downto 8) <= X"CCCCCC";
83 when "000001" =>
84 Rdata(31 downto 16) <= X"FFFF";
85 Rdata(15 downto 0) <= Rec.FFT_Data;
86 when "000010" =>
87 Rdata(31 downto 16) <= X"FFFF";
88 Rdata(15 downto 0) <= Rec.FFT_Reel;
89 when "000011" =>
90 Rdata(31 downto 16) <= X"FFFF";
91 Rdata(15 downto 0) <= Rec.FFT_Img;
92 when others =>
93 Rdata <= (others => '0');
94 end case;
95 end if;
96
97 end if;
98 apbo.pconfig <= pconfig;
99 end process;
100
101 apbo.prdata <= Rdata when apbi.penable = '1';
102
103 end ar_APB_FFTexp; No newline at end of file
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: CoreFFT.vhd
10 -- Description: CoreFFT
11 -- Top level FFT module
12 -- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production
13 -- Notes: FFT In/out pins:
14 -- Input | Output | Comments
15 -- ------------+------------+------------------
16 -- clk | ifoPong |
17 -- ifiNreset | |async reset active low
18 -- start | |sync reset active high
19 -- Load Input data group |
20 -- d_im[15:0] | load |when high the inBuf is being loaded
21 -- d_re[15:0] | |
22 -- d_valid | |
23 -- Upload Output data group |
24 -- read_y | y_im[15:0] |
25 -- | y_re[15:0] |
26 -- | y_valid |marks a new output sample)
27 -- | y_rdy |when high the results are being uploaded
28 --------------------------------------------------------------------------------
29 library IEEE;
30 use IEEE.STD_LOGIC_1164.all;
31 USE work.fft_components.all;
32
33 ENTITY CoreFFT IS
34 GENERIC (
35 LOGPTS : integer := gLOGPTS;
36 LOGLOGPTS : integer := gLOGLOGPTS;
37 WSIZE : integer := gWSIZE;
38 TWIDTH : integer := gTWIDTH;
39 DWIDTH : integer := gDWIDTH;
40 TDWIDTH : integer := gTDWIDTH;
41 RND_MODE : integer := gRND_MODE;
42 SCALE_MODE : integer := gSCALE_MODE;
43 PTS : integer := gPTS;
44 HALFPTS : integer := gHALFPTS;
45 inBuf_RWDLY : integer := gInBuf_RWDLY );
46 PORT (
47 clk,ifiStart,ifiNreset : IN std_logic;
48 ifiD_valid, ifiRead_y : IN std_logic;
49 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
50 ifoLoad, ifoPong : OUT std_logic;
51 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
52 ifoY_valid, ifoY_rdy : OUT std_logic);
53 END ENTITY CoreFFT;
54
55 ARCHITECTURE translated OF CoreFFT IS
56
57 COMPONENT autoScale
58 GENERIC (SCALE_MODE : integer := 1 );
59 PORT (clk, clkEn, wLastStage : IN std_logic;
60 ldRiskOV, bflyRiskOV : IN std_logic;
61 startLoad, ifo_loadOn : IN std_logic;
62 bflyOutValid, startFFT : IN std_logic;
63 wEn_even, wEn_odd : IN std_logic;
64 upScale : OUT std_logic);
65 END COMPONENT;
66
67 COMPONENT bfly2
68 GENERIC ( RND_MODE : integer := 0;
69 WSIZE : integer := 16;
70 DWIDTH : integer := 32;
71 TWIDTH : integer := 16;
72 TDWIDTH : integer := 32 );
73 PORT (clk, validIn : IN std_logic;
74 swCrossIn : IN std_logic;
75 upScale : IN std_logic;
76 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
77 T : IN std_logic_vector(TDWIDTH-1 DOWNTO 0);
78 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
79 validOut, swCrossOut : OUT std_logic);
80 END COMPONENT;
81
82 COMPONENT sm_top
83 GENERIC ( PTS : integer := 256;
84 HALFPTS : integer := 128;
85 LOGPTS : integer := 8;
86 LOGLOGPTS : integer := 3;
87 inBuf_RWDLY : integer := 12 );
88 PORT (clk,clkEn : IN std_logic;
89 ifiStart, ifiNreset : IN std_logic;
90 ifiD_valid, ifiRead_y : IN std_logic;
91 ldA, rA, wA, tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
92 twid_wA, outBuf_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
93 outBuf_rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
94 wEn_even, wEn_odd : OUT std_logic;
95 preSwCross, twid_wEn : OUT std_logic;
96 inBuf_wEn, outBuf_wEn : OUT std_logic;
97 smPong, ldValid : OUT std_logic;
98 inBuf_rdValid : OUT std_logic;
99 wLastStage : OUT std_logic;
100 smStartFFTrd : OUT std_logic;
101 smStartLoad, ifoLoad : OUT std_logic;
102 ifoY_valid, ifoY_rdy : OUT std_logic);
103 END COMPONENT;
104
105 COMPONENT twiddle
106 PORT (A : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
107 T : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0));
108 END COMPONENT;
109
110 COMPONENT pipoBuffer
111 GENERIC ( LOGPTS : integer := 8;
112 DWIDTH : integer := 32 );
113 PORT (
114 clk, clkEn, pong, rEn : IN std_logic;
115 rA, wA_load, wA_bfly : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
116 ldData,wP_bfly,wQ_bfly : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
117 wEn_bfly,wEn_even,wEn_odd : IN std_logic;
118 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0) );
119 END COMPONENT;
120
121 COMPONENT switch
122 GENERIC ( DWIDTH : integer := 16 );
123 PORT (clk, sel, validIn : IN std_logic;
124 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
125 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
126 validOut : OUT std_logic);
127 END COMPONENT;
128
129 COMPONENT twidLUT
130 GENERIC ( LOGPTS : integer := 8;
131 TDWIDTH : integer := 32 );
132 PORT (clk, wEn : IN std_logic;
133 wA, rA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
134 D : IN std_logic_vector(TDWIDTH-1 DOWNTO 0);
135 Q : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0));
136 END COMPONENT;
137
138 COMPONENT outBuff
139 GENERIC ( LOGPTS : integer := 8;
140 DWIDTH : integer := 32 );
141 PORT (clk, clkEn, wEn : IN std_logic;
142 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
143 wA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
144 rA : IN std_logic_vector(LOGPTS-1 DOWNTO 0);
145 outD : OUT std_logic_vector(DWIDTH-1 DOWNTO 0));
146 END COMPONENT;
147
148 SIGNAL ldA_w, rA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
149 SIGNAL wA_w, tA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
150 SIGNAL twid_wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
151 SIGNAL outBuf_wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
152 SIGNAL outBuf_rA_w : std_logic_vector(LOGPTS-1 DOWNTO 0);
153 SIGNAL wEn_even_w : std_logic;
154 SIGNAL wEn_odd_w : std_logic;
155 SIGNAL inBuf_wEn_w : std_logic;
156 SIGNAL preSwCross_w : std_logic;
157 SIGNAL postSwCross_w : std_logic;
158 SIGNAL twid_wEn_w : std_logic;
159 SIGNAL outBuf_wEn_w : std_logic;
160 SIGNAL ldRiskOV_w : std_logic;
161 SIGNAL bflyRiskOV_w : std_logic;
162 SIGNAL readP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
163 SIGNAL readQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
164 SIGNAL bflyInP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
165 SIGNAL bflyInQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
166 SIGNAL bflyOutP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
167 SIGNAL bflyOutQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
168 SIGNAL T_w : std_logic_vector(TDWIDTH-1 DOWNTO 0);
169 SIGNAL twidData_w : std_logic_vector(TDWIDTH-1 DOWNTO 0);
170 SIGNAL outEven_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
171 SIGNAL outOdd_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
172 SIGNAL inBufValid_w : std_logic;
173 SIGNAL preSwValid_w : std_logic;
174 SIGNAL bflyValid_w : std_logic;
175 SIGNAL wLastStage_w : std_logic;
176 SIGNAL startFFTrd_w : std_logic;
177 SIGNAL startLoad_w : std_logic;
178 SIGNAL upScale_w : std_logic;
179 SIGNAL port_xhdl15 : std_logic;
180 SIGNAL xhdl_17 : std_logic_vector(DWIDTH-1 DOWNTO 0);
181 SIGNAL xhdl_23 : std_logic_vector(DWIDTH-1 DOWNTO 0);
182 SIGNAL clkEn_const : std_logic;
183 SIGNAL ifoLoad_xhdl1 : std_logic;
184 SIGNAL ifoY_im_xhdl2 : std_logic_vector(WSIZE-1 DOWNTO 0);
185 SIGNAL ifoY_re_xhdl3 : std_logic_vector(WSIZE-1 DOWNTO 0);
186 SIGNAL ifoPong_xhdl4 : std_logic;
187 SIGNAL ifoY_valid_xhdl5 : std_logic;
188 SIGNAL ifoY_rdy_xhdl6 : std_logic;
189 SIGNAL displayBflyOutP : std_logic;
190 SIGNAL displayBflyOutQ : std_logic;
191 SIGNAL displayInBuf_wEn : std_logic;
192 SIGNAL ldValid_w : std_logic;
193
194 BEGIN
195 ifoLoad <= ifoLoad_xhdl1;
196 ifoY_im <= ifoY_im_xhdl2;
197 ifoY_re <= ifoY_re_xhdl3;
198 ifoPong <= ifoPong_xhdl4;
199 ifoY_valid <= ifoY_valid_xhdl5;
200 ifoY_rdy <= ifoY_rdy_xhdl6;
201 -- debug only
202 displayBflyOutP <= bflyOutP_w(0) ;
203 displayBflyOutQ <= bflyOutQ_w(0) ;
204 displayInBuf_wEn <= inBuf_wEn_w ;
205 port_xhdl15 <= '1';
206
207 smTop_0 : sm_top
208 GENERIC MAP ( PTS => PTS, HALFPTS => HALFPTS,
209 LOGPTS => LOGPTS, LOGLOGPTS => LOGLOGPTS, inBuf_RWDLY => inBuf_RWDLY )
210 PORT MAP (
211 clk => clk,
212 clkEn => port_xhdl15,
213 ifiStart => ifiStart,
214 ifiNreset => ifiNreset,
215 ifiD_valid => ifiD_valid,
216 ifiRead_y => ifiRead_y,
217 ldA => ldA_w,
218 rA => rA_w,
219 wA => wA_w,
220 tA => tA_w,
221 twid_wA => twid_wA_w,
222 outBuf_wA => outBuf_wA_w,
223 outBuf_rA => outBuf_rA_w,
224 wEn_even => wEn_even_w,
225 wEn_odd => wEn_odd_w,
226 preSwCross => preSwCross_w,
227 twid_wEn => twid_wEn_w,
228 inBuf_wEn => inBuf_wEn_w,
229 outBuf_wEn => outBuf_wEn_w,
230 smPong => ifoPong_xhdl4,
231 ldValid => ldValid_w,
232 inBuf_rdValid => inBufValid_w,
233 wLastStage => wLastStage_w,
234 smStartFFTrd => startFFTrd_w,
235 smStartLoad => startLoad_w,
236 ifoLoad => ifoLoad_xhdl1,
237 ifoY_valid => ifoY_valid_xhdl5,
238 ifoY_rdy => ifoY_rdy_xhdl6);
239
240 xhdl_17 <= ifiD_im & ifiD_re;
241
242 inBuf_0 : pipoBuffer
243 GENERIC MAP ( LOGPTS => LOGPTS,
244 DWIDTH => DWIDTH )
245 PORT MAP (
246 clk => clk,
247 clkEn => '1',
248 rEn => '1',
249 rA => rA_w,
250 wA_load => ldA_w,
251 wA_bfly => wA_w,
252 ldData => xhdl_17,
253 wP_bfly => outEven_w,
254 wQ_bfly => outOdd_w,
255 wEn_bfly => inBuf_wEn_w,
256 wEn_even => wEn_even_w,
257 wEn_odd => wEn_odd_w,
258 pong => ifoPong_xhdl4,
259 outP => readP_w,
260 outQ => readQ_w);
261
262 preBflySw_0 : switch
263 GENERIC MAP ( DWIDTH => DWIDTH )
264 PORT MAP (
265 clk => clk,
266 inP => readP_w,
267 inQ => readQ_w,
268 sel => preSwCross_w,
269 outP => bflyInP_w,
270 outQ => bflyInQ_w,
271 validIn => inBufValid_w,
272 validOut => preSwValid_w);
273
274 bfly_0 : bfly2
275 GENERIC MAP (RND_MODE => RND_MODE, WSIZE => WSIZE, DWIDTH => DWIDTH,
276 TWIDTH => TWIDTH, TDWIDTH => TDWIDTH )
277 PORT MAP (
278 clk => clk,
279 upScale => upScale_w,
280 inP => bflyInP_w,
281 inQ => bflyInQ_w,
282 T => T_w,
283 outP => bflyOutP_w,
284 outQ => bflyOutQ_w,
285 validIn => preSwValid_w,
286 validOut => bflyValid_w,
287 swCrossIn => preSwCross_w,
288 swCrossOut => postSwCross_w);
289
290 lut_0 : twiddle
291 PORT MAP (A => twid_wA_w, T => twidData_w);
292
293 twidLUT_1 : twidLUT
294 GENERIC MAP ( LOGPTS => LOGPTS, TDWIDTH => TDWIDTH )
295 PORT MAP (
296 clk => clk,
297 wA => twid_wA_w,
298 wEn => twid_wEn_w,
299 rA => tA_w,
300 D => twidData_w,
301 Q => T_w);
302
303 postBflySw_0 : switch
304 GENERIC MAP ( DWIDTH => DWIDTH )
305 PORT MAP (
306 clk => clk,
307 inP => bflyOutP_w,
308 inQ => bflyOutQ_w,
309 sel => postSwCross_w,
310 outP => outEven_w,
311 outQ => outOdd_w,
312 validIn => bflyValid_w,
313 validOut => open);
314
315 ifoY_im_xhdl2 <= xhdl_23(DWIDTH-1 DOWNTO WSIZE);
316 ifoY_re_xhdl3 <= xhdl_23(WSIZE-1 DOWNTO 0);
317 outBuff_0 : outBuff
318 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
319 PORT MAP (
320 clk => clk, clkEn => '1',
321 rA => outBuf_rA_w,
322 wA => outBuf_wA_w,
323 inP => outEven_w,
324 inQ => outOdd_w,
325 wEn => outBuf_wEn_w,
326 outD => xhdl_23);
327
328 -- Autoscaling
329 -- monitor if input data .im and .re have MSB == sign
330 ldRiskOV_w <= to_logic(
331 NOT ((ifiD_im(WSIZE-1) = ifiD_im(WSIZE-2))
332 AND (ifiD_re(WSIZE-1) = ifiD_re(WSIZE-2))) );
333
334 bflyRiskOV_w <= to_logic(
335 NOT ((((bflyOutP_w(DWIDTH-1) = bflyOutP_w(DWIDTH- 2))
336 AND (bflyOutP_w(WSIZE-1) = bflyOutP_w(WSIZE-2)))
337 AND (bflyOutQ_w(DWIDTH-1) = bflyOutQ_w(DWIDTH-2)))
338 AND (bflyOutQ_w(WSIZE-1) = bflyOutQ_w(WSIZE-2))) );
339 clkEn_const <= '1';
340 autoScale_0 : autoScale
341 GENERIC MAP (SCALE_MODE => SCALE_MODE)
342 PORT MAP (
343 clk => clk,
344 clkEn => clkEn_const,
345 ldRiskOV => ldRiskOV_w,
346 bflyRiskOV => bflyRiskOV_w,
347 startLoad => startLoad_w,
348 startFFT => startFFTrd_w,
349 bflyOutValid => bflyValid_w,
350 wLastStage => wLastStage_w,
351 wEn_even => wEn_even_w,
352 wEn_odd => wEn_odd_w,
353 ifo_loadOn => ifoLoad_xhdl1,
354 upScale => upScale_w);
355
356 END ARCHITECTURE translated;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FFT_config.all;
26
27 entity Driver_IN is
28 port(
29 clk,raz : in std_logic;
30 load : in std_logic;
31 data : in std_logic_vector(15 downto 0);
32 start : out std_logic;
33 read_y : out std_logic;
34 d_valid : out std_logic;
35 d_re : out std_logic_vector(15 downto 0);
36 d_im : out std_logic_vector(15 downto 0)
37 );
38 end Driver_IN;
39
40
41 architecture ar_Driver_IN of Driver_IN is
42
43 begin
44 process (clk,raz)
45 begin
46 if(raz='0')then
47 start <= '1';
48 d_valid <= '0';
49 d_re <= (others => '0');
50 d_im <= (others => '0');
51
52 elsif(clk' event and clk='1')then
53 start <= '0';
54 if(load='1')then
55 d_valid <= '1';
56 d_re <= data;
57 else
58 d_valid <= '0';
59 end if;
60
61 end if;
62 end process;
63
64 read_y <= '1';
65
66 end ar_Driver_IN; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 Package FFT_config is
27
28 --===========================================================|
29 --======================= Valeurs ===========================|
30 --===================== Sinus 500 hz ========================|
31 --========================== et =============================|
32 --==================== Somme de Sinus =======================|
33 --===========================================================|
34
35 type Tbl is array(natural range <>) of std_logic_vector(15 downto 0);
36
37 constant Tablo_In : Tbl (0 to 99):= (X"0000",X"080A",X"100B",X"17FC",X"1FD5",X"278E",X"2F1F",X"3680",X"3DAA",X"4496",X"4B3D",X"5197",X"579F",X"5D4F",X"62A0",X"678E",X"6C13",X"702B",X"73D1",X"7703",X"79BC",X"7BFB",X"7DBC",X"7EFE",X"7FBF",X"7FFF",X"7FBF",X"7EFE",X"7DBC",X"7BFB",X"79BC",X"7703",X"73D1",X"702B",X"6C13",X"678E",X"62A0",X"5D4F",X"579F",X"5197",X"4B3D",X"4496",X"3DAA",X"3680",X"2F1F",X"278E",X"1FD5",X"17FC",X"100B",X"080A",X"0000",X"F7F6",X"EFF5",X"E804",X"E02B",X"D872",X"D0E1",X"C980",X"C256",X"BB6A",X"B4C3",X"AE69",X"A861",X"A2B1",X"9D60",X"9872",X"93ED",X"8FD5",X"8C2F",X"88FD",X"8644",X"8405",X"8244",X"8102",X"8041",X"8000",X"8041",X"8102",X"8244",X"8405",X"8644",X"88FD",X"8C2F",X"8FD5",X"93ED",X"9872",X"9D60",X"A2B1",X"A861",X"AE69",X"B4C3",X"BB6A",X"C256",X"C980",X"D0E1",X"D872",X"E02B",X"E804",X"EFF5",X"F7F6");
38
39 constant Tablo_Input : Tbl (0 to 249):= (X"0000",X"1AA8",X"3151",X"409E",X"4661",X"41EE",X"343D",X"1FBE",X"07F6",X"F0F1",X"DE9A",X"D420",X"D36B",X"DCD9",X"EF26",X"07A5",X"22AA",X"3C22",X"5039",X"5BF5",X"5DB3",X"5564",X"4495",X"2E2C",X"15F4",X"0000",X"F007",X"E8C8",X"EBA1",X"F84D",X"0CFB",X"268C",X"411C",X"589D",X"697A",X"7130",X"6EAD",X"6280",X"4EC4",X"36C4",X"1E7A",X"09E9",X"FC7D",X"F879",X"FEA1",X"0E19",X"2485",X"3E6C",X"57C6",X"6CA0",X"79BC",X"7D19",X"7640",X"665B",X"5004",X"36D8",X"1EEA",X"0C17",X"0168",X"009B",X"09D6",X"1BA6",X"3337",X"4CC7",X"6442",X"75E9",X"7EE7",X"7DC7",X"72B1",X"5F61",X"46E3",X"2D14",X"1603",X"0551",X"FD98",X"0000",X"0C14",X"1FD2",X"37FD",X"50A2",X"65B8",X"73C8",X"7876",X"72E6",X"63DA",X"4D99",X"338D",X"19BA",X"0419",X"F5F9",X"F170",X"F711",X"05CA",X"1B17",X"3365",X"4AA5",X"5CF2",X"6732",X"6790",X"5DCA",X"4B3D",X"32A9",X"17C5",X"FEA4",X"EB13",X"DFF7",X"DEDE",X"E7BB",X"F8E9",X"0F6F",X"277A",X"3CF7",X"4C3B",X"529A",X"4ED0",X"413B",X"2BC4",X"119A",X"F6A9",X"DEFD",X"CE1D",X"C678",X"C906",X"D51E",X"E88F",X"0000",X"1771",X"2AE2",X"36FA",X"3988",X"31E3",X"2103",X"0957",X"EE66",X"D43C",X"BEC5",X"B130",X"AD66",X"B3C5",X"C309",X"D886",X"F091",X"0717",X"1845",X"2122",X"2009",X"14ED",X"015C",X"E83B",X"CD57",X"B4C3",X"A236",X"9870",X"98CE",X"A30E",X"B55B",X"CC9B",X"E4E9",X"FA36",X"08EF",X"0E90",X"0A07",X"FBE7",X"E646",X"CC73",X"B267",X"9C26",X"8D1A",X"878A",X"8C38",X"9A48",X"AF5E",X"C803",X"E02E",X"F3EC",X"0000",X"0268",X"FAAF",X"E9FD",X"D2EC",X"B91D",X"A09F",X"8D4F",X"8239",X"8119",X"8A17",X"9BBE",X"B339",X"CCC9",X"E45A",X"F62A",X"FF65",X"FE98",X"F3E9",X"E116",X"C928",X"AFFC",X"99A5",X"89C0",X"82E7",X"8644",X"9360",X"A83A",X"C194",X"DB7B",X"F1E7",X"015F",X"0787",X"0383",X"F617",X"E186",X"C93C",X"B13C",X"9D80",X"9153",X"8ED0",X"9686",X"A763",X"BEE4",X"D974",X"F305",X"07B3",X"145F",X"1738",X"0FF9",X"0000",X"EA0C",X"D1D4",X"BB6B",X"AA9C",X"A24D",X"A40B",X"AFC7",X"C3DE",X"DD56",X"F85B",X"10DA",X"2327",X"2C95",X"2BE0",X"2166",X"0F0F",X"F80A",X"E042",X"CBC3",X"BE12",X"B99F",X"BF62",X"CEAF",X"E558");
40
41 end; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FFT_config.all;
26
27 entity Sinus_In is
28 port(
29 clk,raz : in std_logic;
30 load : in std_logic;
31 pong : in std_logic;
32 start : out std_logic;
33 read_y : out std_logic;
34 d_valid : out std_logic;
35 d_re : out std_logic_vector(15 downto 0);
36 d_im : out std_logic_vector(15 downto 0)
37 );
38 end Sinus_In;
39
40
41 architecture ar_Sinus_In of Sinus_In is
42
43 signal i : integer range 0 to Tablo_Input'length;
44
45 begin
46 process (clk,raz)
47 begin
48 if(raz='0')then
49 start <= '1';
50 d_valid <= '0';
51 d_re <= (others => '0');
52 d_im <= (others => '0');
53 i <= 0;
54
55 elsif(clk' event and clk='1')then
56 start <= '0';
57 if(load='1')then
58 d_valid <= '1';
59
60 if(pong='1')then
61 d_re <= Tablo_In(i);
62 if(i=Tablo_In'length-1)then
63 i <= 0;
64 else
65 i <= i+1;
66 end if;
67 else
68 d_re <= Tablo_Input(i);
69 if(i=Tablo_Input'length-1)then
70 i <= 0;
71 else
72 i <= i+1;
73 end if;
74 end if;
75
76 else
77 d_valid <= '0';
78 i <= 0;
79 end if;
80 end if;
81 end process;
82
83 read_y <= '1';
84
85 end ar_Sinus_In; No newline at end of file
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@@ -0,0 +1,71
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 USE work.fft_components.all;
26
27 entity Top_FFT is
28 port(
29 clk,raz : in std_logic;
30 data : in std_logic_vector(15 downto 0);
31 y_valid : out std_logic;
32 d_valid : out std_logic;
33 y_re : out std_logic_vector(15 downto 0);
34 y_im : out std_logic_vector(15 downto 0)
35 );
36 end Top_FFT;
37
38
39 architecture ar_Top_FFT of Top_FFT is
40
41 signal load : std_logic;
42 signal start : std_logic;
43 signal read_y : std_logic;
44 signal val : std_logic;
45 signal d_re : std_logic_vector(15 downto 0);
46 signal d_im : std_logic_vector(15 downto 0);
47
48 begin
49
50 FFT : entity work.CoreFFT
51 GENERIC map(
52 LOGPTS => gLOGPTS,
53 LOGLOGPTS => gLOGLOGPTS,
54 WSIZE => gWSIZE,
55 TWIDTH => gTWIDTH,
56 DWIDTH => gDWIDTH,
57 TDWIDTH => gTDWIDTH,
58 RND_MODE => gRND_MODE,
59 SCALE_MODE => gSCALE_MODE,
60 PTS => gPTS,
61 HALFPTS => gHALFPTS,
62 inBuf_RWDLY => gInBuf_RWDLY)
63 port map(clk,start,raz,val,read_y,d_im,d_re,load,open,y_im,y_re,y_valid,open);
64
65
66 Input : entity work.Driver_IN
67 port map(clk,raz,load,data,start,read_y,val,d_re,d_im);
68
69 d_valid <= val;
70
71 end ar_Top_FFT; No newline at end of file
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1 -- Version: 9.0 9.0.0.15
2
3 library ieee;
4 use ieee.std_logic_1164.all;
5 library proasic3;
6 use proasic3.all;
7
8 entity actar is
9 port( DataA : in std_logic_vector(15 downto 0); DataB : in
10 std_logic_vector(15 downto 0); Mult : out
11 std_logic_vector(31 downto 0);Clock : in std_logic) ;
12 end actar;
13
14
15 architecture DEF_ARCH of actar is
16
17 component BUFF
18 port(A : in std_logic := 'U'; Y : out std_logic) ;
19 end component;
20
21 component DFN1
22 port(D, CLK : in std_logic := 'U'; Q : out std_logic) ;
23 end component;
24
25 component MX2
26 port(A, B, S : in std_logic := 'U'; Y : out std_logic) ;
27 end component;
28
29 component XOR2
30 port(A, B : in std_logic := 'U'; Y : out std_logic) ;
31 end component;
32
33 component AND2
34 port(A, B : in std_logic := 'U'; Y : out std_logic) ;
35 end component;
36
37 component AO1
38 port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
39 end component;
40
41 component MAJ3
42 port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
43 end component;
44
45 component XNOR2
46 port(A, B : in std_logic := 'U'; Y : out std_logic) ;
47 end component;
48
49 component XOR3
50 port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
51 end component;
52
53 component NOR2
54 port(A, B : in std_logic := 'U'; Y : out std_logic) ;
55 end component;
56
57 component OR3
58 port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
59 end component;
60
61 component AND3
62 port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
63 end component;
64
65 component AND2A
66 port(A, B : in std_logic := 'U'; Y : out std_logic) ;
67 end component;
68
69 component AOI1
70 port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
71 end component;
72
73 component VCC
74 port( Y : out std_logic);
75 end component;
76
77 component GND
78 port( Y : out std_logic);
79 end component;
80
81 signal S_0_net, S_1_net, S_2_net, S_3_net, S_4_net, S_5_net,
82 S_6_net, S_7_net, E_0_net, E_1_net, E_2_net, E_3_net,
83 E_4_net, E_5_net, E_6_net, E_7_net, EBAR, PP0_0_net,
84 PP0_1_net, PP0_2_net, PP0_3_net, PP0_4_net, PP0_5_net,
85 PP0_6_net, PP0_7_net, PP0_8_net, PP0_9_net, PP0_10_net,
86 PP0_11_net, PP0_12_net, PP0_13_net, PP0_14_net,
87 PP0_15_net, PP0_16_net, PP1_0_net, PP1_1_net, PP1_2_net,
88 PP1_3_net, PP1_4_net, PP1_5_net, PP1_6_net, PP1_7_net,
89 PP1_8_net, PP1_9_net, PP1_10_net, PP1_11_net, PP1_12_net,
90 PP1_13_net, PP1_14_net, PP1_15_net, PP1_16_net, PP2_0_net,
91 PP2_1_net, PP2_2_net, PP2_3_net, PP2_4_net, PP2_5_net,
92 PP2_6_net, PP2_7_net, PP2_8_net, PP2_9_net, PP2_10_net,
93 PP2_11_net, PP2_12_net, PP2_13_net, PP2_14_net,
94 PP2_15_net, PP2_16_net, PP3_0_net, PP3_1_net, PP3_2_net,
95 PP3_3_net, PP3_4_net, PP3_5_net, PP3_6_net, PP3_7_net,
96 PP3_8_net, PP3_9_net, PP3_10_net, PP3_11_net, PP3_12_net,
97 PP3_13_net, PP3_14_net, PP3_15_net, PP3_16_net, PP4_0_net,
98 PP4_1_net, PP4_2_net, PP4_3_net, PP4_4_net, PP4_5_net,
99 PP4_6_net, PP4_7_net, PP4_8_net, PP4_9_net, PP4_10_net,
100 PP4_11_net, PP4_12_net, PP4_13_net, PP4_14_net,
101 PP4_15_net, PP4_16_net, PP5_0_net, PP5_1_net, PP5_2_net,
102 PP5_3_net, PP5_4_net, PP5_5_net, PP5_6_net, PP5_7_net,
103 PP5_8_net, PP5_9_net, PP5_10_net, PP5_11_net, PP5_12_net,
104 PP5_13_net, PP5_14_net, PP5_15_net, PP5_16_net, PP6_0_net,
105 PP6_1_net, PP6_2_net, PP6_3_net, PP6_4_net, PP6_5_net,
106 PP6_6_net, PP6_7_net, PP6_8_net, PP6_9_net, PP6_10_net,
107 PP6_11_net, PP6_12_net, PP6_13_net, PP6_14_net,
108 PP6_15_net, PP6_16_net, PP7_0_net, PP7_1_net, PP7_2_net,
109 PP7_3_net, PP7_4_net, PP7_5_net, PP7_6_net, PP7_7_net,
110 PP7_8_net, PP7_9_net, PP7_10_net, PP7_11_net, PP7_12_net,
111 PP7_13_net, PP7_14_net, PP7_15_net, PP7_16_net,
112 SumA_0_net, SumA_1_net, SumA_2_net, SumA_3_net,
113 SumA_4_net, SumA_5_net, SumA_6_net, SumA_7_net,
114 SumA_8_net, SumA_9_net, SumA_10_net, SumA_11_net,
115 SumA_12_net, SumA_13_net, SumA_14_net, SumA_15_net,
116 SumA_16_net, SumA_17_net, SumA_18_net, SumA_19_net,
117 SumA_20_net, SumA_21_net, SumA_22_net, SumA_23_net,
118 SumA_24_net, SumA_25_net, SumA_26_net, SumA_27_net,
119 SumA_28_net, SumA_29_net, SumA_30_net, SumB_0_net,
120 SumB_1_net, SumB_2_net, SumB_3_net, SumB_4_net,
121 SumB_5_net, SumB_6_net, SumB_7_net, SumB_8_net,
122 SumB_9_net, SumB_10_net, SumB_11_net, SumB_12_net,
123 SumB_13_net, SumB_14_net, SumB_15_net, SumB_16_net,
124 SumB_17_net, SumB_18_net, SumB_19_net, SumB_20_net,
125 SumB_21_net, SumB_22_net, SumB_23_net, SumB_24_net,
126 SumB_25_net, SumB_26_net, SumB_27_net, SumB_28_net,
127 SumB_29_net, SumB_30_net, DFN1_117_Q, DFN1_114_Q,
128 DFN1_25_Q, DFN1_111_Q, DFN1_143_Q, DFN1_124_Q, DFN1_18_Q,
129 DFN1_30_Q, DFN1_97_Q, DFN1_90_Q, DFN1_102_Q, DFN1_63_Q,
130 DFN1_140_Q, DFN1_137_Q, DFN1_45_Q, DFN1_73_Q, DFN1_23_Q,
131 DFN1_120_Q, DFN1_36_Q, DFN1_130_Q, DFN1_42_Q, DFN1_8_Q,
132 DFN1_79_Q, DFN1_78_Q, DFN1_135_Q, DFN1_20_Q, DFN1_112_Q,
133 DFN1_61_Q, DFN1_123_Q, DFN1_70_Q, DFN1_55_Q, DFN1_28_Q,
134 DFN1_95_Q, DFN1_94_Q, DFN1_2_Q, DFN1_34_Q, DFN1_125_Q,
135 DFN1_77_Q, DFN1_145_Q, DFN1_88_Q, DFN1_49_Q, DFN1_17_Q,
136 DFN1_85_Q, DFN1_84_Q, DFN1_147_Q, DFN1_27_Q, DFN1_115_Q,
137 DFN1_66_Q, DFN1_133_Q, DFN1_76_Q, DFN1_10_Q, DFN1_127_Q,
138 DFN1_51_Q, DFN1_50_Q, DFN1_107_Q, DFN1_144_Q, DFN1_81_Q,
139 DFN1_33_Q, DFN1_98_Q, DFN1_43_Q, DFN1_122_Q, DFN1_96_Q,
140 DFN1_13_Q, DFN1_11_Q, DFN1_67_Q, DFN1_106_Q, DFN1_48_Q,
141 DFN1_151_Q, DFN1_58_Q, DFN1_6_Q, DFN1_103_Q, DFN1_64_Q,
142 DFN1_141_Q, DFN1_138_Q, DFN1_46_Q, DFN1_74_Q, DFN1_24_Q,
143 DFN1_121_Q, DFN1_37_Q, DFN1_131_Q, DFN1_59_Q, DFN1_31_Q,
144 DFN1_100_Q, DFN1_99_Q, DFN1_5_Q, DFN1_41_Q, DFN1_132_Q,
145 DFN1_82_Q, DFN1_150_Q, DFN1_91_Q, DFN1_101_Q, DFN1_62_Q,
146 DFN1_139_Q, DFN1_136_Q, DFN1_44_Q, DFN1_72_Q, DFN1_22_Q,
147 DFN1_119_Q, DFN1_35_Q, DFN1_129_Q, DFN1_68_Q, DFN1_118_Q,
148 DFN1_16_Q, DFN1_3_Q, DFN1_86_Q, DFN1_109_Q, DFN1_60_Q,
149 DFN1_83_Q, DFN1_54_Q, DFN1_53_Q, DFN1_19_Q, DFN1_69_Q,
150 DFN1_113_Q, DFN1_105_Q, DFN1_38_Q, DFN1_56_Q, DFN1_12_Q,
151 DFN1_32_Q, DFN1_4_Q, DFN1_1_Q, DFN1_152_Q, DFN1_52_Q,
152 DFN1_93_Q, DFN1_80_Q, DFN1_14_Q, DFN1_39_Q, DFN1_146_Q,
153 DFN1_9_Q, DFN1_134_Q, DFN1_126_Q, DFN1_7_Q, DFN1_57_Q,
154 DFN1_104_Q, DFN1_89_Q, DFN1_26_Q, DFN1_47_Q, DFN1_0_Q,
155 DFN1_21_Q, DFN1_148_Q, DFN1_142_Q, DFN1_92_Q, DFN1_149_Q,
156 DFN1_40_Q, DFN1_29_Q, DFN1_110_Q, DFN1_128_Q, DFN1_87_Q,
157 DFN1_108_Q, DFN1_75_Q, DFN1_71_Q, DFN1_65_Q, DFN1_116_Q,
158 DFN1_15_Q, XOR2_22_Y, AND2_229_Y, XOR3_39_Y, MAJ3_29_Y,
159 XOR3_19_Y, MAJ3_73_Y, XOR2_43_Y, AND2_233_Y, XOR3_10_Y,
160 MAJ3_70_Y, XOR3_44_Y, MAJ3_7_Y, XOR3_63_Y, MAJ3_63_Y,
161 XOR3_48_Y, MAJ3_82_Y, XOR2_19_Y, AND2_124_Y, XOR3_90_Y,
162 MAJ3_16_Y, XOR3_49_Y, MAJ3_80_Y, XOR2_95_Y, AND2_26_Y,
163 XOR3_33_Y, MAJ3_72_Y, XOR3_28_Y, MAJ3_17_Y, XOR2_7_Y,
164 AND2_48_Y, XOR3_52_Y, MAJ3_28_Y, XOR3_76_Y, MAJ3_59_Y,
165 XOR2_52_Y, AND2_154_Y, XOR3_87_Y, MAJ3_12_Y, XOR3_69_Y,
166 MAJ3_23_Y, XOR2_16_Y, AND2_9_Y, XOR3_13_Y, MAJ3_39_Y,
167 XOR3_85_Y, MAJ3_21_Y, XOR3_81_Y, MAJ3_54_Y, XOR2_88_Y,
168 AND2_238_Y, XOR2_106_Y, AND2_121_Y, XOR3_36_Y, MAJ3_11_Y,
169 XOR3_62_Y, MAJ3_32_Y, XOR2_41_Y, AND2_56_Y, XOR3_26_Y,
170 MAJ3_60_Y, XOR3_23_Y, MAJ3_69_Y, XOR3_37_Y, MAJ3_87_Y,
171 XOR3_6_Y, MAJ3_62_Y, XOR3_0_Y, MAJ3_10_Y, XOR3_38_Y,
172 MAJ3_47_Y, XOR3_25_Y, MAJ3_22_Y, XOR3_54_Y, MAJ3_51_Y,
173 XOR3_75_Y, MAJ3_81_Y, XOR3_65_Y, MAJ3_6_Y, XOR3_46_Y,
174 MAJ3_14_Y, XOR3_1_Y, MAJ3_26_Y, XOR3_12_Y, MAJ3_38_Y,
175 XOR3_83_Y, MAJ3_19_Y, XOR3_80_Y, MAJ3_52_Y, XOR3_14_Y,
176 MAJ3_3_Y, XOR3_5_Y, MAJ3_66_Y, XOR3_35_Y, MAJ3_9_Y,
177 XOR3_60_Y, MAJ3_31_Y, XOR3_43_Y, MAJ3_48_Y, XOR3_24_Y,
178 MAJ3_58_Y, XOR3_50_Y, MAJ3_76_Y, XOR3_64_Y, MAJ3_90_Y,
179 XOR3_34_Y, MAJ3_68_Y, XOR3_31_Y, MAJ3_15_Y, XOR3_66_Y,
180 MAJ3_50_Y, XOR3_53_Y, MAJ3_27_Y, XOR3_77_Y, MAJ3_56_Y,
181 XOR3_3_Y, MAJ3_85_Y, XOR2_57_Y, AND2_68_Y, XOR3_72_Y,
182 MAJ3_20_Y, XOR2_44_Y, AND2_132_Y, XOR2_91_Y, AND2_81_Y,
183 XOR3_79_Y, MAJ3_46_Y, XOR3_78_Y, MAJ3_93_Y, XOR3_9_Y,
184 MAJ3_37_Y, XOR3_96_Y, MAJ3_4_Y, XOR3_30_Y, MAJ3_41_Y,
185 XOR3_56_Y, MAJ3_57_Y, XOR3_40_Y, MAJ3_89_Y, XOR3_20_Y,
186 MAJ3_0_Y, XOR3_17_Y, MAJ3_49_Y, XOR3_27_Y, MAJ3_67_Y,
187 XOR3_95_Y, MAJ3_44_Y, XOR3_92_Y, MAJ3_91_Y, XOR3_29_Y,
188 MAJ3_35_Y, XOR3_18_Y, MAJ3_2_Y, XOR3_47_Y, MAJ3_40_Y,
189 XOR3_70_Y, MAJ3_55_Y, XOR3_57_Y, MAJ3_88_Y, XOR3_41_Y,
190 MAJ3_96_Y, XOR3_84_Y, MAJ3_36_Y, XOR3_91_Y, MAJ3_45_Y,
191 XOR3_68_Y, MAJ3_33_Y, XOR3_67_Y, MAJ3_71_Y, XOR2_55_Y,
192 AND2_28_Y, XOR3_8_Y, MAJ3_79_Y, XOR2_79_Y, AND2_197_Y,
193 XOR3_71_Y, MAJ3_64_Y, XOR3_58_Y, MAJ3_18_Y, XOR2_18_Y,
194 AND2_166_Y, XOR3_74_Y, MAJ3_30_Y, XOR3_61_Y, MAJ3_43_Y,
195 XOR3_7_Y, MAJ3_78_Y, XOR3_55_Y, MAJ3_84_Y, XOR3_82_Y,
196 MAJ3_92_Y, XOR3_22_Y, MAJ3_94_Y, XOR3_93_Y, MAJ3_24_Y,
197 XOR3_94_Y, MAJ3_77_Y, XOR3_88_Y, MAJ3_53_Y, XOR3_42_Y,
198 MAJ3_42_Y, XOR3_32_Y, MAJ3_86_Y, XOR3_15_Y, MAJ3_25_Y,
199 XOR3_51_Y, MAJ3_5_Y, XOR3_21_Y, MAJ3_65_Y, XOR3_2_Y,
200 MAJ3_61_Y, XOR3_11_Y, MAJ3_13_Y, XOR3_73_Y, MAJ3_83_Y,
201 XOR3_16_Y, MAJ3_1_Y, XOR3_89_Y, MAJ3_34_Y, XOR3_4_Y,
202 MAJ3_8_Y, XOR3_86_Y, MAJ3_95_Y, XOR3_59_Y, MAJ3_75_Y,
203 XOR3_45_Y, MAJ3_74_Y, BUFF_33_Y, BUFF_11_Y, BUFF_24_Y,
204 BUFF_39_Y, BUFF_31_Y, BUFF_29_Y, BUFF_32_Y, BUFF_6_Y,
205 BUFF_45_Y, BUFF_3_Y, BUFF_53_Y, BUFF_40_Y, BUFF_10_Y,
206 BUFF_16_Y, BUFF_8_Y, BUFF_52_Y, BUFF_17_Y, BUFF_22_Y,
207 BUFF_13_Y, BUFF_44_Y, BUFF_50_Y, BUFF_12_Y, BUFF_49_Y,
208 BUFF_18_Y, BUFF_28_Y, BUFF_2_Y, BUFF_19_Y, BUFF_36_Y,
209 BUFF_1_Y, BUFF_35_Y, BUFF_54_Y, BUFF_47_Y, BUFF_55_Y,
210 BUFF_48_Y, BUFF_25_Y, XOR2_86_Y, XOR2_70_Y, AO1_59_Y,
211 XOR2_56_Y, NOR2_17_Y, MX2_86_Y, AND2_163_Y, MX2_64_Y,
212 AND2_137_Y, MX2_102_Y, AND2_136_Y, MX2_41_Y, AND2_256_Y,
213 MX2_15_Y, XNOR2_3_Y, XOR2_51_Y, NOR2_1_Y, AND2_134_Y,
214 MX2_122_Y, AND2_244_Y, MX2_72_Y, AND2_151_Y, MX2_98_Y,
215 AND2_161_Y, MX2_53_Y, AND2_139_Y, MX2_39_Y, AND2_78_Y,
216 MX2_16_Y, XNOR2_4_Y, XOR2_66_Y, NOR2_6_Y, AND2_110_Y,
217 MX2_23_Y, AND2_230_Y, MX2_119_Y, AND2_149_Y, AND2_215_Y,
218 MX2_113_Y, AND2_118_Y, MX2_1_Y, AND2_218_Y, MX2_112_Y,
219 XNOR2_5_Y, OR3_3_Y, AND3_5_Y, BUFF_20_Y, BUFF_9_Y,
220 BUFF_43_Y, XOR2_2_Y, XOR2_33_Y, AO1_77_Y, XOR2_31_Y,
221 NOR2_0_Y, MX2_79_Y, AND2_111_Y, MX2_12_Y, AND2_17_Y,
222 MX2_58_Y, AND2_127_Y, MX2_25_Y, AND2_43_Y, MX2_6_Y,
223 XNOR2_7_Y, XOR2_15_Y, NOR2_12_Y, AND2_91_Y, MX2_50_Y,
224 AND2_22_Y, MX2_109_Y, AND2_116_Y, MX2_54_Y, AND2_64_Y,
225 MX2_45_Y, AND2_185_Y, MX2_105_Y, AND2_167_Y, MX2_40_Y,
226 XNOR2_15_Y, XOR2_65_Y, NOR2_9_Y, AND2_65_Y, MX2_22_Y,
227 AND2_52_Y, MX2_91_Y, AND2_101_Y, AND2_82_Y, MX2_77_Y,
228 AND2_175_Y, MX2_71_Y, AND2_227_Y, MX2_27_Y, XNOR2_0_Y,
229 OR3_0_Y, AND3_3_Y, BUFF_21_Y, BUFF_14_Y, BUFF_46_Y,
230 XOR2_99_Y, XOR2_47_Y, AO1_73_Y, XOR2_17_Y, NOR2_2_Y,
231 MX2_11_Y, AND2_120_Y, MX2_13_Y, AND2_20_Y, MX2_3_Y,
232 AND2_232_Y, MX2_7_Y, AND2_150_Y, MX2_42_Y, XNOR2_10_Y,
233 XOR2_14_Y, NOR2_15_Y, AND2_143_Y, MX2_83_Y, AND2_222_Y,
234 MX2_19_Y, AND2_221_Y, MX2_61_Y, AND2_223_Y, MX2_60_Y,
235 AND2_71_Y, MX2_66_Y, AND2_211_Y, MX2_88_Y, XNOR2_20_Y,
236 XOR2_58_Y, NOR2_18_Y, AND2_255_Y, MX2_65_Y, AND2_236_Y,
237 MX2_52_Y, AND2_79_Y, AND2_193_Y, MX2_124_Y, AND2_45_Y,
238 MX2_36_Y, AND2_77_Y, MX2_56_Y, XNOR2_16_Y, OR3_2_Y,
239 AND3_6_Y, BUFF_30_Y, BUFF_27_Y, BUFF_0_Y, XOR2_62_Y,
240 XOR2_92_Y, AND2A_0_Y, MX2_55_Y, AND2_169_Y, MX2_38_Y,
241 AND2_36_Y, MX2_14_Y, AND2_113_Y, MX2_47_Y, AND2_201_Y,
242 MX2_97_Y, AND2A_2_Y, AND2_162_Y, MX2_75_Y, AND2_180_Y,
243 MX2_9_Y, AND2_141_Y, MX2_18_Y, AND2_86_Y, MX2_80_Y,
244 AND2_98_Y, MX2_100_Y, AND2_203_Y, MX2_81_Y, AND2A_1_Y,
245 AND2_192_Y, MX2_87_Y, AND2_30_Y, MX2_99_Y, AND2_19_Y,
246 AND2_114_Y, MX2_90_Y, AND2_108_Y, MX2_0_Y, AND2_83_Y,
247 MX2_35_Y, OR3_1_Y, AND3_1_Y, BUFF_26_Y, BUFF_23_Y,
248 BUFF_51_Y, XOR2_45_Y, XOR2_38_Y, AO1_31_Y, XOR2_89_Y,
249 NOR2_7_Y, MX2_30_Y, AND2_146_Y, MX2_57_Y, AND2_246_Y,
250 MX2_5_Y, AND2_258_Y, MX2_20_Y, AND2_63_Y, MX2_46_Y,
251 XNOR2_13_Y, XOR2_81_Y, NOR2_4_Y, AND2_181_Y, MX2_70_Y,
252 AND2_90_Y, MX2_32_Y, AND2_138_Y, MX2_48_Y, AND2_23_Y,
253 MX2_121_Y, AND2_38_Y, MX2_37_Y, AND2_254_Y, MX2_26_Y,
254 XNOR2_1_Y, XOR2_5_Y, NOR2_16_Y, AND2_4_Y, MX2_94_Y,
255 AND2_3_Y, MX2_117_Y, AND2_245_Y, AND2_24_Y, MX2_107_Y,
256 AND2_251_Y, MX2_73_Y, AND2_187_Y, MX2_43_Y, XNOR2_19_Y,
257 OR3_4_Y, AND3_7_Y, BUFF_41_Y, BUFF_37_Y, BUFF_7_Y,
258 XOR2_0_Y, XOR2_74_Y, AO1_4_Y, XOR2_1_Y, NOR2_14_Y,
259 MX2_44_Y, AND2_204_Y, MX2_63_Y, AND2_224_Y, MX2_96_Y,
260 AND2_188_Y, MX2_110_Y, AND2_67_Y, MX2_85_Y, XNOR2_6_Y,
261 XOR2_35_Y, NOR2_13_Y, AND2_46_Y, MX2_89_Y, AND2_240_Y,
262 MX2_17_Y, AND2_87_Y, MX2_74_Y, AND2_205_Y, MX2_126_Y,
263 AND2_13_Y, MX2_106_Y, AND2_209_Y, MX2_2_Y, XNOR2_9_Y,
264 XOR2_63_Y, NOR2_3_Y, AND2_119_Y, MX2_104_Y, AND2_35_Y,
265 MX2_10_Y, AND2_109_Y, AND2_106_Y, MX2_59_Y, AND2_156_Y,
266 MX2_125_Y, AND2_252_Y, MX2_93_Y, XNOR2_18_Y, OR3_7_Y,
267 AND3_0_Y, BUFF_15_Y, BUFF_5_Y, BUFF_42_Y, XOR2_49_Y,
268 XOR2_61_Y, AO1_14_Y, XOR2_59_Y, NOR2_20_Y, MX2_28_Y,
269 AND2_123_Y, MX2_118_Y, AND2_10_Y, MX2_4_Y, AND2_142_Y,
270 MX2_82_Y, AND2_129_Y, MX2_103_Y, XNOR2_17_Y, XOR2_109_Y,
271 NOR2_10_Y, AND2_88_Y, MX2_67_Y, AND2_183_Y, MX2_111_Y,
272 AND2_202_Y, MX2_62_Y, AND2_85_Y, MX2_95_Y, AND2_148_Y,
273 MX2_101_Y, AND2_27_Y, MX2_69_Y, XNOR2_14_Y, XOR2_26_Y,
274 NOR2_5_Y, AND2_239_Y, MX2_78_Y, AND2_6_Y, MX2_123_Y,
275 AND2_144_Y, AND2_73_Y, MX2_92_Y, AND2_122_Y, MX2_34_Y,
276 AND2_257_Y, MX2_33_Y, XNOR2_2_Y, OR3_5_Y, AND3_4_Y,
277 BUFF_38_Y, BUFF_34_Y, BUFF_4_Y, XOR2_34_Y, XOR2_80_Y,
278 AO1_17_Y, XOR2_78_Y, NOR2_8_Y, MX2_21_Y, AND2_158_Y,
279 MX2_29_Y, AND2_2_Y, MX2_116_Y, AND2_72_Y, MX2_108_Y,
280 AND2_206_Y, MX2_127_Y, XNOR2_8_Y, XOR2_11_Y, NOR2_11_Y,
281 AND2_0_Y, MX2_120_Y, AND2_32_Y, MX2_114_Y, AND2_173_Y,
282 MX2_51_Y, AND2_107_Y, MX2_8_Y, AND2_145_Y, MX2_84_Y,
283 AND2_217_Y, MX2_24_Y, XNOR2_11_Y, XOR2_105_Y, NOR2_19_Y,
284 AND2_165_Y, MX2_68_Y, AND2_128_Y, MX2_49_Y, AND2_21_Y,
285 AND2_186_Y, MX2_31_Y, AND2_75_Y, MX2_115_Y, AND2_54_Y,
286 MX2_76_Y, XNOR2_12_Y, OR3_6_Y, AND3_2_Y, AND2_8_Y,
287 AND2_16_Y, AND2_11_Y, AND2_171_Y, AND2_94_Y, AND2_147_Y,
288 AND2_133_Y, AND2_184_Y, AND2_74_Y, AND2_241_Y, AND2_164_Y,
289 AND2_194_Y, AND2_126_Y, AND2_253_Y, AND2_42_Y, AND2_76_Y,
290 AND2_12_Y, AND2_51_Y, AND2_189_Y, AND2_5_Y, AND2_196_Y,
291 AND2_216_Y, AND2_170_Y, AND2_18_Y, AND2_62_Y, AND2_96_Y,
292 AND2_40_Y, AND2_70_Y, AND2_214_Y, AND2_84_Y, XOR2_111_Y,
293 XOR2_72_Y, XOR2_107_Y, XOR2_98_Y, XOR2_93_Y, XOR2_76_Y,
294 XOR2_68_Y, XOR2_48_Y, XOR2_30_Y, XOR2_25_Y, XOR2_40_Y,
295 XOR2_113_Y, XOR2_102_Y, XOR2_42_Y, XOR2_67_Y, XOR2_24_Y,
296 XOR2_84_Y, XOR2_46_Y, XOR2_8_Y, XOR2_53_Y, XOR2_83_Y,
297 XOR2_28_Y, XOR2_13_Y, XOR2_85_Y, XOR2_103_Y, XOR2_60_Y,
298 XOR2_4_Y, XOR2_90_Y, XOR2_37_Y, XOR2_96_Y, XOR2_77_Y,
299 AND2_34_Y, AO1_69_Y, AND2_226_Y, AO1_76_Y, AND2_55_Y,
300 AO1_13_Y, AND2_135_Y, AO1_87_Y, AND2_168_Y, AO1_61_Y,
301 AND2_199_Y, AO1_0_Y, AND2_177_Y, AO1_20_Y, AND2_237_Y,
302 AO1_84_Y, AND2_131_Y, AO1_6_Y, AND2_249_Y, AO1_33_Y,
303 AND2_182_Y, AO1_9_Y, AND2_93_Y, AO1_66_Y, AND2_210_Y,
304 AO1_36_Y, AND2_33_Y, AO1_64_Y, AND2_50_Y, AND2_69_Y,
305 AND2_58_Y, AO1_52_Y, AND2_105_Y, AO1_90_Y, AND2_29_Y,
306 AO1_82_Y, AND2_247_Y, AO1_38_Y, AND2_179_Y, AO1_11_Y,
307 AND2_92_Y, AO1_68_Y, AND2_207_Y, AO1_41_Y, AND2_31_Y,
308 AO1_67_Y, AND2_47_Y, AO1_55_Y, AND2_66_Y, AO1_29_Y,
309 AND2_57_Y, AO1_58_Y, AND2_104_Y, AO1_3_Y, AND2_25_Y,
310 AO1_86_Y, AND2_198_Y, AO1_21_Y, AND2_103_Y, AO1_89_Y,
311 AND2_44_Y, AO1_49_Y, AND2_125_Y, AND2_235_Y, AND2_248_Y,
312 AND2_15_Y, AND2_1_Y, AO1_40_Y, AND2_59_Y, AO1_75_Y,
313 AND2_231_Y, AO1_70_Y, AND2_80_Y, AO1_28_Y, AND2_14_Y,
314 AO1_5_Y, AND2_212_Y, AO1_60_Y, AND2_37_Y, AO1_30_Y,
315 AND2_115_Y, AO1_57_Y, AND2_140_Y, AO1_43_Y, AND2_176_Y,
316 AO1_18_Y, AND2_157_Y, AO1_44_Y, AND2_219_Y, AO1_85_Y,
317 AND2_112_Y, AO1_74_Y, AND2_190_Y, AO1_32_Y, AND2_97_Y,
318 AND2_39_Y, AND2_117_Y, AND2_228_Y, AND2_242_Y, AND2_7_Y,
319 AND2_250_Y, AND2_53_Y, AND2_225_Y, AO1_80_Y, AND2_100_Y,
320 AO1_25_Y, AND2_41_Y, AO1_1_Y, AND2_234_Y, AO1_54_Y,
321 AND2_61_Y, AO1_26_Y, AND2_155_Y, AO1_50_Y, AND2_178_Y,
322 AO1_39_Y, AND2_208_Y, AO1_16_Y, AND2_191_Y, AO1_42_Y,
323 AND2_243_Y, AO1_81_Y, AND2_152_Y, AND2_213_Y, AND2_220_Y,
324 AND2_153_Y, AND2_89_Y, AND2_159_Y, AND2_60_Y, AND2_195_Y,
325 AND2_172_Y, AND2_200_Y, AND2_130_Y, AND2_160_Y,
326 AND2_174_Y, AND2_95_Y, AND2_49_Y, AO1_56_Y, AND2_99_Y,
327 AND2_102_Y, AO1_62_Y, AO1_48_Y, AO1_23_Y, AO1_24_Y,
328 AO1_47_Y, AO1_37_Y, AO1_15_Y, AO1_8_Y, AO1_65_Y, AO1_34_Y,
329 AO1_63_Y, AO1_46_Y, AO1_22_Y, AO1_51_Y, AO1_88_Y,
330 AO1_72_Y, AO1_79_Y, AO1_45_Y, AO1_12_Y, AO1_83_Y,
331 AO1_10_Y, AO1_2_Y, AO1_71_Y, AO1_7_Y, AO1_35_Y, AO1_27_Y,
332 AO1_53_Y, AO1_19_Y, AO1_78_Y, XOR2_9_Y, XOR2_97_Y,
333 XOR2_112_Y, XOR2_29_Y, XOR2_50_Y, XOR2_108_Y, XOR2_73_Y,
334 XOR2_94_Y, XOR2_12_Y, XOR2_110_Y, XOR2_39_Y, XOR2_10_Y,
335 XOR2_27_Y, XOR2_71_Y, XOR2_64_Y, XOR2_3_Y, XOR2_82_Y,
336 XOR2_101_Y, XOR2_21_Y, XOR2_69_Y, XOR2_6_Y, XOR2_87_Y,
337 XOR2_104_Y, XOR2_23_Y, XOR2_20_Y, XOR2_75_Y, XOR2_36_Y,
338 XOR2_54_Y, XOR2_100_Y, XOR2_32_Y, VCC_1_net, GND_1_net : std_logic ;
339 begin
340
341 VCC_2_net : VCC port map(Y => VCC_1_net);
342 GND_2_net : GND port map(Y => GND_1_net);
343 BUFF_8 : BUFF
344 port map(A => DataA(7), Y => BUFF_8_Y);
345 DFN1_40 : DFN1
346 port map(D => S_6_net, CLK => Clock, Q => DFN1_40_Q);
347 MX2_113 : MX2
348 port map(A => AND2_215_Y, B => BUFF_3_Y, S => NOR2_6_Y,
349 Y => MX2_113_Y);
350 XOR2_PP7_9_inst : XOR2
351 port map(A => MX2_26_Y, B => BUFF_23_Y, Y => PP7_9_net);
352 DFN1_146 : DFN1
353 port map(D => PP7_7_net, CLK => Clock, Q => DFN1_146_Q);
354 XOR2_Mult_8_inst : XOR2
355 port map(A => XOR2_73_Y, B => AO1_37_Y, Y => Mult(8));
356 DFN1_24 : DFN1
357 port map(D => PP4_8_net, CLK => Clock, Q => DFN1_24_Q);
358 XOR2_Mult_29_inst : XOR2
359 port map(A => XOR2_54_Y, B => AO1_53_Y, Y => Mult(29));
360 AND2_12 : AND2
361 port map(A => SumA_17_net, B => SumB_17_net, Y => AND2_12_Y);
362 AO1_23 : AO1
363 port map(A => AND2_226_Y, B => AO1_62_Y, C => AO1_69_Y,
364 Y => AO1_23_Y);
365 MAJ3_9 : MAJ3
366 port map(A => XOR3_52_Y, B => MAJ3_72_Y, C => XOR2_52_Y,
367 Y => MAJ3_9_Y);
368 AND2_72 : AND2
369 port map(A => XOR2_78_Y, B => BUFF_1_Y, Y => AND2_72_Y);
370 AND2_158 : AND2
371 port map(A => XOR2_78_Y, B => BUFF_19_Y, Y => AND2_158_Y);
372 MX2_PP1_16_inst : MX2
373 port map(A => MX2_11_Y, B => AO1_73_Y, S => NOR2_2_Y, Y =>
374 PP1_16_net);
375 MAJ3_17 : MAJ3
376 port map(A => DFN1_139_Q, B => DFN1_13_Q, C => DFN1_95_Q,
377 Y => MAJ3_17_Y);
378 XNOR2_19 : XNOR2
379 port map(A => DataB(14), B => BUFF_26_Y, Y => XNOR2_19_Y);
380 AND2_225 : AND2
381 port map(A => AND2_59_Y, B => AND2_37_Y, Y => AND2_225_Y);
382 DFN1_149 : DFN1
383 port map(D => S_5_net, CLK => Clock, Q => DFN1_149_Q);
384 MAJ3_62 : MAJ3
385 port map(A => XOR2_22_Y, B => DFN1_132_Q, C => DFN1_81_Q,
386 Y => MAJ3_62_Y);
387 XOR2_58 : XOR2
388 port map(A => DataB(1), B => DataB(2), Y => XOR2_58_Y);
389 XOR2_Mult_13_inst : XOR2
390 port map(A => XOR2_10_Y, B => AO1_63_Y, Y => Mult(13));
391 XOR2_Mult_2_inst : XOR2
392 port map(A => XOR2_9_Y, B => AND2_102_Y, Y => Mult(2));
393 MAJ3_52 : MAJ3
394 port map(A => XOR3_28_Y, B => MAJ3_80_Y, C => AND2_26_Y,
395 Y => MAJ3_52_Y);
396 DFN1_78 : DFN1
397 port map(D => PP1_6_net, CLK => Clock, Q => DFN1_78_Q);
398 XOR3_21 : XOR3
399 port map(A => AND2_81_Y, B => DFN1_127_Q, C => XOR3_79_Y,
400 Y => XOR3_21_Y);
401 DFN1_94 : DFN1
402 port map(D => PP1_16_net, CLK => Clock, Q => DFN1_94_Q);
403 AND2_232 : AND2
404 port map(A => XOR2_17_Y, B => BUFF_1_Y, Y => AND2_232_Y);
405 NOR2_15 : NOR2
406 port map(A => XOR2_14_Y, B => XNOR2_20_Y, Y => NOR2_15_Y);
407 XOR2_PP0_13_inst : XOR2
408 port map(A => MX2_38_Y, B => BUFF_0_Y, Y => PP0_13_net);
409 XOR2_PP5_4_inst : XOR2
410 port map(A => MX2_23_Y, B => BUFF_55_Y, Y => PP5_4_net);
411 AND2_49 : AND2
412 port map(A => AND2_234_Y, B => AND2_243_Y, Y => AND2_49_Y);
413 AND2_23 : AND2
414 port map(A => XOR2_81_Y, B => BUFF_18_Y, Y => AND2_23_Y);
415 XOR3_7 : XOR3
416 port map(A => MAJ3_46_Y, B => XOR2_106_Y, C => XOR3_78_Y,
417 Y => XOR3_7_Y);
418 XOR3_18 : XOR3
419 port map(A => MAJ3_66_Y, B => MAJ3_9_Y, C => XOR3_43_Y,
420 Y => XOR3_18_Y);
421 AO1_22 : AO1
422 port map(A => AND2_14_Y, B => AO1_40_Y, C => AO1_28_Y, Y =>
423 AO1_22_Y);
424 XOR2_40 : XOR2
425 port map(A => SumA_10_net, B => SumB_10_net, Y => XOR2_40_Y);
426 NOR2_12 : NOR2
427 port map(A => XOR2_15_Y, B => XNOR2_15_Y, Y => NOR2_12_Y);
428 AND2_91 : AND2
429 port map(A => XOR2_15_Y, B => BUFF_12_Y, Y => AND2_91_Y);
430 DFN1_SumB_30_inst : DFN1
431 port map(D => AND2_166_Y, CLK => Clock, Q => SumB_30_net);
432 XOR3_31 : XOR3
433 port map(A => DFN1_113_Q, B => DFN1_100_Q, C => XOR2_88_Y,
434 Y => XOR3_31_Y);
435 AND2_248 : AND2
436 port map(A => AND2_58_Y, B => AND2_55_Y, Y => AND2_248_Y);
437 MAJ3_31 : MAJ3
438 port map(A => XOR3_69_Y, B => MAJ3_59_Y, C => AND2_154_Y,
439 Y => MAJ3_31_Y);
440 XOR2_PP6_6_inst : XOR2
441 port map(A => MX2_54_Y, B => BUFF_9_Y, Y => PP6_6_net);
442 BUFF_7 : BUFF
443 port map(A => DataB(9), Y => BUFF_7_Y);
444 XOR3_82 : XOR3
445 port map(A => MAJ3_88_Y, B => XOR3_53_Y, C => XOR3_41_Y,
446 Y => XOR3_82_Y);
447 AO1_54 : AO1
448 port map(A => XOR2_103_Y, B => AO1_18_Y, C => AND2_18_Y,
449 Y => AO1_54_Y);
450 MAJ3_44 : MAJ3
451 port map(A => XOR3_83_Y, B => MAJ3_14_Y, C => MAJ3_26_Y,
452 Y => MAJ3_44_Y);
453 DFN1_SumA_1_inst : DFN1
454 port map(D => DFN1_25_Q, CLK => Clock, Q => SumA_1_net);
455 XOR2_PP6_4_inst : XOR2
456 port map(A => MX2_22_Y, B => BUFF_20_Y, Y => PP6_4_net);
457 XOR2_PP5_13_inst : XOR2
458 port map(A => MX2_64_Y, B => BUFF_25_Y, Y => PP5_13_net);
459 AND2_184 : AND2
460 port map(A => SumA_8_net, B => SumB_8_net, Y => AND2_184_Y);
461 XOR2_PP6_10_inst : XOR2
462 port map(A => MX2_50_Y, B => BUFF_9_Y, Y => PP6_10_net);
463 MX2_124 : MX2
464 port map(A => AND2_193_Y, B => BUFF_45_Y, S => NOR2_18_Y,
465 Y => MX2_124_Y);
466 AO1_84 : AO1
467 port map(A => XOR2_46_Y, B => AND2_76_Y, C => AND2_12_Y,
468 Y => AO1_84_Y);
469 DFN1_117 : DFN1
470 port map(D => PP0_0_net, CLK => Clock, Q => DFN1_117_Q);
471 MX2_89 : MX2
472 port map(A => AND2_46_Y, B => BUFF_44_Y, S => NOR2_13_Y,
473 Y => MX2_89_Y);
474 DFN1_4 : DFN1
475 port map(D => PP6_16_net, CLK => Clock, Q => DFN1_4_Q);
476 OR3_6 : OR3
477 port map(A => DataB(3), B => DataB(4), C => DataB(5), Y =>
478 OR3_6_Y);
479 AND2_69 : AND2
480 port map(A => AND2_34_Y, B => XOR2_107_Y, Y => AND2_69_Y);
481 MX2_37 : MX2
482 port map(A => AND2_38_Y, B => BUFF_52_Y, S => NOR2_4_Y,
483 Y => MX2_37_Y);
484 XOR2_92 : XOR2
485 port map(A => BUFF_54_Y, B => DataB(1), Y => XOR2_92_Y);
486 MX2_54 : MX2
487 port map(A => AND2_116_Y, B => BUFF_40_Y, S => NOR2_12_Y,
488 Y => MX2_54_Y);
489 MX2_75 : MX2
490 port map(A => AND2_162_Y, B => BUFF_13_Y, S => AND2A_2_Y,
491 Y => MX2_75_Y);
492 DFN1_SumA_30_inst : DFN1
493 port map(D => DFN1_116_Q, CLK => Clock, Q => SumA_30_net);
494 AND2_55 : AND2
495 port map(A => XOR2_93_Y, B => XOR2_76_Y, Y => AND2_55_Y);
496 XOR2_Mult_10_inst : XOR2
497 port map(A => XOR2_12_Y, B => AO1_8_Y, Y => Mult(10));
498 MX2_112 : MX2
499 port map(A => AND2_218_Y, B => BUFF_29_Y, S => NOR2_6_Y,
500 Y => MX2_112_Y);
501 MX2_23 : MX2
502 port map(A => AND2_110_Y, B => BUFF_6_Y, S => NOR2_6_Y,
503 Y => MX2_23_Y);
504 MX2_94 : MX2
505 port map(A => AND2_4_Y, B => BUFF_6_Y, S => NOR2_16_Y, Y =>
506 MX2_94_Y);
507 MAJ3_19 : MAJ3
508 port map(A => XOR3_90_Y, B => MAJ3_63_Y, C => XOR2_95_Y,
509 Y => MAJ3_19_Y);
510 XOR2_PP2_4_inst : XOR2
511 port map(A => MX2_68_Y, B => BUFF_38_Y, Y => PP2_4_net);
512 MAJ3_18 : MAJ3
513 port map(A => XOR3_56_Y, B => MAJ3_41_Y, C => XOR3_37_Y,
514 Y => MAJ3_18_Y);
515 AND2_181 : AND2
516 port map(A => XOR2_81_Y, B => BUFF_12_Y, Y => AND2_181_Y);
517 DFN1_SumA_24_inst : DFN1
518 port map(D => MAJ3_64_Y, CLK => Clock, Q => SumA_24_net);
519 MX2_65 : MX2
520 port map(A => AND2_255_Y, B => BUFF_32_Y, S => NOR2_18_Y,
521 Y => MX2_65_Y);
522 MX2_1 : MX2
523 port map(A => AND2_118_Y, B => BUFF_39_Y, S => NOR2_6_Y,
524 Y => MX2_1_Y);
525 DFN1_SumB_18_inst : DFN1
526 port map(D => XOR3_4_Y, CLK => Clock, Q => SumB_18_net);
527 XOR3_86 : XOR3
528 port map(A => MAJ3_37_Y, B => XOR3_62_Y, C => XOR3_96_Y,
529 Y => XOR3_86_Y);
530 DFN1_73 : DFN1
531 port map(D => PP0_15_net, CLK => Clock, Q => DFN1_73_Q);
532 DFN1_142 : DFN1
533 port map(D => S_3_net, CLK => Clock, Q => DFN1_142_Q);
534 XOR2_PP2_11_inst : XOR2
535 port map(A => MX2_8_Y, B => BUFF_34_Y, Y => PP2_11_net);
536 DFN1_140 : DFN1
537 port map(D => PP0_12_net, CLK => Clock, Q => DFN1_140_Q);
538 AND2_96 : AND2
539 port map(A => SumA_26_net, B => SumB_26_net, Y => AND2_96_Y);
540 AND2_253 : AND2
541 port map(A => SumA_14_net, B => SumB_14_net, Y =>
542 AND2_253_Y);
543 AO1_59 : AO1
544 port map(A => XOR2_70_Y, B => OR3_3_Y, C => AND3_5_Y, Y =>
545 AO1_59_Y);
546 XOR2_Mult_12_inst : XOR2
547 port map(A => XOR2_39_Y, B => AO1_34_Y, Y => Mult(12));
548 XOR2_71 : XOR2
549 port map(A => SumA_14_net, B => SumB_14_net, Y => XOR2_71_Y);
550 AND2_146 : AND2
551 port map(A => XOR2_89_Y, B => BUFF_36_Y, Y => AND2_146_Y);
552 XOR3_94 : XOR3
553 port map(A => DFN1_26_Q, B => DFN1_65_Q, C => AND2_28_Y,
554 Y => XOR3_94_Y);
555 DFN1_138 : DFN1
556 port map(D => PP4_5_net, CLK => Clock, Q => DFN1_138_Q);
557 AND2_18 : AND2
558 port map(A => SumA_24_net, B => SumB_24_net, Y => AND2_18_Y);
559 MAJ3_21 : MAJ3
560 port map(A => DFN1_19_Q, B => DFN1_59_Q, C => DFN1_10_Q,
561 Y => MAJ3_21_Y);
562 XOR2_PP1_15_inst : XOR2
563 port map(A => MX2_42_Y, B => BUFF_46_Y, Y => PP1_15_net);
564 BUFF_12 : BUFF
565 port map(A => DataA(10), Y => BUFF_12_Y);
566 XOR2_96 : XOR2
567 port map(A => SumA_29_net, B => SumB_29_net, Y => XOR2_96_Y);
568 AND2_78 : AND2
569 port map(A => XOR2_51_Y, B => BUFF_44_Y, Y => AND2_78_Y);
570 AO1_30 : AO1
571 port map(A => XOR2_83_Y, B => AO1_29_Y, C => AND2_5_Y, Y =>
572 AO1_30_Y);
573 AO1_89 : AO1
574 port map(A => AND2_33_Y, B => AO1_66_Y, C => AO1_36_Y, Y =>
575 AO1_89_Y);
576 DFN1_SumA_5_inst : DFN1
577 port map(D => MAJ3_42_Y, CLK => Clock, Q => SumA_5_net);
578 DFN1_SumA_29_inst : DFN1
579 port map(D => XOR2_18_Y, CLK => Clock, Q => SumA_29_net);
580 AND2_138 : AND2
581 port map(A => XOR2_81_Y, B => BUFF_16_Y, Y => AND2_138_Y);
582 XNOR2_4 : XNOR2
583 port map(A => DataB(10), B => BUFF_48_Y, Y => XNOR2_4_Y);
584 XOR2_PP4_7_inst : XOR2
585 port map(A => MX2_17_Y, B => BUFF_37_Y, Y => PP4_7_net);
586 AND2_40 : AND2
587 port map(A => SumA_27_net, B => SumB_27_net, Y => AND2_40_Y);
588 MX2_121 : MX2
589 port map(A => AND2_23_Y, B => BUFF_12_Y, S => NOR2_4_Y,
590 Y => MX2_121_Y);
591 BUFF_33 : BUFF
592 port map(A => DataA(0), Y => BUFF_33_Y);
593 BUFF_31 : BUFF
594 port map(A => DataA(2), Y => BUFF_31_Y);
595 MX2_100 : MX2
596 port map(A => AND2_98_Y, B => BUFF_8_Y, S => AND2A_2_Y,
597 Y => MX2_100_Y);
598 MAJ3_84 : MAJ3
599 port map(A => XOR3_47_Y, B => MAJ3_2_Y, C => XOR3_24_Y,
600 Y => MAJ3_84_Y);
601 XOR2_24 : XOR2
602 port map(A => SumA_15_net, B => SumB_15_net, Y => XOR2_24_Y);
603 MAJ3_71 : MAJ3
604 port map(A => DFN1_104_Q, B => DFN1_32_Q, C => DFN1_71_Q,
605 Y => MAJ3_71_Y);
606 AND2_153 : AND2
607 port map(A => AND2_225_Y, B => AND2_66_Y, Y => AND2_153_Y);
608 AO1_71 : AO1
609 port map(A => AND2_157_Y, B => AO1_80_Y, C => AO1_18_Y,
610 Y => AO1_71_Y);
611 BUFF_22 : BUFF
612 port map(A => DataA(8), Y => BUFF_22_Y);
613 XOR2_34 : XOR2
614 port map(A => AND2_21_Y, B => BUFF_38_Y, Y => XOR2_34_Y);
615 AND2_32 : AND2
616 port map(A => XOR2_11_Y, B => BUFF_8_Y, Y => AND2_32_Y);
617 XOR2_PP2_14_inst : XOR2
618 port map(A => MX2_108_Y, B => BUFF_4_Y, Y => PP2_14_net);
619 AO1_66 : AO1
620 port map(A => XOR2_60_Y, B => AND2_18_Y, C => AND2_62_Y,
621 Y => AO1_66_Y);
622 AND2_201 : AND2
623 port map(A => DataB(0), B => BUFF_54_Y, Y => AND2_201_Y);
624 AND2_60 : AND2
625 port map(A => AND2_100_Y, B => AND2_140_Y, Y => AND2_60_Y);
626 MAJ3_96 : MAJ3
627 port map(A => XOR3_77_Y, B => MAJ3_15_Y, C => MAJ3_50_Y,
628 Y => MAJ3_96_Y);
629 OR3_4 : OR3
630 port map(A => DataB(13), B => DataB(14), C => DataB(15),
631 Y => OR3_4_Y);
632 XOR2_PP3_0_inst : XOR2
633 port map(A => XOR2_49_Y, B => DataB(7), Y => PP3_0_net);
634 MX2_0 : MX2
635 port map(A => AND2_108_Y, B => BUFF_24_Y, S => AND2A_1_Y,
636 Y => MX2_0_Y);
637 XOR2_43 : XOR2
638 port map(A => DFN1_138_Q, B => DFN1_98_Q, Y => XOR2_43_Y);
639 DFN1_47 : DFN1
640 port map(D => PP7_16_net, CLK => Clock, Q => DFN1_47_Q);
641 DFN1_46 : DFN1
642 port map(D => PP4_6_net, CLK => Clock, Q => DFN1_46_Q);
643 BUFF_4 : BUFF
644 port map(A => DataB(5), Y => BUFF_4_Y);
645 XOR2_61 : XOR2
646 port map(A => BUFF_54_Y, B => DataB(7), Y => XOR2_61_Y);
647 BUFF_48 : BUFF
648 port map(A => DataB(11), Y => BUFF_48_Y);
649 XOR2_49 : XOR2
650 port map(A => AND2_144_Y, B => BUFF_15_Y, Y => XOR2_49_Y);
651 XNOR2_2 : XNOR2
652 port map(A => DataB(6), B => BUFF_15_Y, Y => XNOR2_2_Y);
653 DFN1_11 : DFN1
654 port map(D => PP3_12_net, CLK => Clock, Q => DFN1_11_Q);
655 AND2_85 : AND2
656 port map(A => XOR2_109_Y, B => BUFF_49_Y, Y => AND2_85_Y);
657 AND2_147 : AND2
658 port map(A => SumA_6_net, B => SumB_6_net, Y => AND2_147_Y);
659 AND2_209 : AND2
660 port map(A => XOR2_35_Y, B => BUFF_44_Y, Y => AND2_209_Y);
661 AO1_35 : AO1
662 port map(A => AND2_155_Y, B => AO1_25_Y, C => AO1_26_Y,
663 Y => AO1_35_Y);
664 AO1_27 : AO1
665 port map(A => AND2_178_Y, B => AO1_25_Y, C => AO1_50_Y,
666 Y => AO1_27_Y);
667 MX2_21 : MX2
668 port map(A => BUFF_4_Y, B => XOR2_80_Y, S => XOR2_78_Y,
669 Y => MX2_21_Y);
670 AND2_53 : AND2
671 port map(A => AND2_59_Y, B => AND2_212_Y, Y => AND2_53_Y);
672 XOR3_22 : XOR3
673 port map(A => MAJ3_33_Y, B => AND2_132_Y, C => XOR3_67_Y,
674 Y => XOR3_22_Y);
675 AO1_13 : AO1
676 port map(A => XOR2_48_Y, B => AND2_147_Y, C => AND2_133_Y,
677 Y => AO1_13_Y);
678 XOR3_95 : XOR3
679 port map(A => MAJ3_14_Y, B => MAJ3_26_Y, C => XOR3_83_Y,
680 Y => XOR3_95_Y);
681 MX2_14 : MX2
682 port map(A => AND2_36_Y, B => BUFF_49_Y, S => AND2A_0_Y,
683 Y => MX2_14_Y);
684 AND2_174 : AND2
685 port map(A => AND2_41_Y, B => AND2_208_Y, Y => AND2_174_Y);
686 AND2_125 : AND2
687 port map(A => AND2_50_Y, B => XOR2_77_Y, Y => AND2_125_Y);
688 DFN1_49 : DFN1
689 port map(D => PP2_6_net, CLK => Clock, Q => DFN1_49_Q);
690 MX2_33 : MX2
691 port map(A => AND2_257_Y, B => BUFF_31_Y, S => NOR2_5_Y,
692 Y => MX2_33_Y);
693 XOR3_8 : XOR3
694 port map(A => MAJ3_55_Y, B => XOR3_31_Y, C => XOR3_57_Y,
695 Y => XOR3_8_Y);
696 XOR2_PP7_11_inst : XOR2
697 port map(A => MX2_121_Y, B => BUFF_23_Y, Y => PP7_11_net);
698 XOR3_32 : XOR3
699 port map(A => MAJ3_49_Y, B => XOR3_46_Y, C => XOR3_27_Y,
700 Y => XOR3_32_Y);
701 MAJ3_37 : MAJ3
702 port map(A => AND2_121_Y, B => DFN1_58_Q, C => DFN1_50_Q,
703 Y => MAJ3_37_Y);
704 XOR2_Mult_3_inst : XOR2
705 port map(A => XOR2_97_Y, B => AO1_62_Y, Y => Mult(3));
706 MX2_28 : MX2
707 port map(A => BUFF_42_Y, B => XOR2_61_Y, S => XOR2_59_Y,
708 Y => MX2_28_Y);
709 AND2_99 : AND2
710 port map(A => AND2_234_Y, B => AND2_152_Y, Y => AND2_99_Y);
711 XOR2_PP5_1_inst : XOR2
712 port map(A => MX2_119_Y, B => BUFF_55_Y, Y => PP5_1_net);
713 XOR2_47 : XOR2
714 port map(A => BUFF_54_Y, B => DataB(3), Y => XOR2_47_Y);
715 BUFF_53 : BUFF
716 port map(A => DataA(5), Y => BUFF_53_Y);
717 BUFF_51 : BUFF
718 port map(A => DataB(15), Y => BUFF_51_Y);
719 AND2_233 : AND2
720 port map(A => DFN1_138_Q, B => DFN1_98_Q, Y => AND2_233_Y);
721 XOR2_PP4_10_inst : XOR2
722 port map(A => MX2_89_Y, B => BUFF_37_Y, Y => PP4_10_net);
723 AO1_28 : AO1
724 port map(A => AND2_177_Y, B => AO1_68_Y, C => AO1_0_Y, Y =>
725 AO1_28_Y);
726 XOR2_PP3_11_inst : XOR2
727 port map(A => MX2_95_Y, B => BUFF_5_Y, Y => PP3_11_net);
728 XOR2_9 : XOR2
729 port map(A => SumA_1_net, B => SumB_1_net, Y => XOR2_9_Y);
730 AND2_224 : AND2
731 port map(A => XOR2_1_Y, B => BUFF_2_Y, Y => AND2_224_Y);
732 AO1_12 : AO1
733 port map(A => AND2_57_Y, B => AO1_88_Y, C => AO1_29_Y, Y =>
734 AO1_12_Y);
735 MAJ3_61 : MAJ3
736 port map(A => XOR3_17_Y, B => MAJ3_0_Y, C => XOR3_75_Y,
737 Y => MAJ3_61_Y);
738 AND2_171 : AND2
739 port map(A => SumA_4_net, B => SumB_4_net, Y => AND2_171_Y);
740 MAJ3_51 : MAJ3
741 port map(A => XOR3_19_Y, B => XOR2_43_Y, C => DFN1_3_Q,
742 Y => MAJ3_51_Y);
743 AND2_120 : AND2
744 port map(A => XOR2_17_Y, B => BUFF_19_Y, Y => AND2_120_Y);
745 XOR2_25 : XOR2
746 port map(A => SumA_9_net, B => SumB_9_net, Y => XOR2_25_Y);
747 XOR2_Mult_17_inst : XOR2
748 port map(A => XOR2_3_Y, B => AO1_88_Y, Y => Mult(17));
749 XOR2_35 : XOR2
750 port map(A => DataB(7), B => DataB(8), Y => XOR2_35_Y);
751 AND3_0 : AND3
752 port map(A => DataB(7), B => DataB(8), C => DataB(9), Y =>
753 AND3_0_Y);
754 DFN1_151 : DFN1
755 port map(D => PP3_16_net, CLK => Clock, Q => DFN1_151_Q);
756 DFN1_SumA_27_inst : DFN1
757 port map(D => MAJ3_94_Y, CLK => Clock, Q => SumA_27_net);
758 XOR3_26 : XOR3
759 port map(A => DFN1_49_Q, B => DFN1_102_Q, C => DFN1_103_Q,
760 Y => XOR3_26_Y);
761 XOR2_PP4_0_inst : XOR2
762 port map(A => XOR2_0_Y, B => DataB(9), Y => PP4_0_net);
763 XOR2_PP1_1_inst : XOR2
764 port map(A => MX2_52_Y, B => BUFF_21_Y, Y => PP1_1_net);
765 AND2_250 : AND2
766 port map(A => AND2_59_Y, B => AND2_14_Y, Y => AND2_250_Y);
767 MX2_50 : MX2
768 port map(A => AND2_91_Y, B => BUFF_44_Y, S => NOR2_12_Y,
769 Y => MX2_50_Y);
770 MX2_7 : MX2
771 port map(A => AND2_232_Y, B => BUFF_19_Y, S => NOR2_2_Y,
772 Y => MX2_7_Y);
773 DFN1_SumB_5_inst : DFN1
774 port map(D => XOR3_21_Y, CLK => Clock, Q => SumB_5_net);
775 AND2_17 : AND2
776 port map(A => XOR2_31_Y, B => BUFF_2_Y, Y => AND2_17_Y);
777 AND2_114 : AND2
778 port map(A => DataB(0), B => BUFF_53_Y, Y => AND2_114_Y);
779 DFN1_SumA_22_inst : DFN1
780 port map(D => MAJ3_79_Y, CLK => Clock, Q => SumA_22_net);
781 XOR3_36 : XOR3
782 port map(A => DFN1_78_Q, B => DFN1_97_Q, C => DFN1_145_Q,
783 Y => XOR3_36_Y);
784 AND2_77 : AND2
785 port map(A => XOR2_58_Y, B => BUFF_32_Y, Y => AND2_77_Y);
786 XOR2_PP7_14_inst : XOR2
787 port map(A => MX2_20_Y, B => BUFF_51_Y, Y => PP7_14_net);
788 AO1_3 : AO1
789 port map(A => XOR2_13_Y, B => AO1_33_Y, C => AND2_216_Y,
790 Y => AO1_3_Y);
791 BUFF_16 : BUFF
792 port map(A => DataA(6), Y => BUFF_16_Y);
793 AND3_7 : AND3
794 port map(A => DataB(13), B => DataB(14), C => DataB(15),
795 Y => AND3_7_Y);
796 DFN1_SumB_8_inst : DFN1
797 port map(D => XOR3_86_Y, CLK => Clock, Q => SumB_8_net);
798 MX2_90 : MX2
799 port map(A => AND2_114_Y, B => BUFF_45_Y, S => AND2A_1_Y,
800 Y => MX2_90_Y);
801 AND2_133 : AND2
802 port map(A => SumA_7_net, B => SumB_7_net, Y => AND2_133_Y);
803 NOR2_2 : NOR2
804 port map(A => XOR2_17_Y, B => XNOR2_10_Y, Y => NOR2_2_Y);
805 AND2_38 : AND2
806 port map(A => XOR2_81_Y, B => BUFF_22_Y, Y => AND2_38_Y);
807 OR3_0 : OR3
808 port map(A => DataB(11), B => DataB(12), C => DataB(13),
809 Y => OR3_0_Y);
810 MX2_6 : MX2
811 port map(A => AND2_43_Y, B => BUFF_35_Y, S => NOR2_0_Y,
812 Y => MX2_6_Y);
813 NOR2_3 : NOR2
814 port map(A => XOR2_63_Y, B => XNOR2_18_Y, Y => NOR2_3_Y);
815 XOR2_72 : XOR2
816 port map(A => SumA_1_net, B => SumB_1_net, Y => XOR2_72_Y);
817 AND2_129 : AND2
818 port map(A => XOR2_59_Y, B => BUFF_54_Y, Y => AND2_129_Y);
819 XOR2_PP3_14_inst : XOR2
820 port map(A => MX2_82_Y, B => BUFF_42_Y, Y => PP3_14_net);
821 DFN1_30 : DFN1
822 port map(D => PP0_7_net, CLK => Clock, Q => DFN1_30_Q);
823 MAJ3_27 : MAJ3
824 port map(A => DFN1_134_Q, B => DFN1_35_Q, C => DFN1_108_Q,
825 Y => MAJ3_27_Y);
826 MAJ3_39 : MAJ3
827 port map(A => DFN1_72_Q, B => DFN1_106_Q, C => VCC_1_net,
828 Y => MAJ3_39_Y);
829 AO1_56 : AO1
830 port map(A => AND2_152_Y, B => AO1_1_Y, C => AO1_81_Y, Y =>
831 AO1_56_Y);
832 XOR3_90 : XOR3
833 port map(A => DFN1_115_Q, B => DFN1_23_Q, C => DFN1_24_Q,
834 Y => XOR3_90_Y);
835 XOR2_PP0_12_inst : XOR2
836 port map(A => MX2_14_Y, B => BUFF_0_Y, Y => PP0_12_net);
837 MAJ3_38 : MAJ3
838 port map(A => XOR3_49_Y, B => MAJ3_82_Y, C => AND2_124_Y,
839 Y => MAJ3_38_Y);
840 AO1_0 : AO1
841 port map(A => XOR2_42_Y, B => AND2_194_Y, C => AND2_126_Y,
842 Y => AO1_0_Y);
843 AND2_111 : AND2
844 port map(A => XOR2_31_Y, B => BUFF_36_Y, Y => AND2_111_Y);
845 DFN1_44 : DFN1
846 port map(D => PP5_9_net, CLK => Clock, Q => DFN1_44_Q);
847 BUFF_26 : BUFF
848 port map(A => DataB(15), Y => BUFF_26_Y);
849 XOR3_44 : XOR3
850 port map(A => DFN1_43_Q, B => DFN1_70_Q, C => DFN1_91_Q,
851 Y => XOR3_44_Y);
852 AO1_86 : AO1
853 port map(A => AND2_93_Y, B => AO1_33_Y, C => AO1_9_Y, Y =>
854 AO1_86_Y);
855 DFN1_SumA_18_inst : DFN1
856 port map(D => MAJ3_5_Y, CLK => Clock, Q => SumA_18_net);
857 XOR3_64 : XOR3
858 port map(A => DFN1_146_Q, B => DFN1_22_Q, C => MAJ3_39_Y,
859 Y => XOR3_64_Y);
860 AND2_258 : AND2
861 port map(A => XOR2_89_Y, B => BUFF_35_Y, Y => AND2_258_Y);
862 XOR2_PP0_0_inst : XOR2
863 port map(A => XOR2_62_Y, B => DataB(1), Y => PP0_0_net);
864 AND2_83 : AND2
865 port map(A => DataB(0), B => BUFF_32_Y, Y => AND2_83_Y);
866 DFN1_80 : DFN1
867 port map(D => PP7_4_net, CLK => Clock, Q => DFN1_80_Q);
868 MX2_42 : MX2
869 port map(A => AND2_150_Y, B => BUFF_1_Y, S => NOR2_2_Y,
870 Y => MX2_42_Y);
871 AND2_11 : AND2
872 port map(A => SumA_3_net, B => SumB_3_net, Y => AND2_11_Y);
873 XOR2_18 : XOR2
874 port map(A => DFN1_47_Q, B => VCC_1_net, Y => XOR2_18_Y);
875 AND2_90 : AND2
876 port map(A => XOR2_81_Y, B => BUFF_52_Y, Y => AND2_90_Y);
877 MAJ3_95 : MAJ3
878 port map(A => XOR3_96_Y, B => MAJ3_37_Y, C => XOR3_62_Y,
879 Y => MAJ3_95_Y);
880 XOR2_PP5_12_inst : XOR2
881 port map(A => MX2_102_Y, B => BUFF_25_Y, Y => PP5_12_net);
882 MAJ3_77 : MAJ3
883 port map(A => AND2_28_Y, B => DFN1_26_Q, C => DFN1_65_Q,
884 Y => MAJ3_77_Y);
885 AND2_71 : AND2
886 port map(A => XOR2_14_Y, B => BUFF_17_Y, Y => AND2_71_Y);
887 AND2_185 : AND2
888 port map(A => XOR2_15_Y, B => BUFF_22_Y, Y => AND2_185_Y);
889 BUFF_37 : BUFF
890 port map(A => DataB(9), Y => BUFF_37_Y);
891 AND2_164 : AND2
892 port map(A => SumA_11_net, B => SumB_11_net, Y =>
893 AND2_164_Y);
894 XOR2_20 : XOR2
895 port map(A => SumA_25_net, B => SumB_25_net, Y => XOR2_20_Y);
896 MX2_31 : MX2
897 port map(A => AND2_186_Y, B => BUFF_45_Y, S => NOR2_19_Y,
898 Y => MX2_31_Y);
899 XOR2_76 : XOR2
900 port map(A => SumA_5_net, B => SumB_5_net, Y => XOR2_76_Y);
901 AND2_215 : AND2
902 port map(A => XOR2_66_Y, B => BUFF_40_Y, Y => AND2_215_Y);
903 MX2_85 : MX2
904 port map(A => AND2_67_Y, B => BUFF_35_Y, S => NOR2_14_Y,
905 Y => MX2_85_Y);
906 XOR2_30 : XOR2
907 port map(A => SumA_8_net, B => SumB_8_net, Y => XOR2_30_Y);
908 XOR2_88 : XOR2
909 port map(A => DFN1_151_Q, B => VCC_1_net, Y => XOR2_88_Y);
910 MX2_PP3_16_inst : MX2
911 port map(A => MX2_28_Y, B => AO1_14_Y, S => NOR2_20_Y, Y =>
912 PP3_16_net);
913 MX2_56 : MX2
914 port map(A => AND2_77_Y, B => BUFF_31_Y, S => NOR2_18_Y,
915 Y => MX2_56_Y);
916 MX2_38 : MX2
917 port map(A => AND2_169_Y, B => BUFF_28_Y, S => AND2A_0_Y,
918 Y => MX2_38_Y);
919 AND2_S_3_inst : AND2
920 port map(A => XOR2_49_Y, B => DataB(7), Y => S_3_net);
921 MX2_107 : MX2
922 port map(A => AND2_24_Y, B => BUFF_3_Y, S => NOR2_16_Y,
923 Y => MX2_107_Y);
924 AND2_180 : AND2
925 port map(A => DataB(0), B => BUFF_8_Y, Y => AND2_180_Y);
926 XOR2_62 : XOR2
927 port map(A => AND2_19_Y, B => BUFF_30_Y, Y => XOR2_62_Y);
928 AND2_161 : AND2
929 port map(A => XOR2_51_Y, B => BUFF_18_Y, Y => AND2_161_Y);
930 DFN1_3 : DFN1
931 port map(D => PP6_1_net, CLK => Clock, Q => DFN1_3_Q);
932 AND2_4 : AND2
933 port map(A => XOR2_5_Y, B => BUFF_3_Y, Y => AND2_4_Y);
934 DFN1_115 : DFN1
935 port map(D => PP2_12_net, CLK => Clock, Q => DFN1_115_Q);
936 XOR3_2 : XOR3
937 port map(A => MAJ3_0_Y, B => XOR3_75_Y, C => XOR3_17_Y,
938 Y => XOR3_2_Y);
939 MAJ3_29 : MAJ3
940 port map(A => DFN1_85_Q, B => DFN1_61_Q, C => DFN1_140_Q,
941 Y => MAJ3_29_Y);
942 MX2_96 : MX2
943 port map(A => AND2_224_Y, B => BUFF_18_Y, S => NOR2_14_Y,
944 Y => MX2_96_Y);
945 MAJ3_28 : MAJ3
946 port map(A => DFN1_37_Q, B => DFN1_133_Q, C => DFN1_15_Q,
947 Y => MAJ3_28_Y);
948 DFN1_SumA_4_inst : DFN1
949 port map(D => MAJ3_25_Y, CLK => Clock, Q => SumA_4_net);
950 DFN1_61 : DFN1
951 port map(D => PP1_10_net, CLK => Clock, Q => DFN1_61_Q);
952 MX2_74 : MX2
953 port map(A => AND2_87_Y, B => BUFF_40_Y, S => NOR2_13_Y,
954 Y => MX2_74_Y);
955 MX2_PP6_16_inst : MX2
956 port map(A => MX2_79_Y, B => AO1_77_Y, S => NOR2_0_Y, Y =>
957 PP6_16_net);
958 XOR2_PP7_8_inst : XOR2
959 port map(A => MX2_37_Y, B => BUFF_23_Y, Y => PP7_8_net);
960 AND2_0 : AND2
961 port map(A => XOR2_11_Y, B => BUFF_50_Y, Y => AND2_0_Y);
962 DFN1_104 : DFN1
963 port map(D => PP7_13_net, CLK => Clock, Q => DFN1_104_Q);
964 AND2_230 : AND2
965 port map(A => XOR2_66_Y, B => BUFF_39_Y, Y => AND2_230_Y);
966 DFN1_113 : DFN1
967 port map(D => PP6_10_net, CLK => Clock, Q => DFN1_113_Q);
968 AND2_156 : AND2
969 port map(A => XOR2_63_Y, B => BUFF_29_Y, Y => AND2_156_Y);
970 AO1_34 : AO1
971 port map(A => AND2_179_Y, B => AO1_15_Y, C => AO1_38_Y,
972 Y => AO1_34_Y);
973 XOR3_3 : XOR3
974 port map(A => DFN1_5_Q, B => VCC_1_net, C => DFN1_129_Q,
975 Y => XOR3_3_Y);
976 DFN1_SumA_23_inst : DFN1
977 port map(D => MAJ3_92_Y, CLK => Clock, Q => SumA_23_net);
978 AO1_43 : AO1
979 port map(A => AND2_25_Y, B => AO1_58_Y, C => AO1_3_Y, Y =>
980 AO1_43_Y);
981 DFN1_51 : DFN1
982 port map(D => PP3_1_net, CLK => Clock, Q => DFN1_51_Q);
983 MAJ3_93 : MAJ3
984 port map(A => DFN1_142_Q, B => DFN1_51_Q, C => DFN1_77_Q,
985 Y => MAJ3_93_Y);
986 MX2_116 : MX2
987 port map(A => AND2_2_Y, B => BUFF_49_Y, S => NOR2_8_Y, Y =>
988 MX2_116_Y);
989 AND2_16 : AND2
990 port map(A => SumA_2_net, B => SumB_2_net, Y => AND2_16_Y);
991 MX2_64 : MX2
992 port map(A => AND2_163_Y, B => BUFF_2_Y, S => NOR2_17_Y,
993 Y => MX2_64_Y);
994 DFN1_8 : DFN1
995 port map(D => PP1_4_net, CLK => Clock, Q => DFN1_8_Q);
996 DFN1_SumB_9_inst : DFN1
997 port map(D => XOR3_59_Y, CLK => Clock, Q => SumB_9_net);
998 AND2_76 : AND2
999 port map(A => SumA_16_net, B => SumB_16_net, Y => AND2_76_Y);
1000 MX2_10 : MX2
1001 port map(A => AND2_35_Y, B => BUFF_11_Y, S => NOR2_3_Y,
1002 Y => MX2_10_Y);
1003 AND2_6 : AND2
1004 port map(A => XOR2_26_Y, B => BUFF_24_Y, Y => AND2_6_Y);
1005 MX2_115 : MX2
1006 port map(A => AND2_75_Y, B => BUFF_24_Y, S => NOR2_19_Y,
1007 Y => MX2_115_Y);
1008 AO1_17 : AO1
1009 port map(A => XOR2_80_Y, B => OR3_6_Y, C => AND3_2_Y, Y =>
1010 AO1_17_Y);
1011 XOR2_PP6_13_inst : XOR2
1012 port map(A => MX2_12_Y, B => BUFF_43_Y, Y => PP6_13_net);
1013 XOR3_45 : XOR3
1014 port map(A => XOR2_55_Y, B => DFN1_89_Q, C => MAJ3_71_Y,
1015 Y => XOR3_45_Y);
1016 XNOR2_0 : XNOR2
1017 port map(A => DataB(12), B => BUFF_20_Y, Y => XNOR2_0_Y);
1018 BUFF_44 : BUFF
1019 port map(A => DataA(9), Y => BUFF_44_Y);
1020 XOR3_65 : XOR3
1021 port map(A => MAJ3_73_Y, B => DFN1_1_Q, C => XOR3_10_Y,
1022 Y => XOR3_65_Y);
1023 MAJ3_79 : MAJ3
1024 port map(A => XOR3_57_Y, B => MAJ3_55_Y, C => XOR3_31_Y,
1025 Y => MAJ3_79_Y);
1026 AND2_189 : AND2
1027 port map(A => SumA_19_net, B => SumB_19_net, Y =>
1028 AND2_189_Y);
1029 MAJ3_78 : MAJ3
1030 port map(A => XOR3_78_Y, B => MAJ3_46_Y, C => XOR2_106_Y,
1031 Y => MAJ3_78_Y);
1032 MX2_49 : MX2
1033 port map(A => AND2_128_Y, B => BUFF_33_Y, S => NOR2_19_Y,
1034 Y => MX2_49_Y);
1035 XNOR2_15 : XNOR2
1036 port map(A => DataB(12), B => BUFF_9_Y, Y => XNOR2_15_Y);
1037 MAJ3_67 : MAJ3
1038 port map(A => XOR3_1_Y, B => MAJ3_81_Y, C => MAJ3_6_Y, Y =>
1039 MAJ3_67_Y);
1040 MAJ3_57 : MAJ3
1041 port map(A => XOR3_6_Y, B => MAJ3_60_Y, C => MAJ3_69_Y,
1042 Y => MAJ3_57_Y);
1043 XOR2_66 : XOR2
1044 port map(A => DataB(9), B => DataB(10), Y => XOR2_66_Y);
1045 XOR2_PP0_5_inst : XOR2
1046 port map(A => MX2_90_Y, B => BUFF_30_Y, Y => PP0_5_net);
1047 AO1_42 : AO1
1048 port map(A => AND2_190_Y, B => AO1_44_Y, C => AO1_74_Y,
1049 Y => AO1_42_Y);
1050 AND2_37 : AND2
1051 port map(A => AND2_207_Y, B => AND2_47_Y, Y => AND2_37_Y);
1052 DFN1_121 : DFN1
1053 port map(D => PP4_9_net, CLK => Clock, Q => DFN1_121_Q);
1054 DFN1_SumA_25_inst : DFN1
1055 port map(D => MAJ3_1_Y, CLK => Clock, Q => SumA_25_net);
1056 AO1_18 : AO1
1057 port map(A => AND2_198_Y, B => AO1_58_Y, C => AO1_86_Y,
1058 Y => AO1_18_Y);
1059 XNOR2_20 : XNOR2
1060 port map(A => DataB(2), B => BUFF_14_Y, Y => XNOR2_20_Y);
1061 AND2_238 : AND2
1062 port map(A => DFN1_151_Q, B => VCC_1_net, Y => AND2_238_Y);
1063 XOR3_93 : XOR3
1064 port map(A => MAJ3_44_Y, B => XOR3_80_Y, C => XOR3_92_Y,
1065 Y => XOR3_93_Y);
1066 DFN1_SumB_21_inst : DFN1
1067 port map(D => XOR3_8_Y, CLK => Clock, Q => SumB_21_net);
1068 AO1_39 : AO1
1069 port map(A => AND2_44_Y, B => AO1_18_Y, C => AO1_89_Y, Y =>
1070 AO1_39_Y);
1071 OR3_2 : OR3
1072 port map(A => DataB(1), B => DataB(2), C => DataB(3), Y =>
1073 OR3_2_Y);
1074 DFN1_25 : DFN1
1075 port map(D => PP0_2_net, CLK => Clock, Q => DFN1_25_Q);
1076 MAJ3_90 : MAJ3
1077 port map(A => MAJ3_39_Y, B => DFN1_146_Q, C => DFN1_22_Q,
1078 Y => MAJ3_90_Y);
1079 XOR2_PP2_8_inst : XOR2
1080 port map(A => MX2_84_Y, B => BUFF_34_Y, Y => PP2_8_net);
1081 XOR2_41 : XOR2
1082 port map(A => DFN1_6_Q, B => DFN1_107_Q, Y => XOR2_41_Y);
1083 AO1_21 : AO1
1084 port map(A => XOR2_4_Y, B => AO1_66_Y, C => AND2_96_Y, Y =>
1085 AO1_21_Y);
1086 AND2_194 : AND2
1087 port map(A => SumA_12_net, B => SumB_12_net, Y =>
1088 AND2_194_Y);
1089 XOR2_7 : XOR2
1090 port map(A => DFN1_93_Q, B => DFN1_83_Q, Y => XOR2_7_Y);
1091 XOR2_54 : XOR2
1092 port map(A => SumA_28_net, B => SumB_28_net, Y => XOR2_54_Y);
1093 MAJ3_42 : MAJ3
1094 port map(A => XOR2_91_Y, B => DFN1_148_Q, C => DFN1_34_Q,
1095 Y => MAJ3_42_Y);
1096 BUFF_6 : BUFF
1097 port map(A => DataA(3), Y => BUFF_6_Y);
1098 MAJ3_1 : MAJ3
1099 port map(A => XOR3_91_Y, B => MAJ3_36_Y, C => XOR3_72_Y,
1100 Y => MAJ3_1_Y);
1101 AND2_157 : AND2
1102 port map(A => AND2_104_Y, B => AND2_198_Y, Y => AND2_157_Y);
1103 AND2_44 : AND2
1104 port map(A => AND2_210_Y, B => AND2_33_Y, Y => AND2_44_Y);
1105 DFN1_SumB_3_inst : DFN1
1106 port map(D => XOR3_15_Y, CLK => Clock, Q => SumB_3_net);
1107 XOR3_14 : XOR3
1108 port map(A => MAJ3_16_Y, B => XOR2_7_Y, C => XOR3_33_Y,
1109 Y => XOR3_14_Y);
1110 XOR2_23 : XOR2
1111 port map(A => SumA_24_net, B => SumB_24_net, Y => XOR2_23_Y);
1112 DFN1_95 : DFN1
1113 port map(D => PP1_15_net, CLK => Clock, Q => DFN1_95_Q);
1114 AND2_175 : AND2
1115 port map(A => XOR2_65_Y, B => BUFF_29_Y, Y => AND2_175_Y);
1116 XOR2_PP5_2_inst : XOR2
1117 port map(A => MX2_1_Y, B => BUFF_55_Y, Y => PP5_2_net);
1118 DFN1_37 : DFN1
1119 port map(D => PP4_10_net, CLK => Clock, Q => DFN1_37_Q);
1120 AND2_191 : AND2
1121 port map(A => AND2_219_Y, B => AND2_112_Y, Y => AND2_191_Y);
1122 XOR2_33 : XOR2
1123 port map(A => BUFF_47_Y, B => DataB(13), Y => XOR2_33_Y);
1124 AND2_31 : AND2
1125 port map(A => AND2_177_Y, B => XOR2_67_Y, Y => AND2_31_Y);
1126 DFN1_36 : DFN1
1127 port map(D => PP1_1_net, CLK => Clock, Q => DFN1_36_Q);
1128 MAJ3_69 : MAJ3
1129 port map(A => DFN1_41_Q, B => DFN1_144_Q, C => DFN1_20_Q,
1130 Y => MAJ3_69_Y);
1131 XOR2_PP2_15_inst : XOR2
1132 port map(A => MX2_127_Y, B => BUFF_4_Y, Y => PP2_15_net);
1133 MX2_16 : MX2
1134 port map(A => AND2_78_Y, B => BUFF_22_Y, S => NOR2_1_Y,
1135 Y => MX2_16_Y);
1136 AND2_122 : AND2
1137 port map(A => XOR2_26_Y, B => BUFF_31_Y, Y => AND2_122_Y);
1138 XOR2_29 : XOR2
1139 port map(A => SumA_4_net, B => SumB_4_net, Y => XOR2_29_Y);
1140 MAJ3_59 : MAJ3
1141 port map(A => DFN1_136_Q, B => DFN1_11_Q, C => DFN1_94_Q,
1142 Y => MAJ3_59_Y);
1143 AND2_241 : AND2
1144 port map(A => SumA_10_net, B => SumB_10_net, Y =>
1145 AND2_241_Y);
1146 MAJ3_68 : MAJ3
1147 port map(A => XOR3_81_Y, B => MAJ3_21_Y, C => DFN1_69_Q,
1148 Y => MAJ3_68_Y);
1149 AND2_64 : AND2
1150 port map(A => XOR2_15_Y, B => BUFF_18_Y, Y => AND2_64_Y);
1151 XOR3_40 : XOR3
1152 port map(A => MAJ3_87_Y, B => MAJ3_62_Y, C => XOR3_38_Y,
1153 Y => XOR3_40_Y);
1154 BUFF_39 : BUFF
1155 port map(A => DataA(1), Y => BUFF_39_Y);
1156 MAJ3_58 : MAJ3
1157 port map(A => XOR3_85_Y, B => MAJ3_23_Y, C => DFN1_39_Q,
1158 Y => MAJ3_58_Y);
1159 XOR3_60 : XOR3
1160 port map(A => MAJ3_59_Y, B => AND2_154_Y, C => XOR3_69_Y,
1161 Y => XOR3_60_Y);
1162 XOR2_39 : XOR2
1163 port map(A => SumA_11_net, B => SumB_11_net, Y => XOR2_39_Y);
1164 DFN1_107 : DFN1
1165 port map(D => PP3_3_net, CLK => Clock, Q => DFN1_107_Q);
1166 XOR2_PP0_9_inst : XOR2
1167 port map(A => MX2_81_Y, B => BUFF_27_Y, Y => PP0_9_net);
1168 XOR2_PP3_5_inst : XOR2
1169 port map(A => MX2_92_Y, B => BUFF_15_Y, Y => PP3_5_net);
1170 AND2_136 : AND2
1171 port map(A => XOR2_56_Y, B => BUFF_35_Y, Y => AND2_136_Y);
1172 AND2_170 : AND2
1173 port map(A => SumA_23_net, B => SumB_23_net, Y =>
1174 AND2_170_Y);
1175 DFN1_87 : DFN1
1176 port map(D => E_2_net, CLK => Clock, Q => DFN1_87_Q);
1177 XOR2_PP2_6_inst : XOR2
1178 port map(A => MX2_51_Y, B => BUFF_34_Y, Y => PP2_6_net);
1179 AND2_19 : AND2
1180 port map(A => DataB(0), B => BUFF_33_Y, Y => AND2_19_Y);
1181 XOR2_Mult_28_inst : XOR2
1182 port map(A => XOR2_36_Y, B => AO1_27_Y, Y => Mult(28));
1183 DFN1_86 : DFN1
1184 port map(D => PP6_2_net, CLK => Clock, Q => DFN1_86_Q);
1185 AND2_79 : AND2
1186 port map(A => XOR2_58_Y, B => BUFF_33_Y, Y => AND2_79_Y);
1187 DFN1_39 : DFN1
1188 port map(D => PP7_6_net, CLK => Clock, Q => DFN1_39_Q);
1189 MX2_57 : MX2
1190 port map(A => AND2_146_Y, B => BUFF_2_Y, S => NOR2_7_Y,
1191 Y => MX2_57_Y);
1192 AND2_249 : AND2
1193 port map(A => XOR2_8_Y, B => XOR2_53_Y, Y => AND2_249_Y);
1194 DFN1_71 : DFN1
1195 port map(D => E_5_net, CLK => Clock, Q => DFN1_71_Q);
1196 XOR2_27 : XOR2
1197 port map(A => SumA_13_net, B => SumB_13_net, Y => XOR2_27_Y);
1198 MX2_8 : MX2
1199 port map(A => AND2_107_Y, B => BUFF_50_Y, S => NOR2_11_Y,
1200 Y => MX2_8_Y);
1201 XOR2_6 : XOR2
1202 port map(A => SumA_21_net, B => SumB_21_net, Y => XOR2_6_Y);
1203 AND2_227 : AND2
1204 port map(A => XOR2_65_Y, B => BUFF_6_Y, Y => AND2_227_Y);
1205 XOR2_37 : XOR2
1206 port map(A => SumA_28_net, B => SumB_28_net, Y => XOR2_37_Y);
1207 DFN1_118 : DFN1
1208 port map(D => PP5_16_net, CLK => Clock, Q => DFN1_118_Q);
1209 MX2_97 : MX2
1210 port map(A => AND2_201_Y, B => BUFF_1_Y, S => AND2A_0_Y,
1211 Y => MX2_97_Y);
1212 DFN1_SumB_0_inst : DFN1
1213 port map(D => DFN1_0_Q, CLK => Clock, Q => SumB_0_net);
1214 BUFF_13 : BUFF
1215 port map(A => DataA(9), Y => BUFF_13_Y);
1216 BUFF_11 : BUFF
1217 port map(A => DataA(0), Y => BUFF_11_Y);
1218 AND2_115 : AND2
1219 port map(A => AND2_57_Y, B => XOR2_83_Y, Y => AND2_115_Y);
1220 DFN1_SumB_26_inst : DFN1
1221 port map(D => XOR3_22_Y, CLK => Clock, Q => SumB_26_net);
1222 XOR2_PP7_0_inst : XOR2
1223 port map(A => XOR2_45_Y, B => DataB(15), Y => PP7_0_net);
1224 BUFF_45 : BUFF
1225 port map(A => DataA(4), Y => BUFF_45_Y);
1226 DFN1_89 : DFN1
1227 port map(D => PP7_14_net, CLK => Clock, Q => DFN1_89_Q);
1228 BUFF_40 : BUFF
1229 port map(A => DataA(5), Y => BUFF_40_Y);
1230 XOR2_55 : XOR2
1231 port map(A => DFN1_4_Q, B => VCC_1_net, Y => XOR2_55_Y);
1232 MX2_PP0_16_inst : MX2
1233 port map(A => MX2_55_Y, B => EBAR, S => AND2A_0_Y, Y =>
1234 PP0_16_net);
1235 XOR2_Mult_15_inst : XOR2
1236 port map(A => XOR2_71_Y, B => AO1_22_Y, Y => Mult(15));
1237 AND2A_2 : AND2A
1238 port map(A => DataB(0), B => BUFF_27_Y, Y => AND2A_2_Y);
1239 XOR2_109 : XOR2
1240 port map(A => DataB(5), B => DataB(6), Y => XOR2_109_Y);
1241 DFN1_SumB_20_inst : DFN1
1242 port map(D => XOR3_89_Y, CLK => Clock, Q => SumB_20_net);
1243 AND2_104 : AND2
1244 port map(A => AND2_131_Y, B => AND2_249_Y, Y => AND2_104_Y);
1245 AND2_36 : AND2
1246 port map(A => DataB(0), B => BUFF_28_Y, Y => AND2_36_Y);
1247 AND2_179 : AND2
1248 port map(A => AND2_168_Y, B => XOR2_40_Y, Y => AND2_179_Y);
1249 DFN1_152 : DFN1
1250 port map(D => PP7_1_net, CLK => Clock, Q => DFN1_152_Q);
1251 MAJ3_82 : MAJ3
1252 port map(A => DFN1_101_Q, B => DFN1_122_Q, C => DFN1_55_Q,
1253 Y => MAJ3_82_Y);
1254 AND2_9 : AND2
1255 port map(A => DFN1_14_Q, B => DFN1_53_Q, Y => AND2_9_Y);
1256 DFN1_150 : DFN1
1257 port map(D => PP5_3_net, CLK => Clock, Q => DFN1_150_Q);
1258 XNOR2_16 : XNOR2
1259 port map(A => DataB(2), B => BUFF_21_Y, Y => XNOR2_16_Y);
1260 MX2_123 : MX2
1261 port map(A => AND2_6_Y, B => BUFF_33_Y, S => NOR2_5_Y, Y =>
1262 MX2_123_Y);
1263 AND2_226 : AND2
1264 port map(A => XOR2_107_Y, B => XOR2_98_Y, Y => AND2_226_Y);
1265 AND2_214 : AND2
1266 port map(A => SumA_29_net, B => SumB_29_net, Y =>
1267 AND2_214_Y);
1268 XOR3_58 : XOR3
1269 port map(A => MAJ3_41_Y, B => XOR3_37_Y, C => XOR3_56_Y,
1270 Y => XOR3_58_Y);
1271 XOR2_PP6_5_inst : XOR2
1272 port map(A => MX2_77_Y, B => BUFF_20_Y, Y => PP6_5_net);
1273 AND2A_1 : AND2A
1274 port map(A => DataB(0), B => BUFF_30_Y, Y => AND2A_1_Y);
1275 MX2_70 : MX2
1276 port map(A => AND2_181_Y, B => BUFF_44_Y, S => NOR2_4_Y,
1277 Y => MX2_70_Y);
1278 XOR2_PP6_8_inst : XOR2
1279 port map(A => MX2_105_Y, B => BUFF_9_Y, Y => PP6_8_net);
1280 XOR3_15 : XOR3
1281 port map(A => DFN1_130_Q, B => DFN1_143_Q, C => DFN1_2_Q,
1282 Y => XOR3_15_Y);
1283 AND2_110 : AND2
1284 port map(A => XOR2_66_Y, B => BUFF_3_Y, Y => AND2_110_Y);
1285 BUFF_23 : BUFF
1286 port map(A => DataB(15), Y => BUFF_23_Y);
1287 XOR2_PP4_3_inst : XOR2
1288 port map(A => MX2_93_Y, B => BUFF_41_Y, Y => PP4_3_net);
1289 XOR2_PP4_13_inst : XOR2
1290 port map(A => MX2_63_Y, B => BUFF_7_Y, Y => PP4_13_net);
1291 BUFF_21 : BUFF
1292 port map(A => DataB(3), Y => BUFF_21_Y);
1293 NOR2_5 : NOR2
1294 port map(A => XOR2_26_Y, B => XNOR2_2_Y, Y => NOR2_5_Y);
1295 MX2_60 : MX2
1296 port map(A => AND2_223_Y, B => BUFF_50_Y, S => NOR2_15_Y,
1297 Y => MX2_60_Y);
1298 DFN1_SumB_11_inst : DFN1
1299 port map(D => XOR3_88_Y, CLK => Clock, Q => SumB_11_net);
1300 AND2_101 : AND2
1301 port map(A => XOR2_65_Y, B => BUFF_11_Y, Y => AND2_101_Y);
1302 AND2_137 : AND2
1303 port map(A => XOR2_56_Y, B => BUFF_2_Y, Y => AND2_137_Y);
1304 AO1_47 : AO1
1305 port map(A => AND2_55_Y, B => AO1_23_Y, C => AO1_76_Y, Y =>
1306 AO1_47_Y);
1307 DFN1_131 : DFN1
1308 port map(D => PP4_11_net, CLK => Clock, Q => DFN1_131_Q);
1309 XOR2_PP7_15_inst : XOR2
1310 port map(A => MX2_46_Y, B => BUFF_51_Y, Y => PP7_15_net);
1311 DFN1_34 : DFN1
1312 port map(D => PP2_1_net, CLK => Clock, Q => DFN1_34_Q);
1313 AND2_165 : AND2
1314 port map(A => XOR2_105_Y, B => BUFF_45_Y, Y => AND2_165_Y);
1315 AND2_182 : AND2
1316 port map(A => XOR2_83_Y, B => XOR2_28_Y, Y => AND2_182_Y);
1317 AND2_10 : AND2
1318 port map(A => XOR2_59_Y, B => BUFF_28_Y, Y => AND2_10_Y);
1319 XOR2_PP6_9_inst : XOR2
1320 port map(A => MX2_40_Y, B => BUFF_9_Y, Y => PP6_9_net);
1321 XOR2_PP1_2_inst : XOR2
1322 port map(A => MX2_36_Y, B => BUFF_21_Y, Y => PP1_2_net);
1323 AND2_119 : AND2
1324 port map(A => XOR2_63_Y, B => BUFF_3_Y, Y => AND2_119_Y);
1325 AND2_70 : AND2
1326 port map(A => SumA_28_net, B => SumB_28_net, Y => AND2_70_Y);
1327 DFN1_126 : DFN1
1328 port map(D => PP7_10_net, CLK => Clock, Q => DFN1_126_Q);
1329 XOR3_78 : XOR3
1330 port map(A => DFN1_51_Q, B => DFN1_77_Q, C => DFN1_142_Q,
1331 Y => XOR3_78_Y);
1332 AOI1_E_0_inst : AOI1
1333 port map(A => XOR2_92_Y, B => OR3_1_Y, C => AND3_1_Y, Y =>
1334 E_0_net);
1335 XOR2_PP1_10_inst : XOR2
1336 port map(A => MX2_83_Y, B => BUFF_14_Y, Y => PP1_10_net);
1337 XOR2_PP3_15_inst : XOR2
1338 port map(A => MX2_103_Y, B => BUFF_42_Y, Y => PP3_15_net);
1339 DFN1_22 : DFN1
1340 port map(D => PP5_11_net, CLK => Clock, Q => DFN1_22_Q);
1341 MAJ3_16 : MAJ3
1342 port map(A => DFN1_24_Q, B => DFN1_115_Q, C => DFN1_23_Q,
1343 Y => MAJ3_16_Y);
1344 MX2_PP5_16_inst : MX2
1345 port map(A => MX2_86_Y, B => AO1_59_Y, S => NOR2_17_Y, Y =>
1346 PP5_16_net);
1347 AO1_48 : AO1
1348 port map(A => XOR2_107_Y, B => AO1_62_Y, C => AND2_16_Y,
1349 Y => AO1_48_Y);
1350 XNOR2_7 : XNOR2
1351 port map(A => DataB(12), B => BUFF_43_Y, Y => XNOR2_7_Y);
1352 AND2_205 : AND2
1353 port map(A => XOR2_35_Y, B => BUFF_18_Y, Y => AND2_205_Y);
1354 XOR2_42 : XOR2
1355 port map(A => SumA_13_net, B => SumB_13_net, Y => XOR2_42_Y);
1356 DFN1_10 : DFN1
1357 port map(D => PP2_16_net, CLK => Clock, Q => DFN1_10_Q);
1358 AO1_36 : AO1
1359 port map(A => XOR2_90_Y, B => AND2_96_Y, C => AND2_40_Y,
1360 Y => AO1_36_Y);
1361 XOR2_PP5_9_inst : XOR2
1362 port map(A => MX2_16_Y, B => BUFF_48_Y, Y => PP5_9_net);
1363 DFN1_84 : DFN1
1364 port map(D => PP2_9_net, CLK => Clock, Q => DFN1_84_Q);
1365 XOR2_Mult_21_inst : XOR2
1366 port map(A => XOR2_69_Y, B => AO1_12_Y, Y => Mult(21));
1367 AND2_160 : AND2
1368 port map(A => AND2_41_Y, B => AND2_178_Y, Y => AND2_160_Y);
1369 XOR3_43 : XOR3
1370 port map(A => MAJ3_28_Y, B => XOR2_16_Y, C => XOR3_87_Y,
1371 Y => XOR3_43_Y);
1372 XOR3_63 : XOR3
1373 port map(A => DFN1_27_Q, B => DFN1_73_Q, C => DFN1_74_Q,
1374 Y => XOR3_63_Y);
1375 DFN1_129 : DFN1
1376 port map(D => PP5_14_net, CLK => Clock, Q => DFN1_129_Q);
1377 XOR2_50 : XOR2
1378 port map(A => SumA_5_net, B => SumB_5_net, Y => XOR2_50_Y);
1379 MX2_84 : MX2
1380 port map(A => AND2_145_Y, B => BUFF_8_Y, S => NOR2_11_Y,
1381 Y => MX2_84_Y);
1382 XOR3_49 : XOR3
1383 port map(A => DFN1_96_Q, B => DFN1_28_Q, C => DFN1_62_Q,
1384 Y => XOR3_49_Y);
1385 XOR2_0 : XOR2
1386 port map(A => AND2_109_Y, B => BUFF_41_Y, Y => XOR2_0_Y);
1387 XOR2_101 : XOR2
1388 port map(A => SumA_18_net, B => SumB_18_net, Y =>
1389 XOR2_101_Y);
1390 XOR3_69 : XOR3
1391 port map(A => DFN1_67_Q, B => DFN1_128_Q, C => DFN1_44_Q,
1392 Y => XOR3_69_Y);
1393 AO1_11 : AO1
1394 port map(A => AND2_199_Y, B => AO1_87_Y, C => AO1_61_Y,
1395 Y => AO1_11_Y);
1396 AND2_94 : AND2
1397 port map(A => SumA_5_net, B => SumB_5_net, Y => AND2_94_Y);
1398 MX2_122 : MX2
1399 port map(A => AND2_134_Y, B => BUFF_44_Y, S => NOR2_1_Y,
1400 Y => MX2_122_Y);
1401 DFN1_92 : DFN1
1402 port map(D => S_4_net, CLK => Clock, Q => DFN1_92_Q);
1403 AND2_222 : AND2
1404 port map(A => XOR2_14_Y, B => BUFF_8_Y, Y => AND2_222_Y);
1405 MX2_17 : MX2
1406 port map(A => AND2_240_Y, B => BUFF_16_Y, S => NOR2_13_Y,
1407 Y => MX2_17_Y);
1408 AO1_70 : AO1
1409 port map(A => XOR2_102_Y, B => AO1_11_Y, C => AND2_194_Y,
1410 Y => AO1_70_Y);
1411 MX2_76 : MX2
1412 port map(A => AND2_54_Y, B => BUFF_31_Y, S => NOR2_19_Y,
1413 Y => MX2_76_Y);
1414 XOR3_10 : XOR3
1415 port map(A => DFN1_147_Q, B => DFN1_45_Q, C => DFN1_46_Q,
1416 Y => XOR3_10_Y);
1417 AND2_22 : AND2
1418 port map(A => XOR2_15_Y, B => BUFF_52_Y, Y => AND2_22_Y);
1419 AO1_63 : AO1
1420 port map(A => AND2_92_Y, B => AO1_15_Y, C => AO1_11_Y, Y =>
1421 AO1_63_Y);
1422 MAJ3_3 : MAJ3
1423 port map(A => XOR3_33_Y, B => MAJ3_16_Y, C => XOR2_7_Y,
1424 Y => MAJ3_3_Y);
1425 XOR2_PP6_12_inst : XOR2
1426 port map(A => MX2_58_Y, B => BUFF_43_Y, Y => PP6_12_net);
1427 MX2_53 : MX2
1428 port map(A => AND2_161_Y, B => BUFF_12_Y, S => NOR2_1_Y,
1429 Y => MX2_53_Y);
1430 AND2_39 : AND2
1431 port map(A => AND2_1_Y, B => XOR2_30_Y, Y => AND2_39_Y);
1432 XOR2_PP0_1_inst : XOR2
1433 port map(A => MX2_99_Y, B => BUFF_30_Y, Y => PP0_1_net);
1434 XOR2_PP4_1_inst : XOR2
1435 port map(A => MX2_10_Y, B => BUFF_41_Y, Y => PP4_1_net);
1436 XOR2_PP5_3_inst : XOR2
1437 port map(A => MX2_112_Y, B => BUFF_55_Y, Y => PP5_3_net);
1438 MX2_110 : MX2
1439 port map(A => AND2_188_Y, B => BUFF_36_Y, S => NOR2_14_Y,
1440 Y => MX2_110_Y);
1441 XOR2_46 : XOR2
1442 port map(A => SumA_17_net, B => SumB_17_net, Y => XOR2_46_Y);
1443 MX2_66 : MX2
1444 port map(A => AND2_71_Y, B => BUFF_8_Y, S => NOR2_15_Y,
1445 Y => MX2_66_Y);
1446 MAJ3_41 : MAJ3
1447 port map(A => XOR3_23_Y, B => MAJ3_32_Y, C => AND2_56_Y,
1448 Y => MAJ3_41_Y);
1449 AND2_169 : AND2
1450 port map(A => DataB(0), B => BUFF_19_Y, Y => AND2_169_Y);
1451 XOR2_Mult_24_inst : XOR2
1452 port map(A => XOR2_104_Y, B => AO1_2_Y, Y => Mult(24));
1453 DFN1_SumB_16_inst : DFN1
1454 port map(D => XOR3_93_Y, CLK => Clock, Q => SumB_16_net);
1455 MX2_93 : MX2
1456 port map(A => AND2_252_Y, B => BUFF_29_Y, S => NOR2_3_Y,
1457 Y => MX2_93_Y);
1458 XOR3_47 : XOR3
1459 port map(A => MAJ3_31_Y, B => MAJ3_48_Y, C => XOR3_50_Y,
1460 Y => XOR3_47_Y);
1461 MX2_45 : MX2
1462 port map(A => AND2_64_Y, B => BUFF_12_Y, S => NOR2_12_Y,
1463 Y => MX2_45_Y);
1464 XOR3_67 : XOR3
1465 port map(A => DFN1_32_Q, B => DFN1_71_Q, C => DFN1_104_Q,
1466 Y => XOR3_67_Y);
1467 DFN1_144 : DFN1
1468 port map(D => PP3_4_net, CLK => Clock, Q => DFN1_144_Q);
1469 DFN1_SumB_10_inst : DFN1
1470 port map(D => XOR3_58_Y, CLK => Clock, Q => SumB_10_net);
1471 AO1_62 : AO1
1472 port map(A => XOR2_72_Y, B => AND2_102_Y, C => AND2_8_Y,
1473 Y => AO1_62_Y);
1474 DFN1_28 : DFN1
1475 port map(D => PP1_14_net, CLK => Clock, Q => DFN1_28_Q);
1476 DFN1_1 : DFN1
1477 port map(D => PP7_0_net, CLK => Clock, Q => DFN1_1_Q);
1478 AOI1_E_2_inst : AOI1
1479 port map(A => XOR2_80_Y, B => OR3_6_Y, C => AND3_2_Y, Y =>
1480 E_2_net);
1481 XOR3_91 : XOR3
1482 port map(A => AND2_68_Y, B => DFN1_7_Q, C => MAJ3_85_Y,
1483 Y => XOR3_91_Y);
1484 MAJ3_94 : MAJ3
1485 port map(A => XOR3_67_Y, B => MAJ3_33_Y, C => AND2_132_Y,
1486 Y => MAJ3_94_Y);
1487 XOR2_Mult_6_inst : XOR2
1488 port map(A => XOR2_50_Y, B => AO1_24_Y, Y => Mult(6));
1489 AND2_195 : AND2
1490 port map(A => AND2_100_Y, B => AND2_176_Y, Y => AND2_195_Y);
1491 XOR2_103 : XOR2
1492 port map(A => SumA_24_net, B => SumB_24_net, Y =>
1493 XOR2_103_Y);
1494 DFN1_122 : DFN1
1495 port map(D => PP3_9_net, CLK => Clock, Q => DFN1_122_Q);
1496 BUFF_17 : BUFF
1497 port map(A => DataA(8), Y => BUFF_17_Y);
1498 DFN1_120 : DFN1
1499 port map(D => PP1_0_net, CLK => Clock, Q => DFN1_120_Q);
1500 AND2_45 : AND2
1501 port map(A => XOR2_58_Y, B => BUFF_31_Y, Y => AND2_45_Y);
1502 AO1_75 : AO1
1503 port map(A => AND2_247_Y, B => AO1_52_Y, C => AO1_82_Y,
1504 Y => AO1_75_Y);
1505 DFN1_98 : DFN1
1506 port map(D => PP3_7_net, CLK => Clock, Q => DFN1_98_Q);
1507 MAJ3_2 : MAJ3
1508 port map(A => XOR3_43_Y, B => MAJ3_66_Y, C => MAJ3_9_Y,
1509 Y => MAJ3_2_Y);
1510 XOR2_Mult_16_inst : XOR2
1511 port map(A => XOR2_64_Y, B => AO1_51_Y, Y => Mult(16));
1512 AOI1_E_7_inst : AOI1
1513 port map(A => XOR2_38_Y, B => OR3_4_Y, C => AND3_7_Y, Y =>
1514 E_7_net);
1515 XOR2_21 : XOR2
1516 port map(A => SumA_19_net, B => SumB_19_net, Y => XOR2_21_Y);
1517 AND2_190 : AND2
1518 port map(A => AND2_44_Y, B => AND2_50_Y, Y => AND2_190_Y);
1519 DFN1_45 : DFN1
1520 port map(D => PP0_14_net, CLK => Clock, Q => DFN1_45_Q);
1521 XOR2_PP0_2_inst : XOR2
1522 port map(A => MX2_0_Y, B => BUFF_30_Y, Y => PP0_2_net);
1523 XOR2_31 : XOR2
1524 port map(A => DataB(11), B => DataB(12), Y => XOR2_31_Y);
1525 AND2_172 : AND2
1526 port map(A => AND2_100_Y, B => AND2_157_Y, Y => AND2_172_Y);
1527 XOR2_PP6_3_inst : XOR2
1528 port map(A => MX2_27_Y, B => BUFF_20_Y, Y => PP6_3_net);
1529 XOR2_Mult_31_inst : XOR2
1530 port map(A => XOR2_32_Y, B => AO1_78_Y, Y => Mult(31));
1531 AND2_128 : AND2
1532 port map(A => XOR2_105_Y, B => BUFF_24_Y, Y => AND2_128_Y);
1533 DFN1_SumA_7_inst : DFN1
1534 port map(D => MAJ3_78_Y, CLK => Clock, Q => SumA_7_net);
1535 AND2_251 : AND2
1536 port map(A => XOR2_5_Y, B => BUFF_29_Y, Y => AND2_251_Y);
1537 XOR2_PP0_11_inst : XOR2
1538 port map(A => MX2_80_Y, B => BUFF_27_Y, Y => PP0_11_net);
1539 AND2_65 : AND2
1540 port map(A => XOR2_65_Y, B => BUFF_3_Y, Y => AND2_65_Y);
1541 XOR2_14 : XOR2
1542 port map(A => DataB(1), B => DataB(2), Y => XOR2_14_Y);
1543 AO1_EBAR : AO1
1544 port map(A => XOR2_92_Y, B => OR3_1_Y, C => AND3_1_Y, Y =>
1545 EBAR);
1546 DFN1_SumA_2_inst : DFN1
1547 port map(D => DFN1_21_Q, CLK => Clock, Q => SumA_2_net);
1548 BUFF_27 : BUFF
1549 port map(A => DataB(1), Y => BUFF_27_Y);
1550 BUFF_3 : BUFF
1551 port map(A => DataA(4), Y => BUFF_3_Y);
1552 AND2_30 : AND2
1553 port map(A => DataB(0), B => BUFF_24_Y, Y => AND2_30_Y);
1554 MX2_22 : MX2
1555 port map(A => AND2_65_Y, B => BUFF_6_Y, S => NOR2_9_Y, Y =>
1556 MX2_22_Y);
1557 MAJ3_7 : MAJ3
1558 port map(A => DFN1_91_Q, B => DFN1_43_Q, C => DFN1_70_Q,
1559 Y => MAJ3_7_Y);
1560 BUFF_38 : BUFF
1561 port map(A => DataB(5), Y => BUFF_38_Y);
1562 MAJ3_81 : MAJ3
1563 port map(A => XOR3_44_Y, B => AND2_233_Y, C => DFN1_86_Q,
1564 Y => MAJ3_81_Y);
1565 DFN1_136 : DFN1
1566 port map(D => PP5_8_net, CLK => Clock, Q => DFN1_136_Q);
1567 AND2_28 : AND2
1568 port map(A => DFN1_4_Q, B => VCC_1_net, Y => AND2_28_Y);
1569 MAJ3_15 : MAJ3
1570 port map(A => XOR2_88_Y, B => DFN1_113_Q, C => DFN1_100_Q,
1571 Y => MAJ3_15_Y);
1572 XOR2_84 : XOR2
1573 port map(A => SumA_16_net, B => SumB_16_net, Y => XOR2_84_Y);
1574 XOR2_53 : XOR2
1575 port map(A => SumA_19_net, B => SumB_19_net, Y => XOR2_53_Y);
1576 DFN1_23 : DFN1
1577 port map(D => PP0_16_net, CLK => Clock, Q => DFN1_23_Q);
1578 MX2_51 : MX2
1579 port map(A => AND2_173_Y, B => BUFF_53_Y, S => NOR2_11_Y,
1580 Y => MX2_51_Y);
1581 XOR2_PP5_11_inst : XOR2
1582 port map(A => MX2_53_Y, B => BUFF_48_Y, Y => PP5_11_net);
1583 XOR2_4 : XOR2
1584 port map(A => SumA_26_net, B => SumB_26_net, Y => XOR2_4_Y);
1585 AO1_53 : AO1
1586 port map(A => AND2_208_Y, B => AO1_25_Y, C => AO1_39_Y,
1587 Y => AO1_53_Y);
1588 XOR2_59 : XOR2
1589 port map(A => DataB(5), B => DataB(6), Y => XOR2_59_Y);
1590 XOR3_88 : XOR3
1591 port map(A => MAJ3_57_Y, B => XOR3_0_Y, C => XOR3_40_Y,
1592 Y => XOR3_88_Y);
1593 XNOR2_13 : XNOR2
1594 port map(A => DataB(14), B => BUFF_51_Y, Y => XNOR2_13_Y);
1595 AND2_199 : AND2
1596 port map(A => XOR2_40_Y, B => XOR2_113_Y, Y => AND2_199_Y);
1597 XOR3_13 : XOR3
1598 port map(A => DFN1_106_Q, B => VCC_1_net, C => DFN1_72_Q,
1599 Y => XOR3_13_Y);
1600 DFN1_SumA_11_inst : DFN1
1601 port map(D => MAJ3_18_Y, CLK => Clock, Q => SumA_11_net);
1602 XOR2_PP1_9_inst : XOR2
1603 port map(A => MX2_88_Y, B => BUFF_14_Y, Y => PP1_9_net);
1604 DFN1_139 : DFN1
1605 port map(D => PP5_7_net, CLK => Clock, Q => DFN1_139_Q);
1606 DFN1_105 : DFN1
1607 port map(D => PP6_11_net, CLK => Clock, Q => DFN1_105_Q);
1608 MX2_13 : MX2
1609 port map(A => AND2_120_Y, B => BUFF_28_Y, S => NOR2_2_Y,
1610 Y => MX2_13_Y);
1611 MX2_91 : MX2
1612 port map(A => AND2_52_Y, B => BUFF_11_Y, S => NOR2_9_Y,
1613 Y => MX2_91_Y);
1614 AO1_83 : AO1
1615 port map(A => AND2_115_Y, B => AO1_80_Y, C => AO1_30_Y,
1616 Y => AO1_83_Y);
1617 AO1_7 : AO1
1618 port map(A => AND2_61_Y, B => AO1_25_Y, C => AO1_54_Y, Y =>
1619 AO1_7_Y);
1620 DFN1_60 : DFN1
1621 port map(D => PP6_4_net, CLK => Clock, Q => DFN1_60_Q);
1622 MX2_58 : MX2
1623 port map(A => AND2_17_Y, B => BUFF_18_Y, S => NOR2_0_Y,
1624 Y => MX2_58_Y);
1625 XOR3_19 : XOR3
1626 port map(A => DFN1_123_Q, B => DFN1_137_Q, C => DFN1_84_Q,
1627 Y => XOR3_19_Y);
1628 DFN1_147 : DFN1
1629 port map(D => PP2_10_net, CLK => Clock, Q => DFN1_147_Q);
1630 XOR2_PP5_6_inst : XOR2
1631 port map(A => MX2_98_Y, B => BUFF_48_Y, Y => PP5_6_net);
1632 XOR2_98 : XOR2
1633 port map(A => SumA_3_net, B => SumB_3_net, Y => XOR2_98_Y);
1634 DFN1_103 : DFN1
1635 port map(D => PP4_2_net, CLK => Clock, Q => DFN1_103_Q);
1636 DFN1_93 : DFN1
1637 port map(D => PP7_3_net, CLK => Clock, Q => DFN1_93_Q);
1638 AND2_112 : AND2
1639 port map(A => AND2_44_Y, B => XOR2_37_Y, Y => AND2_112_Y);
1640 XOR2_PP0_14_inst : XOR2
1641 port map(A => MX2_47_Y, B => BUFF_0_Y, Y => PP0_14_net);
1642 DFN1_17 : DFN1
1643 port map(D => PP2_7_net, CLK => Clock, Q => DFN1_17_Q);
1644 DFN1_16 : DFN1
1645 port map(D => PP6_0_net, CLK => Clock, Q => DFN1_16_Q);
1646 MX2_77 : MX2
1647 port map(A => AND2_82_Y, B => BUFF_3_Y, S => NOR2_9_Y, Y =>
1648 MX2_77_Y);
1649 DFN1_50 : DFN1
1650 port map(D => PP3_2_net, CLK => Clock, Q => DFN1_50_Q);
1651 AND2_105 : AND2
1652 port map(A => AND2_34_Y, B => AND2_226_Y, Y => AND2_105_Y);
1653 AND2_52 : AND2
1654 port map(A => XOR2_65_Y, B => BUFF_39_Y, Y => AND2_52_Y);
1655 MX2_98 : MX2
1656 port map(A => AND2_151_Y, B => BUFF_40_Y, S => NOR2_1_Y,
1657 Y => MX2_98_Y);
1658 AO1_52 : AO1
1659 port map(A => AND2_226_Y, B => AO1_62_Y, C => AO1_69_Y,
1660 Y => AO1_52_Y);
1661 MAJ3_36 : MAJ3
1662 port map(A => MAJ3_27_Y, B => MAJ3_56_Y, C => XOR2_57_Y,
1663 Y => MAJ3_36_Y);
1664 MX2_80 : MX2
1665 port map(A => AND2_86_Y, B => BUFF_50_Y, S => AND2A_2_Y,
1666 Y => MX2_80_Y);
1667 XOR2_57 : XOR2
1668 port map(A => DFN1_126_Q, B => DFN1_38_Q, Y => XOR2_57_Y);
1669 AO1_41 : AO1
1670 port map(A => XOR2_67_Y, B => AO1_0_Y, C => AND2_253_Y,
1671 Y => AO1_41_Y);
1672 AO1_82 : AO1
1673 port map(A => AND2_135_Y, B => AO1_76_Y, C => AO1_13_Y,
1674 Y => AO1_82_Y);
1675 OR3_3 : OR3
1676 port map(A => DataB(9), B => DataB(10), C => DataB(11),
1677 Y => OR3_3_Y);
1678 AND2_1 : AND2
1679 port map(A => AND2_105_Y, B => AND2_247_Y, Y => AND2_1_Y);
1680 XOR2_PP4_12_inst : XOR2
1681 port map(A => MX2_96_Y, B => BUFF_7_Y, Y => PP4_12_net);
1682 MX2_67 : MX2
1683 port map(A => AND2_88_Y, B => BUFF_13_Y, S => NOR2_10_Y,
1684 Y => MX2_67_Y);
1685 XOR2_PP5_14_inst : XOR2
1686 port map(A => MX2_41_Y, B => BUFF_25_Y, Y => PP5_14_net);
1687 AND2_7 : AND2
1688 port map(A => AND2_59_Y, B => AND2_80_Y, Y => AND2_7_Y);
1689 MAJ3_13 : MAJ3
1690 port map(A => XOR3_95_Y, B => MAJ3_67_Y, C => XOR3_12_Y,
1691 Y => MAJ3_13_Y);
1692 AND2_204 : AND2
1693 port map(A => XOR2_1_Y, B => BUFF_36_Y, Y => AND2_204_Y);
1694 XOR3_17 : XOR3
1695 port map(A => MAJ3_22_Y, B => MAJ3_51_Y, C => XOR3_65_Y,
1696 Y => XOR3_17_Y);
1697 MAJ3_47 : MAJ3
1698 port map(A => XOR3_39_Y, B => DFN1_16_Q, C => DFN1_141_Q,
1699 Y => MAJ3_47_Y);
1700 XOR2_PP3_1_inst : XOR2
1701 port map(A => MX2_123_Y, B => BUFF_15_Y, Y => PP3_1_net);
1702 XOR2_PP0_6_inst : XOR2
1703 port map(A => MX2_18_Y, B => BUFF_27_Y, Y => PP0_6_net);
1704 AND2_100 : AND2
1705 port map(A => AND2_231_Y, B => AND2_37_Y, Y => AND2_100_Y);
1706 DFN1_19 : DFN1
1707 port map(D => PP6_8_net, CLK => Clock, Q => DFN1_19_Q);
1708 XOR2_15 : XOR2
1709 port map(A => DataB(11), B => DataB(12), Y => XOR2_15_Y);
1710 AND2_43 : AND2
1711 port map(A => XOR2_31_Y, B => BUFF_47_Y, Y => AND2_43_Y);
1712 MAJ3_6 : MAJ3
1713 port map(A => XOR3_10_Y, B => MAJ3_73_Y, C => DFN1_1_Q,
1714 Y => MAJ3_6_Y);
1715 AND2_223 : AND2
1716 port map(A => XOR2_14_Y, B => BUFF_49_Y, Y => AND2_223_Y);
1717 AO1_67 : AO1
1718 port map(A => AND2_237_Y, B => AO1_0_Y, C => AO1_20_Y, Y =>
1719 AO1_67_Y);
1720 BUFF_5 : BUFF
1721 port map(A => DataB(7), Y => BUFF_5_Y);
1722 AND2_217 : AND2
1723 port map(A => XOR2_11_Y, B => BUFF_13_Y, Y => AND2_217_Y);
1724 MX2_29 : MX2
1725 port map(A => AND2_158_Y, B => BUFF_28_Y, S => NOR2_8_Y,
1726 Y => MX2_29_Y);
1727 MAJ3_5 : MAJ3
1728 port map(A => XOR3_29_Y, B => MAJ3_91_Y, C => XOR3_5_Y,
1729 Y => MAJ3_5_Y);
1730 DFN1_SumB_24_inst : DFN1
1731 port map(D => XOR3_16_Y, CLK => Clock, Q => SumB_24_net);
1732 XOR2_85 : XOR2
1733 port map(A => SumA_23_net, B => SumB_23_net, Y => XOR2_85_Y);
1734 MX2_4 : MX2
1735 port map(A => AND2_10_Y, B => BUFF_49_Y, S => NOR2_20_Y,
1736 Y => MX2_4_Y);
1737 XOR2_106 : XOR2
1738 port map(A => DFN1_79_Q, B => DFN1_30_Q, Y => XOR2_106_Y);
1739 AND2_188 : AND2
1740 port map(A => XOR2_1_Y, B => BUFF_35_Y, Y => AND2_188_Y);
1741 AND2_144 : AND2
1742 port map(A => XOR2_26_Y, B => BUFF_33_Y, Y => AND2_144_Y);
1743 XOR2_Mult_23_inst : XOR2
1744 port map(A => XOR2_87_Y, B => AO1_10_Y, Y => Mult(23));
1745 NOR2_20 : NOR2
1746 port map(A => XOR2_59_Y, B => XNOR2_17_Y, Y => NOR2_20_Y);
1747 AND2_162 : AND2
1748 port map(A => DataB(0), B => BUFF_50_Y, Y => AND2_162_Y);
1749 AND3_4 : AND3
1750 port map(A => DataB(5), B => DataB(6), C => DataB(7), Y =>
1751 AND3_4_Y);
1752 DFN1_6 : DFN1
1753 port map(D => PP4_1_net, CLK => Clock, Q => DFN1_6_Q);
1754 XOR2_PP2_2_inst : XOR2
1755 port map(A => MX2_115_Y, B => BUFF_38_Y, Y => PP2_2_net);
1756 XOR3_92 : XOR3
1757 port map(A => MAJ3_38_Y, B => MAJ3_19_Y, C => XOR3_14_Y,
1758 Y => XOR3_92_Y);
1759 AND2_231 : AND2
1760 port map(A => AND2_105_Y, B => AND2_247_Y, Y => AND2_231_Y);
1761 AND2_216 : AND2
1762 port map(A => SumA_22_net, B => SumB_22_net, Y =>
1763 AND2_216_Y);
1764 AND2_63 : AND2
1765 port map(A => XOR2_89_Y, B => BUFF_47_Y, Y => AND2_63_Y);
1766 XOR2_PP1_0_inst : XOR2
1767 port map(A => XOR2_99_Y, B => DataB(3), Y => PP1_0_net);
1768 MX2_117 : MX2
1769 port map(A => AND2_3_Y, B => BUFF_11_Y, S => NOR2_16_Y,
1770 Y => MX2_117_Y);
1771 NOR2_1 : NOR2
1772 port map(A => XOR2_51_Y, B => XNOR2_4_Y, Y => NOR2_1_Y);
1773 DFN1_132 : DFN1
1774 port map(D => PP5_1_net, CLK => Clock, Q => DFN1_132_Q);
1775 NOR2_17 : NOR2
1776 port map(A => XOR2_56_Y, B => XNOR2_3_Y, Y => NOR2_17_Y);
1777 BUFF_19 : BUFF
1778 port map(A => DataA(13), Y => BUFF_19_Y);
1779 DFN1_130 : DFN1
1780 port map(D => PP1_2_net, CLK => Clock, Q => DFN1_130_Q);
1781 AO1_68 : AO1
1782 port map(A => AND2_199_Y, B => AO1_87_Y, C => AO1_61_Y,
1783 Y => AO1_68_Y);
1784 XNOR2_8 : XNOR2
1785 port map(A => DataB(4), B => BUFF_4_Y, Y => XNOR2_8_Y);
1786 AND2_109 : AND2
1787 port map(A => XOR2_63_Y, B => BUFF_11_Y, Y => AND2_109_Y);
1788 MAJ3_10 : MAJ3
1789 port map(A => AND2_229_Y, B => DFN1_82_Q, C => DFN1_33_Q,
1790 Y => MAJ3_10_Y);
1791 DFN1_SumA_16_inst : DFN1
1792 port map(D => MAJ3_13_Y, CLK => Clock, Q => SumA_16_net);
1793 DFN1_5 : DFN1
1794 port map(D => PP4_16_net, CLK => Clock, Q => DFN1_5_Q);
1795 AND2_123 : AND2
1796 port map(A => XOR2_59_Y, B => BUFF_19_Y, Y => AND2_123_Y);
1797 DFN1_SumA_8_inst : DFN1
1798 port map(D => MAJ3_83_Y, CLK => Clock, Q => SumA_8_net);
1799 MAJ3_26 : MAJ3
1800 port map(A => XOR3_63_Y, B => MAJ3_70_Y, C => XOR2_19_Y,
1801 Y => MAJ3_26_Y);
1802 NOR2_8 : NOR2
1803 port map(A => XOR2_78_Y, B => XNOR2_8_Y, Y => NOR2_8_Y);
1804 DFN1_SumB_29_inst : DFN1
1805 port map(D => MAJ3_77_Y, CLK => Clock, Q => SumB_29_net);
1806 XOR3_41 : XOR3
1807 port map(A => MAJ3_15_Y, B => MAJ3_50_Y, C => XOR3_77_Y,
1808 Y => XOR3_41_Y);
1809 MX2_32 : MX2
1810 port map(A => AND2_90_Y, B => BUFF_16_Y, S => NOR2_4_Y,
1811 Y => MX2_32_Y);
1812 XOR3_61 : XOR3
1813 port map(A => MAJ3_45_Y, B => MAJ3_20_Y, C => XOR3_68_Y,
1814 Y => XOR3_61_Y);
1815 DFN1_SumA_10_inst : DFN1
1816 port map(D => MAJ3_75_Y, CLK => Clock, Q => SumA_10_net);
1817 AND2_141 : AND2
1818 port map(A => DataB(0), B => BUFF_10_Y, Y => AND2_141_Y);
1819 AND2_239 : AND2
1820 port map(A => XOR2_26_Y, B => BUFF_45_Y, Y => AND2_239_Y);
1821 AOI1_E_4_inst : AOI1
1822 port map(A => XOR2_74_Y, B => OR3_7_Y, C => AND3_0_Y, Y =>
1823 E_4_net);
1824 AO1_74 : AO1
1825 port map(A => AND2_50_Y, B => AO1_89_Y, C => AO1_64_Y, Y =>
1826 AO1_74_Y);
1827 MX2_104 : MX2
1828 port map(A => AND2_119_Y, B => BUFF_6_Y, S => NOR2_3_Y,
1829 Y => MX2_104_Y);
1830 AND2_95 : AND2
1831 port map(A => AND2_234_Y, B => AND2_191_Y, Y => AND2_95_Y);
1832 AND3_1 : AND3
1833 port map(A => GND_1_net, B => DataB(0), C => DataB(1), Y =>
1834 AND3_1_Y);
1835 XOR2_22 : XOR2
1836 port map(A => DFN1_112_Q, B => DFN1_63_Q, Y => XOR2_22_Y);
1837 MX2_86 : MX2
1838 port map(A => BUFF_25_Y, B => XOR2_70_Y, S => XOR2_56_Y,
1839 Y => MX2_86_Y);
1840 MX2_11 : MX2
1841 port map(A => BUFF_46_Y, B => XOR2_47_Y, S => XOR2_17_Y,
1842 Y => MX2_11_Y);
1843 AND2_27 : AND2
1844 port map(A => XOR2_109_Y, B => BUFF_13_Y, Y => AND2_27_Y);
1845 MAJ3_49 : MAJ3
1846 port map(A => XOR3_65_Y, B => MAJ3_22_Y, C => MAJ3_51_Y,
1847 Y => MAJ3_49_Y);
1848 DFN1_42 : DFN1
1849 port map(D => PP1_3_net, CLK => Clock, Q => DFN1_42_Q);
1850 BUFF_29 : BUFF
1851 port map(A => DataA(2), Y => BUFF_29_Y);
1852 XOR2_32 : XOR2
1853 port map(A => SumA_30_net, B => SumB_30_net, Y => XOR2_32_Y);
1854 MAJ3_48 : MAJ3
1855 port map(A => XOR3_87_Y, B => MAJ3_28_Y, C => XOR2_16_Y,
1856 Y => MAJ3_48_Y);
1857 AND2_14 : AND2
1858 port map(A => AND2_207_Y, B => AND2_177_Y, Y => AND2_14_Y);
1859 XOR3_96 : XOR3
1860 port map(A => XOR2_41_Y, B => DFN1_92_Q, C => MAJ3_11_Y,
1861 Y => XOR3_96_Y);
1862 MAJ3_76 : MAJ3
1863 port map(A => XOR3_13_Y, B => MAJ3_12_Y, C => AND2_9_Y,
1864 Y => MAJ3_76_Y);
1865 XOR2_Mult_20_inst : XOR2
1866 port map(A => XOR2_21_Y, B => AO1_45_Y, Y => Mult(20));
1867 XOR2_PP6_1_inst : XOR2
1868 port map(A => MX2_91_Y, B => BUFF_20_Y, Y => PP6_1_net);
1869 AND2_74 : AND2
1870 port map(A => SumA_9_net, B => SumB_9_net, Y => AND2_74_Y);
1871 DFN1_14 : DFN1
1872 port map(D => PP7_5_net, CLK => Clock, Q => DFN1_14_Q);
1873 AND2_82 : AND2
1874 port map(A => XOR2_65_Y, B => BUFF_40_Y, Y => AND2_82_Y);
1875 AND2_58 : AND2
1876 port map(A => AND2_34_Y, B => AND2_226_Y, Y => AND2_58_Y);
1877 XOR2_10 : XOR2
1878 port map(A => SumA_12_net, B => SumB_12_net, Y => XOR2_10_Y);
1879 MX2_18 : MX2
1880 port map(A => AND2_141_Y, B => BUFF_53_Y, S => AND2A_2_Y,
1881 Y => MX2_18_Y);
1882 AND2_245 : AND2
1883 port map(A => XOR2_5_Y, B => BUFF_11_Y, Y => AND2_245_Y);
1884 XOR3_28 : XOR3
1885 port map(A => DFN1_13_Q, B => DFN1_95_Q, C => DFN1_139_Q,
1886 Y => XOR3_28_Y);
1887 XNOR2_9 : XNOR2
1888 port map(A => DataB(8), B => BUFF_37_Y, Y => XNOR2_9_Y);
1889 MAJ3_87 : MAJ3
1890 port map(A => DFN1_149_Q, B => DFN1_64_Q, C => DFN1_17_Q,
1891 Y => MAJ3_87_Y);
1892 XOR2_PP3_6_inst : XOR2
1893 port map(A => MX2_62_Y, B => BUFF_5_Y, Y => PP3_6_net);
1894 AO1_20 : AO1
1895 port map(A => XOR2_24_Y, B => AND2_253_Y, C => AND2_42_Y,
1896 Y => AO1_20_Y);
1897 DFN1_70 : DFN1
1898 port map(D => PP1_12_net, CLK => Clock, Q => DFN1_70_Q);
1899 XOR2_PP1_13_inst : XOR2
1900 port map(A => MX2_13_Y, B => BUFF_46_Y, Y => PP1_13_net);
1901 XOR3_38 : XOR3
1902 port map(A => DFN1_16_Q, B => DFN1_141_Q, C => XOR3_39_Y,
1903 Y => XOR3_38_Y);
1904 MX2_126 : MX2
1905 port map(A => AND2_205_Y, B => BUFF_12_Y, S => NOR2_13_Y,
1906 Y => MX2_126_Y);
1907 XOR2_80 : XOR2
1908 port map(A => BUFF_54_Y, B => DataB(5), Y => XOR2_80_Y);
1909 MX2_125 : MX2
1910 port map(A => AND2_156_Y, B => BUFF_39_Y, S => NOR2_3_Y,
1911 Y => MX2_125_Y);
1912 DFN1_108 : DFN1
1913 port map(D => E_3_net, CLK => Clock, Q => DFN1_108_Q);
1914 XOR2_Mult_22_inst : XOR2
1915 port map(A => XOR2_6_Y, B => AO1_83_Y, Y => Mult(22));
1916 MX2_73 : MX2
1917 port map(A => AND2_251_Y, B => BUFF_39_Y, S => NOR2_16_Y,
1918 Y => MX2_73_Y);
1919 XNOR2_12 : XNOR2
1920 port map(A => DataB(4), B => BUFF_38_Y, Y => XNOR2_12_Y);
1921 AND2_S_4_inst : AND2
1922 port map(A => XOR2_0_Y, B => DataB(9), Y => S_4_net);
1923 XOR2_26 : XOR2
1924 port map(A => DataB(5), B => DataB(6), Y => XOR2_26_Y);
1925 AO1_79 : AO1
1926 port map(A => AND2_131_Y, B => AO1_88_Y, C => AO1_84_Y,
1927 Y => AO1_79_Y);
1928 AND2_212 : AND2
1929 port map(A => AND2_207_Y, B => AND2_31_Y, Y => AND2_212_Y);
1930 XOR2_PP2_1_inst : XOR2
1931 port map(A => MX2_49_Y, B => BUFF_38_Y, Y => PP2_1_net);
1932 XOR2_36 : XOR2
1933 port map(A => SumA_27_net, B => SumB_27_net, Y => XOR2_36_Y);
1934 MX2_44 : MX2
1935 port map(A => BUFF_7_Y, B => XOR2_74_Y, S => XOR2_1_Y, Y =>
1936 MX2_44_Y);
1937 AND2_21 : AND2
1938 port map(A => XOR2_105_Y, B => BUFF_33_Y, Y => AND2_21_Y);
1939 BUFF_34 : BUFF
1940 port map(A => DataB(5), Y => BUFF_34_Y);
1941 MAJ3_35 : MAJ3
1942 port map(A => XOR3_35_Y, B => MAJ3_52_Y, C => MAJ3_3_Y,
1943 Y => MAJ3_35_Y);
1944 XOR2_PP2_10_inst : XOR2
1945 port map(A => MX2_120_Y, B => BUFF_34_Y, Y => PP2_10_net);
1946 AO1_57 : AO1
1947 port map(A => AND2_182_Y, B => AO1_29_Y, C => AO1_33_Y,
1948 Y => AO1_57_Y);
1949 MX2_63 : MX2
1950 port map(A => AND2_204_Y, B => BUFF_2_Y, S => NOR2_14_Y,
1951 Y => MX2_63_Y);
1952 MX2_39 : MX2
1953 port map(A => AND2_139_Y, B => BUFF_52_Y, S => NOR2_1_Y,
1954 Y => MX2_39_Y);
1955 MX2_101 : MX2
1956 port map(A => AND2_148_Y, B => BUFF_8_Y, S => NOR2_10_Y,
1957 Y => MX2_101_Y);
1958 AND2_192 : AND2
1959 port map(A => DataB(0), B => BUFF_45_Y, Y => AND2_192_Y);
1960 XOR3_54 : XOR3
1961 port map(A => XOR2_43_Y, B => DFN1_3_Q, C => XOR3_19_Y,
1962 Y => XOR3_54_Y);
1963 DFN1_67 : DFN1
1964 port map(D => PP3_13_net, CLK => Clock, Q => DFN1_67_Q);
1965 AND2_3 : AND2
1966 port map(A => XOR2_5_Y, B => BUFF_39_Y, Y => AND2_3_Y);
1967 XOR2_PP1_6_inst : XOR2
1968 port map(A => MX2_61_Y, B => BUFF_14_Y, Y => PP1_6_net);
1969 AO1_87 : AO1
1970 port map(A => XOR2_25_Y, B => AND2_184_Y, C => AND2_74_Y,
1971 Y => AO1_87_Y);
1972 DFN1_66 : DFN1
1973 port map(D => PP2_13_net, CLK => Clock, Q => DFN1_66_Q);
1974 AND2_S_6_inst : AND2
1975 port map(A => XOR2_2_Y, B => DataB(13), Y => S_6_net);
1976 AND2_220 : AND2
1977 port map(A => AND2_225_Y, B => AND2_131_Y, Y => AND2_220_Y);
1978 DFN1_SumB_7_inst : DFN1
1979 port map(D => XOR3_73_Y, CLK => Clock, Q => SumB_7_net);
1980 XOR2_102 : XOR2
1981 port map(A => SumA_12_net, B => SumB_12_net, Y =>
1982 XOR2_102_Y);
1983 DFN1_111 : DFN1
1984 port map(D => PP0_3_net, CLK => Clock, Q => DFN1_111_Q);
1985 DFN1_48 : DFN1
1986 port map(D => PP3_15_net, CLK => Clock, Q => DFN1_48_Q);
1987 XOR2_PP7_3_inst : XOR2
1988 port map(A => MX2_43_Y, B => BUFF_26_Y, Y => PP7_3_net);
1989 DFN1_SumB_14_inst : DFN1
1990 port map(D => XOR3_32_Y, CLK => Clock, Q => SumB_14_net);
1991 MX2_PP7_16_inst : MX2
1992 port map(A => MX2_30_Y, B => AO1_31_Y, S => NOR2_7_Y, Y =>
1993 PP7_16_net);
1994 DFN1_57 : DFN1
1995 port map(D => PP7_12_net, CLK => Clock, Q => DFN1_57_Q);
1996 AND2_183 : AND2
1997 port map(A => XOR2_109_Y, B => BUFF_8_Y, Y => AND2_183_Y);
1998 DFN1_56 : DFN1
1999 port map(D => PP6_13_net, CLK => Clock, Q => DFN1_56_Q);
2000 MAJ3_66 : MAJ3
2001 port map(A => XOR3_76_Y, B => MAJ3_17_Y, C => AND2_48_Y,
2002 Y => MAJ3_66_Y);
2003 AND2_178 : AND2
2004 port map(A => AND2_157_Y, B => AND2_103_Y, Y => AND2_178_Y);
2005 MAJ3_56 : MAJ3
2006 port map(A => AND2_238_Y, B => DFN1_105_Q, C => DFN1_99_Q,
2007 Y => MAJ3_56_Y);
2008 AO1_58 : AO1
2009 port map(A => AND2_249_Y, B => AO1_84_Y, C => AO1_6_Y, Y =>
2010 AO1_58_Y);
2011 XOR2_PP3_4_inst : XOR2
2012 port map(A => MX2_78_Y, B => BUFF_15_Y, Y => PP3_4_net);
2013 MAJ3_89 : MAJ3
2014 port map(A => XOR3_38_Y, B => MAJ3_87_Y, C => MAJ3_62_Y,
2015 Y => MAJ3_89_Y);
2016 AO1_25 : AO1
2017 port map(A => AND2_37_Y, B => AO1_75_Y, C => AO1_60_Y, Y =>
2018 AO1_25_Y);
2019 DFN1_SumB_27_inst : DFN1
2020 port map(D => XOR3_45_Y, CLK => Clock, Q => SumB_27_net);
2021 MAJ3_88 : MAJ3
2022 port map(A => XOR3_66_Y, B => MAJ3_90_Y, C => MAJ3_68_Y,
2023 Y => MAJ3_88_Y);
2024 XOR2_78 : XOR2
2025 port map(A => DataB(3), B => DataB(4), Y => XOR2_78_Y);
2026 DFN1_7 : DFN1
2027 port map(D => PP7_11_net, CLK => Clock, Q => DFN1_7_Q);
2028 DFN1_69 : DFN1
2029 port map(D => PP6_9_net, CLK => Clock, Q => DFN1_69_Q);
2030 AO1_88 : AO1
2031 port map(A => AND2_37_Y, B => AO1_40_Y, C => AO1_60_Y, Y =>
2032 AO1_88_Y);
2033 DFN1_SumB_22_inst : DFN1
2034 port map(D => XOR3_82_Y, CLK => Clock, Q => SumB_22_net);
2035 AND2_93 : AND2
2036 port map(A => XOR2_13_Y, B => XOR2_85_Y, Y => AND2_93_Y);
2037 DFN1_SumB_19_inst : DFN1
2038 port map(D => XOR3_55_Y, CLK => Clock, Q => SumB_19_net);
2039 AND2A_0 : AND2A
2040 port map(A => DataB(0), B => BUFF_0_Y, Y => AND2A_0_Y);
2041 DFN1_59 : DFN1
2042 port map(D => PP4_12_net, CLK => Clock, Q => DFN1_59_Q);
2043 XOR3_74 : XOR3
2044 port map(A => MAJ3_89_Y, B => XOR3_25_Y, C => XOR3_20_Y,
2045 Y => XOR3_74_Y);
2046 XOR2_51 : XOR2
2047 port map(A => DataB(9), B => DataB(10), Y => XOR2_51_Y);
2048 AND2_26 : AND2
2049 port map(A => DFN1_52_Q, B => DFN1_60_Q, Y => AND2_26_Y);
2050 XOR3_9 : XOR3
2051 port map(A => DFN1_58_Q, B => DFN1_50_Q, C => AND2_121_Y,
2052 Y => XOR3_9_Y);
2053 MAJ3_33 : MAJ3
2054 port map(A => XOR2_44_Y, B => DFN1_57_Q, C => DFN1_12_Q,
2055 Y => MAJ3_33_Y);
2056 DFN1_35 : DFN1
2057 port map(D => PP5_13_net, CLK => Clock, Q => DFN1_35_Q);
2058 XOR2_104 : XOR2
2059 port map(A => SumA_23_net, B => SumB_23_net, Y =>
2060 XOR2_104_Y);
2061 AND2_88 : AND2
2062 port map(A => XOR2_109_Y, B => BUFF_50_Y, Y => AND2_88_Y);
2063 MAJ3_25 : MAJ3
2064 port map(A => DFN1_2_Q, B => DFN1_130_Q, C => DFN1_143_Q,
2065 Y => MAJ3_25_Y);
2066 AND2_228 : AND2
2067 port map(A => AND2_1_Y, B => AND2_179_Y, Y => AND2_228_Y);
2068 XOR2_PP4_8_inst : XOR2
2069 port map(A => MX2_106_Y, B => BUFF_37_Y, Y => PP4_8_net);
2070 XOR2_111 : XOR2
2071 port map(A => SumA_0_net, B => SumB_0_net, Y => XOR2_111_Y);
2072 XOR2_Mult_30_inst : XOR2
2073 port map(A => XOR2_100_Y, B => AO1_19_Y, Y => Mult(30));
2074 DFN1_SumA_9_inst : DFN1
2075 port map(D => MAJ3_95_Y, CLK => Clock, Q => SumA_9_net);
2076 XOR3_11 : XOR3
2077 port map(A => MAJ3_67_Y, B => XOR3_12_Y, C => XOR3_95_Y,
2078 Y => XOR3_11_Y);
2079 AND2_S_0_inst : AND2
2080 port map(A => XOR2_62_Y, B => DataB(1), Y => S_0_net);
2081 BUFF_54 : BUFF
2082 port map(A => DataA(15), Y => BUFF_54_Y);
2083 MX2_109 : MX2
2084 port map(A => AND2_22_Y, B => BUFF_16_Y, S => NOR2_12_Y,
2085 Y => MX2_109_Y);
2086 XOR3_42 : XOR3
2087 port map(A => DFN1_148_Q, B => DFN1_34_Q, C => XOR2_91_Y,
2088 Y => XOR3_42_Y);
2089 DFN1_85 : DFN1
2090 port map(D => PP2_8_net, CLK => Clock, Q => DFN1_85_Q);
2091 XOR3_62 : XOR3
2092 port map(A => DFN1_135_Q, B => DFN1_90_Q, C => DFN1_88_Q,
2093 Y => XOR3_62_Y);
2094 AND2_118 : AND2
2095 port map(A => XOR2_66_Y, B => BUFF_29_Y, Y => AND2_118_Y);
2096 XOR2_13 : XOR2
2097 port map(A => SumA_22_net, B => SumB_22_net, Y => XOR2_13_Y);
2098 DFN1_43 : DFN1
2099 port map(D => PP3_8_net, CLK => Clock, Q => DFN1_43_Q);
2100 XOR2_2 : XOR2
2101 port map(A => AND2_101_Y, B => BUFF_20_Y, Y => XOR2_2_Y);
2102 MX2_87 : MX2
2103 port map(A => AND2_192_Y, B => BUFF_32_Y, S => AND2A_1_Y,
2104 Y => MX2_87_Y);
2105 XOR3_55 : XOR3
2106 port map(A => MAJ3_2_Y, B => XOR3_24_Y, C => XOR3_47_Y,
2107 Y => XOR3_55_Y);
2108 BUFF_42 : BUFF
2109 port map(A => DataB(7), Y => BUFF_42_Y);
2110 XOR2_Mult_19_inst : XOR2
2111 port map(A => XOR2_101_Y, B => AO1_79_Y, Y => Mult(19));
2112 AND2_57 : AND2
2113 port map(A => AND2_131_Y, B => AND2_249_Y, Y => AND2_57_Y);
2114 MX2_71 : MX2
2115 port map(A => AND2_175_Y, B => BUFF_39_Y, S => NOR2_9_Y,
2116 Y => MX2_71_Y);
2117 MAJ3_75 : MAJ3
2118 port map(A => XOR3_30_Y, B => MAJ3_4_Y, C => XOR3_26_Y,
2119 Y => MAJ3_75_Y);
2120 DFN1_SumB_2_inst : DFN1
2121 port map(D => XOR2_79_Y, CLK => Clock, Q => SumB_2_net);
2122 AND2_34 : AND2
2123 port map(A => XOR2_111_Y, B => XOR2_72_Y, Y => AND2_34_Y);
2124 XOR2_3 : XOR2
2125 port map(A => SumA_16_net, B => SumB_16_net, Y => XOR2_3_Y);
2126 XOR2_PP7_10_inst : XOR2
2127 port map(A => MX2_70_Y, B => BUFF_23_Y, Y => PP7_10_net);
2128 XOR2_19 : XOR2
2129 port map(A => DFN1_152_Q, B => DFN1_109_Q, Y => XOR2_19_Y);
2130 AND2_102 : AND2
2131 port map(A => SumA_0_net, B => SumB_0_net, Y => AND2_102_Y);
2132 AO1_2 : AO1
2133 port map(A => AND2_176_Y, B => AO1_80_Y, C => AO1_43_Y,
2134 Y => AO1_2_Y);
2135 XOR2_PP3_7_inst : XOR2
2136 port map(A => MX2_111_Y, B => BUFF_5_Y, Y => PP3_7_net);
2137 XOR2_83 : XOR2
2138 port map(A => SumA_20_net, B => SumB_20_net, Y => XOR2_83_Y);
2139 MAJ3_30 : MAJ3
2140 port map(A => XOR3_20_Y, B => MAJ3_89_Y, C => XOR3_25_Y,
2141 Y => MAJ3_30_Y);
2142 XNOR2_3 : XNOR2
2143 port map(A => DataB(10), B => BUFF_25_Y, Y => XNOR2_3_Y);
2144 AO1_61 : AO1
2145 port map(A => XOR2_113_Y, B => AND2_241_Y, C => AND2_164_Y,
2146 Y => AO1_61_Y);
2147 XOR2_Mult_27_inst : XOR2
2148 port map(A => XOR2_75_Y, B => AO1_35_Y, Y => Mult(27));
2149 XOR2_68 : XOR2
2150 port map(A => SumA_6_net, B => SumB_6_net, Y => XOR2_68_Y);
2151 MX2_61 : MX2
2152 port map(A => AND2_221_Y, B => BUFF_53_Y, S => NOR2_15_Y,
2153 Y => MX2_61_Y);
2154 XOR2_PP0_4_inst : XOR2
2155 port map(A => MX2_87_Y, B => BUFF_30_Y, Y => PP0_4_net);
2156 MX2_78 : MX2
2157 port map(A => AND2_239_Y, B => BUFF_32_Y, S => NOR2_5_Y,
2158 Y => MX2_78_Y);
2159 DFN1_145 : DFN1
2160 port map(D => PP2_4_net, CLK => Clock, Q => DFN1_145_Q);
2161 MAJ3_92 : MAJ3
2162 port map(A => XOR3_41_Y, B => MAJ3_88_Y, C => XOR3_53_Y,
2163 Y => MAJ3_92_Y);
2164 XOR2_89 : XOR2
2165 port map(A => DataB(13), B => DataB(14), Y => XOR2_89_Y);
2166 XOR2_PP3_10_inst : XOR2
2167 port map(A => MX2_67_Y, B => BUFF_5_Y, Y => PP3_10_net);
2168 XOR2_PP1_8_inst : XOR2
2169 port map(A => MX2_66_Y, B => BUFF_14_Y, Y => PP1_8_net);
2170 XOR2_PP7_4_inst : XOR2
2171 port map(A => MX2_94_Y, B => BUFF_26_Y, Y => PP7_4_net);
2172 DFN1_64 : DFN1
2173 port map(D => PP4_3_net, CLK => Clock, Q => DFN1_64_Q);
2174 BUFF_9 : BUFF
2175 port map(A => DataB(13), Y => BUFF_9_Y);
2176 MAJ3_23 : MAJ3
2177 port map(A => DFN1_44_Q, B => DFN1_67_Q, C => DFN1_128_Q,
2178 Y => MAJ3_23_Y);
2179 AO1_33 : AO1
2180 port map(A => XOR2_28_Y, B => AND2_5_Y, C => AND2_196_Y,
2181 Y => AO1_33_Y);
2182 BUFF_35 : BUFF
2183 port map(A => DataA(14), Y => BUFF_35_Y);
2184 DFN1_SumA_28_inst : DFN1
2185 port map(D => MAJ3_74_Y, CLK => Clock, Q => SumA_28_net);
2186 DFN1_143 : DFN1
2187 port map(D => PP0_4_net, CLK => Clock, Q => DFN1_143_Q);
2188 XOR2_PP3_9_inst : XOR2
2189 port map(A => MX2_69_Y, B => BUFF_5_Y, Y => PP3_9_net);
2190 AND2_126 : AND2
2191 port map(A => SumA_13_net, B => SumB_13_net, Y =>
2192 AND2_126_Y);
2193 DFN1_Mult_0_inst : DFN1
2194 port map(D => DFN1_117_Q, CLK => Clock, Q => Mult(0));
2195 BUFF_30 : BUFF
2196 port map(A => DataB(1), Y => BUFF_30_Y);
2197 XOR2_PP6_11_inst : XOR2
2198 port map(A => MX2_45_Y, B => BUFF_9_Y, Y => PP6_11_net);
2199 XOR3_46 : XOR3
2200 port map(A => MAJ3_7_Y, B => DFN1_29_Q, C => XOR3_48_Y,
2201 Y => XOR3_46_Y);
2202 XOR3_66 : XOR3
2203 port map(A => DFN1_9_Q, B => DFN1_119_Q, C => MAJ3_54_Y,
2204 Y => XOR3_66_Y);
2205 MX2_68 : MX2
2206 port map(A => AND2_165_Y, B => BUFF_32_Y, S => NOR2_19_Y,
2207 Y => MX2_68_Y);
2208 MX2_25 : MX2
2209 port map(A => AND2_127_Y, B => BUFF_36_Y, S => NOR2_0_Y,
2210 Y => MX2_25_Y);
2211 DFN1_54 : DFN1
2212 port map(D => PP6_6_net, CLK => Clock, Q => DFN1_54_Q);
2213 XOR2_17 : XOR2
2214 port map(A => DataB(1), B => DataB(2), Y => XOR2_17_Y);
2215 XOR2_113 : XOR2
2216 port map(A => SumA_11_net, B => SumB_11_net, Y =>
2217 XOR2_113_Y);
2218 XOR3_75 : XOR3
2219 port map(A => AND2_233_Y, B => DFN1_86_Q, C => XOR3_44_Y,
2220 Y => XOR3_75_Y);
2221 AND2_207 : AND2
2222 port map(A => AND2_168_Y, B => AND2_199_Y, Y => AND2_207_Y);
2223 XOR2_PP0_15_inst : XOR2
2224 port map(A => MX2_97_Y, B => BUFF_0_Y, Y => PP0_15_net);
2225 AND2_154 : AND2
2226 port map(A => DFN1_80_Q, B => DFN1_54_Q, Y => AND2_154_Y);
2227 DFN1_77 : DFN1
2228 port map(D => PP2_3_net, CLK => Clock, Q => DFN1_77_Q);
2229 AND2_145 : AND2
2230 port map(A => XOR2_11_Y, B => BUFF_17_Y, Y => AND2_145_Y);
2231 AND2_168 : AND2
2232 port map(A => XOR2_30_Y, B => XOR2_25_Y, Y => AND2_168_Y);
2233 AND2_51 : AND2
2234 port map(A => SumA_18_net, B => SumB_18_net, Y => AND2_51_Y);
2235 DFN1_76 : DFN1
2236 port map(D => PP2_15_net, CLK => Clock, Q => DFN1_76_Q);
2237 AO1_10 : AO1
2238 port map(A => AND2_140_Y, B => AO1_80_Y, C => AO1_57_Y,
2239 Y => AO1_10_Y);
2240 DFN1_0 : DFN1
2241 port map(D => S_0_net, CLK => Clock, Q => DFN1_0_Q);
2242 OR3_1 : OR3
2243 port map(A => GND_1_net, B => DataB(0), C => DataB(1), Y =>
2244 OR3_1_Y);
2245 XOR2_87 : XOR2
2246 port map(A => SumA_22_net, B => SumB_22_net, Y => XOR2_87_Y);
2247 AO1_32 : AO1
2248 port map(A => AND2_125_Y, B => AO1_89_Y, C => AO1_49_Y,
2249 Y => AO1_32_Y);
2250 XOR2_PP5_8_inst : XOR2
2251 port map(A => MX2_39_Y, B => BUFF_48_Y, Y => PP5_8_net);
2252 MAJ3_73 : MAJ3
2253 port map(A => DFN1_84_Q, B => DFN1_123_Q, C => DFN1_137_Q,
2254 Y => MAJ3_73_Y);
2255 NOR2_18 : NOR2
2256 port map(A => XOR2_58_Y, B => XNOR2_16_Y, Y => NOR2_18_Y);
2257 XOR2_PP6_7_inst : XOR2
2258 port map(A => MX2_109_Y, B => BUFF_9_Y, Y => PP6_7_net);
2259 AO1_76 : AO1
2260 port map(A => XOR2_76_Y, B => AND2_171_Y, C => AND2_94_Y,
2261 Y => AO1_76_Y);
2262 DFN1_SumB_23_inst : DFN1
2263 port map(D => XOR3_71_Y, CLK => Clock, Q => SumB_23_net);
2264 BUFF_1 : BUFF
2265 port map(A => DataA(14), Y => BUFF_1_Y);
2266 MAJ3_14 : MAJ3
2267 port map(A => XOR3_48_Y, B => MAJ3_7_Y, C => DFN1_29_Q,
2268 Y => MAJ3_14_Y);
2269 AND2_173 : AND2
2270 port map(A => XOR2_11_Y, B => BUFF_10_Y, Y => AND2_173_Y);
2271 AND2_29 : AND2
2272 port map(A => AND2_55_Y, B => XOR2_68_Y, Y => AND2_29_Y);
2273 AND2_206 : AND2
2274 port map(A => XOR2_78_Y, B => BUFF_54_Y, Y => AND2_206_Y);
2275 BUFF_18 : BUFF
2276 port map(A => DataA(11), Y => BUFF_18_Y);
2277 AND2_244 : AND2
2278 port map(A => XOR2_51_Y, B => BUFF_52_Y, Y => AND2_244_Y);
2279 XOR2_PP5_15_inst : XOR2
2280 port map(A => MX2_15_Y, B => BUFF_25_Y, Y => PP5_15_net);
2281 DFN1_SumB_17_inst : DFN1
2282 port map(D => XOR3_51_Y, CLK => Clock, Q => SumB_17_net);
2283 MX2_40 : MX2
2284 port map(A => AND2_167_Y, B => BUFF_22_Y, S => NOR2_12_Y,
2285 Y => MX2_40_Y);
2286 AND2_140 : AND2
2287 port map(A => AND2_57_Y, B => AND2_182_Y, Y => AND2_140_Y);
2288 XOR2_PP1_5_inst : XOR2
2289 port map(A => MX2_124_Y, B => BUFF_21_Y, Y => PP1_5_net);
2290 MAJ3_20 : MAJ3
2291 port map(A => DFN1_56_Q, B => DFN1_68_Q, C => DFN1_75_Q,
2292 Y => MAJ3_20_Y);
2293 MAJ3_65 : MAJ3
2294 port map(A => XOR3_79_Y, B => AND2_81_Y, C => DFN1_127_Q,
2295 Y => MAJ3_65_Y);
2296 AND2_151 : AND2
2297 port map(A => XOR2_51_Y, B => BUFF_16_Y, Y => AND2_151_Y);
2298 MAJ3_55 : MAJ3
2299 port map(A => XOR3_34_Y, B => MAJ3_58_Y, C => MAJ3_76_Y,
2300 Y => MAJ3_55_Y);
2301 XOR3_50 : XOR3
2302 port map(A => MAJ3_12_Y, B => AND2_9_Y, C => XOR3_13_Y,
2303 Y => XOR3_50_Y);
2304 AND2_213 : AND2
2305 port map(A => AND2_225_Y, B => XOR2_84_Y, Y => AND2_213_Y);
2306 DFN1_SumA_0_inst : DFN1
2307 port map(D => DFN1_114_Q, CLK => Clock, Q => SumA_0_net);
2308 DFN1_79 : DFN1
2309 port map(D => PP1_5_net, CLK => Clock, Q => DFN1_79_Q);
2310 MX2_108 : MX2
2311 port map(A => AND2_72_Y, B => BUFF_19_Y, S => NOR2_8_Y,
2312 Y => MX2_108_Y);
2313 XOR2_PP6_14_inst : XOR2
2314 port map(A => MX2_25_Y, B => BUFF_43_Y, Y => PP6_14_net);
2315 DFN1_SumB_12_inst : DFN1
2316 port map(D => XOR3_74_Y, CLK => Clock, Q => SumB_12_net);
2317 XOR2_PP1_3_inst : XOR2
2318 port map(A => MX2_56_Y, B => BUFF_21_Y, Y => PP1_3_net);
2319 XOR2_PP2_5_inst : XOR2
2320 port map(A => MX2_31_Y, B => BUFF_38_Y, Y => PP2_5_net);
2321 DFN1_116 : DFN1
2322 port map(D => E_7_net, CLK => Clock, Q => DFN1_116_Q);
2323 XOR2_PP2_7_inst : XOR2
2324 port map(A => MX2_114_Y, B => BUFF_34_Y, Y => PP2_7_net);
2325 DFN1_21 : DFN1
2326 port map(D => S_1_net, CLK => Clock, Q => DFN1_21_Q);
2327 BUFF_2 : BUFF
2328 port map(A => DataA(12), Y => BUFF_2_Y);
2329 AND2_15 : AND2
2330 port map(A => AND2_58_Y, B => AND2_29_Y, Y => AND2_15_Y);
2331 AND2_87 : AND2
2332 port map(A => XOR2_35_Y, B => BUFF_16_Y, Y => AND2_87_Y);
2333 AO1_90 : AO1
2334 port map(A => XOR2_68_Y, B => AO1_76_Y, C => AND2_147_Y,
2335 Y => AO1_90_Y);
2336 BUFF_28 : BUFF
2337 port map(A => DataA(12), Y => BUFF_28_Y);
2338 DFN1_SumB_25_inst : DFN1
2339 port map(D => XOR3_61_Y, CLK => Clock, Q => SumB_25_net);
2340 XOR2_PP4_4_inst : XOR2
2341 port map(A => MX2_104_Y, B => BUFF_41_Y, Y => PP4_4_net);
2342 AND2_75 : AND2
2343 port map(A => XOR2_105_Y, B => BUFF_31_Y, Y => AND2_75_Y);
2344 AND2_127 : AND2
2345 port map(A => XOR2_31_Y, B => BUFF_35_Y, Y => AND2_127_Y);
2346 AO1_24 : AO1
2347 port map(A => XOR2_93_Y, B => AO1_23_Y, C => AND2_171_Y,
2348 Y => AO1_24_Y);
2349 BUFF_0 : BUFF
2350 port map(A => DataB(1), Y => BUFF_0_Y);
2351 MAJ3_70 : MAJ3
2352 port map(A => DFN1_46_Q, B => DFN1_147_Q, C => DFN1_45_Q,
2353 Y => MAJ3_70_Y);
2354 BUFF_55 : BUFF
2355 port map(A => DataB(11), Y => BUFF_55_Y);
2356 AND2_255 : AND2
2357 port map(A => XOR2_58_Y, B => BUFF_45_Y, Y => AND2_255_Y);
2358 AND2_56 : AND2
2359 port map(A => DFN1_6_Q, B => DFN1_107_Q, Y => AND2_56_Y);
2360 DFN1_119 : DFN1
2361 port map(D => PP5_12_net, CLK => Clock, Q => DFN1_119_Q);
2362 BUFF_50 : BUFF
2363 port map(A => DataA(10), Y => BUFF_50_Y);
2364 XOR2_PP2_9_inst : XOR2
2365 port map(A => MX2_24_Y, B => BUFF_34_Y, Y => PP2_9_net);
2366 AND2_149 : AND2
2367 port map(A => XOR2_66_Y, B => BUFF_11_Y, Y => AND2_149_Y);
2368 XOR2_PP1_12_inst : XOR2
2369 port map(A => MX2_3_Y, B => BUFF_46_Y, Y => PP1_12_net);
2370 DFN1_SumA_14_inst : DFN1
2371 port map(D => MAJ3_61_Y, CLK => Clock, Q => SumA_14_net);
2372 XOR2_52 : XOR2
2373 port map(A => DFN1_80_Q, B => DFN1_54_Q, Y => XOR2_52_Y);
2374 AND2_113 : AND2
2375 port map(A => DataB(0), B => BUFF_1_Y, Y => AND2_113_Y);
2376 AO1_15 : AO1
2377 port map(A => AND2_247_Y, B => AO1_52_Y, C => AO1_82_Y,
2378 Y => AO1_15_Y);
2379 XNOR2_6 : XNOR2
2380 port map(A => DataB(8), B => BUFF_7_Y, Y => XNOR2_6_Y);
2381 DFN1_32 : DFN1
2382 port map(D => PP6_15_net, CLK => Clock, Q => DFN1_32_Q);
2383 XOR3_84 : XOR3
2384 port map(A => MAJ3_56_Y, B => XOR2_57_Y, C => MAJ3_27_Y,
2385 Y => XOR3_84_Y);
2386 DFN1_91 : DFN1
2387 port map(D => PP5_4_net, CLK => Clock, Q => DFN1_91_Q);
2388 XOR3_70 : XOR3
2389 port map(A => MAJ3_58_Y, B => MAJ3_76_Y, C => XOR3_34_Y,
2390 Y => XOR3_70_Y);
2391 MX2_83 : MX2
2392 port map(A => AND2_143_Y, B => BUFF_13_Y, S => NOR2_15_Y,
2393 Y => MX2_83_Y);
2394 AO1_51 : AO1
2395 port map(A => AND2_212_Y, B => AO1_40_Y, C => AO1_5_Y, Y =>
2396 AO1_51_Y);
2397 MX2_120 : MX2
2398 port map(A => AND2_0_Y, B => BUFF_13_Y, S => NOR2_11_Y,
2399 Y => MX2_120_Y);
2400 XOR3_12 : XOR3
2401 port map(A => MAJ3_82_Y, B => AND2_124_Y, C => XOR3_49_Y,
2402 Y => XOR3_12_Y);
2403 BUFF_46 : BUFF
2404 port map(A => DataB(3), Y => BUFF_46_Y);
2405 MAJ3_63 : MAJ3
2406 port map(A => DFN1_74_Q, B => DFN1_27_Q, C => DFN1_73_Q,
2407 Y => MAJ3_63_Y);
2408 XOR3_4 : XOR3
2409 port map(A => MAJ3_35_Y, B => XOR3_60_Y, C => XOR3_18_Y,
2410 Y => XOR3_4_Y);
2411 AND2_186 : AND2
2412 port map(A => XOR2_105_Y, B => BUFF_53_Y, Y => AND2_186_Y);
2413 MAJ3_53 : MAJ3
2414 port map(A => XOR3_40_Y, B => MAJ3_57_Y, C => XOR3_0_Y,
2415 Y => MAJ3_53_Y);
2416 XOR3_6 : XOR3
2417 port map(A => DFN1_132_Q, B => DFN1_81_Q, C => XOR2_22_Y,
2418 Y => XOR3_6_Y);
2419 XOR2_94 : XOR2
2420 port map(A => SumA_8_net, B => SumB_8_net, Y => XOR2_94_Y);
2421 AO1_81 : AO1
2422 port map(A => AND2_97_Y, B => AO1_44_Y, C => AO1_32_Y, Y =>
2423 AO1_81_Y);
2424 DFN1_82 : DFN1
2425 port map(D => PP5_2_net, CLK => Clock, Q => DFN1_82_Q);
2426 AOI1_E_6_inst : AOI1
2427 port map(A => XOR2_33_Y, B => OR3_0_Y, C => AND3_3_Y, Y =>
2428 E_6_net);
2429 DFN1_SumA_19_inst : DFN1
2430 port map(D => MAJ3_8_Y, CLK => Clock, Q => SumA_19_net);
2431 AND2_202 : AND2
2432 port map(A => XOR2_109_Y, B => BUFF_10_Y, Y => AND2_202_Y);
2433 AND2_81 : AND2
2434 port map(A => DFN1_42_Q, B => DFN1_124_Q, Y => AND2_81_Y);
2435 AND2_198 : AND2
2436 port map(A => AND2_182_Y, B => AND2_93_Y, Y => AND2_198_Y);
2437 MX2_46 : MX2
2438 port map(A => AND2_63_Y, B => BUFF_35_Y, S => NOR2_7_Y,
2439 Y => MX2_46_Y);
2440 AND2_20 : AND2
2441 port map(A => XOR2_17_Y, B => BUFF_28_Y, Y => AND2_20_Y);
2442 AND2_134 : AND2
2443 port map(A => XOR2_51_Y, B => BUFF_12_Y, Y => AND2_134_Y);
2444 DFN1_74 : DFN1
2445 port map(D => PP4_7_net, CLK => Clock, Q => DFN1_74_Q);
2446 MX2_35 : MX2
2447 port map(A => AND2_83_Y, B => BUFF_31_Y, S => AND2A_1_Y,
2448 Y => MX2_35_Y);
2449 AO1_29 : AO1
2450 port map(A => AND2_249_Y, B => AO1_84_Y, C => AO1_6_Y, Y =>
2451 AO1_29_Y);
2452 XOR2_56 : XOR2
2453 port map(A => DataB(9), B => DataB(10), Y => XOR2_56_Y);
2454 XNOR2_5 : XNOR2
2455 port map(A => DataB(10), B => BUFF_55_Y, Y => XNOR2_5_Y);
2456 DFN1_148 : DFN1
2457 port map(D => S_2_net, CLK => Clock, Q => DFN1_148_Q);
2458 AND2_163 : AND2
2459 port map(A => XOR2_56_Y, B => BUFF_36_Y, Y => AND2_163_Y);
2460 DFN1_SumB_1_inst : DFN1
2461 port map(D => DFN1_120_Q, CLK => Clock, Q => SumB_1_net);
2462 MAJ3_4 : MAJ3
2463 port map(A => MAJ3_11_Y, B => XOR2_41_Y, C => DFN1_92_Q,
2464 Y => MAJ3_4_Y);
2465 XOR3_16 : XOR3
2466 port map(A => MAJ3_36_Y, B => XOR3_72_Y, C => XOR3_91_Y,
2467 Y => XOR3_16_Y);
2468 MAJ3_60 : MAJ3
2469 port map(A => DFN1_103_Q, B => DFN1_49_Q, C => DFN1_102_Q,
2470 Y => MAJ3_60_Y);
2471 XOR2_PP2_0_inst : XOR2
2472 port map(A => XOR2_34_Y, B => DataB(5), Y => PP2_0_net);
2473 MAJ3_50 : MAJ3
2474 port map(A => MAJ3_54_Y, B => DFN1_9_Q, C => DFN1_119_Q,
2475 Y => MAJ3_50_Y);
2476 AO1_1 : AO1
2477 port map(A => AND2_37_Y, B => AO1_75_Y, C => AO1_60_Y, Y =>
2478 AO1_1_Y);
2479 AND2_131 : AND2
2480 port map(A => XOR2_84_Y, B => XOR2_46_Y, Y => AND2_131_Y);
2481 XOR2_PP4_11_inst : XOR2
2482 port map(A => MX2_126_Y, B => BUFF_37_Y, Y => PP4_11_net);
2483 XOR2_PP7_1_inst : XOR2
2484 port map(A => MX2_117_Y, B => BUFF_26_Y, Y => PP7_1_net);
2485 DFN1_SumB_13_inst : DFN1
2486 port map(D => XOR3_2_Y, CLK => Clock, Q => SumB_13_net);
2487 DFN1_112 : DFN1
2488 port map(D => PP1_9_net, CLK => Clock, Q => DFN1_112_Q);
2489 DFN1_38 : DFN1
2490 port map(D => PP6_12_net, CLK => Clock, Q => DFN1_38_Q);
2491 DFN1_110 : DFN1
2492 port map(D => E_0_net, CLK => Clock, Q => DFN1_110_Q);
2493 DFN1_124 : DFN1
2494 port map(D => PP0_5_net, CLK => Clock, Q => DFN1_124_Q);
2495 AO1_37 : AO1
2496 port map(A => AND2_29_Y, B => AO1_23_Y, C => AO1_90_Y, Y =>
2497 AO1_37_Y);
2498 XOR2_100 : XOR2
2499 port map(A => SumA_29_net, B => SumB_29_net, Y =>
2500 XOR2_100_Y);
2501 XOR3_85 : XOR3
2502 port map(A => DFN1_59_Q, B => DFN1_10_Q, C => DFN1_19_Q,
2503 Y => XOR3_85_Y);
2504 XOR3_53 : XOR3
2505 port map(A => DFN1_35_Q, B => DFN1_108_Q, C => DFN1_134_Q,
2506 Y => XOR3_53_Y);
2507 MX2_2 : MX2
2508 port map(A => AND2_209_Y, B => BUFF_22_Y, S => NOR2_13_Y,
2509 Y => MX2_2_Y);
2510 XOR2_PP4_9_inst : XOR2
2511 port map(A => MX2_2_Y, B => BUFF_37_Y, Y => PP4_9_net);
2512 AND2_187 : AND2
2513 port map(A => XOR2_5_Y, B => BUFF_6_Y, Y => AND2_187_Y);
2514 XNOR2_14 : XNOR2
2515 port map(A => DataB(6), B => BUFF_5_Y, Y => XNOR2_14_Y);
2516 XOR2_PP2_13_inst : XOR2
2517 port map(A => MX2_29_Y, B => BUFF_4_Y, Y => PP2_13_net);
2518 AND2_13 : AND2
2519 port map(A => XOR2_35_Y, B => BUFF_22_Y, Y => AND2_13_Y);
2520 AND2_210 : AND2
2521 port map(A => XOR2_103_Y, B => XOR2_60_Y, Y => AND2_210_Y);
2522 AND2_86 : AND2
2523 port map(A => DataB(0), B => BUFF_49_Y, Y => AND2_86_Y);
2524 AND2_73 : AND2
2525 port map(A => XOR2_26_Y, B => BUFF_53_Y, Y => AND2_73_Y);
2526 AND2_59 : AND2
2527 port map(A => AND2_105_Y, B => AND2_247_Y, Y => AND2_59_Y);
2528 XOR3_59 : XOR3
2529 port map(A => MAJ3_4_Y, B => XOR3_26_Y, C => XOR3_30_Y,
2530 Y => XOR3_59_Y);
2531 MAJ3_91 : MAJ3
2532 port map(A => XOR3_14_Y, B => MAJ3_38_Y, C => MAJ3_19_Y,
2533 Y => MAJ3_91_Y);
2534 DFN1_88 : DFN1
2535 port map(D => PP2_5_net, CLK => Clock, Q => DFN1_88_Q);
2536 AO1_40 : AO1
2537 port map(A => AND2_247_Y, B => AO1_52_Y, C => AO1_82_Y,
2538 Y => AO1_40_Y);
2539 AND2_235 : AND2
2540 port map(A => AND2_58_Y, B => XOR2_93_Y, Y => AND2_235_Y);
2541 XOR2_95 : XOR2
2542 port map(A => DFN1_52_Q, B => DFN1_60_Q, Y => XOR2_95_Y);
2543 DFN1_SumB_15_inst : DFN1
2544 port map(D => XOR3_11_Y, CLK => Clock, Q => SumB_15_net);
2545 AO1_38 : AO1
2546 port map(A => XOR2_40_Y, B => AO1_87_Y, C => AND2_241_Y,
2547 Y => AO1_38_Y);
2548 AO1_9 : AO1
2549 port map(A => XOR2_85_Y, B => AND2_216_Y, C => AND2_170_Y,
2550 Y => AO1_9_Y);
2551 XOR2_11 : XOR2
2552 port map(A => DataB(3), B => DataB(4), Y => XOR2_11_Y);
2553 MX2_81 : MX2
2554 port map(A => AND2_203_Y, B => BUFF_17_Y, S => AND2A_2_Y,
2555 Y => MX2_81_Y);
2556 MX2_52 : MX2
2557 port map(A => AND2_236_Y, B => BUFF_33_Y, S => NOR2_18_Y,
2558 Y => MX2_52_Y);
2559 XOR2_PP4_14_inst : XOR2
2560 port map(A => MX2_110_Y, B => BUFF_7_Y, Y => PP4_14_net);
2561 AND2_35 : AND2
2562 port map(A => XOR2_63_Y, B => BUFF_39_Y, Y => AND2_35_Y);
2563 AND2_108 : AND2
2564 port map(A => DataB(0), B => BUFF_31_Y, Y => AND2_108_Y);
2565 XOR2_48 : XOR2
2566 port map(A => SumA_7_net, B => SumB_7_net, Y => XOR2_48_Y);
2567 XOR2_PP3_3_inst : XOR2
2568 port map(A => MX2_33_Y, B => BUFF_15_Y, Y => PP3_3_net);
2569 MAJ3_34 : MAJ3
2570 port map(A => XOR3_70_Y, B => MAJ3_40_Y, C => XOR3_64_Y,
2571 Y => MAJ3_34_Y);
2572 XOR3_57 : XOR3
2573 port map(A => MAJ3_90_Y, B => MAJ3_68_Y, C => XOR3_66_Y,
2574 Y => XOR3_57_Y);
2575 XOR2_81 : XOR2
2576 port map(A => DataB(13), B => DataB(14), Y => XOR2_81_Y);
2577 MX2_92 : MX2
2578 port map(A => AND2_73_Y, B => BUFF_45_Y, S => NOR2_5_Y,
2579 Y => MX2_92_Y);
2580 XOR3_73 : XOR3
2581 port map(A => MAJ3_93_Y, B => XOR3_36_Y, C => XOR3_9_Y,
2582 Y => XOR3_73_Y);
2583 XOR2_PP3_8_inst : XOR2
2584 port map(A => MX2_101_Y, B => BUFF_5_Y, Y => PP3_8_net);
2585 NOR2_9 : NOR2
2586 port map(A => XOR2_65_Y, B => XNOR2_0_Y, Y => NOR2_9_Y);
2587 AOI1_E_1_inst : AOI1
2588 port map(A => XOR2_47_Y, B => OR3_2_Y, C => AND3_6_Y, Y =>
2589 E_1_net);
2590 XOR2_PP0_3_inst : XOR2
2591 port map(A => MX2_35_Y, B => BUFF_30_Y, Y => PP0_3_net);
2592 MX2_88 : MX2
2593 port map(A => AND2_211_Y, B => BUFF_17_Y, S => NOR2_15_Y,
2594 Y => MX2_88_Y);
2595 BUFF_14 : BUFF
2596 port map(A => DataB(3), Y => BUFF_14_Y);
2597 XOR3_24 : XOR3
2598 port map(A => MAJ3_23_Y, B => DFN1_39_Q, C => XOR3_85_Y,
2599 Y => XOR3_24_Y);
2600 AND2_218 : AND2
2601 port map(A => XOR2_66_Y, B => BUFF_6_Y, Y => AND2_218_Y);
2602 DFN1_SumA_17_inst : DFN1
2603 port map(D => MAJ3_24_Y, CLK => Clock, Q => SumA_17_net);
2604 DFN1_15 : DFN1
2605 port map(D => EBAR, CLK => Clock, Q => DFN1_15_Q);
2606 XOR3_79 : XOR3
2607 port map(A => DFN1_8_Q, B => DFN1_18_Q, C => DFN1_125_Q,
2608 Y => XOR3_79_Y);
2609 DFN1_33 : DFN1
2610 port map(D => PP3_6_net, CLK => Clock, Q => DFN1_33_Q);
2611 XOR2_5 : XOR2
2612 port map(A => DataB(13), B => DataB(14), Y => XOR2_5_Y);
2613 AND2_176 : AND2
2614 port map(A => AND2_104_Y, B => AND2_25_Y, Y => AND2_176_Y);
2615 MAJ3_8 : MAJ3
2616 port map(A => XOR3_18_Y, B => MAJ3_35_Y, C => XOR3_60_Y,
2617 Y => MAJ3_8_Y);
2618 XOR2_PP4_6_inst : XOR2
2619 port map(A => MX2_74_Y, B => BUFF_37_Y, Y => PP4_6_net);
2620 XOR2_PP0_8_inst : XOR2
2621 port map(A => MX2_100_Y, B => BUFF_27_Y, Y => PP0_8_net);
2622 XOR3_34 : XOR3
2623 port map(A => MAJ3_21_Y, B => DFN1_69_Q, C => XOR3_81_Y,
2624 Y => XOR3_34_Y);
2625 XNOR2_17 : XNOR2
2626 port map(A => DataB(6), B => BUFF_42_Y, Y => XNOR2_17_Y);
2627 DFN1_SumA_12_inst : DFN1
2628 port map(D => MAJ3_53_Y, CLK => Clock, Q => SumA_12_net);
2629 XOR2_Mult_25_inst : XOR2
2630 port map(A => XOR2_23_Y, B => AO1_71_Y, Y => Mult(25));
2631 AND2_193 : AND2
2632 port map(A => XOR2_58_Y, B => BUFF_53_Y, Y => AND2_193_Y);
2633 XOR3_1 : XOR3
2634 port map(A => MAJ3_70_Y, B => XOR2_19_Y, C => XOR3_63_Y,
2635 Y => XOR3_1_Y);
2636 AO1_14 : AO1
2637 port map(A => XOR2_61_Y, B => OR3_5_Y, C => AND3_4_Y, Y =>
2638 AO1_14_Y);
2639 XOR3_80 : XOR3
2640 port map(A => MAJ3_80_Y, B => AND2_26_Y, C => XOR3_28_Y,
2641 Y => XOR3_80_Y);
2642 MX2_103 : MX2
2643 port map(A => AND2_129_Y, B => BUFF_1_Y, S => NOR2_20_Y,
2644 Y => MX2_103_Y);
2645 AO1_45 : AO1
2646 port map(A => AND2_66_Y, B => AO1_88_Y, C => AO1_55_Y, Y =>
2647 AO1_45_Y);
2648 DFN1_83 : DFN1
2649 port map(D => PP6_5_net, CLK => Clock, Q => DFN1_83_Q);
2650 AND2_155 : AND2
2651 port map(A => AND2_157_Y, B => AND2_210_Y, Y => AND2_155_Y);
2652 BUFF_24 : BUFF
2653 port map(A => DataA(1), Y => BUFF_24_Y);
2654 XOR2_112 : XOR2
2655 port map(A => SumA_3_net, B => SumB_3_net, Y => XOR2_112_Y);
2656 AND2_142 : AND2
2657 port map(A => XOR2_59_Y, B => BUFF_1_Y, Y => AND2_142_Y);
2658 XOR3_77 : XOR3
2659 port map(A => DFN1_105_Q, B => DFN1_99_Q, C => AND2_238_Y,
2660 Y => XOR3_77_Y);
2661 XOR2_PP0_7_inst : XOR2
2662 port map(A => MX2_9_Y, B => BUFF_27_Y, Y => PP0_7_net);
2663 MX2_47 : MX2
2664 port map(A => AND2_113_Y, B => BUFF_19_Y, S => AND2A_0_Y,
2665 Y => MX2_47_Y);
2666 XOR2_90 : XOR2
2667 port map(A => SumA_27_net, B => SumB_27_net, Y => XOR2_90_Y);
2668 AND2_50 : AND2
2669 port map(A => XOR2_37_Y, B => XOR2_96_Y, Y => AND2_50_Y);
2670 DFN1_127 : DFN1
2671 port map(D => PP3_0_net, CLK => Clock, Q => DFN1_127_Q);
2672 XOR2_Mult_1_inst : XOR2
2673 port map(A => SumA_0_net, B => SumB_0_net, Y => Mult(1));
2674 MX2_24 : MX2
2675 port map(A => AND2_217_Y, B => BUFF_17_Y, S => NOR2_11_Y,
2676 Y => MX2_24_Y);
2677 XOR2_PP7_13_inst : XOR2
2678 port map(A => MX2_57_Y, B => BUFF_51_Y, Y => PP7_13_net);
2679 XNOR2_18 : XNOR2
2680 port map(A => DataB(8), B => BUFF_41_Y, Y => XNOR2_18_Y);
2681 AND2_254 : AND2
2682 port map(A => XOR2_81_Y, B => BUFF_44_Y, Y => AND2_254_Y);
2683 DFN1_101 : DFN1
2684 port map(D => PP5_5_net, CLK => Clock, Q => DFN1_101_Q);
2685 MX2_114 : MX2
2686 port map(A => AND2_32_Y, B => BUFF_10_Y, S => NOR2_11_Y,
2687 Y => MX2_114_Y);
2688 AND2_150 : AND2
2689 port map(A => XOR2_17_Y, B => BUFF_54_Y, Y => AND2_150_Y);
2690 MAJ3_24 : MAJ3
2691 port map(A => XOR3_92_Y, B => MAJ3_44_Y, C => XOR3_80_Y,
2692 Y => MAJ3_24_Y);
2693 MX2_59 : MX2
2694 port map(A => AND2_106_Y, B => BUFF_3_Y, S => NOR2_3_Y,
2695 Y => MX2_59_Y);
2696 AND2_89 : AND2
2697 port map(A => AND2_225_Y, B => AND2_57_Y, Y => AND2_89_Y);
2698 AND2_116 : AND2
2699 port map(A => XOR2_15_Y, B => BUFF_16_Y, Y => AND2_116_Y);
2700 MX2_127 : MX2
2701 port map(A => AND2_206_Y, B => BUFF_1_Y, S => NOR2_8_Y,
2702 Y => MX2_127_Y);
2703 XOR2_PP3_13_inst : XOR2
2704 port map(A => MX2_118_Y, B => BUFF_42_Y, Y => PP3_13_net);
2705 MAJ3_46 : MAJ3
2706 port map(A => DFN1_125_Q, B => DFN1_8_Q, C => DFN1_18_Q,
2707 Y => MAJ3_46_Y);
2708 MX2_3 : MX2
2709 port map(A => AND2_20_Y, B => BUFF_49_Y, S => NOR2_2_Y,
2710 Y => MX2_3_Y);
2711 AO1_26 : AO1
2712 port map(A => AND2_210_Y, B => AO1_18_Y, C => AO1_66_Y,
2713 Y => AO1_26_Y);
2714 MX2_99 : MX2
2715 port map(A => AND2_30_Y, B => BUFF_33_Y, S => AND2A_1_Y,
2716 Y => MX2_99_Y);
2717 AND2_203 : AND2
2718 port map(A => DataB(0), B => BUFF_13_Y, Y => AND2_203_Y);
2719 XOR2_74 : XOR2
2720 port map(A => BUFF_47_Y, B => DataB(9), Y => XOR2_74_Y);
2721 AND2_247 : AND2
2722 port map(A => AND2_55_Y, B => AND2_135_Y, Y => AND2_247_Y);
2723 NOR2_11 : NOR2
2724 port map(A => XOR2_11_Y, B => XNOR2_11_Y, Y => NOR2_11_Y);
2725 AO1_19 : AO1
2726 port map(A => AND2_191_Y, B => AO1_1_Y, C => AO1_16_Y, Y =>
2727 AO1_19_Y);
2728 AND2_177 : AND2
2729 port map(A => XOR2_102_Y, B => XOR2_42_Y, Y => AND2_177_Y);
2730 XOR2_PP7_6_inst : XOR2
2731 port map(A => MX2_48_Y, B => BUFF_23_Y, Y => PP7_6_net);
2732 XOR3_25 : XOR3
2733 port map(A => DFN1_40_Q, B => DFN1_150_Q, C => MAJ3_29_Y,
2734 Y => XOR3_25_Y);
2735 DFN1_134 : DFN1
2736 port map(D => PP7_9_net, CLK => Clock, Q => DFN1_134_Q);
2737 AND2_42 : AND2
2738 port map(A => SumA_15_net, B => SumB_15_net, Y => AND2_42_Y);
2739 MAJ3_74 : MAJ3
2740 port map(A => MAJ3_71_Y, B => XOR2_55_Y, C => DFN1_89_Q,
2741 Y => MAJ3_74_Y);
2742 AND2_33 : AND2
2743 port map(A => XOR2_4_Y, B => XOR2_90_Y, Y => AND2_33_Y);
2744 XOR3_35 : XOR3
2745 port map(A => MAJ3_72_Y, B => XOR2_52_Y, C => XOR3_52_Y,
2746 Y => XOR3_35_Y);
2747 AO1_4 : AO1
2748 port map(A => XOR2_74_Y, B => OR3_7_Y, C => AND3_0_Y, Y =>
2749 AO1_4_Y);
2750 AND2_159 : AND2
2751 port map(A => AND2_100_Y, B => AND2_115_Y, Y => AND2_159_Y);
2752 NOR2_10 : NOR2
2753 port map(A => XOR2_109_Y, B => XNOR2_14_Y, Y => NOR2_10_Y);
2754 MX2_12 : MX2
2755 port map(A => AND2_111_Y, B => BUFF_2_Y, S => NOR2_0_Y,
2756 Y => MX2_12_Y);
2757 AND2_246 : AND2
2758 port map(A => XOR2_89_Y, B => BUFF_2_Y, Y => AND2_246_Y);
2759 AND2_2 : AND2
2760 port map(A => XOR2_78_Y, B => BUFF_28_Y, Y => AND2_2_Y);
2761 MX2_102 : MX2
2762 port map(A => AND2_137_Y, B => BUFF_18_Y, S => NOR2_17_Y,
2763 Y => MX2_102_Y);
2764 DFN1_41 : DFN1
2765 port map(D => PP5_0_net, CLK => Clock, Q => DFN1_41_Q);
2766 AND2_221 : AND2
2767 port map(A => XOR2_14_Y, B => BUFF_10_Y, Y => AND2_221_Y);
2768 BUFF_43 : BUFF
2769 port map(A => DataB(13), Y => BUFF_43_Y);
2770 AND2_62 : AND2
2771 port map(A => SumA_25_net, B => SumB_25_net, Y => AND2_62_Y);
2772 XOR2_107 : XOR2
2773 port map(A => SumA_2_net, B => SumB_2_net, Y => XOR2_107_Y);
2774 BUFF_41 : BUFF
2775 port map(A => DataB(9), Y => BUFF_41_Y);
2776 AND2_103 : AND2
2777 port map(A => AND2_210_Y, B => XOR2_4_Y, Y => AND2_103_Y);
2778 XOR2_PP5_0_inst : XOR2
2779 port map(A => XOR2_86_Y, B => DataB(11), Y => PP5_0_net);
2780 XOR2_PP6_15_inst : XOR2
2781 port map(A => MX2_6_Y, B => BUFF_43_Y, Y => PP6_15_net);
2782 XNOR2_1 : XNOR2
2783 port map(A => DataB(14), B => BUFF_23_Y, Y => XNOR2_1_Y);
2784 AND3_2 : AND3
2785 port map(A => DataB(3), B => DataB(4), C => DataB(5), Y =>
2786 AND3_2_Y);
2787 XOR2_PP7_7_inst : XOR2
2788 port map(A => MX2_32_Y, B => BUFF_23_Y, Y => PP7_7_net);
2789 AND2_166 : AND2
2790 port map(A => DFN1_47_Q, B => VCC_1_net, Y => AND2_166_Y);
2791 MX2_111 : MX2
2792 port map(A => AND2_183_Y, B => BUFF_10_Y, S => NOR2_10_Y,
2793 Y => MX2_111_Y);
2794 DFN1_SumA_13_inst : DFN1
2795 port map(D => MAJ3_30_Y, CLK => Clock, Q => SumA_13_net);
2796 BUFF_15 : BUFF
2797 port map(A => DataB(7), Y => BUFF_15_Y);
2798 DFN1_SumB_6_inst : DFN1
2799 port map(D => XOR3_7_Y, CLK => Clock, Q => SumB_6_net);
2800 BUFF_10 : BUFF
2801 port map(A => DataA(6), Y => BUFF_10_Y);
2802 XOR2_12 : XOR2
2803 port map(A => SumA_9_net, B => SumB_9_net, Y => XOR2_12_Y);
2804 NOR2_13 : NOR2
2805 port map(A => XOR2_35_Y, B => XNOR2_9_Y, Y => NOR2_13_Y);
2806 AND2_117 : AND2
2807 port map(A => AND2_1_Y, B => AND2_168_Y, Y => AND2_117_Y);
2808 AND2_229 : AND2
2809 port map(A => DFN1_112_Q, B => DFN1_63_Q, Y => AND2_229_Y);
2810 AND2_135 : AND2
2811 port map(A => XOR2_68_Y, B => XOR2_48_Y, Y => AND2_135_Y);
2812 XOR2_64 : XOR2
2813 port map(A => SumA_15_net, B => SumB_15_net, Y => XOR2_64_Y);
2814 AND2_80 : AND2
2815 port map(A => AND2_92_Y, B => XOR2_102_Y, Y => AND2_80_Y);
2816 XOR2_82 : XOR2
2817 port map(A => SumA_17_net, B => SumB_17_net, Y => XOR2_82_Y);
2818 XOR3_83 : XOR3
2819 port map(A => MAJ3_63_Y, B => XOR2_95_Y, C => XOR3_90_Y,
2820 Y => XOR3_83_Y);
2821 MAJ3_86 : MAJ3
2822 port map(A => XOR3_27_Y, B => MAJ3_49_Y, C => XOR3_46_Y,
2823 Y => MAJ3_86_Y);
2824 XOR2_Mult_5_inst : XOR2
2825 port map(A => XOR2_29_Y, B => AO1_23_Y, Y => Mult(5));
2826 XOR2_75 : XOR2
2827 port map(A => SumA_26_net, B => SumB_26_net, Y => XOR2_75_Y);
2828 BUFF_25 : BUFF
2829 port map(A => DataB(11), Y => BUFF_25_Y);
2830 OR3_7 : OR3
2831 port map(A => DataB(7), B => DataB(8), C => DataB(9), Y =>
2832 OR3_7_Y);
2833 DFN1_12 : DFN1
2834 port map(D => PP6_14_net, CLK => Clock, Q => DFN1_12_Q);
2835 BUFF_20 : BUFF
2836 port map(A => DataB(13), Y => BUFF_20_Y);
2837 AND2_234 : AND2
2838 port map(A => AND2_231_Y, B => AND2_37_Y, Y => AND2_234_Y);
2839 DFN1_SumA_15_inst : DFN1
2840 port map(D => MAJ3_86_Y, CLK => Clock, Q => SumA_15_net);
2841 MAJ3_64 : MAJ3
2842 port map(A => XOR3_84_Y, B => MAJ3_96_Y, C => XOR3_3_Y,
2843 Y => MAJ3_64_Y);
2844 XOR3_20 : XOR3
2845 port map(A => MAJ3_10_Y, B => MAJ3_47_Y, C => XOR3_54_Y,
2846 Y => XOR3_20_Y);
2847 XOR3_89 : XOR3
2848 port map(A => MAJ3_40_Y, B => XOR3_64_Y, C => XOR3_70_Y,
2849 Y => XOR3_89_Y);
2850 MAJ3_54 : MAJ3
2851 port map(A => DFN1_31_Q, B => DFN1_48_Q, C => DFN1_87_Q,
2852 Y => MAJ3_54_Y);
2853 MAJ3_12 : MAJ3
2854 port map(A => DFN1_131_Q, B => DFN1_76_Q, C => DFN1_110_Q,
2855 Y => MAJ3_12_Y);
2856 AND2_130 : AND2
2857 port map(A => AND2_41_Y, B => AND2_155_Y, Y => AND2_130_Y);
2858 DFN1_65 : DFN1
2859 port map(D => E_6_net, CLK => Clock, Q => DFN1_65_Q);
2860 MX2_34 : MX2
2861 port map(A => AND2_122_Y, B => BUFF_24_Y, S => NOR2_5_Y,
2862 Y => MX2_34_Y);
2863 XOR2_Mult_7_inst : XOR2
2864 port map(A => XOR2_108_Y, B => AO1_47_Y, Y => Mult(7));
2865 AO1_31 : AO1
2866 port map(A => XOR2_38_Y, B => OR3_4_Y, C => AND3_7_Y, Y =>
2867 AO1_31_Y);
2868 XOR2_93 : XOR2
2869 port map(A => SumA_4_net, B => SumB_4_net, Y => XOR2_93_Y);
2870 XOR2_PP7_5_inst : XOR2
2871 port map(A => MX2_107_Y, B => BUFF_26_Y, Y => PP7_5_net);
2872 MX2_19 : MX2
2873 port map(A => AND2_222_Y, B => BUFF_10_Y, S => NOR2_15_Y,
2874 Y => MX2_19_Y);
2875 MX2_43 : MX2
2876 port map(A => AND2_187_Y, B => BUFF_29_Y, S => NOR2_16_Y,
2877 Y => MX2_43_Y);
2878 XOR3_30 : XOR3
2879 port map(A => MAJ3_32_Y, B => AND2_56_Y, C => XOR3_23_Y,
2880 Y => XOR3_30_Y);
2881 XOR2_16 : XOR2
2882 port map(A => DFN1_14_Q, B => DFN1_53_Q, Y => XOR2_16_Y);
2883 DFN1_55 : DFN1
2884 port map(D => PP1_13_net, CLK => Clock, Q => DFN1_55_Q);
2885 AND2_242 : AND2
2886 port map(A => AND2_1_Y, B => AND2_92_Y, Y => AND2_242_Y);
2887 XOR2_99 : XOR2
2888 port map(A => AND2_79_Y, B => BUFF_21_Y, Y => XOR2_99_Y);
2889 NOR2_7 : NOR2
2890 port map(A => XOR2_89_Y, B => XNOR2_13_Y, Y => NOR2_7_Y);
2891 XOR2_PP4_2_inst : XOR2
2892 port map(A => MX2_125_Y, B => BUFF_41_Y, Y => PP4_2_net);
2893 XOR3_51 : XOR3
2894 port map(A => MAJ3_91_Y, B => XOR3_5_Y, C => XOR3_29_Y,
2895 Y => XOR3_51_Y);
2896 AND2_24 : AND2
2897 port map(A => XOR2_5_Y, B => BUFF_40_Y, Y => AND2_24_Y);
2898 XOR2_PP2_12_inst : XOR2
2899 port map(A => MX2_116_Y, B => BUFF_4_Y, Y => PP2_12_net);
2900 AND2_48 : AND2
2901 port map(A => DFN1_93_Q, B => DFN1_83_Q, Y => AND2_48_Y);
2902 DFN1_137 : DFN1
2903 port map(D => PP0_13_net, CLK => Clock, Q => DFN1_137_Q);
2904 XOR2_Mult_26_inst : XOR2
2905 port map(A => XOR2_20_Y, B => AO1_7_Y, Y => Mult(26));
2906 AO1_44 : AO1
2907 port map(A => AND2_198_Y, B => AO1_58_Y, C => AO1_86_Y,
2908 Y => AO1_44_Y);
2909 XOR2_86 : XOR2
2910 port map(A => AND2_149_Y, B => BUFF_55_Y, Y => XOR2_86_Y);
2911 AND2_167 : AND2
2912 port map(A => XOR2_15_Y, B => BUFF_44_Y, Y => AND2_167_Y);
2913 XOR2_Mult_18_inst : XOR2
2914 port map(A => XOR2_82_Y, B => AO1_72_Y, Y => Mult(18));
2915 MX2_119 : MX2
2916 port map(A => AND2_230_Y, B => BUFF_11_Y, S => NOR2_6_Y,
2917 Y => MX2_119_Y);
2918 DFN1_SumA_6_inst : DFN1
2919 port map(D => MAJ3_65_Y, CLK => Clock, Q => SumA_6_net);
2920 XOR3_87 : XOR3
2921 port map(A => DFN1_76_Q, B => DFN1_110_Q, C => DFN1_131_Q,
2922 Y => XOR3_87_Y);
2923 AO1_60 : AO1
2924 port map(A => AND2_47_Y, B => AO1_68_Y, C => AO1_67_Y, Y =>
2925 AO1_60_Y);
2926 AND2_200 : AND2
2927 port map(A => AND2_41_Y, B => AND2_61_Y, Y => AND2_200_Y);
2928 AND2_139 : AND2
2929 port map(A => XOR2_51_Y, B => BUFF_22_Y, Y => AND2_139_Y);
2930 DFN1_SumA_21_inst : DFN1
2931 port map(D => MAJ3_34_Y, CLK => Clock, Q => SumA_21_net);
2932 MAJ3_45 : MAJ3
2933 port map(A => MAJ3_85_Y, B => AND2_68_Y, C => DFN1_7_Q,
2934 Y => MAJ3_45_Y);
2935 MX2_20 : MX2
2936 port map(A => AND2_258_Y, B => BUFF_36_Y, S => NOR2_7_Y,
2937 Y => MX2_20_Y);
2938 XOR2_97 : XOR2
2939 port map(A => SumA_2_net, B => SumB_2_net, Y => XOR2_97_Y);
2940 AND2_68 : AND2
2941 port map(A => DFN1_126_Q, B => DFN1_38_Q, Y => AND2_68_Y);
2942 DFN1_106 : DFN1
2943 port map(D => PP3_14_net, CLK => Clock, Q => DFN1_106_Q);
2944 DFN1_20 : DFN1
2945 port map(D => PP1_8_net, CLK => Clock, Q => DFN1_20_Q);
2946 AND2_196 : AND2
2947 port map(A => SumA_21_net, B => SumB_21_net, Y =>
2948 AND2_196_Y);
2949 XOR2_65 : XOR2
2950 port map(A => DataB(11), B => DataB(12), Y => XOR2_65_Y);
2951 XOR2_PP6_0_inst : XOR2
2952 port map(A => XOR2_2_Y, B => DataB(13), Y => PP6_0_net);
2953 MX2_PP2_16_inst : MX2
2954 port map(A => MX2_21_Y, B => AO1_17_Y, S => NOR2_8_Y, Y =>
2955 PP2_16_net);
2956 NOR2_16 : NOR2
2957 port map(A => XOR2_5_Y, B => XNOR2_19_Y, Y => NOR2_16_Y);
2958 XOR2_PP0_10_inst : XOR2
2959 port map(A => MX2_75_Y, B => BUFF_27_Y, Y => PP0_10_net);
2960 DFN1_18 : DFN1
2961 port map(D => PP0_6_net, CLK => Clock, Q => DFN1_18_Q);
2962 XOR3_71 : XOR3
2963 port map(A => MAJ3_96_Y, B => XOR3_3_Y, C => XOR3_84_Y,
2964 Y => XOR3_71_Y);
2965 XOR2_70 : XOR2
2966 port map(A => BUFF_47_Y, B => DataB(11), Y => XOR2_70_Y);
2967 DFN1_109 : DFN1
2968 port map(D => PP6_3_net, CLK => Clock, Q => DFN1_109_Q);
2969 XOR2_PP6_2_inst : XOR2
2970 port map(A => MX2_71_Y, B => BUFF_20_Y, Y => PP6_2_net);
2971 AO1_49 : AO1
2972 port map(A => XOR2_77_Y, B => AO1_64_Y, C => AND2_84_Y,
2973 Y => AO1_49_Y);
2974 AO1_16 : AO1
2975 port map(A => AND2_112_Y, B => AO1_44_Y, C => AO1_85_Y,
2976 Y => AO1_16_Y);
2977 AO1_73 : AO1
2978 port map(A => XOR2_47_Y, B => OR3_2_Y, C => AND3_6_Y, Y =>
2979 AO1_73_Y);
2980 MX2_72 : MX2
2981 port map(A => AND2_244_Y, B => BUFF_16_Y, S => NOR2_1_Y,
2982 Y => MX2_72_Y);
2983 AND2_5 : AND2
2984 port map(A => SumA_20_net, B => SumB_20_net, Y => AND2_5_Y);
2985 DFN1_90 : DFN1
2986 port map(D => PP0_9_net, CLK => Clock, Q => DFN1_90_Q);
2987 AND2_92 : AND2
2988 port map(A => AND2_168_Y, B => AND2_199_Y, Y => AND2_92_Y);
2989 XOR2_28 : XOR2
2990 port map(A => SumA_21_net, B => SumB_21_net, Y => XOR2_28_Y);
2991 AND2_208 : AND2
2992 port map(A => AND2_157_Y, B => AND2_44_Y, Y => AND2_208_Y);
2993 NOR2_6 : NOR2
2994 port map(A => XOR2_66_Y, B => XNOR2_5_Y, Y => NOR2_6_Y);
2995 XOR2_PP5_10_inst : XOR2
2996 port map(A => MX2_122_Y, B => BUFF_48_Y, Y => PP5_10_net);
2997 BUFF_32 : BUFF
2998 port map(A => DataA(3), Y => BUFF_32_Y);
2999 XOR2_38 : XOR2
3000 port map(A => BUFF_47_Y, B => DataB(15), Y => XOR2_38_Y);
3001 MX2_62 : MX2
3002 port map(A => AND2_202_Y, B => BUFF_53_Y, S => NOR2_10_Y,
3003 Y => MX2_62_Y);
3004 MAJ3_43 : MAJ3
3005 port map(A => XOR3_68_Y, B => MAJ3_45_Y, C => MAJ3_20_Y,
3006 Y => MAJ3_43_Y);
3007 AO1_65 : AO1
3008 port map(A => AND2_168_Y, B => AO1_15_Y, C => AO1_87_Y,
3009 Y => AO1_65_Y);
3010 XOR2_PP4_15_inst : XOR2
3011 port map(A => MX2_85_Y, B => BUFF_7_Y, Y => PP4_15_net);
3012 XOR2_PP1_11_inst : XOR2
3013 port map(A => MX2_60_Y, B => BUFF_14_Y, Y => PP1_11_net);
3014 AND2_148 : AND2
3015 port map(A => XOR2_109_Y, B => BUFF_17_Y, Y => AND2_148_Y);
3016 AO1_72 : AO1
3017 port map(A => XOR2_84_Y, B => AO1_88_Y, C => AND2_76_Y,
3018 Y => AO1_72_Y);
3019 AND2_152 : AND2
3020 port map(A => AND2_219_Y, B => AND2_97_Y, Y => AND2_152_Y);
3021 XOR2_1 : XOR2
3022 port map(A => DataB(7), B => DataB(8), Y => XOR2_1_Y);
3023 MX2_41 : MX2
3024 port map(A => AND2_136_Y, B => BUFF_36_Y, S => NOR2_17_Y,
3025 Y => MX2_41_Y);
3026 BUFF_47 : BUFF
3027 port map(A => DataA(15), Y => BUFF_47_Y);
3028 XOR2_PP7_12_inst : XOR2
3029 port map(A => MX2_5_Y, B => BUFF_51_Y, Y => PP7_12_net);
3030 DFN1_SumB_4_inst : DFN1
3031 port map(D => XOR3_42_Y, CLK => Clock, Q => SumB_4_net);
3032 XOR3_23 : XOR3
3033 port map(A => DFN1_144_Q, B => DFN1_20_Q, C => DFN1_41_Q,
3034 Y => XOR3_23_Y);
3035 DFN1_2 : DFN1
3036 port map(D => PP2_0_net, CLK => Clock, Q => DFN1_2_Q);
3037 MX2_118 : MX2
3038 port map(A => AND2_123_Y, B => BUFF_28_Y, S => NOR2_20_Y,
3039 Y => MX2_118_Y);
3040 XOR2_PP1_7_inst : XOR2
3041 port map(A => MX2_19_Y, B => BUFF_14_Y, Y => PP1_7_net);
3042 XOR2_8 : XOR2
3043 port map(A => SumA_18_net, B => SumB_18_net, Y => XOR2_8_Y);
3044 MAJ3_85 : MAJ3
3045 port map(A => DFN1_129_Q, B => DFN1_5_Q, C => VCC_1_net,
3046 Y => MAJ3_85_Y);
3047 DFN1_SumA_26_inst : DFN1
3048 port map(D => MAJ3_43_Y, CLK => Clock, Q => SumA_26_net);
3049 XOR2_105 : XOR2
3050 port map(A => DataB(3), B => DataB(4), Y => XOR2_105_Y);
3051 AND2_197 : AND2
3052 port map(A => DFN1_36_Q, B => DFN1_111_Q, Y => AND2_197_Y);
3053 MX2_26 : MX2
3054 port map(A => AND2_254_Y, B => BUFF_22_Y, S => NOR2_4_Y,
3055 Y => MX2_26_Y);
3056 DFN1_75 : DFN1
3057 port map(D => E_4_net, CLK => Clock, Q => DFN1_75_Q);
3058 XOR3_29 : XOR3
3059 port map(A => MAJ3_52_Y, B => MAJ3_3_Y, C => XOR3_35_Y,
3060 Y => XOR3_29_Y);
3061 MX2_48 : MX2
3062 port map(A => AND2_138_Y, B => BUFF_40_Y, S => NOR2_4_Y,
3063 Y => MX2_48_Y);
3064 MX2_55 : MX2
3065 port map(A => BUFF_0_Y, B => XOR2_92_Y, S => DataB(0), Y =>
3066 MX2_55_Y);
3067 XOR3_33 : XOR3
3068 port map(A => DFN1_66_Q, B => DFN1_15_Q, C => DFN1_121_Q,
3069 Y => XOR3_33_Y);
3070 XOR2_PP3_12_inst : XOR2
3071 port map(A => MX2_4_Y, B => BUFF_42_Y, Y => PP3_12_net);
3072 DFN1_13 : DFN1
3073 port map(D => PP3_11_net, CLK => Clock, Q => DFN1_13_Q);
3074 XOR2_Mult_11_inst : XOR2
3075 port map(A => XOR2_110_Y, B => AO1_65_Y, Y => Mult(11));
3076 DFN1_SumA_20_inst : DFN1
3077 port map(D => MAJ3_84_Y, CLK => Clock, Q => SumA_20_net);
3078 XOR2_60 : XOR2
3079 port map(A => SumA_25_net, B => SumB_25_net, Y => XOR2_60_Y);
3080 XOR2_110 : XOR2
3081 port map(A => SumA_10_net, B => SumB_10_net, Y =>
3082 XOR2_110_Y);
3083 MAJ3_40 : MAJ3
3084 port map(A => XOR3_50_Y, B => MAJ3_31_Y, C => MAJ3_48_Y,
3085 Y => MAJ3_40_Y);
3086 XOR3_39 : XOR3
3087 port map(A => DFN1_61_Q, B => DFN1_140_Q, C => DFN1_85_Q,
3088 Y => XOR3_39_Y);
3089 AND2_257 : AND2
3090 port map(A => XOR2_26_Y, B => BUFF_32_Y, Y => AND2_257_Y);
3091 AND2_106 : AND2
3092 port map(A => XOR2_63_Y, B => BUFF_40_Y, Y => AND2_106_Y);
3093 DFN1_125 : DFN1
3094 port map(D => PP2_2_net, CLK => Clock, Q => DFN1_125_Q);
3095 MX2_95 : MX2
3096 port map(A => AND2_85_Y, B => BUFF_50_Y, S => NOR2_10_Y,
3097 Y => MX2_95_Y);
3098 XOR2_PP5_5_inst : XOR2
3099 port map(A => MX2_113_Y, B => BUFF_55_Y, Y => PP5_5_net);
3100 AO1_50 : AO1
3101 port map(A => AND2_103_Y, B => AO1_18_Y, C => AO1_21_Y,
3102 Y => AO1_50_Y);
3103 XOR2_PP1_14_inst : XOR2
3104 port map(A => MX2_7_Y, B => BUFF_46_Y, Y => PP1_14_net);
3105 DFN1_102 : DFN1
3106 port map(D => PP0_10_net, CLK => Clock, Q => DFN1_102_Q);
3107 DFN1_9 : DFN1
3108 port map(D => PP7_8_net, CLK => Clock, Q => DFN1_9_Q);
3109 XOR2_Mult_9_inst : XOR2
3110 port map(A => XOR2_94_Y, B => AO1_15_Y, Y => Mult(9));
3111 AND2_47 : AND2
3112 port map(A => AND2_177_Y, B => AND2_237_Y, Y => AND2_47_Y);
3113 DFN1_62 : DFN1
3114 port map(D => PP5_6_net, CLK => Clock, Q => DFN1_62_Q);
3115 DFN1_100 : DFN1
3116 port map(D => PP4_14_net, CLK => Clock, Q => DFN1_100_Q);
3117 MX2_79 : MX2
3118 port map(A => BUFF_43_Y, B => XOR2_33_Y, S => XOR2_31_Y,
3119 Y => MX2_79_Y);
3120 DFN1_123 : DFN1
3121 port map(D => PP1_11_net, CLK => Clock, Q => DFN1_123_Q);
3122 AO1_80 : AO1
3123 port map(A => AND2_37_Y, B => AO1_75_Y, C => AO1_60_Y, Y =>
3124 AO1_80_Y);
3125 DFN1_141 : DFN1
3126 port map(D => PP4_4_net, CLK => Clock, Q => DFN1_141_Q);
3127 MX2_30 : MX2
3128 port map(A => BUFF_51_Y, B => XOR2_38_Y, S => XOR2_89_Y,
3129 Y => MX2_30_Y);
3130 XOR3_27 : XOR3
3131 port map(A => MAJ3_81_Y, B => MAJ3_6_Y, C => XOR3_1_Y, Y =>
3132 XOR3_27_Y);
3133 AND2_54 : AND2
3134 port map(A => XOR2_105_Y, B => BUFF_32_Y, Y => AND2_54_Y);
3135 XNOR2_10 : XNOR2
3136 port map(A => DataB(2), B => BUFF_46_Y, Y => XNOR2_10_Y);
3137 DFN1_52 : DFN1
3138 port map(D => PP7_2_net, CLK => Clock, Q => DFN1_52_Q);
3139 AO1_6 : AO1
3140 port map(A => XOR2_53_Y, B => AND2_51_Y, C => AND2_189_Y,
3141 Y => AO1_6_Y);
3142 BUFF_52 : BUFF
3143 port map(A => DataA(7), Y => BUFF_52_Y);
3144 AND2_256 : AND2
3145 port map(A => XOR2_56_Y, B => BUFF_47_Y, Y => AND2_256_Y);
3146 XOR2_PP4_5_inst : XOR2
3147 port map(A => MX2_59_Y, B => BUFF_41_Y, Y => PP4_5_net);
3148 MX2_69 : MX2
3149 port map(A => AND2_27_Y, B => BUFF_17_Y, S => NOR2_10_Y,
3150 Y => MX2_69_Y);
3151 XOR3_52 : XOR3
3152 port map(A => DFN1_133_Q, B => DFN1_15_Q, C => DFN1_37_Q,
3153 Y => XOR3_52_Y);
3154 AND2_S_5_inst : AND2
3155 port map(A => XOR2_86_Y, B => DataB(11), Y => S_5_net);
3156 XOR2_PP3_2_inst : XOR2
3157 port map(A => MX2_34_Y, B => BUFF_15_Y, Y => PP3_2_net);
3158 XOR3_37 : XOR3
3159 port map(A => DFN1_64_Q, B => DFN1_17_Q, C => DFN1_149_Q,
3160 Y => XOR3_37_Y);
3161 XOR2_108 : XOR2
3162 port map(A => SumA_6_net, B => SumB_6_net, Y => XOR2_108_Y);
3163 AND2_67 : AND2
3164 port map(A => XOR2_1_Y, B => BUFF_47_Y, Y => AND2_67_Y);
3165 MAJ3_32 : MAJ3
3166 port map(A => DFN1_88_Q, B => DFN1_135_Q, C => DFN1_90_Q,
3167 Y => MAJ3_32_Y);
3168 XOR2_Mult_14_inst : XOR2
3169 port map(A => XOR2_27_Y, B => AO1_46_Y, Y => Mult(14));
3170 XOR2_PP5_7_inst : XOR2
3171 port map(A => MX2_72_Y, B => BUFF_48_Y, Y => PP5_7_net);
3172 AND3_5 : AND3
3173 port map(A => DataB(9), B => DataB(10), C => DataB(11),
3174 Y => AND3_5_Y);
3175 AND2_8 : AND2
3176 port map(A => SumA_1_net, B => SumB_1_net, Y => AND2_8_Y);
3177 MAJ3_83 : MAJ3
3178 port map(A => XOR3_9_Y, B => MAJ3_93_Y, C => XOR3_36_Y,
3179 Y => MAJ3_83_Y);
3180 MAJ3_0 : MAJ3
3181 port map(A => XOR3_54_Y, B => MAJ3_10_Y, C => MAJ3_47_Y,
3182 Y => MAJ3_0_Y);
3183 XNOR2_11 : XNOR2
3184 port map(A => DataB(4), B => BUFF_34_Y, Y => XNOR2_11_Y);
3185 AND2_98 : AND2
3186 port map(A => DataB(0), B => BUFF_17_Y, Y => AND2_98_Y);
3187 NOR2_0 : NOR2
3188 port map(A => XOR2_31_Y, B => XNOR2_7_Y, Y => NOR2_0_Y);
3189 MAJ3_11 : MAJ3
3190 port map(A => DFN1_145_Q, B => DFN1_78_Q, C => DFN1_97_Q,
3191 Y => MAJ3_11_Y);
3192 AND2_243 : AND2
3193 port map(A => AND2_219_Y, B => AND2_190_Y, Y => AND2_243_Y);
3194 XOR2_73 : XOR2
3195 port map(A => SumA_7_net, B => SumB_7_net, Y => XOR2_73_Y);
3196 XOR2_PP7_2_inst : XOR2
3197 port map(A => MX2_73_Y, B => BUFF_26_Y, Y => PP7_2_net);
3198 AND2_41 : AND2
3199 port map(A => AND2_231_Y, B => AND2_37_Y, Y => AND2_41_Y);
3200 XOR2_79 : XOR2
3201 port map(A => DFN1_36_Q, B => DFN1_111_Q, Y => XOR2_79_Y);
3202 XOR2_44 : XOR2
3203 port map(A => DFN1_118_Q, B => VCC_1_net, Y => XOR2_44_Y);
3204 DFN1_31 : DFN1
3205 port map(D => PP4_13_net, CLK => Clock, Q => DFN1_31_Q);
3206 OR3_5 : OR3
3207 port map(A => DataB(5), B => DataB(6), C => DataB(7), Y =>
3208 OR3_5_Y);
3209 MX2_106 : MX2
3210 port map(A => AND2_13_Y, B => BUFF_52_Y, S => NOR2_13_Y,
3211 Y => MX2_106_Y);
3212 AND2_S_1_inst : AND2
3213 port map(A => XOR2_99_Y, B => DataB(3), Y => S_1_net);
3214 AO1_55 : AO1
3215 port map(A => XOR2_8_Y, B => AO1_84_Y, C => AND2_51_Y, Y =>
3216 AO1_55_Y);
3217 AND2_132 : AND2
3218 port map(A => DFN1_118_Q, B => VCC_1_net, Y => AND2_132_Y);
3219 XOR3_56 : XOR3
3220 port map(A => MAJ3_60_Y, B => MAJ3_69_Y, C => XOR3_6_Y,
3221 Y => XOR3_56_Y);
3222 AND2_107 : AND2
3223 port map(A => XOR2_11_Y, B => BUFF_49_Y, Y => AND2_107_Y);
3224 XOR2_PP1_4_inst : XOR2
3225 port map(A => MX2_65_Y, B => BUFF_21_Y, Y => PP1_4_net);
3226 XOR3_72 : XOR3
3227 port map(A => DFN1_68_Q, B => DFN1_75_Q, C => DFN1_56_Q,
3228 Y => XOR3_72_Y);
3229 AND2_S_7_inst : AND2
3230 port map(A => XOR2_45_Y, B => DataB(15), Y => S_7_net);
3231 NOR2_19 : NOR2
3232 port map(A => XOR2_105_Y, B => XNOR2_12_Y, Y => NOR2_19_Y);
3233 MX2_105 : MX2
3234 port map(A => AND2_185_Y, B => BUFF_52_Y, S => NOR2_12_Y,
3235 Y => MX2_105_Y);
3236 DFN1_27 : DFN1
3237 port map(D => PP2_11_net, CLK => Clock, Q => DFN1_27_Q);
3238 XOR3_48 : XOR3
3239 port map(A => DFN1_122_Q, B => DFN1_55_Q, C => DFN1_101_Q,
3240 Y => XOR3_48_Y);
3241 XOR3_81 : XOR3
3242 port map(A => DFN1_48_Q, B => DFN1_87_Q, C => DFN1_31_Q,
3243 Y => XOR3_81_Y);
3244 XOR3_68 : XOR3
3245 port map(A => DFN1_57_Q, B => DFN1_12_Q, C => XOR2_44_Y,
3246 Y => XOR3_68_Y);
3247 DFN1_68 : DFN1
3248 port map(D => PP5_15_net, CLK => Clock, Q => DFN1_68_Q);
3249 BUFF_36 : BUFF
3250 port map(A => DataA(13), Y => BUFF_36_Y);
3251 DFN1_26 : DFN1
3252 port map(D => PP7_15_net, CLK => Clock, Q => DFN1_26_Q);
3253 AO1_85 : AO1
3254 port map(A => XOR2_37_Y, B => AO1_89_Y, C => AND2_70_Y,
3255 Y => AO1_85_Y);
3256 AND2_211 : AND2
3257 port map(A => XOR2_14_Y, B => BUFF_13_Y, Y => AND2_211_Y);
3258 AND2_61 : AND2
3259 port map(A => AND2_157_Y, B => XOR2_103_Y, Y => AND2_61_Y);
3260 MAJ3_80 : MAJ3
3261 port map(A => DFN1_62_Q, B => DFN1_96_Q, C => DFN1_28_Q,
3262 Y => MAJ3_80_Y);
3263 AND2_143 : AND2
3264 port map(A => XOR2_14_Y, B => BUFF_50_Y, Y => AND2_143_Y);
3265 DFN1_81 : DFN1
3266 port map(D => PP3_5_net, CLK => Clock, Q => DFN1_81_Q);
3267 AND3_3 : AND3
3268 port map(A => DataB(11), B => DataB(12), C => DataB(13),
3269 Y => AND3_3_Y);
3270 XOR2_77 : XOR2
3271 port map(A => SumA_30_net, B => SumB_30_net, Y => XOR2_77_Y);
3272 DFN1_58 : DFN1
3273 port map(D => PP4_0_net, CLK => Clock, Q => DFN1_58_Q);
3274 AO1_46 : AO1
3275 port map(A => AND2_80_Y, B => AO1_40_Y, C => AO1_70_Y, Y =>
3276 AO1_46_Y);
3277 XOR2_91 : XOR2
3278 port map(A => DFN1_42_Q, B => DFN1_124_Q, Y => XOR2_91_Y);
3279 MAJ3_22 : MAJ3
3280 port map(A => MAJ3_29_Y, B => DFN1_40_Q, C => DFN1_150_Q,
3281 Y => MAJ3_22_Y);
3282 MX2_36 : MX2
3283 port map(A => AND2_45_Y, B => BUFF_24_Y, S => NOR2_18_Y,
3284 Y => MX2_36_Y);
3285 AO1_77 : AO1
3286 port map(A => XOR2_33_Y, B => OR3_0_Y, C => AND3_3_Y, Y =>
3287 AO1_77_Y);
3288 AND2_252 : AND2
3289 port map(A => XOR2_63_Y, B => BUFF_6_Y, Y => AND2_252_Y);
3290 DFN1_97 : DFN1
3291 port map(D => PP0_8_net, CLK => Clock, Q => DFN1_97_Q);
3292 MX2_15 : MX2
3293 port map(A => AND2_256_Y, B => BUFF_35_Y, S => NOR2_17_Y,
3294 Y => MX2_15_Y);
3295 DFN1_29 : DFN1
3296 port map(D => S_7_net, CLK => Clock, Q => DFN1_29_Q);
3297 AND2_237 : AND2
3298 port map(A => XOR2_67_Y, B => XOR2_24_Y, Y => AND2_237_Y);
3299 DFN1_96 : DFN1
3300 port map(D => PP3_10_net, CLK => Clock, Q => DFN1_96_Q);
3301 BUFF_49 : BUFF
3302 port map(A => DataA(11), Y => BUFF_49_Y);
3303 AND2_219 : AND2
3304 port map(A => AND2_104_Y, B => AND2_198_Y, Y => AND2_219_Y);
3305 AND2_25 : AND2
3306 port map(A => AND2_182_Y, B => XOR2_13_Y, Y => AND2_25_Y);
3307 AOI1_E_3_inst : AOI1
3308 port map(A => XOR2_61_Y, B => OR3_5_Y, C => AND3_4_Y, Y =>
3309 E_3_net);
3310 AO1_64 : AO1
3311 port map(A => XOR2_96_Y, B => AND2_70_Y, C => AND2_214_Y,
3312 Y => AO1_64_Y);
3313 AND2_S_2_inst : AND2
3314 port map(A => XOR2_34_Y, B => DataB(5), Y => S_2_net);
3315 XOR2_63 : XOR2
3316 port map(A => DataB(7), B => DataB(8), Y => XOR2_63_Y);
3317 AND2_46 : AND2
3318 port map(A => XOR2_35_Y, B => BUFF_12_Y, Y => AND2_46_Y);
3319 XOR3_76 : XOR3
3320 port map(A => DFN1_11_Q, B => DFN1_94_Q, C => DFN1_136_Q,
3321 Y => XOR3_76_Y);
3322 AND2_84 : AND2
3323 port map(A => SumA_30_net, B => SumB_30_net, Y => AND2_84_Y);
3324 NOR2_14 : NOR2
3325 port map(A => XOR2_1_Y, B => XNOR2_6_Y, Y => NOR2_14_Y);
3326 MX2_PP4_16_inst : MX2
3327 port map(A => MX2_44_Y, B => AO1_4_Y, S => NOR2_14_Y, Y =>
3328 PP4_16_net);
3329 XOR2_69 : XOR2
3330 port map(A => SumA_20_net, B => SumB_20_net, Y => XOR2_69_Y);
3331 MX2_27 : MX2
3332 port map(A => AND2_227_Y, B => BUFF_29_Y, S => NOR2_9_Y,
3333 Y => MX2_27_Y);
3334 MAJ3_72 : MAJ3
3335 port map(A => DFN1_121_Q, B => DFN1_66_Q, C => DFN1_15_Q,
3336 Y => MAJ3_72_Y);
3337 AND2_236 : AND2
3338 port map(A => XOR2_58_Y, B => BUFF_24_Y, Y => AND2_236_Y);
3339 AO1_78 : AO1
3340 port map(A => AND2_243_Y, B => AO1_1_Y, C => AO1_42_Y, Y =>
3341 AO1_78_Y);
3342 AO1_5 : AO1
3343 port map(A => AND2_31_Y, B => AO1_68_Y, C => AO1_41_Y, Y =>
3344 AO1_5_Y);
3345 DFN1_99 : DFN1
3346 port map(D => PP4_15_net, CLK => Clock, Q => DFN1_99_Q);
3347 AND2_124 : AND2
3348 port map(A => DFN1_152_Q, B => DFN1_109_Q, Y => AND2_124_Y);
3349 DFN1_72 : DFN1
3350 port map(D => PP5_10_net, CLK => Clock, Q => DFN1_72_Q);
3351 XOR2_45 : XOR2
3352 port map(A => AND2_245_Y, B => BUFF_26_Y, Y => XOR2_45_Y);
3353 DFN1_114 : DFN1
3354 port map(D => PP0_1_net, CLK => Clock, Q => DFN1_114_Q);
3355 DFN1_135 : DFN1
3356 port map(D => PP1_7_net, CLK => Clock, Q => DFN1_135_Q);
3357 AND2_66 : AND2
3358 port map(A => AND2_131_Y, B => XOR2_8_Y, Y => AND2_66_Y);
3359 DFN1_SumB_28_inst : DFN1
3360 port map(D => XOR3_94_Y, CLK => Clock, Q => SumB_28_net);
3361 AO1_8 : AO1
3362 port map(A => XOR2_30_Y, B => AO1_15_Y, C => AND2_184_Y,
3363 Y => AO1_8_Y);
3364 DFN1_128 : DFN1
3365 port map(D => E_1_net, CLK => Clock, Q => DFN1_128_Q);
3366 DFN1_63 : DFN1
3367 port map(D => PP0_11_net, CLK => Clock, Q => DFN1_63_Q);
3368 XOR2_PP2_3_inst : XOR2
3369 port map(A => MX2_76_Y, B => BUFF_38_Y, Y => PP2_3_net);
3370 AOI1_E_5_inst : AOI1
3371 port map(A => XOR2_70_Y, B => OR3_3_Y, C => AND3_5_Y, Y =>
3372 E_5_net);
3373 AND3_6 : AND3
3374 port map(A => DataB(1), B => DataB(2), C => DataB(3), Y =>
3375 AND3_6_Y);
3376 DFN1_SumA_3_inst : DFN1
3377 port map(D => AND2_197_Y, CLK => Clock, Q => SumA_3_net);
3378 MX2_5 : MX2
3379 port map(A => AND2_246_Y, B => BUFF_18_Y, S => NOR2_7_Y,
3380 Y => MX2_5_Y);
3381 DFN1_133 : DFN1
3382 port map(D => PP2_14_net, CLK => Clock, Q => DFN1_133_Q);
3383 XOR2_67 : XOR2
3384 port map(A => SumA_14_net, B => SumB_14_net, Y => XOR2_67_Y);
3385 DFN1_53 : DFN1
3386 port map(D => PP6_7_net, CLK => Clock, Q => DFN1_53_Q);
3387 XOR3_0 : XOR3
3388 port map(A => DFN1_82_Q, B => DFN1_33_Q, C => AND2_229_Y,
3389 Y => XOR3_0_Y);
3390 AND2_121 : AND2
3391 port map(A => DFN1_79_Q, B => DFN1_30_Q, Y => AND2_121_Y);
3392 MX2_9 : MX2
3393 port map(A => AND2_180_Y, B => BUFF_10_Y, S => AND2A_2_Y,
3394 Y => MX2_9_Y);
3395 XOR2_Mult_4_inst : XOR2
3396 port map(A => XOR2_112_Y, B => AO1_48_Y, Y => Mult(4));
3397 MX2_82 : MX2
3398 port map(A => AND2_142_Y, B => BUFF_19_Y, S => NOR2_20_Y,
3399 Y => MX2_82_Y);
3400 AO1_69 : AO1
3401 port map(A => XOR2_98_Y, B => AND2_16_Y, C => AND2_11_Y,
3402 Y => AO1_69_Y);
3403 NOR2_4 : NOR2
3404 port map(A => XOR2_81_Y, B => XNOR2_1_Y, Y => NOR2_4_Y);
3405 AND2_97 : AND2
3406 port map(A => AND2_44_Y, B => AND2_125_Y, Y => AND2_97_Y);
3407 XOR3_5 : XOR3
3408 port map(A => MAJ3_17_Y, B => AND2_48_Y, C => XOR3_76_Y,
3409 Y => XOR3_5_Y);
3410 AND2_240 : AND2
3411 port map(A => XOR2_35_Y, B => BUFF_52_Y, Y => AND2_240_Y);
3412 end DEF_ARCH;
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1 -- Version: 9.0 9.0.0.15
2
3 library ieee;
4 use ieee.std_logic_1164.all;
5 library proasic3;
6 use proasic3.all;
7
8 entity actram is
9 port( DI : in std_logic_vector(31 downto 0); DO : out
10 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
11 WADDR : in std_logic_vector(6 downto 0); RADDR : in
12 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
13 std_logic) ;
14 end actram;
15
16
17 architecture DEF_ARCH of actram is
18
19 component RAM512X18
20 generic (MEMORYFILE:string := "");
21
22 port(RADDR8, RADDR7, RADDR6, RADDR5, RADDR4, RADDR3,
23 RADDR2, RADDR1, RADDR0, WADDR8, WADDR7, WADDR6, WADDR5,
24 WADDR4, WADDR3, WADDR2, WADDR1, WADDR0, WD17, WD16, WD15,
25 WD14, WD13, WD12, WD11, WD10, WD9, WD8, WD7, WD6, WD5,
26 WD4, WD3, WD2, WD1, WD0, RW0, RW1, WW0, WW1, PIPE, REN,
27 WEN, RCLK, WCLK, RESET : in std_logic := 'U'; RD17, RD16,
28 RD15, RD14, RD13, RD12, RD11, RD10, RD9, RD8, RD7, RD6,
29 RD5, RD4, RD3, RD2, RD1, RD0 : out std_logic) ;
30 end component;
31
32 component VCC
33 port( Y : out std_logic);
34 end component;
35
36 component GND
37 port( Y : out std_logic);
38 end component;
39
40 signal VCC_1_net, GND_1_net : std_logic ;
41 begin
42
43 VCC_2_net : VCC port map(Y => VCC_1_net);
44 GND_2_net : GND port map(Y => GND_1_net);
45 actram_R0C1 : RAM512X18
46 port map(RADDR8 => GND_1_net, RADDR7 => GND_1_net,
47 RADDR6 => RADDR(6), RADDR5 => RADDR(5), RADDR4 =>
48 RADDR(4), RADDR3 => RADDR(3), RADDR2 => RADDR(2),
49 RADDR1 => RADDR(1), RADDR0 => RADDR(0), WADDR8 =>
50 GND_1_net, WADDR7 => GND_1_net, WADDR6 => WADDR(6),
51 WADDR5 => WADDR(5), WADDR4 => WADDR(4), WADDR3 =>
52 WADDR(3), WADDR2 => WADDR(2), WADDR1 => WADDR(1),
53 WADDR0 => WADDR(0), WD17 => GND_1_net, WD16 => GND_1_net,
54 WD15 => DI(31), WD14 => DI(30), WD13 => DI(29), WD12 =>
55 DI(28), WD11 => DI(27), WD10 => DI(26), WD9 => DI(25),
56 WD8 => DI(24), WD7 => DI(23), WD6 => DI(22), WD5 =>
57 DI(21), WD4 => DI(20), WD3 => DI(19), WD2 => DI(18),
58 WD1 => DI(17), WD0 => DI(16), RW0 => GND_1_net, RW1 =>
59 VCC_1_net, WW0 => GND_1_net, WW1 => VCC_1_net, PIPE =>
60 VCC_1_net, REN => RDB, WEN => WRB, RCLK => RCLOCK,
61 WCLK => WCLOCK, RESET => VCC_1_net, RD17 => OPEN ,
62 RD16 => OPEN , RD15 => DO(31), RD14 => DO(30), RD13 =>
63 DO(29), RD12 => DO(28), RD11 => DO(27), RD10 => DO(26),
64 RD9 => DO(25), RD8 => DO(24), RD7 => DO(23), RD6 =>
65 DO(22), RD5 => DO(21), RD4 => DO(20), RD3 => DO(19),
66 RD2 => DO(18), RD1 => DO(17), RD0 => DO(16));
67 actram_R0C0 : RAM512X18
68 port map(RADDR8 => GND_1_net, RADDR7 => GND_1_net,
69 RADDR6 => RADDR(6), RADDR5 => RADDR(5), RADDR4 =>
70 RADDR(4), RADDR3 => RADDR(3), RADDR2 => RADDR(2),
71 RADDR1 => RADDR(1), RADDR0 => RADDR(0), WADDR8 =>
72 GND_1_net, WADDR7 => GND_1_net, WADDR6 => WADDR(6),
73 WADDR5 => WADDR(5), WADDR4 => WADDR(4), WADDR3 =>
74 WADDR(3), WADDR2 => WADDR(2), WADDR1 => WADDR(1),
75 WADDR0 => WADDR(0), WD17 => GND_1_net, WD16 => GND_1_net,
76 WD15 => DI(15), WD14 => DI(14), WD13 => DI(13), WD12 =>
77 DI(12), WD11 => DI(11), WD10 => DI(10), WD9 => DI(9),
78 WD8 => DI(8), WD7 => DI(7), WD6 => DI(6), WD5 => DI(5),
79 WD4 => DI(4), WD3 => DI(3), WD2 => DI(2), WD1 => DI(1),
80 WD0 => DI(0), RW0 => GND_1_net, RW1 => VCC_1_net, WW0 =>
81 GND_1_net, WW1 => VCC_1_net, PIPE => VCC_1_net, REN =>
82 RDB, WEN => WRB, RCLK => RCLOCK, WCLK => WCLOCK, RESET =>
83 VCC_1_net, RD17 => OPEN , RD16 => OPEN , RD15 => DO(15),
84 RD14 => DO(14), RD13 => DO(13), RD12 => DO(12), RD11 =>
85 DO(11), RD10 => DO(10), RD9 => DO(9), RD8 => DO(8),
86 RD7 => DO(7), RD6 => DO(6), RD5 => DO(5), RD4 => DO(4),
87 RD3 => DO(3), RD2 => DO(2), RD1 => DO(1), RD0 => DO(0));
88 end DEF_ARCH;
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: fftDp.vhd
10 -- Description: CoreFFT
11 -- FFT dapa path module
12 -- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production
13 --
14 --
15 --------------------------------------------------------------------------------
16 -------------------------------- SWITCH -------------------------------
17 -- if (sel) straight, else cross
18 LIBRARY IEEE;
19 USE IEEE.std_logic_1164.all;
20
21 ENTITY switch IS
22 GENERIC ( DWIDTH : integer := 32 );
23 PORT (
24 clk, sel, validIn : IN std_logic;
25 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
26 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
27 validOut : OUT std_logic);
28 END ENTITY switch;
29
30 ARCHITECTURE translated OF switch IS
31 CONSTANT tscale : time := 1 ns;
32
33 SIGNAL leftQ_r, rightP_r : std_logic_vector(DWIDTH-1 DOWNTO 0);
34 SIGNAL pipe1 : std_logic;
35 SIGNAL muxP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
36 SIGNAL muxQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
37 SIGNAL temp_xhdl4 : std_logic_vector(DWIDTH-1 DOWNTO 0);
38 SIGNAL temp_xhdl5 : std_logic_vector(DWIDTH-1 DOWNTO 0);
39 SIGNAL outP_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0);
40 SIGNAL outQ_xhdl2 : std_logic_vector(DWIDTH-1 DOWNTO 0);
41 SIGNAL validOut_xhdl3 : std_logic;
42
43 BEGIN
44 outP <= outP_xhdl1;
45 outQ <= outQ_xhdl2;
46 validOut <= validOut_xhdl3;
47 temp_xhdl4 <= leftQ_r WHEN sel = '1' ELSE inP;
48 muxP_w <= temp_xhdl4 ;
49 temp_xhdl5 <= leftQ_r WHEN NOT sel = '1' ELSE inP;
50 muxQ_w <= temp_xhdl5 ;
51
52 PROCESS (clk)
53 BEGIN
54 IF (clk'EVENT AND clk = '1') THEN
55 outP_xhdl1 <= rightP_r AFTER tscale;
56 outQ_xhdl2 <= muxQ_w AFTER tscale;
57 leftQ_r <= inQ AFTER tscale;
58 rightP_r <= muxP_w AFTER tscale;
59 validOut_xhdl3 <= pipe1 AFTER tscale;
60 pipe1 <= validIn AFTER tscale;
61 END IF;
62 END PROCESS;
63 END ARCHITECTURE translated;
64
65 ---------------------------- B U T T E R F L Y --------------------------------
66 ------------------------- Simple Round Up: 1-clk delay ----------------------V
67 ---------- Use it when it is known INBITWIDTH > OUTBITWIDTH --------------------
68 LIBRARY IEEE;
69 USE IEEE.std_logic_1164.all;
70 USE IEEE.numeric_std.all;
71
72 ENTITY kitRndUp IS
73 GENERIC (OUTBITWIDTH : integer := 12;
74 RND_MODE : integer := 0 );
75 PORT (nGrst, rst, clk, clkEn : IN std_logic;
76 inp : IN std_logic_vector(OUTBITWIDTH DOWNTO 0);
77 valInp : IN std_logic;
78 outp : OUT std_logic_vector(OUTBITWIDTH-1 DOWNTO 0);
79 valOutp : OUT std_logic);
80 END ENTITY kitRndUp;
81
82 ARCHITECTURE rtl OF kitRndUp IS
83 CONSTANT tscale : time := 1 ns;
84
85 SIGNAL int_outp : signed(OUTBITWIDTH DOWNTO 0);
86 SIGNAL int_valOutp : std_logic;
87
88 BEGIN
89 outp <= std_logic_vector(int_outp(OUTBITWIDTH DOWNTO 1));
90 valOutp <= int_valOutp;
91
92 PROCESS (clk, nGrst)
93 BEGIN
94 IF (NOT nGrst = '1') THEN
95 int_outp <= to_signed(0, OUTBITWIDTH+1);
96 int_valOutp <= '0';
97 ELSIF (clk'EVENT AND clk = '1') THEN
98 IF (rst = '1') THEN
99 int_outp <= to_signed(0, OUTBITWIDTH+1) AFTER tscale;
100 int_valOutp <= '0' AFTER 1 ns;
101 ELSIF (clkEn = '1') THEN
102 IF (valInp = '1') THEN
103 IF(RND_MODE = 1) THEN
104 int_outp <= signed(inp) + to_signed(1, OUTBITWIDTH+1) AFTER tscale;
105 ELSE int_outp <= signed(inp);
106 END IF;
107 END IF;
108 int_valOutp <= valInp AFTER tscale;
109 END IF; --rst and no rst
110 END IF; --nGrst and no nGrst
111 END PROCESS;
112 END ARCHITECTURE rtl;
113
114 -------------------------------- MULT -----------------------------V
115 library IEEE;
116 use IEEE.STD_LOGIC_1164.all;
117
118 ENTITY agen IS
119 GENERIC ( RND_MODE : integer := 0;
120 WSIZE : integer := 16;
121 DWIDTH : integer := 16;
122 TWIDTH : integer := 16 );
123 PORT ( -- synthesis syn_preserve=1
124 clk : IN std_logic;
125 a : IN std_logic_vector(WSIZE-1 DOWNTO 0);
126 t : IN std_logic_vector(TWIDTH-1 DOWNTO 0);
127 arout : OUT std_logic_vector(WSIZE-1 DOWNTO 0));
128 END ENTITY agen;
129
130 ARCHITECTURE rtl OF agen IS
131 CONSTANT tscale : time := 1 ns;
132 COMPONENT actar
133 PORT (DataA : IN std_logic_vector(WSIZE-1 DOWNTO 0);
134 DataB : IN std_logic_vector(TWIDTH-1 DOWNTO 0);
135 Mult : OUT std_logic_vector(WSIZE+TWIDTH-1 DOWNTO 0);
136 Clock : IN std_logic );
137 END COMPONENT;
138
139 COMPONENT kitRndUp
140 GENERIC (
141 OUTBITWIDTH : integer := 12;
142 RND_MODE : integer := 0 );
143 PORT (nGrst, rst, clk, clkEn : IN std_logic;
144 inp : IN std_logic_vector(OUTBITWIDTH DOWNTO 0);
145 valInp : IN std_logic;
146 outp : OUT std_logic_vector(OUTBITWIDTH-1 DOWNTO 0);
147 valOutp : OUT std_logic);
148 END COMPONENT;
149
150 SIGNAL a_r : std_logic_vector(WSIZE-1 DOWNTO 0);
151 SIGNAL t_r : std_logic_vector(TWIDTH-1 DOWNTO 0);
152 SIGNAL out1 : std_logic_vector(WSIZE DOWNTO 0);
153 SIGNAL out_w : std_logic_vector(WSIZE+TWIDTH-1 DOWNTO 0);
154 SIGNAL out_VHDL : std_logic_vector(WSIZE-1 DOWNTO 0);
155
156 BEGIN
157 arout <= out_VHDL;
158 actar_0 : actar
159 PORT MAP (DataA => a_r, DataB => t_r, Mult => out_w, Clock => clk);
160
161 kitRndUp_0: kitRndUp
162 GENERIC MAP ( OUTBITWIDTH => WSIZE, RND_MODE => RND_MODE )
163 PORT MAP (nGrst => '1', rst => '0', clk => clk, clkEn => '1',
164 inp => out1, valInp => '1', outp => out_VHDL, valOutp => open);
165
166 PROCESS (clk)
167 BEGIN
168 IF (clk'EVENT AND clk = '1') THEN
169 a_r <= a AFTER tscale;
170 t_r <= t AFTER tscale;
171
172 out1 <= out_w(DWIDTH-1 DOWNTO WSIZE-1) AFTER tscale;
173 END IF;
174 END PROCESS;
175 END ARCHITECTURE rtl;
176 -------------------------------------------------------------------------------
177
178 library IEEE;
179 use IEEE.STD_LOGIC_1164.all;
180 use IEEE.STD_LOGIC_UNSIGNED.all;
181 use IEEE.STD_LOGIC_ARITH.all;
182
183 ENTITY bfly2 IS
184 GENERIC ( RND_MODE : integer := 0;
185 WSIZE : integer := 16;
186 DWIDTH : integer := 32;
187 TWIDTH : integer := 16;
188 TDWIDTH : integer := 32 );
189 PORT (clk, validIn : IN std_logic;
190 swCrossIn : IN std_logic;
191 upScale : IN std_logic; --don't do downscaling if upScale==1
192 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
193 T : IN std_logic_vector(TDWIDTH-1 DOWNTO 0);
194 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
195 --Signals need to be delayed by the bfly latency. That's why they are here
196 validOut, swCrossOut : OUT std_logic);
197 END ENTITY bfly2;
198
199 ARCHITECTURE translated OF bfly2 IS
200 CONSTANT tscale : time := 1 ns;
201
202 COMPONENT agen
203 GENERIC ( RND_MODE : integer := 0;
204 WSIZE : integer := 16;
205 DWIDTH : integer := 16;
206 TWIDTH : integer := 16 );
207 PORT (clk : IN std_logic;
208 a : IN std_logic_vector(WSIZE-1 DOWNTO 0);
209 t : IN std_logic_vector(TWIDTH-1 DOWNTO 0);
210 arout : OUT std_logic_vector(WSIZE-1 DOWNTO 0));
211 END COMPONENT;
212
213 -- CONVENTION: real - LSBs[15:0], imag - MSBs[31:16]
214 SIGNAL inPr_w, inPi_w, inQr_w, inQi_w : std_logic_vector(WSIZE-1 DOWNTO 0);
215 SIGNAL Tr_w, Ti_w : std_logic_vector(TWIDTH-1 DOWNTO 0);
216 SIGNAL Hr_w, Hi_w, Hr, Hi : std_logic_vector(WSIZE-1 DOWNTO 0);
217 SIGNAL PrT1_r, PrT2_r, PrT3_r, PrT4_r : std_logic_vector(WSIZE-1 DOWNTO 0);
218 SIGNAL PrT5_r, PrT6_r, PiT1_r, PiT2_r : std_logic_vector(WSIZE-1 DOWNTO 0);
219 SIGNAL PiT3_r, PiT4_r, PiT5_r, PiT6_r : std_logic_vector(WSIZE-1 DOWNTO 0);
220 SIGNAL QrTr_w, QiTi_w, QiTr_w, QrTi_w : std_logic_vector(WSIZE-1 DOWNTO 0);
221 SIGNAL pipe1,pipe2,pipe3,pipe4,pipe5 : std_logic_vector(1 DOWNTO 0);
222 SIGNAL pipe6 : std_logic_vector(1 DOWNTO 0);
223 -- select either 16-bit value or sign-extended 15-bit value (downscaled one)
224 SIGNAL temp_xhdl5 : std_logic_vector(WSIZE-1 DOWNTO 0);
225 SIGNAL temp_xhdl6 : std_logic_vector(DWIDTH-1 DOWNTO WSIZE);
226 -- select either 16-bit value or left-shifted value (upscaled one)
227 SIGNAL temp_xhdl7 : std_logic_vector(WSIZE-1 DOWNTO 0);
228 SIGNAL temp_xhdl8 : std_logic_vector(WSIZE-1 DOWNTO 0);
229 SIGNAL outP_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0);
230 SIGNAL outQ_xhdl2 : std_logic_vector(DWIDTH-1 DOWNTO 0);
231 SIGNAL validOut_xhdl3 : std_logic;
232 SIGNAL swCrossOut_xhdl4 : std_logic;
233
234 BEGIN
235 outP <= outP_xhdl1;
236 outQ <= outQ_xhdl2;
237 validOut <= validOut_xhdl3;
238 swCrossOut <= swCrossOut_xhdl4;
239 Tr_w <= T(TWIDTH-1 DOWNTO 0) ;
240 Ti_w <= T(TDWIDTH-1 DOWNTO TWIDTH) ;
241 temp_xhdl5 <= inP(WSIZE-1 DOWNTO 0) WHEN upScale = '1' ELSE inP(WSIZE-1) &
242 inP(WSIZE-1 DOWNTO 1);
243 inPr_w <= temp_xhdl5 AFTER tscale;
244 temp_xhdl6 <= inP(DWIDTH-1 DOWNTO WSIZE) WHEN upScale = '1' ELSE inP(DWIDTH-1)
245 & inP(DWIDTH-1 DOWNTO WSIZE+1);
246 inPi_w <= temp_xhdl6 AFTER tscale;
247 temp_xhdl7 <= inQ(WSIZE-2 DOWNTO 0) & '0' WHEN upScale = '1' ELSE inQ(WSIZE-1
248 DOWNTO 0);
249 inQr_w <= temp_xhdl7 AFTER tscale;
250 temp_xhdl8 <= inQ(DWIDTH-2 DOWNTO WSIZE) & '0' WHEN upScale = '1' ELSE
251 inQ(DWIDTH-1 DOWNTO WSIZE);
252 inQi_w <= temp_xhdl8 AFTER tscale;
253
254 am3QrTr : agen
255 GENERIC MAP ( RND_MODE => RND_MODE, WSIZE => WSIZE,
256 DWIDTH => DWIDTH, TWIDTH => TWIDTH)
257 PORT MAP (clk => clk, a => inQr_w, t => Tr_w, arout => QrTr_w);
258 am3QiTi : agen
259 GENERIC MAP ( RND_MODE => RND_MODE, WSIZE => WSIZE,
260 DWIDTH => DWIDTH, TWIDTH => TWIDTH)
261 PORT MAP (clk => clk, a => inQi_w, t => Ti_w, arout => QiTi_w);
262 am3QiTr : agen
263 GENERIC MAP ( RND_MODE => RND_MODE, WSIZE => WSIZE,
264 DWIDTH => DWIDTH, TWIDTH => TWIDTH)
265 PORT MAP (clk => clk, a => inQi_w, t => Tr_w, arout => QiTr_w);
266 am3QrTi : agen
267 GENERIC MAP ( RND_MODE => RND_MODE, WSIZE => WSIZE,
268 DWIDTH => DWIDTH, TWIDTH => TWIDTH)
269 PORT MAP (clk => clk, a => inQr_w, t => Ti_w, arout => QrTi_w);
270
271 Hr_w <= QrTr_w + QiTi_w AFTER tscale;
272 Hi_w <= QiTr_w - QrTi_w AFTER tscale;
273
274 PROCESS (clk)
275 BEGIN
276 IF (clk'EVENT AND clk = '1') THEN
277 outQ_xhdl2(DWIDTH-1 DOWNTO WSIZE) <= PiT6_r - Hi AFTER tscale;
278 outQ_xhdl2(WSIZE-1 DOWNTO 0) <= PrT6_r - Hr AFTER tscale;
279 outP_xhdl1(DWIDTH-1 DOWNTO WSIZE) <= PiT6_r + Hi AFTER tscale;
280 outP_xhdl1(WSIZE-1 DOWNTO 0) <= PrT6_r + Hr AFTER tscale;
281 -- pipes
282
283 PrT6_r <= PrT5_r AFTER tscale; PiT6_r <= PiT5_r AFTER tscale;
284 PrT5_r <= PrT4_r AFTER tscale; PiT5_r <= PiT4_r AFTER tscale;
285 PrT4_r <= PrT3_r AFTER tscale; PiT4_r <= PiT3_r AFTER tscale;
286 PrT3_r <= PrT2_r AFTER tscale; PiT3_r <= PiT2_r AFTER tscale;
287 PrT2_r <= PrT1_r AFTER tscale; PiT2_r <= PiT1_r AFTER tscale;
288 PrT1_r <= inPr_w AFTER tscale; PiT1_r <= inPi_w AFTER tscale;
289 Hr <= Hr_w AFTER tscale; Hi <= Hi_w AFTER tscale;
290 validOut_xhdl3 <= pipe6(0) AFTER tscale;
291 swCrossOut_xhdl4 <= pipe6(1) AFTER tscale;
292 pipe6 <= pipe5 AFTER tscale; pipe5 <= pipe4 AFTER tscale;
293 pipe4 <= pipe3 AFTER tscale; pipe3 <= pipe2 AFTER tscale;
294 pipe2 <= pipe1 AFTER tscale; pipe1(0) <= validIn AFTER tscale;
295 pipe1(1) <= swCrossIn AFTER tscale;
296 END IF;
297 END PROCESS;
298 END ARCHITECTURE translated;
299 --------------------------------------------------------------------------------
300
301 --********************************** B U F F E R *******************************
302 ----------------------------------- inBuffer ----------------------------------V
303 -- InBuf stores double complex words so that FFT engine can read two cmplx
304 -- words per clock. Thus the depth of the buffer is `LOGPTS-1
305 LIBRARY IEEE;
306 USE IEEE.std_logic_1164.all;
307
308 ENTITY inBuffer IS
309 GENERIC ( LOGPTS : integer := 8;
310 DWIDTH : integer := 32 );
311 PORT (
312 clk, clkEn : IN std_logic;
313 rA, wA_bfly, wA_load : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
314 -- new data to load, data coming from FFT engine
315 ldData, wP_bfly, wQ_bfly: IN std_logic_vector(DWIDTH-1 DOWNTO 0);
316 wEn_bfly : IN std_logic; --wEn to store FFT engine data
317 wEn_even, wEn_odd : IN std_logic; --wEn to store new data in even/odd subbuffers
318 rEn : IN std_logic; --used only by FFT engine
319 -- pipo=pong for pong buffer, =/pong for ping buffer
320 pipo : IN std_logic; --controls buffer input muxes.
321 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0)); -- output data to FFT engine
322 END ENTITY inBuffer;
323
324 ARCHITECTURE translated OF inBuffer IS
325 CONSTANT tscale : time := 1 ns;
326
327 COMPONENT wrapRam
328 GENERIC ( LOGPTS : integer := 8;
329 DWIDTH : integer := 32 );
330 PORT( clk, wEn : in std_logic;
331 wA, rA : in std_logic_vector(LOGPTS-2 downto 0);
332 D : in std_logic_vector(DWIDTH-1 downto 0);
333 Q : out std_logic_vector(DWIDTH-1 downto 0) );
334 end component;
335
336 -- internal wires, &-gates
337 SIGNAL wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
338 SIGNAL wP_w, wQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
339 SIGNAL wEn_P, wEn_Q : std_logic;
340 SIGNAL rEn_ce_w,wEnP_ce_w,wEnQ_ce_w : std_logic;
341 SIGNAL temp_xhdl3 : std_logic;
342 SIGNAL temp_xhdl4 : std_logic;
343 SIGNAL temp_xhdl5 : std_logic_vector(LOGPTS-2 DOWNTO 0);
344 SIGNAL temp_xhdl6 : std_logic_vector(DWIDTH-1 DOWNTO 0);
345 SIGNAL temp_xhdl7 : std_logic_vector(DWIDTH-1 DOWNTO 0);
346 SIGNAL outP_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0);
347 SIGNAL outQ_xhdl2 : std_logic_vector(DWIDTH-1 DOWNTO 0);
348
349 BEGIN
350 outP <= outP_xhdl1;
351 outQ <= outQ_xhdl2;
352 rEn_ce_w <= rEn AND clkEn ;
353 wEnP_ce_w <= wEn_P AND clkEn ;
354 wEnQ_ce_w <= wEn_Q AND clkEn ;
355 temp_xhdl3 <= wEn_bfly WHEN pipo = '1' ELSE wEn_even;
356 wEn_P <= temp_xhdl3 ;
357 temp_xhdl4 <= wEn_bfly WHEN pipo = '1' ELSE wEn_odd;
358 wEn_Q <= temp_xhdl4 ;
359 temp_xhdl5 <= wA_bfly WHEN pipo = '1' ELSE wA_load;
360 wA_w <= temp_xhdl5 ;
361 temp_xhdl6 <= wP_bfly WHEN pipo = '1' ELSE ldData;
362 wP_w <= temp_xhdl6 ;
363 temp_xhdl7 <= wQ_bfly WHEN pipo = '1' ELSE ldData;
364 wQ_w <= temp_xhdl7 ;
365 -- if(~pipo) LOAD, else - RUN BFLY. Use MUX'es
366
367 -- instantiate two mem blocks `HALFPTS deep each
368 memP : wrapRam
369 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
370 PORT MAP (D => wP_w, Q => outP_xhdl1, wA => wA_w, rA => rA,
371 wEn => wEnP_ce_w, clk => clk);
372
373 memQ : wrapRam
374 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
375 PORT MAP (D => wQ_w, Q => outQ_xhdl2, wA => wA_w, rA => rA,
376 wEn => wEnQ_ce_w, clk => clk);
377 END ARCHITECTURE translated;
378 --------------------------------------------------------------------------------
379 ------------------------------- pipoBuffer ------------------------------------V
380 LIBRARY IEEE;
381 USE IEEE.std_logic_1164.all;
382
383 ENTITY pipoBuffer IS
384 GENERIC ( LOGPTS : integer := 8;
385 DWIDTH : integer := 32 );
386 PORT (
387 clk, clkEn, pong, rEn : IN std_logic;
388 rA, wA_load, wA_bfly : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
389 ldData,wP_bfly,wQ_bfly : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
390 wEn_bfly,wEn_even,wEn_odd : IN std_logic;
391 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0) );
392 END ENTITY pipoBuffer;
393
394 ARCHITECTURE translated OF pipoBuffer IS
395 CONSTANT tscale : time := 1 ns;
396
397 COMPONENT inBuffer
398 GENERIC ( LOGPTS : integer := 8;
399 DWIDTH : integer := 32 );
400 PORT (
401 clk, clkEn, rEn, pipo : IN std_logic;
402 rA,wA_bfly,wA_load : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
403 ldData,wP_bfly,wQ_bfly : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
404 wEn_bfly,wEn_even,wEn_odd : IN std_logic;
405 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0));
406 END COMPONENT;
407
408 --internal signals
409 SIGNAL pi_outP, pi_outQ : std_logic_vector(DWIDTH-1 DOWNTO 0);
410 SIGNAL po_outP, po_outQ : std_logic_vector(DWIDTH-1 DOWNTO 0);
411 SIGNAL port_xhdl17 : std_logic;
412 SIGNAL temp_xhdl32 : std_logic_vector(DWIDTH-1 DOWNTO 0);
413 SIGNAL temp_xhdl33 : std_logic_vector(DWIDTH-1 DOWNTO 0);
414 SIGNAL outP_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0);
415 SIGNAL outQ_xhdl2 : std_logic_vector(DWIDTH-1 DOWNTO 0);
416
417 BEGIN
418 outP <= outP_xhdl1;
419 outQ <= outQ_xhdl2;
420 port_xhdl17 <= NOT pong;
421 piBuf : inBuffer
422 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
423 PORT MAP (clk => clk, rA => rA, wA_bfly => wA_bfly,
424 wA_load => wA_load, ldData => ldData, wP_bfly => wP_bfly,
425 wQ_bfly => wQ_bfly, wEn_bfly => wEn_bfly,
426 wEn_even => wEn_even, wEn_odd => wEn_odd, rEn => rEn,
427 clkEn => clkEn, pipo => port_xhdl17,
428 outP => pi_outP, outQ => pi_outQ);
429
430 poBuf : inBuffer
431 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
432 PORT MAP (clk => clk, rA => rA, wA_bfly => wA_bfly,
433 wA_load => wA_load, ldData => ldData, wP_bfly => wP_bfly,
434 wQ_bfly => wQ_bfly, wEn_bfly => wEn_bfly,
435 wEn_even => wEn_even, wEn_odd => wEn_odd, rEn => rEn,
436 clkEn => clkEn, pipo => pong,
437 outP => po_outP, outQ => po_outQ);
438
439 temp_xhdl32 <= po_outP WHEN pong = '1' ELSE pi_outP;
440 outP_xhdl1 <= temp_xhdl32 ;
441 temp_xhdl33 <= po_outQ WHEN pong = '1' ELSE pi_outQ;
442 outQ_xhdl2 <= temp_xhdl33 ;
443
444 END ARCHITECTURE translated;
445 --------------------------------------------------------------------------------
446 --******************************* outBuffer *********************************V
447 LIBRARY IEEE;
448 USE IEEE.std_logic_1164.all;
449
450 ENTITY outBuff IS
451 GENERIC ( LOGPTS : integer := 8;
452 DWIDTH : integer := 32 );
453 PORT (
454 clk, clkEn, wEn : IN std_logic;
455 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
456 wA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
457 rA : IN std_logic_vector(LOGPTS-1 DOWNTO 0);
458 outD : OUT std_logic_vector(DWIDTH-1 DOWNTO 0));
459 END ENTITY outBuff;
460
461 ARCHITECTURE translated OF outBuff IS
462 CONSTANT tscale : time := 1 ns;
463
464 COMPONENT wrapRam
465 GENERIC ( LOGPTS : integer := 8;
466 DWIDTH : integer := 32 );
467 PORT( clk, wEn : in std_logic;
468 wA, rA : in std_logic_vector(LOGPTS-2 downto 0);
469 D : in std_logic_vector(DWIDTH-1 downto 0);
470 Q : out std_logic_vector(DWIDTH-1 downto 0) );
471 end component;
472
473 SIGNAL wEn_r : std_logic;
474 SIGNAL inP_r, inQ_r : std_logic_vector(DWIDTH-1 DOWNTO 0);
475 SIGNAL wA_r : std_logic_vector(LOGPTS-2 DOWNTO 0);
476 SIGNAL rAmsb_r1, rAmsb_r2 : std_logic;
477 SIGNAL P_w, Q_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
478 SIGNAL outPQ : std_logic_vector(DWIDTH-1 DOWNTO 0);
479 SIGNAL temp_xhdl10 : std_logic_vector(DWIDTH-1 DOWNTO 0);
480 SIGNAL outD_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0);
481
482 BEGIN
483 outD <= outD_xhdl1;
484 outBuf_0 : wrapRam
485 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
486 PORT MAP (D => inP_r, Q => P_w, wA => wA_r,
487 rA => rA(LOGPTS-2 DOWNTO 0),
488 wEn => wEn_r, clk => clk);
489 outBuf_1 : wrapRam
490 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
491 PORT MAP (D => inQ_r, Q => Q_w, wA => wA_r,
492 rA => rA(LOGPTS-2 DOWNTO 0),
493 wEn => wEn_r, clk => clk);
494
495 temp_xhdl10 <= Q_w WHEN rAmsb_r2 = '1' ELSE P_w;
496 outPQ <= temp_xhdl10 ;
497
498 PROCESS (clk)
499 BEGIN
500 IF (clk'EVENT AND clk = '1') THEN
501 inP_r <= inP AFTER 1*tscale;
502 inQ_r <= inQ AFTER 1*tscale; -- pipes
503 wEn_r <= wEn AFTER 1*tscale;
504 wA_r <= wA AFTER 1*tscale;
505 rAmsb_r2 <= rAmsb_r1 AFTER 1*tscale;
506 rAmsb_r1 <= rA(LOGPTS-1) AFTER 1*tscale;
507 outD_xhdl1 <= outPQ AFTER 1*tscale;
508 END IF;
509 END PROCESS;
510 END ARCHITECTURE translated;
511 --------------------------------------------------------------------------------
512 --************************ T W I D D L E L U T ******************************V
513 -- RAM-block based twiddle LUT
514 LIBRARY IEEE;
515 USE IEEE.std_logic_1164.all;
516
517 ENTITY twidLUT IS
518 GENERIC ( LOGPTS : integer := 8;
519 TDWIDTH : integer := 32 );
520 PORT (
521 clk, wEn : IN std_logic;
522 wA, rA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
523 D : IN std_logic_vector(TDWIDTH-1 DOWNTO 0);
524 Q : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0));
525 END ENTITY twidLUT;
526
527 ARCHITECTURE translated OF twidLUT IS
528 CONSTANT tscale : time := 1 ns;
529
530 COMPONENT wrapRam
531 GENERIC ( LOGPTS : integer := 8;
532 DWIDTH : integer := 32 );
533 PORT( clk, wEn : in std_logic;
534 wA, rA : in std_logic_vector(LOGPTS-2 downto 0);
535 D : in std_logic_vector(TDWIDTH-1 downto 0);
536 Q : out std_logic_vector(TDWIDTH-1 downto 0) );
537 end component;
538
539 SIGNAL rA_r : std_logic_vector(LOGPTS-2 DOWNTO 0);
540 SIGNAL Q_xhdl1 : std_logic_vector(TDWIDTH-1 DOWNTO 0);
541
542 BEGIN
543 Q <= Q_xhdl1;
544 twidLUT_0 : wrapRam
545 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => TDWIDTH )
546 PORT MAP (D => D, Q => Q_xhdl1, wA => wA, rA => rA_r,
547 wEn => wEn, clk => clk);
548
549 PROCESS (clk)
550 BEGIN
551 IF (clk'EVENT AND clk = '1') THEN
552 rA_r <= rA AFTER tscale;
553 END IF;
554 END PROCESS;
555 END ARCHITECTURE translated;
556 --------------------------------------------------------------------------------
557 ------------------------- R A M -----------------------
558 LIBRARY IEEE;
559 USE IEEE.std_logic_1164.all;
560
561 ENTITY wrapRam IS
562 GENERIC ( LOGPTS : integer := 8;
563 DWIDTH : integer := 32 );
564 PORT (clk, wEn : IN std_logic;
565 D : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
566 rA, wA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
567 Q : OUT std_logic_vector(DWIDTH-1 DOWNTO 0) );
568 END ENTITY wrapRam;
569
570 ARCHITECTURE rtl OF wrapRam IS
571 CONSTANT RE : std_logic := '0';
572 COMPONENT actram
573 port(WRB, RDB, WCLOCK, RCLOCK : IN std_logic;
574 DI : in std_logic_vector(DWIDTH-1 downto 0);
575 DO : out std_logic_vector(DWIDTH-1 downto 0);
576 WADDR,RADDR : IN std_logic_vector(LOGPTS-2 downto 0) );
577 end COMPONENT;
578
579 SIGNAL nwEn : std_logic;
580
581 BEGIN
582 nwEn <= NOT wEn;
583 wrapRam_0 : actram
584 PORT MAP (DI => D, WADDR => wA, RADDR => rA, WRB => nwEn,
585 RDB => RE, RCLOCK => clk, WCLOCK => clk, DO => Q);
586 END ARCHITECTURE rtl;
587 -------------------------------------------------------------------------------V
588 LIBRARY IEEE;
589 USE IEEE.std_logic_1164.all;
590 USE work.fft_components.all;
591
592 ENTITY autoScale IS
593 GENERIC (SCALE_MODE : integer := 1 ); -- enable autoscaling
594 PORT (
595 clk, clkEn, wLastStage : IN std_logic;
596 ldRiskOV, bflyRiskOV : IN std_logic;
597 startLoad, ifo_loadOn : IN std_logic;
598 bflyOutValid, startFFT : IN std_logic;
599 wEn_even, wEn_odd : IN std_logic;
600 -- scaleMode : IN std_logic; --set 1 to turn autoscaling ON
601 upScale : OUT std_logic);
602 END ENTITY autoScale;
603
604 ARCHITECTURE translated OF autoScale IS
605 CONSTANT tscale : time := 1 ns;
606
607 SIGNAL ldMonitor, bflyMonitor, stageEnd_w : std_logic;
608 SIGNAL xhdl_5 : std_logic;
609 SIGNAL upScale_xhdl1 : std_logic;
610
611 BEGIN
612 upScale <= upScale_xhdl1;
613 xhdl_5 <= (bflyOutValid AND (NOT wLastStage));
614 fedge_0 : edgeDetect
615 GENERIC MAP (INPIPE => 0, FEDGE => 1)
616 PORT MAP (clk => clk, clkEn => clkEn, edgeIn => xhdl_5, edgeOut => stageEnd_w);
617
618 PROCESS (clk)
619 BEGIN
620 IF (clk'EVENT AND clk = '1') THEN
621 -- Initialize ldMonitor
622 IF (startLoad = '1') THEN
623 ldMonitor <= to_logic(SCALE_MODE) AFTER tscale;
624 ELSE
625 -- Monitor the data being loaded: turn down ldMonitor
626 -- if any valid input data violates the condition
627 IF ((ldRiskOV AND (wEn_even OR wEn_odd)) = '1') THEN
628 ldMonitor <= '0' AFTER tscale;
629 END IF;
630 END IF;
631 -- monitor the data being FFT'ed
632 IF ((bflyRiskOV AND bflyOutValid) = '1') THEN
633 bflyMonitor <= '0';
634 END IF;
635 --check ldMonitor on startFFT (startFFT coinsides with the next startLoad)
636 IF (startFFT = '1') THEN
637 upScale_xhdl1 <= ldMonitor AFTER tscale;
638 -- initialize bflyMonitor
639 bflyMonitor <= to_logic(SCALE_MODE) AFTER tscale;
640 ELSE
641 -- Check the bflyMonitor at a stage end except the last stage, since the
642 -- end of the last stage may come on or even after the startFFT signal
643 -- when the upScale is supposed to check the ldMonitor only
644 IF (stageEnd_w = '1') THEN
645 upScale_xhdl1 <= bflyMonitor AFTER tscale;
646 -- initialize bflyMonitor at the beginning of every stage
647 bflyMonitor <= to_logic(SCALE_MODE) AFTER tscale;
648 END IF;
649 END IF;
650 END IF;
651 END PROCESS;
652
653 END ARCHITECTURE translated;
654 --------------------------------------------------------------------------------
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: fftSm.vhd
10 -- Description: CoreFFT
11 -- FFT state machine module
12 -- Rev: 3.0 3/28/2007 4:43PM VlaD : Variable bitwidth
13 --
14 --
15 --------------------------------------------------------------------------------
16 --************************** TWIDDLE rA GENERATOR **************************
17 LIBRARY IEEE;
18 USE IEEE.std_logic_1164.all;
19 USE IEEE.std_logic_unsigned.all;
20 USE work.fft_components.all;
21
22 ENTITY twid_rA IS
23 GENERIC (LOGPTS : integer := 8;
24 LOGLOGPTS : integer := 3 );
25 PORT (clk : IN std_logic;
26 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
27 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
28 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
29 END ENTITY twid_rA;
30
31 ARCHITECTURE translated OF twid_rA IS
32 CONSTANT timescale : time := 1 ns;
33 --twiddleMask = ~(0xFFFFFFFF<<(NumberOfStages-1));
34 --addrTwiddle=reverseBits(count, NumberOfStages-1)<<(NumberOfStages-1-stage);
35 --mask out extra left bits: addrTwiddle = addrTwiddle & twiddleMask;
36 --reverse bits of the timer;
37 SIGNAL reverseBitTimer : bit_vector(LOGPTS-2 DOWNTO 0);
38 SIGNAL tA_w, tA_reg : std_logic_vector(LOGPTS-2 DOWNTO 0);
39
40 BEGIN
41 tA <= tA_reg;
42 PROCESS (timer)
43 BEGIN
44 reverseBitTimer <= reverse(timer);
45 END PROCESS;
46 -- Left shift by
47 tA_w <= To_StdLogicVector(reverseBitTimer SLL (LOGPTS-1 - to_integer(stage)) )
48 AFTER timescale;
49
50 PROCESS (clk)
51 BEGIN
52 IF (clk'EVENT AND clk = '1') THEN
53 tA_reg <= tA_w AFTER timescale;
54 END IF;
55 END PROCESS;
56 END ARCHITECTURE translated;
57 --------------------------------------------------------------------------------
58 --***************************** TIMERS & rdValid ***************************
59 -- FFT computation sequence is predefined. Once it gets started it runs for
60 -- a number of stages, `HALFPTS+ clk per stage. The following module sets the
61 -- read inBuf time sequence. Every stage takes HALFPTS + inBuf_RWDLY clk for
62 -- the inBuf to write Bfly results back in place before it starts next stage
63 LIBRARY IEEE;
64 USE IEEE.std_logic_1164.all;
65 USE work.fft_components.all;
66
67 ENTITY rdFFTtimer IS
68 GENERIC (LOGPTS : integer := 8;
69 LOGLOGPTS : integer := 3;
70 HALFPTS : integer := 128;
71 inBuf_RWDLY : integer := 12 );
72 PORT (
73 clk, cntEn, rst, nGrst : IN std_logic;
74 startFFT, fft_runs : IN std_logic;
75 timerTC, lastStage : OUT std_logic; --terminal counts of rA and stage
76 stage : OUT std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
77 timer : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
78 rdValid : OUT std_logic );
79 END ENTITY rdFFTtimer;
80
81 ARCHITECTURE translated OF rdFFTtimer IS
82 CONSTANT dlta : time := 1 ns;
83
84 SIGNAL preRdValid : std_logic;
85 SIGNAL pipe1, pipe2 : std_logic;
86 SIGNAL rst_comb, timerTCx1 : std_logic;
87 SIGNAL lastStage_xhdl2 : std_logic;
88 SIGNAL stage_xhdl3 : std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
89 SIGNAL timer_xhdl4 : std_logic_vector(LOGPTS-1 DOWNTO 0);
90 SIGNAL rdValid_xhdl5 : std_logic;
91
92 BEGIN
93 timerTC <= timerTCx1;
94 lastStage <= lastStage_xhdl2;
95 stage <= stage_xhdl3;
96 timer <= timer_xhdl4;
97 rdValid <= rdValid_xhdl5;
98 rst_comb <= rst OR startFFT;
99
100 rA_timer : counter
101 GENERIC MAP (WIDTH =>LOGPTS, TERMCOUNT =>HALFPTS+inBuf_RWDLY-1)
102 PORT MAP (clk => clk, nGrst => nGrst, rst => rst_comb,
103 cntEn => cntEn, tc => timerTCx1, Q => timer_xhdl4);
104 stage_timer : counter
105 GENERIC MAP (WIDTH => LOGLOGPTS, TERMCOUNT => LOGPTS-1)
106 PORT MAP (clk => clk, nGrst => nGrst, rst => rst_comb,
107 cntEn => timerTCx1, tc => lastStage_xhdl2,
108 Q => stage_xhdl3);
109
110 PROCESS (clk, nGrst)
111 BEGIN
112 IF (NOT nGrst = '1') THEN
113 preRdValid <= '0';
114 ELSIF (clk'EVENT AND clk = '1') THEN
115 IF (rst = '1') THEN
116 preRdValid <= '0' AFTER dlta;
117 ELSE
118 IF (cntEn = '1') THEN
119 IF ( to_integer(timer_xhdl4) = HALFPTS-1 ) THEN
120 preRdValid <= '0' AFTER dlta;
121 END IF;
122 -- on startFFT the valid reading session always starts
123 IF (startFFT = '1') THEN preRdValid <= '1' AFTER dlta;
124 END IF;
125 -- reading session starts on rTimerTC except after the lastStage
126 IF ((((NOT lastStage_xhdl2) AND timerTCx1) AND fft_runs) = '1') THEN
127 preRdValid <= '1' AFTER dlta;
128 END IF;
129 END IF;
130 END IF;
131 END IF;
132 END PROCESS;
133
134 PROCESS (clk)
135 BEGIN
136 IF (clk'EVENT AND clk = '1') THEN
137 rdValid_xhdl5 <= pipe2 AFTER dlta;
138 pipe2 <= pipe1 AFTER dlta;
139 pipe1 <= preRdValid AFTER dlta;
140 END IF;
141 END PROCESS;
142 END ARCHITECTURE translated;
143 --------------------------------------------------------------------------------
144 LIBRARY IEEE;
145 USE IEEE.std_logic_1164.all;
146 USE work.fft_components.all;
147
148 ENTITY wrFFTtimer IS
149 GENERIC (LOGPTS : integer := 8;
150 LOGLOGPTS : integer := 3;
151 HALFPTS : integer := 128 );
152 PORT (
153 clk, cntEn, nGrst, rst : IN std_logic;
154 rstStage, rstTime : IN std_logic;
155 timerTC, lastStage : OUT std_logic; -- terminal counts of wA and stage
156 stage : OUT std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
157 timer : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
158 END ENTITY wrFFTtimer;
159
160 ARCHITECTURE translated OF wrFFTtimer IS
161 CONSTANT timescale : time := 1 ns;
162
163 SIGNAL rst_VHDL,rstStage_VHDL : std_logic;
164 SIGNAL timerTC_xhdl1 : std_logic;
165 SIGNAL lastStage_xhdl2 : std_logic;
166 SIGNAL stage_xhdl3 : std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
167 SIGNAL timer_xhdl4 : std_logic_vector(LOGPTS-2 DOWNTO 0);
168
169 BEGIN
170 timerTC <= timerTC_xhdl1;
171 lastStage <= lastStage_xhdl2;
172 stage <= stage_xhdl3;
173 timer <= timer_xhdl4;
174 rst_VHDL <= rstTime OR rst;
175 wA_timer : counter
176 GENERIC MAP (WIDTH => LOGPTS-1, TERMCOUNT =>HALFPTS-1)
177 PORT MAP (clk => clk, nGrst => nGrst, rst => rst_VHDL, cntEn => cntEn,
178 tc => timerTC_xhdl1, Q => timer_xhdl4);
179 rstStage_VHDL <= rstStage OR rst;
180
181 stage_timer : counter
182 GENERIC MAP (WIDTH => LOGLOGPTS, TERMCOUNT =>LOGPTS-1)
183 PORT MAP (clk => clk, nGrst => nGrst, rst => rstStage_VHDL,
184 cntEn => timerTC_xhdl1, tc => lastStage_xhdl2,
185 Q => stage_xhdl3);
186 END ARCHITECTURE translated;
187 --------------------------------------------------------------------------------
188 --********************* inBuf LOAD ADDRESS GENERATOR *********************
189 LIBRARY IEEE;
190 USE IEEE.std_logic_1164.all;
191 USE work.fft_components.all;
192
193 ENTITY inBuf_ldA IS
194 GENERIC (PTS : integer := 256;
195 LOGPTS : integer := 8 );
196 PORT (
197 clk, clkEn, nGrst : IN std_logic;
198 --comes from topSM to reset ldA count & start another loading cycle
199 startLoad : IN std_logic;
200 ifi_dataRdy : IN std_logic; -- inData strobe
201 ifo_loadOn : OUT std_logic;-- inBuf is ready for new data
202 --tells topSM the buffer is fully loaded and ready for FFTing
203 load_done : OUT std_logic;
204 ldA : OUT std_logic_vector(LOGPTS-1 DOWNTO 1);
205 wEn_even, wEn_odd : OUT std_logic;
206 ldValid : OUT std_logic);
207 END ENTITY inBuf_ldA;
208
209 ARCHITECTURE translated OF inBuf_ldA IS
210 CONSTANT timescale : time := 1 ns;
211
212 -- just LSB of the counter below. Counts even/odd samples
213 SIGNAL ldCountLsb_w : std_logic;
214 SIGNAL closeLoad_w, cntEn_w : std_logic;
215 SIGNAL loadOver_w : std_logic;
216 SIGNAL xhdl_9 : std_logic_vector(LOGPTS-1 DOWNTO 0);
217 SIGNAL ifo_loadOn_int : std_logic;
218 SIGNAL load_done_int : std_logic;
219 SIGNAL ldA_int : std_logic_vector(LOGPTS-1 DOWNTO 1);
220 SIGNAL wEn_even_int : std_logic;
221 SIGNAL wEn_odd_int : std_logic;
222 SIGNAL ldValid_int : std_logic;
223
224 BEGIN
225 ifo_loadOn <= ifo_loadOn_int;
226 load_done <= load_done_int;
227 ldA <= ldA_int;
228 wEn_even <= wEn_even_int;
229 wEn_odd <= wEn_odd_int;
230 ldValid <= ldValid_int;
231 cntEn_w <= clkEn AND ifi_dataRdy ;
232 loadOver_w <= closeLoad_w AND wEn_odd_int ;
233 ldValid_int <= ifo_loadOn_int AND ifi_dataRdy ;
234 wEn_even_int <= NOT ldCountLsb_w AND ldValid_int ;
235 wEn_odd_int <= ldCountLsb_w AND ldValid_int ;
236 -- xhdl_9 <= ldA_int & ldCountLsb_w;
237 ldA_int <= xhdl_9(LOGPTS-1 DOWNTO 1);
238 ldCountLsb_w <= xhdl_9(0);
239 -- counts samples loaded. There is `PTS samples to load, not `PTS/2
240 ldCount : counter
241 GENERIC MAP (WIDTH =>LOGPTS, TERMCOUNT =>PTS-1)
242 PORT MAP (clk => clk, nGrst => nGrst, rst => startLoad,
243 cntEn => cntEn_w, tc => closeLoad_w, Q => xhdl_9);
244
245 -- A user can stop supplying ifi_dataRdy after loadOver gets high, thus
246 -- the loadOver can stay high indefinitely. Shorten it!
247 edge_0 : edgeDetect
248 GENERIC MAP (INPIPE => 0, FEDGE => 1)
249 PORT MAP (clk => clk, clkEn => clkEn, edgeIn => loadOver_w,
250 edgeOut => load_done_int);
251
252 PROCESS (clk, nGrst)
253 BEGIN
254 -- generate ifo_loadOn:
255 IF (NOT nGrst = '1') THEN
256 ifo_loadOn_int <= '0';
257 ELSE
258 IF (clk'EVENT AND clk = '1') THEN
259 IF (clkEn = '1') THEN
260 -- if (load_done) ifo_loadOn <= #1 0;
261 IF (loadOver_w = '1') THEN
262 ifo_loadOn_int <= '0' AFTER timescale;
263 ELSE
264 IF (startLoad = '1') THEN
265 ifo_loadOn_int <= '1' AFTER timescale;
266 END IF;
267 END IF;
268 END IF;
269 END IF;
270 END IF;
271 END PROCESS;
272 END ARCHITECTURE translated;
273 --------------------------------------------------------------------------------
274 --****************** inBuf ADDRESS GENERATOR for BFLY DATA *****************
275 -- Implements both read and write data generators. The core utilizes inPlace
276 -- algorithm thus the wA is a delayed copy of the rA
277 LIBRARY IEEE;
278 USE IEEE.std_logic_1164.all;
279 USE IEEE.STD_LOGIC_UNSIGNED.all;
280 USE work.fft_components.all;
281
282 ENTITY inBuf_fftA IS
283 GENERIC (LOGPTS : integer := 8;
284 LOGLOGPTS : integer := 3 );
285 PORT (
286 clk, clkEn :IN std_logic;
287 timer :IN std_logic_vector(LOGPTS-2 DOWNTO 0);
288 stage :IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
289 timerTC, lastStage :IN std_logic;
290 fftDone, swCross :OUT std_logic;
291 bflyA :OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
292 END ENTITY inBuf_fftA;
293
294 ARCHITECTURE translated OF inBuf_fftA IS
295 CONSTANT timescale : time := 1 ns;
296 CONSTANT offsetConst : bit_vector(LOGPTS-1 DOWNTO 0):=('1', others=>'0');
297 CONSTANT addrMask1: BIT_VECTOR(LOGPTS-1 DOWNTO 0) := ('0', OTHERS=>'1');
298 CONSTANT addrMask2: BIT_VECTOR(LOGPTS-1 DOWNTO 0) := (OTHERS=>'1');
299
300 SIGNAL fftDone_w, swCross_w: std_logic;
301 SIGNAL bflyA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
302 SIGNAL addrP_w, offsetPQ_w : std_logic_vector(LOGPTS-1 DOWNTO 0);
303 --rA takes either Paddr or Qaddr value (Qaddr=Paddr+offsetPQ) per clock.
304 --At even clk rA=Paddr, at odd clk rA=Qaddr. (Every addr holds a pair of
305 --data samples). Timer LSB controls which clk is happening now. LSB of
306 --the same timer controls switch(es).
307 SIGNAL bflyA_w_int : std_logic_vector(LOGPTS-1 DOWNTO 1);
308 SIGNAL swCross_w_int,swCross_int: std_logic;
309 SIGNAL fftDone_int : std_logic;
310 SIGNAL bflyA_int : std_logic_vector(LOGPTS-2 DOWNTO 0);
311
312 BEGIN
313 fftDone <= fftDone_int;
314 bflyA <= bflyA_int;
315 swCross <= swCross_int;
316 --addrP_w=( (timer<<1)&(~(addrMask2>>stage)) ) | (timer&(addrMask1>>stage));
317 addrP_w <= To_StdLogicVector(
318 ( (('0'& To_BitVector(timer)) SLL 1) AND (NOT (addrMask2 SRL to_integer(stage)) ) )
319 OR ( ('0'& To_BitVector(timer)) AND (addrMask1 SRL to_integer(stage)) ) );
320
321 -- address offset between P and Q offsetPQ_w= ( 1<<(`LOGPTS-1) )>>stage;
322 offsetPQ_w <= To_StdLogicVector(offsetConst SRL to_integer(stage));
323
324 -- bflyA_w = timer[0] ? (addrP_w[`LOGPTS-1:1]+offsetPQ_w[`LOGPTS-1:1]):
325 -- addrP_w[`LOGPTS-1:1];
326 bflyA_w_int <=
327 (addrP_w(LOGPTS-1 DOWNTO 1) + offsetPQ_w(LOGPTS-1 DOWNTO 1)) WHEN
328 timer(0) = '1'
329 ELSE addrP_w(LOGPTS-1 DOWNTO 1);
330
331 bflyA_w <= bflyA_w_int AFTER timescale;
332 fftDone_w <= lastStage AND timerTC AFTER timescale;
333 swCross_w_int <= '0' WHEN lastStage = '1' ELSE timer(0);
334 swCross_w <= swCross_w_int AFTER timescale;
335
336 PROCESS (clk)
337 BEGIN
338 IF (clk'EVENT AND clk = '1') THEN
339 IF (clkEn = '1') THEN
340 bflyA_int <= bflyA_w AFTER timescale;
341 swCross_int <= swCross_w AFTER timescale;
342 fftDone_int <= fftDone_w AFTER timescale;
343 END IF;
344 END IF;
345 END PROCESS;
346 END ARCHITECTURE translated;
347 --------------------------------------------------------------------------------
348 --************************** TWIDDLE wA GENERATOR ****************************
349 -- initializes Twiddle LUT on rst based on contents of twiddle.v file.
350 -- Generates trueRst when the initialization is over
351 LIBRARY IEEE;
352 USE IEEE.std_logic_1164.all;
353 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
354 USE work.fft_components.all;
355
356 ENTITY twid_wAmod IS
357 GENERIC (LOGPTS : integer := 8 );
358 PORT (
359 clk, ifiNreset : IN std_logic; -- async global reset
360 twid_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
361 twid_wEn,twidInit : OUT std_logic;
362 rstAfterInit : OUT std_logic);
363 END ENTITY twid_wAmod;
364
365 ARCHITECTURE translated OF twid_wAmod IS
366 CONSTANT timescale : time := 1 ns;
367 CONSTANT allOnes : std_logic_vector(LOGPTS+1 DOWNTO 0):=(OTHERS=>'1');
368
369 SIGNAL slowTimer_w : std_logic_vector(LOGPTS+1 DOWNTO 0);
370 SIGNAL preRstAfterInit : std_logic;
371 SIGNAL twid_wA_int : std_logic_vector(LOGPTS-2 DOWNTO 0);
372 SIGNAL twid_wEn_int : std_logic;
373 SIGNAL rstAfterInit_int : std_logic;
374 SIGNAL twidInit_int : std_logic;
375
376 BEGIN
377 twid_wA <= twid_wA_int;
378 twid_wEn <= twid_wEn_int;
379 rstAfterInit <= rstAfterInit_int;
380 twidInit <= twidInit_int;
381
382 -- slow counter not to worry about the clk rate
383 slowTimer : bcounter
384 GENERIC MAP (WIDTH => LOGPTS+2)
385 PORT MAP (clk => clk, nGrst => ifiNreset, rst => '0',
386 cntEn => twidInit_int, Q => slowTimer_w);
387 -- wEn = 2-clk wide for the RAM to have enough time
388 twid_wEn_int <= to_logic(slowTimer_w(2 DOWNTO 1) = "11");
389 twid_wA_int <= slowTimer_w(LOGPTS+1 DOWNTO 3);
390
391 PROCESS (clk, ifiNreset)
392 BEGIN
393 IF (NOT ifiNreset = '1') THEN
394 twidInit_int <= '1' AFTER timescale;
395 ELSIF (clk'EVENT AND clk = '1') THEN
396 rstAfterInit_int <= preRstAfterInit AFTER timescale;
397 IF (slowTimer_w = allOnes) THEN twidInit_int <='0' AFTER timescale;
398 END IF;
399 preRstAfterInit <= to_logic(slowTimer_w = allOnes) AFTER timescale;
400 END IF;
401 END PROCESS;
402 END ARCHITECTURE translated;
403 --------------------------------------------------------------------------------
404 ----------------------------------- outBufA ------------------------------------
405 LIBRARY IEEE;
406 USE IEEE.std_logic_1164.all;
407 USE IEEE.STD_LOGIC_UNSIGNED.all;
408 USE work.fft_components.all;
409
410 ENTITY outBufA IS
411 GENERIC (PTS : integer := 256;
412 LOGPTS : integer := 8 );
413 PORT (clk, clkEn, nGrst : IN std_logic;
414 rst, outBuf_wEn : IN std_logic;
415 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
416 -- host can slow down results reading by lowering the signal
417 rdCtl : IN std_logic;
418 wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
419 rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
420 outBuf_rEn, rdValid : OUT std_logic);
421 END ENTITY outBufA;
422
423 ARCHITECTURE translated OF outBufA IS
424 CONSTANT timescale : time := 1 ns;
425
426 SIGNAL reverseBitTimer, wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
427 SIGNAL outBufwEnFall_w : std_logic;
428 SIGNAL rA_TC_w, preOutBuf_rEn: std_logic;
429 SIGNAL pipe11, pipe12, pipe21: std_logic;
430 SIGNAL pipe22, rdCtl_reg : std_logic;
431 -- Reset a binary counter on the rear edge
432 SIGNAL rstVhdl, rdValid_int : std_logic;
433 SIGNAL wA_int : std_logic_vector(LOGPTS-2 DOWNTO 0);
434 SIGNAL rA_int : std_logic_vector(LOGPTS-1 DOWNTO 0);
435 SIGNAL outBuf_rEn_int : std_logic;
436
437 BEGIN
438 wA <= wA_int;
439 rA <= rA_int;
440 outBuf_rEn <= outBuf_rEn_int;
441 rdValid <= rdValid_int;
442
443 PROCESS (timer)
444 VARIABLE reverseBitTimer_int : std_logic_vector(LOGPTS-2 DOWNTO 0);
445 BEGIN
446 reverseBitTimer_int := reverseStd(timer);
447 reverseBitTimer <= reverseBitTimer_int;
448 END PROCESS;
449 wA_w <= reverseBitTimer AFTER timescale;
450 -- rA generator. Detect rear edge of the outBuf wEn
451 fedge_0 : edgeDetect
452 GENERIC MAP (INPIPE => 0, FEDGE => 1)
453 PORT MAP (clk => clk, clkEn => '1', edgeIn => outBuf_wEn,
454 edgeOut => outBufwEnFall_w);
455
456 rstVhdl <= rst OR outBufwEnFall_w;
457
458 outBuf_rA_0 : counter
459 GENERIC MAP (WIDTH => LOGPTS, TERMCOUNT =>PTS-1)
460 PORT MAP (clk => clk, nGrst => nGrst, rst => rstVhdl,
461 cntEn => rdCtl_reg, tc => rA_TC_w, Q => rA_int);
462
463 PROCESS (clk, nGrst)
464 BEGIN
465 -- RS FF preOutBuf_rEn
466 IF (NOT nGrst = '1') THEN
467 preOutBuf_rEn <= '0' AFTER timescale;
468 ELSE
469 IF (clk'EVENT AND clk = '1') THEN
470 IF ((rst OR outBuf_wEn OR rA_TC_w) = '1') THEN
471 preOutBuf_rEn <= '0' AFTER timescale;
472 ELSE
473 IF (outBufwEnFall_w = '1') THEN
474 preOutBuf_rEn <= '1' AFTER timescale;
475 END IF;
476 END IF;
477 END IF;
478 END IF;
479 END PROCESS;
480
481 PROCESS (clk)
482 BEGIN
483 IF (clk'EVENT AND clk = '1') THEN
484 wA_int <= wA_w AFTER timescale;
485 rdCtl_reg <= rdCtl AFTER timescale;
486 outBuf_rEn_int <= pipe12 AFTER timescale;
487 pipe12 <= pipe11 AFTER timescale;
488 pipe11 <= preOutBuf_rEn AFTER timescale;
489 rdValid_int <= pipe22 AFTER timescale;
490 pipe22 <= pipe21 AFTER timescale;
491 pipe21 <= preOutBuf_rEn AND rdCtl_reg AFTER timescale;
492 END IF;
493 END PROCESS;
494 END ARCHITECTURE translated;
495 ----------------------------------------------------------------------------------------------
496 --********************************** SM TOP ********************************
497 LIBRARY IEEE;
498 USE IEEE.std_logic_1164.all;
499 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
500 USE IEEE.std_logic_arith.all;
501 USE work.fft_components.all;
502
503 ENTITY sm_top IS
504 GENERIC ( PTS : integer := 256;
505 HALFPTS : integer := 128;
506 LOGPTS : integer := 8;
507 LOGLOGPTS : integer := 3;
508 inBuf_RWDLY : integer := 12 );
509 PORT (clk,clkEn : IN std_logic;
510 ifiStart, ifiNreset : IN std_logic; --sync and async reset
511 ifiD_valid, ifiRead_y : IN std_logic;
512 ldA, rA, wA, tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
513 twid_wA, outBuf_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
514 outBuf_rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
515 wEn_even, wEn_odd : OUT std_logic;
516 preSwCross, twid_wEn : OUT std_logic;
517 inBuf_wEn, outBuf_wEn : OUT std_logic;
518 smPong, ldValid : OUT std_logic;
519 inBuf_rdValid : OUT std_logic;
520 wLastStage : OUT std_logic;
521 smStartFFTrd : OUT std_logic;
522 smStartLoad, ifoLoad : OUT std_logic;
523 ifoY_valid, ifoY_rdy : OUT std_logic);
524 END ENTITY sm_top;
525
526 ARCHITECTURE translated OF sm_top IS
527 CONSTANT timescale : time := 1 ns;
528
529 COMPONENT inBuf_fftA
530 GENERIC (LOGPTS : integer := 8;
531 LOGLOGPTS : integer := 3 );
532 PORT (clk, clkEn : IN std_logic;
533 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
534 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
535 timerTC, lastStage : IN std_logic;
536 fftDone, swCross : OUT std_logic;
537 bflyA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0) );
538 END COMPONENT;
539
540 COMPONENT inBuf_ldA
541 GENERIC (PTS : integer := 8;
542 LOGPTS : integer := 3 );
543 PORT (
544 clk, clkEn, nGrst : IN std_logic;
545 startLoad, ifi_dataRdy : IN std_logic;
546 ifo_loadOn, load_done : OUT std_logic;
547 ldA : OUT std_logic_vector(LOGPTS-1 DOWNTO 1);
548 wEn_even, wEn_odd : OUT std_logic;
549 ldValid : OUT std_logic);
550 END COMPONENT;
551
552
553 COMPONENT outBufA
554 GENERIC (PTS : integer := 256;
555 LOGPTS : integer := 8 );
556 PORT (clk,clkEn,nGrst : IN std_logic;
557 rst, outBuf_wEn, rdCtl : IN std_logic;
558 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
559 wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
560 rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
561 outBuf_rEn, rdValid : OUT std_logic);
562 END COMPONENT;
563
564 COMPONENT rdFFTtimer
565 GENERIC (LOGPTS : integer := 8;
566 LOGLOGPTS : integer := 3;
567 HALFPTS : integer := 128;
568 inBuf_RWDLY : integer := 12 );
569 PORT (clk, cntEn, rst : IN std_logic;
570 startFFT,fft_runs,nGrst : IN std_logic;
571 timerTC, lastStage : OUT std_logic;
572 stage : OUT std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
573 timer : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
574 rdValid : OUT std_logic );
575 END COMPONENT;
576
577 COMPONENT twid_rA
578 GENERIC (LOGPTS : integer := 8;
579 LOGLOGPTS : integer := 3 );
580 PORT (
581 clk : IN std_logic;
582 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
583 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
584 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
585 END COMPONENT;
586
587 COMPONENT twid_wAmod
588 GENERIC (LOGPTS : integer := 8 );
589 PORT (clk, ifiNreset: IN std_logic;
590 twid_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
591 twid_wEn,twidInit : OUT std_logic;
592 rstAfterInit : OUT std_logic );
593 END COMPONENT;
594
595 COMPONENT wrFFTtimer
596 GENERIC (LOGPTS : integer := 8;
597 LOGLOGPTS : integer := 3;
598 HALFPTS : integer := 128 );
599 PORT (
600 clk, cntEn, nGrst, rst : IN std_logic;
601 rstStage, rstTime : IN std_logic;
602 timerTC, lastStage : OUT std_logic;
603 stage : OUT std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
604 timer : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
605 END COMPONENT;
606
607 SIGNAL rTimer_w : std_logic_vector(LOGPTS-1 DOWNTO 0);
608 SIGNAL wTimer_w, timerT1 : std_logic_vector(LOGPTS-2 DOWNTO 0);
609 SIGNAL rStage_w,wStage_w : std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
610 SIGNAL stageT1, stageT2 : std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
611 SIGNAL rLastStage_w : std_logic;
612 SIGNAL rTimerTC_w : std_logic;
613 SIGNAL wTimerTC_w : std_logic;
614 SIGNAL load_done_w : std_logic;
615 SIGNAL sync_rAwA : std_logic;
616 SIGNAL fftRd_done_w : std_logic;
617 SIGNAL preInBuf_wEn : std_logic;
618 SIGNAL preOutBuf_wEn : std_logic;
619 SIGNAL trueRst : std_logic;
620 SIGNAL smBuf_full : std_logic; -- top level SM registers
621 SIGNAL smFft_rdy : std_logic; -- top level SM registers
622 SIGNAL smFft_runs : std_logic; -- top level SM registers
623 -- Reset logic:
624 -- - On ifiNreset start loading twidLUT.
625 -- - While it is loading keep global async rst nGrst active
626 -- - Once load is over issue short rstAfterInit which is just another ifiStart
627 SIGNAL initRst, nGrst : std_logic;
628 SIGNAL rstAfterInit : std_logic;
629 SIGNAL trueRst_w : std_logic;
630 SIGNAL xhdl_27, rdTimer_cntEn : std_logic;
631 SIGNAL port_xhdl37 : std_logic_vector(LOGPTS-2 DOWNTO 0);
632 SIGNAL ldA_xhdl1 : std_logic_vector(LOGPTS-2 DOWNTO 0);
633 SIGNAL rA_xhdl2 : std_logic_vector(LOGPTS-2 DOWNTO 0);
634 SIGNAL wA_xhdl3 : std_logic_vector(LOGPTS-2 DOWNTO 0);
635 SIGNAL tA_xhdl4 : std_logic_vector(LOGPTS-2 DOWNTO 0);
636 SIGNAL twid_wA_xhdl5 : std_logic_vector(LOGPTS-2 DOWNTO 0);
637 SIGNAL outBuf_wA_xhdl6 : std_logic_vector(LOGPTS-2 DOWNTO 0);
638 SIGNAL outBuf_rA_xhdl7 : std_logic_vector(LOGPTS-1 DOWNTO 0);
639 SIGNAL wEn_even_xhdl8 : std_logic;
640 SIGNAL wEn_odd_xhdl9 : std_logic;
641 SIGNAL preSwCross_xhdl10 : std_logic;
642 SIGNAL twid_wEn_xhdl11 : std_logic;
643 SIGNAL inBuf_wEn_xhdl12 : std_logic;
644 SIGNAL outBuf_wEn_xhdl13 : std_logic;
645 SIGNAL smPong_xhdl14 : std_logic;
646 SIGNAL ldValid_xhdl15 : std_logic;
647 SIGNAL inBuf_rdValid_int : std_logic;
648 SIGNAL wLastStage_xhdl17 : std_logic;
649 SIGNAL smStartFFTrd_int : std_logic;
650 SIGNAL smStartLoad_int : std_logic;
651 SIGNAL ifoLoad_xhdl20 : std_logic;
652 SIGNAL ifoY_valid_xhdl21 : std_logic;
653 SIGNAL ifoY_rdy_xhdl22 : std_logic;
654 SIGNAL smStartLoad_w : std_logic;
655
656 BEGIN
657 ldA <= ldA_xhdl1;
658 rA <= rA_xhdl2;
659 wA <= wA_xhdl3;
660 tA <= tA_xhdl4;
661 twid_wA <= twid_wA_xhdl5;
662 outBuf_wA <= outBuf_wA_xhdl6;
663 outBuf_rA <= outBuf_rA_xhdl7;
664 wEn_even <= wEn_even_xhdl8;
665 wEn_odd <= wEn_odd_xhdl9;
666 preSwCross <= preSwCross_xhdl10;
667 twid_wEn <= twid_wEn_xhdl11;
668 inBuf_wEn <= inBuf_wEn_xhdl12;
669 outBuf_wEn <= outBuf_wEn_xhdl13;
670 smPong <= smPong_xhdl14;
671 ldValid <= ldValid_xhdl15;
672 inBuf_rdValid <= inBuf_rdValid_int;
673 wLastStage <= wLastStage_xhdl17;
674 smStartFFTrd <= smStartFFTrd_int;
675 smStartLoad <= smStartLoad_int;
676 ifoLoad <= ifoLoad_xhdl20;
677 ifoY_valid <= ifoY_valid_xhdl21;
678 ifoY_rdy <= ifoY_rdy_xhdl22;
679 nGrst <= ifiNreset AND (NOT initRst) ;
680 trueRst_w <= rstAfterInit OR ifiStart ;
681 -- Top SM outputs
682 smStartFFTrd_int <= smBuf_full AND smFft_rdy ;
683 -- Start loading on FFT start or initially on trueRst.
684 smStartLoad_w <= trueRst_w OR smStartFFTrd_int ;
685 -- To prevent fake ifoY_rdy and ifoY_valid do not let rdFFTTimer run
686 -- outside smFft_runs
687 rdTimer_cntEn <= clkEn AND (smFft_runs OR smStartFFTrd_int);
688
689 -- FFT read inBuf timer
690 rdFFTtimer_0 : rdFFTtimer
691 GENERIC MAP (LOGPTS => LOGPTS,
692 LOGLOGPTS => LOGLOGPTS,
693 HALFPTS => HALFPTS,
694 inBuf_RWDLY => inBuf_RWDLY )
695 PORT MAP (
696 clk => clk,
697 cntEn => rdTimer_cntEn,
698 nGrst => nGrst,
699 rst => trueRst,
700 startFFT => smStartFFTrd_int,
701 timer => rTimer_w,
702 timerTC => rTimerTC_w,
703 stage => rStage_w,
704 lastStage => rLastStage_w,
705 fft_runs => smFft_runs,
706 rdValid => inBuf_rdValid_int);
707
708 -- FFT write inBuf timer
709 sync_rAwA <= To_logic(rTimer_w = CONV_STD_LOGIC_VECTOR(inBuf_RWDLY, LOGPTS-1)) ;
710 xhdl_27 <= sync_rAwA OR smStartFFTrd_int;
711 wrFFTtimer_0 : wrFFTtimer
712 GENERIC MAP (LOGPTS => LOGPTS,
713 LOGLOGPTS => LOGLOGPTS,
714 HALFPTS => HALFPTS )
715 PORT MAP (
716 clk => clk,
717 rst => trueRst,
718 nGrst => nGrst,
719 rstStage => smStartFFTrd_int,
720 rstTime => xhdl_27,
721 cntEn => clkEn,
722 timer => wTimer_w,
723 timerTC => wTimerTC_w,
724 stage => wStage_w,
725 lastStage => wLastStage_xhdl17);
726
727 --inData strobe
728 --out; inBuf is ready for new data (PTS new samples)
729 --out; tells topSM the buffer is fully loaded and ready for FFTing
730 inBuf_ldA_0 : inBuf_ldA
731 GENERIC MAP (PTS => PTS,
732 LOGPTS => LOGPTS )
733 PORT MAP (
734 clk => clk,
735 clkEn => clkEn,
736 nGrst => nGrst,
737 startLoad => smStartLoad_int,
738 ifi_dataRdy => ifiD_valid,
739 ifo_loadOn => ifoLoad_xhdl20,
740 load_done => load_done_w,
741 ldA => ldA_xhdl1,
742 wEn_even => wEn_even_xhdl8,
743 wEn_odd => wEn_odd_xhdl9,
744 ldValid => ldValid_xhdl15);
745
746 port_xhdl37 <= rTimer_w(LOGPTS-2 DOWNTO 0);
747 inBuf_rA_0 : inBuf_fftA
748 GENERIC MAP (LOGPTS => LOGPTS,
749 LOGLOGPTS => LOGLOGPTS )
750 PORT MAP (
751 clk => clk,
752 clkEn => clkEn,
753 timer => port_xhdl37,
754 stage => rStage_w,
755 timerTC => rTimerTC_w,
756 lastStage => rLastStage_w,
757 fftDone => fftRd_done_w,
758 bflyA => rA_xhdl2,
759 swCross => preSwCross_xhdl10); -- out
760
761 twid_rA_0 : twid_rA
762 GENERIC MAP (LOGPTS => LOGPTS,
763 LOGLOGPTS => LOGLOGPTS )
764 PORT MAP (
765 clk => clk,
766 timer => timerT1,
767 stage => stageT2,
768 tA => tA_xhdl4);
769
770 -- Twiddle LUT initialization
771 twid_wA_0 : twid_wAmod
772 GENERIC MAP (LOGPTS => LOGPTS )
773 PORT MAP (
774 clk => clk,
775 ifiNreset => ifiNreset,
776 twid_wA => twid_wA_xhdl5,
777 twid_wEn => twid_wEn_xhdl11,
778 twidInit => initRst,
779 rstAfterInit => rstAfterInit);
780
781 -- wA generator. On the last stage the fftRd_done comes before the last
782 -- FFT results get written back to the inBuf, but it is not necessary since
783 -- the results get written into the output buffer.
784 inBuf_wA_0 : inBuf_fftA
785 GENERIC MAP (LOGPTS => LOGPTS,
786 LOGLOGPTS => LOGLOGPTS )
787 PORT MAP (
788 clk => clk,
789 clkEn => clkEn,
790 timer => wTimer_w,
791 stage => wStage_w,
792 timerTC => wTimerTC_w,
793 lastStage => wLastStage_xhdl17,
794 fftDone => open,
795 bflyA => wA_xhdl3,
796 swCross => open);
797
798 outBufA_0 : outBufA
799 GENERIC MAP (PTS => PTS,
800 LOGPTS => LOGPTS )
801 PORT MAP (
802 clk => clk,
803 clkEn => clkEn,
804 nGrst => nGrst,
805 rst => trueRst,
806 timer => wTimer_w,
807 outBuf_wEn => outBuf_wEn_xhdl13,
808 rdCtl => ifiRead_y,
809 wA => outBuf_wA_xhdl6,
810 rA => outBuf_rA_xhdl7,
811 outBuf_rEn => ifoY_rdy_xhdl22,
812 rdValid => ifoY_valid_xhdl21);
813
814 PROCESS (clk)
815 BEGIN
816 IF (clk'EVENT AND clk = '1') THEN -- pipes
817 trueRst <= trueRst_w AFTER timescale;
818 smStartLoad_int <= smStartLoad_w AFTER timescale;
819 timerT1 <= rTimer_w(LOGPTS-2 DOWNTO 0) AFTER timescale;
820 stageT1 <= rStage_w AFTER timescale;
821 stageT2 <= stageT1 AFTER timescale;
822 inBuf_wEn_xhdl12 <= preInBuf_wEn AFTER timescale;
823 outBuf_wEn_xhdl13 <= preOutBuf_wEn AFTER timescale;
824 END IF;
825 END PROCESS;
826
827 PROCESS (clk, nGrst)
828 BEGIN
829 IF (NOT nGrst = '1') THEN -- reset topSM
830 smBuf_full <= '0';
831 smFft_rdy <= '0';
832 smFft_runs <= '0';
833 smPong_xhdl14 <= '1';
834 preInBuf_wEn <= '0';
835 preOutBuf_wEn <= '0';
836 --nGrst
837 ELSIF (clk'EVENT AND clk = '1') THEN
838 --mark A
839 IF (trueRst = '1') THEN
840 -- reset topSM
841 smBuf_full <= '0' AFTER timescale;
842 smFft_rdy <= '1' AFTER timescale;
843 smFft_runs <= '0' AFTER timescale;
844 smPong_xhdl14 <= '1' AFTER timescale;
845 preInBuf_wEn <= '0' AFTER timescale;
846 preOutBuf_wEn <= '0' AFTER timescale;
847 ELSE
848 -- mark B
849 IF (load_done_w = '1') THEN
850 smBuf_full <= '1' AFTER timescale;
851 END IF;
852 IF (fftRd_done_w = '1') THEN
853 smFft_rdy <= '1' AFTER timescale;
854 smFft_runs <= '0' AFTER timescale;
855 END IF;
856 IF (smStartFFTrd_int = '1') THEN
857 smBuf_full <= '0' AFTER timescale;
858 smFft_rdy <= '0' AFTER timescale;
859 smFft_runs <= '1' AFTER timescale;
860 smPong_xhdl14 <= NOT smPong_xhdl14 AFTER timescale;
861 END IF;
862 IF (sync_rAwA = '1') THEN
863 IF (rLastStage_w = '1') THEN
864 preOutBuf_wEn <= '1' AFTER timescale;
865 ELSE
866 IF (smFft_runs = '1') THEN
867 preInBuf_wEn <= '1' AFTER timescale;
868 END IF;
869 END IF;
870 END IF;
871 IF (wTimerTC_w = '1') THEN
872 preInBuf_wEn <= '0' AFTER timescale;
873 preOutBuf_wEn <= '0' AFTER timescale;
874 END IF;
875 END IF;
876 -- mark B
877 END IF;
878 -- mark A
879 END PROCESS;
880 END ARCHITECTURE translated;
881 ------------------------------------------------------------------------------
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- Package: fft_components.vhd
10 -- Description: CoreFFT
11 -- Core package
12 -- Rev: 0.1 8/31/2005 12:54PM VD : Pre Production
13 --
14 --
15 --------------------------------------------------------------------------------
16 library IEEE;
17 use IEEE.STD_LOGIC_1164.all;
18 USE IEEE.numeric_std.all;
19 USE std.textio.all;
20 USE IEEE.STD_LOGIC_TEXTIO.all;
21
22 package FFT_COMPONENTS is
23 CONSTANT gPTS : integer:=256; --Number of FFT points
24 CONSTANT gLOGPTS : integer:=8; --Log2(PTS)
25 CONSTANT gLOGLOGPTS : integer:=3; --Stage counter width
26 -------------------------------------------------
27 CONSTANT gWSIZE : integer:=16; -- FFT bit resolution; length of a re or im sample
28 CONSTANT gTWIDTH : integer:=16; -- Twiddle, sin or cos bit resolution
29 CONSTANT gHALFPTS : integer:=gPTS/2; -- Num of FFT points (PTS) divided by 2
30 CONSTANT gDWIDTH : integer:=2*gWSIZE; -- width of a complex input word,
31 CONSTANT gTDWIDTH : integer:=2*gTWIDTH; -- width of a complex twiddle factor
32 CONSTANT gRND_MODE : integer:=1; -- enable product rounding
33 CONSTANT gSCALE_MODE : integer:=1; -- scale mode
34 CONSTANT gInBuf_RWDLY : integer:=12;
35
36 function to_logic ( x : integer) return std_logic;
37 function to_logic ( x : boolean) return std_logic;
38 FUNCTION to_integer( sig : std_logic_vector) return integer;
39 function to_integer( x : boolean) return integer;
40 function maskbar (barn, bar_enable,dma_reg_bar,dma_reg_loc : integer) return integer;
41 function anyfifo (bar0, bar1, bar2, bar3, bar4, bar5 : integer) return integer;
42 FUNCTION reverse (x : std_logic_vector) RETURN bit_vector;
43 FUNCTION reverseStd(x : std_logic_vector) RETURN std_logic_vector;
44
45 COMPONENT counter
46 GENERIC (
47 WIDTH : integer := 7;
48 TERMCOUNT : integer := 127 );
49 PORT (
50 clk, nGrst, rst, cntEn : IN std_logic;
51 tc : OUT std_logic;
52 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0));
53 END COMPONENT;
54
55 COMPONENT bcounter
56 GENERIC (
57 WIDTH : integer := 7);
58 PORT (
59 clk, nGrst, rst, cntEn : IN std_logic;
60 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
61 END COMPONENT;
62
63 COMPONENT edgeDetect
64 GENERIC (
65 INPIPE :integer := 0; --if (INPIPE==1) insert input pipeline reg
66 FEDGE :integer := 0);--If FEDGE==1 detect falling edge, else-rising edge
67 PORT (
68 clk, clkEn, edgeIn : IN std_logic;
69 edgeOut : OUT std_logic);
70 END COMPONENT;
71
72 end FFT_COMPONENTS;
73
74 package body FFT_COMPONENTS is
75
76 function to_logic ( x : integer) return std_logic is
77 variable y : std_logic;
78 begin
79 if x = 0 then
80 y := '0';
81 else
82 y := '1';
83 end if;
84 return y;
85 end to_logic;
86
87 function to_logic( x : boolean) return std_logic is
88 variable y : std_logic;
89 begin
90 if x then
91 y := '1';
92 else
93 y := '0';
94 end if;
95 return(y);
96 end to_logic;
97
98 -- added 081805
99 function to_integer(sig : std_logic_vector) return integer is
100 variable num : integer := 0; -- descending sig as integer
101 begin
102 for i in sig'range loop
103 if sig(i)='1' then
104 num := num*2+1;
105 else -- use anything other than '1' as '0'
106 num := num*2;
107 end if;
108 end loop; -- i
109 return num;
110 end function to_integer;
111
112 function to_integer( x : boolean) return integer is
113 variable y : integer;
114 begin
115 if x then
116 y := 1;
117 else
118 y := 0;
119 end if;
120 return(y);
121 end to_integer;
122
123 function maskbar (barn, bar_enable,dma_reg_bar,dma_reg_loc : integer) return integer is
124 begin
125 if ( dma_reg_loc>= 2 and barn=dma_reg_bar) then
126 return(0);
127 else
128 return(bar_enable);
129 end if;
130 end maskbar;
131
132
133 function anyfifo ( bar0, bar1, bar2, bar3, bar4, bar5 : integer) return integer is
134 begin
135 if ( bar0=2 or bar1=2 or bar2=2 or bar3=2 or bar4=2 or bar5=2) then
136 return(1);
137 else
138 return(0);
139 end if;
140 end anyfifo;
141
142 FUNCTION reverse (x :IN std_logic_vector)
143 RETURN bit_vector IS
144 VARIABLE i : integer;
145 VARIABLE reverse : bit_vector(x'HIGH DOWNTO x'LOW);
146 BEGIN
147 FOR i IN x'range LOOP
148 reverse(i) := To_bit( x(x'HIGH - i));
149 END LOOP;
150 RETURN(reverse);
151 END FUNCTION reverse;
152
153 FUNCTION reverseStd (x :IN std_logic_vector)
154 RETURN std_logic_vector IS
155 VARIABLE i : integer;
156 VARIABLE reverse : std_logic_vector(x'HIGH DOWNTO x'LOW);
157 BEGIN
158 FOR i IN x'range LOOP
159 reverse(i) := x(x'HIGH - i);
160 END LOOP;
161 RETURN(reverse);
162 END FUNCTION reverseStd;
163
164 end FFT_COMPONENTS;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29 use work.FFT_Config.all;
30 USE work.fft_components.all;
31
32 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
33
34 package lpp_fft is
35
36 component APB_FFT is
37 generic (
38 pindex : integer := 0;
39 paddr : integer := 0;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
42 abits : integer := 8);
43 port (
44 clk : in std_logic;
45 rst : in std_logic;
46 apbi : in apb_slv_in_type;
47 apbo : out apb_slv_out_type
48 );
49 end component;
50
51
52 component Top_FFT is
53 port(
54 clk,raz : in std_logic;
55 data : in std_logic_vector(15 downto 0);
56 y_valid : out std_logic;
57 d_valid : out std_logic;
58 y_re : out std_logic_vector(15 downto 0);
59 y_im : out std_logic_vector(15 downto 0)
60 );
61 end component;
62
63
64 component Driver_IN is
65 port(
66 clk,raz : in std_logic;
67 load : in std_logic;
68 data : in std_logic_vector(15 downto 0);
69 start : out std_logic;
70 read_y : out std_logic;
71 d_valid : out std_logic;
72 flag_RE : out std_logic;
73 d_re : out std_logic_vector(15 downto 0);
74 d_im : out std_logic_vector(15 downto 0)
75 );
76 end component;
77
78
79 component CoreFFT IS
80 GENERIC (
81 LOGPTS : integer := gLOGPTS;
82 LOGLOGPTS : integer := gLOGLOGPTS;
83 WSIZE : integer := gWSIZE;
84 TWIDTH : integer := gTWIDTH;
85 DWIDTH : integer := gDWIDTH;
86 TDWIDTH : integer := gTDWIDTH;
87 RND_MODE : integer := gRND_MODE;
88 SCALE_MODE : integer := gSCALE_MODE;
89 PTS : integer := gPTS;
90 HALFPTS : integer := gHALFPTS;
91 inBuf_RWDLY : integer := gInBuf_RWDLY );
92 PORT (
93 clk,ifiStart,ifiNreset : IN std_logic;
94 ifiD_valid, ifiRead_y : IN std_logic;
95 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
96 ifoLoad, ifoPong : OUT std_logic;
97 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
98 ifoY_valid, ifoY_rdy : OUT std_logic);
99 END component;
100
101
102 component actar is
103 port( DataA : in std_logic_vector(15 downto 0); DataB : in
104 std_logic_vector(15 downto 0); Mult : out
105 std_logic_vector(31 downto 0);Clock : in std_logic) ;
106 end component;
107
108 component actram is
109 port( DI : in std_logic_vector(31 downto 0); DO : out
110 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
111 WADDR : in std_logic_vector(6 downto 0); RADDR : in
112 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
113 std_logic) ;
114 end component;
115
116 component switch IS
117 GENERIC ( DWIDTH : integer := 32 );
118 PORT (
119 clk, sel, validIn : IN std_logic;
120 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
121 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
122 validOut : OUT std_logic);
123 END component;
124
125 component twid_rA IS
126 GENERIC (LOGPTS : integer := 8;
127 LOGLOGPTS : integer := 3 );
128 PORT (clk : IN std_logic;
129 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
130 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
131 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
132 END component;
133
134 component counter IS
135 GENERIC (
136 WIDTH : integer := 7;
137 TERMCOUNT : integer := 127 );
138 PORT (
139 clk, nGrst, rst, cntEn : IN std_logic;
140 tc : OUT std_logic;
141 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
142 END component;
143
144
145 component twiddle IS
146 PORT (
147 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
148 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
149 END component;
150
151
152 --===========================================================|
153 --======================= Exemple ===========================|
154 --===========================================================|
155
156 component APB_FFTexp is
157 generic (
158 pindex : integer := 0;
159 paddr : integer := 0;
160 pmask : integer := 16#fff#;
161 pirq : integer := 0;
162 abits : integer := 8);
163 port (
164 clk : in std_logic;
165 rst : in std_logic;
166 apbi : in apb_slv_in_type;
167 apbo : out apb_slv_out_type
168 );
169 end component;
170
171
172 component topFFTbis is
173 port(
174 clk,raz : in std_logic;
175 y_valid : out std_logic;
176 y_rdy : out std_logic;
177 y_re : out std_logic_vector(15 downto 0);
178 y_im : out std_logic_vector(15 downto 0)
179 );
180 end component;
181
182
183 component Sinus_In is
184 port(
185 clk,raz : in std_logic;
186 load : in std_logic;
187 pong : in std_logic;
188 start : out std_logic;
189 read_y : out std_logic;
190 d_valid : out std_logic;
191 d_re : out std_logic_vector(15 downto 0);
192 d_im : out std_logic_vector(15 downto 0)
193 );
194 end component;
195
196
197
198 end; No newline at end of file
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: primitives.vhd
10 -- Description: CoreFFT
11 -- FFT primitives module
12 -- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production
13 --
14 --
15 --------------------------------------------------------------------------------
16 -- counts up to TERMCOUNT, then jumps to 0.
17 -- Generates tc signal on count==TERMCOUNT-1
18 LIBRARY IEEE;
19 USE IEEE.std_logic_1164.all;
20 USE IEEE.numeric_std.all;
21 USE work.fft_components.all;
22
23 ENTITY counter IS
24 GENERIC (
25 WIDTH : integer := 7;
26 TERMCOUNT : integer := 127 );
27 PORT (
28 clk, nGrst, rst, cntEn : IN std_logic;
29 tc : OUT std_logic;
30 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
31 END ENTITY counter;
32
33 ARCHITECTURE translated OF counter IS
34 SIGNAL tc_out : std_logic;
35 SIGNAL Q_out : unsigned(WIDTH-1 DOWNTO 0);
36
37 BEGIN
38 tc <= tc_out;
39 Q <= std_logic_vector(Q_out);
40 PROCESS (clk, nGrst)
41 BEGIN
42 IF (nGrst = '0') THEN
43 Q_out <= (OTHERS => '0');
44 tc_out <= '0';
45 ELSIF (clk'EVENT AND clk = '1') THEN -- nGrst!=0
46 IF (rst = '1') THEN
47 Q_out <= (OTHERS => '0');
48 tc_out <= '0';
49 ELSE
50 IF (cntEn = '1') THEN -- start cntEn
51 tc_out <= to_logic( Q_out = to_unsigned((TERMCOUNT-1),WIDTH));
52 IF (Q_out = to_unsigned(TERMCOUNT, WIDTH)) THEN
53 Q_out <= (OTHERS => '0');
54 ELSE
55 Q_out <= unsigned(Q_out) + to_unsigned(1, WIDTH);
56 END IF;
57 END IF; -- end cntEn
58 END IF; -- end rst
59 END IF; -- end nGrst
60 END PROCESS;
61 END ARCHITECTURE translated;
62
63 --------------------------------------------------------------------------
64 -- binary counter with no feedback. Counts up to 2^WIDTH - 1
65 LIBRARY IEEE;
66 USE IEEE.std_logic_1164.all;
67 USE IEEE.numeric_std.all;
68
69 ENTITY bcounter IS
70 GENERIC (WIDTH : integer:=7 );
71 PORT (clk, nGrst, rst, cntEn : IN std_logic;
72 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0));
73 END ENTITY bcounter;
74
75 ARCHITECTURE translated OF bcounter IS
76 SIGNAL Q_out : unsigned(WIDTH-1 DOWNTO 0);
77
78 BEGIN
79 Q <= std_logic_vector(Q_out);
80 PROCESS (clk, nGrst)
81 BEGIN
82 IF (nGrst = '0') THEN
83 Q_out <= (OTHERS => '0');
84 ELSIF (clk'EVENT AND clk = '1') THEN
85 IF (cntEn = '1') THEN
86 IF (rst = '1') THEN
87 Q_out <= (OTHERS => '0');
88 ELSE
89 Q_out <= unsigned(Q_out) + to_unsigned(1, WIDTH);
90 END IF;
91 END IF;
92 END IF;
93 END PROCESS;
94 END ARCHITECTURE translated;
95 --------------------------------------------------------------------------
96 -- rising-falling edge detector
97 LIBRARY IEEE;
98 USE IEEE.std_logic_1164.all;
99
100 ENTITY edgeDetect IS
101 GENERIC (
102 INPIPE :integer := 0; --if (INPIPE==1) insert input pipeline reg
103 FEDGE :integer := 0);--If FEDGE==1 detect falling edge, else-rising edge
104 PORT (
105 clk, clkEn, edgeIn : IN std_logic;
106 edgeOut : OUT std_logic);
107 END ENTITY edgeDetect;
108
109 ARCHITECTURE translated OF edgeDetect IS
110 SIGNAL in_pipe, in_t1 : std_logic; -- regs
111 SIGNAL temp_input : std_logic;
112 SIGNAL in_w : std_logic;
113 SIGNAL temp_output : std_logic;
114 SIGNAL out_w : std_logic;
115 SIGNAL output_reg : std_logic;
116
117 BEGIN
118 edgeOut <= output_reg;
119 temp_input <= (in_pipe) WHEN INPIPE /= 0 ELSE edgeIn;
120 in_w <= temp_input ;
121 temp_output<=
122 ((NOT in_w) AND in_t1) WHEN FEDGE /= 0 ELSE (in_w AND (NOT in_t1));
123 out_w <= temp_output ;
124
125 PROCESS (clk)
126 BEGIN
127 IF (clk'EVENT AND clk = '1') THEN
128 in_pipe <= edgeIn;
129 in_t1 <= in_w;
130 output_reg <= out_w;
131 END IF;
132 END PROCESS;
133 END ARCHITECTURE translated;
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1 -- topFFTbis.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5 USE work.fft_components.all;
6
7 entity topFFTbis is
8 port(
9 clk,raz : in std_logic;
10 y_valid : out std_logic;
11 y_rdy : out std_logic;
12 y_re : out std_logic_vector(15 downto 0);
13 y_im : out std_logic_vector(15 downto 0)
14 );
15 end topFFTbis;
16
17
18 architecture ar_topFFTbis of topFFTbis is
19
20 signal load : std_logic;
21 signal pong : std_logic;
22 signal start : std_logic;
23 signal read_y : std_logic;
24 signal d_valid : std_logic;
25 signal d_re : std_logic_vector(15 downto 0);
26 signal d_im : std_logic_vector(15 downto 0);
27
28 begin
29
30 FFT : entity work.CoreFFT
31 GENERIC map(
32 LOGPTS => gLOGPTS,
33 LOGLOGPTS => gLOGLOGPTS,
34 WSIZE => gWSIZE,
35 TWIDTH => gTWIDTH,
36 DWIDTH => gDWIDTH,
37 TDWIDTH => gTDWIDTH,
38 RND_MODE => gRND_MODE,
39 SCALE_MODE => gSCALE_MODE,
40 PTS => gPTS,
41 HALFPTS => gHALFPTS,
42 inBuf_RWDLY => gInBuf_RWDLY)
43 port map(clk,start,raz,d_valid,read_y,d_im,d_re,load,pong,y_im,y_re,y_valid,y_rdy);
44
45
46 Input : entity work.Sinus_In
47 port map(clk,raz,load,pong,start,read_y,d_valid,d_re,d_im);
48
49 end ar_topFFTbis; No newline at end of file
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@@ -0,0 +1,171
1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: twiddle.v
10 --
11 -- Description: CoreFFT
12 -- Twiddle factor table
13 --
14 -- Rev: 0.1 5/10/2005 8:36AM VD : Pre Production
15 -- History: 5/10/2005 8:36AM - created
16 --
17 --------------------------------------------------------------------------------
18 LIBRARY IEEE;
19 USE IEEE.std_logic_1164.all;
20 USE work.fft_components.all;
21
22 ENTITY twiddle IS
23 PORT (
24 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
25 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
26 END ENTITY twiddle;
27
28 ARCHITECTURE translated OF twiddle IS
29 SIGNAL T_int : std_logic_vector(gTDWIDTH-1 DOWNTO 0);
30
31 BEGIN
32 T <= T_int;
33
34 PROCESS (A)
35 VARIABLE T_int1 : std_logic_vector(gTDWIDTH-1 DOWNTO 0);
36 BEGIN
37 CASE A IS -- synopsys parallel_case
38 WHEN "0000000" => T_int1 := "00000000000000000111111111111111"; -- X0000 X7fff
39 WHEN "0000001" => T_int1 := "00000011001001000111111111110101"; -- X0324 X7ff5
40 WHEN "0000010" => T_int1 := "00000110010010000111111111011000"; -- X0648 X7fd8
41 WHEN "0000011" => T_int1 := "00001001011010100111111110100110"; -- X096a X7fa6
42 WHEN "0000100" => T_int1 := "00001100100011000111111101100001"; -- X0c8c X7f61
43 WHEN "0000101" => T_int1 := "00001111101010110111111100001001"; -- X0fab X7f09
44 WHEN "0000110" => T_int1 := "00010010110010000111111010011100"; -- X12c8 X7e9c
45 WHEN "0000111" => T_int1 := "00010101111000100111111000011101"; -- X15e2 X7e1d
46 WHEN "0001000" => T_int1 := "00011000111110010111110110001001"; -- X18f9 X7d89
47 WHEN "0001001" => T_int1 := "00011100000010110111110011100011"; -- X1c0b X7ce3
48 WHEN "0001010" => T_int1 := "00011111000110100111110000101001"; -- X1f1a X7c29
49 WHEN "0001011" => T_int1 := "00100010001000110111101101011100"; -- X2223 X7b5c
50 WHEN "0001100" => T_int1 := "00100101001010000111101001111100"; -- X2528 X7a7c
51 WHEN "0001101" => T_int1 := "00101000001001100111100110001001"; -- X2826 X7989
52 WHEN "0001110" => T_int1 := "00101011000111110111100010000100"; -- X2b1f X7884
53 WHEN "0001111" => T_int1 := "00101110000100010111011101101011"; -- X2e11 X776b
54 WHEN "0010000" => T_int1 := "00110000111110110111011001000001"; -- X30fb X7641
55 WHEN "0010001" => T_int1 := "00110011110111110111010100000100"; -- X33df X7504
56 WHEN "0010010" => T_int1 := "00110110101110100111001110110101"; -- X36ba X73b5
57 WHEN "0010011" => T_int1 := "00111001100011000111001001010100"; -- X398c X7254
58 WHEN "0010100" => T_int1 := "00111100010101100111000011100010"; -- X3c56 X70e2
59 WHEN "0010101" => T_int1 := "00111111000101110110111101011110"; -- X3f17 X6f5e
60 WHEN "0010110" => T_int1 := "01000001110011100110110111001001"; -- X41ce X6dc9
61 WHEN "0010111" => T_int1 := "01000100011110100110110000100011"; -- X447a X6c23
62 WHEN "0011000" => T_int1 := "01000111000111000110101001101101"; -- X471c X6a6d
63 WHEN "0011001" => T_int1 := "01001001101101000110100010100110"; -- X49b4 X68a6
64 WHEN "0011010" => T_int1 := "01001100001111110110011011001111"; -- X4c3f X66cf
65 WHEN "0011011" => T_int1 := "01001110101111110110010011101000"; -- X4ebf X64e8
66 WHEN "0011100" => T_int1 := "01010001001100110110001011110001"; -- X5133 X62f1
67 WHEN "0011101" => T_int1 := "01010011100110110110000011101011"; -- X539b X60eb
68 WHEN "0011110" => T_int1 := "01010101111101010101111011010111"; -- X55f5 X5ed7
69 WHEN "0011111" => T_int1 := "01011000010000100101110010110011"; -- X5842 X5cb3
70 WHEN "0100000" => T_int1 := "01011010100000100101101010000010"; -- X5a82 X5a82
71 WHEN "0100001" => T_int1 := "01011100101100110101100001000010"; -- X5cb3 X5842
72 WHEN "0100010" => T_int1 := "01011110110101110101010111110101"; -- X5ed7 X55f5
73 WHEN "0100011" => T_int1 := "01100000111010110101001110011011"; -- X60eb X539b
74 WHEN "0100100" => T_int1 := "01100010111100010101000100110011"; -- X62f1 X5133
75 WHEN "0100101" => T_int1 := "01100100111010000100111010111111"; -- X64e8 X4ebf
76 WHEN "0100110" => T_int1 := "01100110110011110100110000111111"; -- X66cf X4c3f
77 WHEN "0100111" => T_int1 := "01101000101001100100100110110100"; -- X68a6 X49b4
78 WHEN "0101000" => T_int1 := "01101010011011010100011100011100"; -- X6a6d X471c
79 WHEN "0101001" => T_int1 := "01101100001000110100010001111010"; -- X6c23 X447a
80 WHEN "0101010" => T_int1 := "01101101110010010100000111001110"; -- X6dc9 X41ce
81 WHEN "0101011" => T_int1 := "01101111010111100011111100010111"; -- X6f5e X3f17
82 WHEN "0101100" => T_int1 := "01110000111000100011110001010110"; -- X70e2 X3c56
83 WHEN "0101101" => T_int1 := "01110010010101000011100110001100"; -- X7254 X398c
84 WHEN "0101110" => T_int1 := "01110011101101010011011010111010"; -- X73b5 X36ba
85 WHEN "0101111" => T_int1 := "01110101000001000011001111011111"; -- X7504 X33df
86 WHEN "0110000" => T_int1 := "01110110010000010011000011111011"; -- X7641 X30fb
87 WHEN "0110001" => T_int1 := "01110111011010110010111000010001"; -- X776b X2e11
88 WHEN "0110010" => T_int1 := "01111000100001000010101100011111"; -- X7884 X2b1f
89 WHEN "0110011" => T_int1 := "01111001100010010010100000100110"; -- X7989 X2826
90 WHEN "0110100" => T_int1 := "01111010011111000010010100101000"; -- X7a7c X2528
91 WHEN "0110101" => T_int1 := "01111011010111000010001000100011"; -- X7b5c X2223
92 WHEN "0110110" => T_int1 := "01111100001010010001111100011010"; -- X7c29 X1f1a
93 WHEN "0110111" => T_int1 := "01111100111000110001110000001011"; -- X7ce3 X1c0b
94 WHEN "0111000" => T_int1 := "01111101100010010001100011111001"; -- X7d89 X18f9
95 WHEN "0111001" => T_int1 := "01111110000111010001010111100010"; -- X7e1d X15e2
96 WHEN "0111010" => T_int1 := "01111110100111000001001011001000"; -- X7e9c X12c8
97 WHEN "0111011" => T_int1 := "01111111000010010000111110101011"; -- X7f09 X0fab
98 WHEN "0111100" => T_int1 := "01111111011000010000110010001100"; -- X7f61 X0c8c
99 WHEN "0111101" => T_int1 := "01111111101001100000100101101010"; -- X7fa6 X096a
100 WHEN "0111110" => T_int1 := "01111111110110000000011001001000"; -- X7fd8 X0648
101 WHEN "0111111" => T_int1 := "01111111111101010000001100100100"; -- X7ff5 X0324
102 WHEN "1000000" => T_int1 := "01111111111111110000000000000000"; -- X7fff X0000
103 WHEN "1000001" => T_int1 := "01111111111101011111110011011100"; -- X7ff5 Xfcdc
104 WHEN "1000010" => T_int1 := "01111111110110001111100110111000"; -- X7fd8 Xf9b8
105 WHEN "1000011" => T_int1 := "01111111101001101111011010010110"; -- X7fa6 Xf696
106 WHEN "1000100" => T_int1 := "01111111011000011111001101110100"; -- X7f61 Xf374
107 WHEN "1000101" => T_int1 := "01111111000010011111000001010101"; -- X7f09 Xf055
108 WHEN "1000110" => T_int1 := "01111110100111001110110100111000"; -- X7e9c Xed38
109 WHEN "1000111" => T_int1 := "01111110000111011110101000011110"; -- X7e1d Xea1e
110 WHEN "1001000" => T_int1 := "01111101100010011110011100000111"; -- X7d89 Xe707
111 WHEN "1001001" => T_int1 := "01111100111000111110001111110101"; -- X7ce3 Xe3f5
112 WHEN "1001010" => T_int1 := "01111100001010011110000011100110"; -- X7c29 Xe0e6
113 WHEN "1001011" => T_int1 := "01111011010111001101110111011101"; -- X7b5c Xdddd
114 WHEN "1001100" => T_int1 := "01111010011111001101101011011000"; -- X7a7c Xdad8
115 WHEN "1001101" => T_int1 := "01111001100010011101011111011010"; -- X7989 Xd7da
116 WHEN "1001110" => T_int1 := "01111000100001001101010011100001"; -- X7884 Xd4e1
117 WHEN "1001111" => T_int1 := "01110111011010111101000111101111"; -- X776b Xd1ef
118 WHEN "1010000" => T_int1 := "01110110010000011100111100000101"; -- X7641 Xcf05
119 WHEN "1010001" => T_int1 := "01110101000001001100110000100001"; -- X7504 Xcc21
120 WHEN "1010010" => T_int1 := "01110011101101011100100101000110"; -- X73b5 Xc946
121 WHEN "1010011" => T_int1 := "01110010010101001100011001110100"; -- X7254 Xc674
122 WHEN "1010100" => T_int1 := "01110000111000101100001110101010"; -- X70e2 Xc3aa
123 WHEN "1010101" => T_int1 := "01101111010111101100000011101001"; -- X6f5e Xc0e9
124 WHEN "1010110" => T_int1 := "01101101110010011011111000110010"; -- X6dc9 Xbe32
125 WHEN "1010111" => T_int1 := "01101100001000111011101110000110"; -- X6c23 Xbb86
126 WHEN "1011000" => T_int1 := "01101010011011011011100011100100"; -- X6a6d Xb8e4
127 WHEN "1011001" => T_int1 := "01101000101001101011011001001100"; -- X68a6 Xb64c
128 WHEN "1011010" => T_int1 := "01100110110011111011001111000001"; -- X66cf Xb3c1
129 WHEN "1011011" => T_int1 := "01100100111010001011000101000001"; -- X64e8 Xb141
130 WHEN "1011100" => T_int1 := "01100010111100011010111011001101"; -- X62f1 Xaecd
131 WHEN "1011101" => T_int1 := "01100000111010111010110001100101"; -- X60eb Xac65
132 WHEN "1011110" => T_int1 := "01011110110101111010101000001011"; -- X5ed7 Xaa0b
133 WHEN "1011111" => T_int1 := "01011100101100111010011110111110"; -- X5cb3 Xa7be
134 WHEN "1100000" => T_int1 := "01011010100000101010010101111110"; -- X5a82 Xa57e
135 WHEN "1100001" => T_int1 := "01011000010000101010001101001101"; -- X5842 Xa34d
136 WHEN "1100010" => T_int1 := "01010101111101011010000100101001"; -- X55f5 Xa129
137 WHEN "1100011" => T_int1 := "01010011100110111001111100010101"; -- X539b X9f15
138 WHEN "1100100" => T_int1 := "01010001001100111001110100001111"; -- X5133 X9d0f
139 WHEN "1100101" => T_int1 := "01001110101111111001101100011000"; -- X4ebf X9b18
140 WHEN "1100110" => T_int1 := "01001100001111111001100100110001"; -- X4c3f X9931
141 WHEN "1100111" => T_int1 := "01001001101101001001011101011010"; -- X49b4 X975a
142 WHEN "1101000" => T_int1 := "01000111000111001001010110010011"; -- X471c X9593
143 WHEN "1101001" => T_int1 := "01000100011110101001001111011101"; -- X447a X93dd
144 WHEN "1101010" => T_int1 := "01000001110011101001001000110111"; -- X41ce X9237
145 WHEN "1101011" => T_int1 := "00111111000101111001000010100010"; -- X3f17 X90a2
146 WHEN "1101100" => T_int1 := "00111100010101101000111100011110"; -- X3c56 X8f1e
147 WHEN "1101101" => T_int1 := "00111001100011001000110110101100"; -- X398c X8dac
148 WHEN "1101110" => T_int1 := "00110110101110101000110001001011"; -- X36ba X8c4b
149 WHEN "1101111" => T_int1 := "00110011110111111000101011111100"; -- X33df X8afc
150 WHEN "1110000" => T_int1 := "00110000111110111000100110111111"; -- X30fb X89bf
151 WHEN "1110001" => T_int1 := "00101110000100011000100010010101"; -- X2e11 X8895
152 WHEN "1110010" => T_int1 := "00101011000111111000011101111100"; -- X2b1f X877c
153 WHEN "1110011" => T_int1 := "00101000001001101000011001110111"; -- X2826 X8677
154 WHEN "1110100" => T_int1 := "00100101001010001000010110000100"; -- X2528 X8584
155 WHEN "1110101" => T_int1 := "00100010001000111000010010100100"; -- X2223 X84a4
156 WHEN "1110110" => T_int1 := "00011111000110101000001111010111"; -- X1f1a X83d7
157 WHEN "1110111" => T_int1 := "00011100000010111000001100011101"; -- X1c0b X831d
158 WHEN "1111000" => T_int1 := "00011000111110011000001001110111"; -- X18f9 X8277
159 WHEN "1111001" => T_int1 := "00010101111000101000000111100011"; -- X15e2 X81e3
160 WHEN "1111010" => T_int1 := "00010010110010001000000101100100"; -- X12c8 X8164
161 WHEN "1111011" => T_int1 := "00001111101010111000000011110111"; -- X0fab X80f7
162 WHEN "1111100" => T_int1 := "00001100100011001000000010011111"; -- X0c8c X809f
163 WHEN "1111101" => T_int1 := "00001001011010101000000001011010"; -- X096a X805a
164 WHEN "1111110" => T_int1 := "00000110010010001000000000101000"; -- X0648 X8028
165 WHEN "1111111" => T_int1 := "00000011001001001000000000001011"; -- X0324 X800b
166 WHEN OTHERS => NULL;
167 END CASE;
168 T_int <= T_int1;
169 END PROCESS;
170
171 END ARCHITECTURE translated;
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@@ -0,0 +1,127
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
35 entity APB_FifoRead is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
45 port (
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
49 Flag_WR : in std_logic; --! Demande l'οΏ½criture dans la mοΏ½moire, gοΏ½rοΏ½ hors de l'IP
50 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'οΏ½criture dans la mοΏ½moire
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 );
53 end APB_FifoRead;
54
55
56 architecture ar_APB_FifoRead of APB_FifoRead is
57
58 constant REVISION : integer := 1;
59
60 constant pconfig : apb_config_type := (
61 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0),
62 1 => apb_iobar(paddr, pmask));
63
64 type FIFO_ctrlr_Reg is record
65 FIFO_Cfg : std_logic_vector(1 downto 0);
66 FIFO_DataW : std_logic_vector(15 downto 0);
67 FIFO_DataR : std_logic_vector(15 downto 0);
68 FIFO_AddrR : std_logic_vector(7 downto 0);
69 end record;
70
71 signal Rec : FIFO_ctrlr_Reg;
72 signal Rdata : std_logic_vector(31 downto 0);
73
74 signal flag_RE : std_logic;
75 signal empty : std_logic;
76
77 begin
78
79 Rec.FIFO_Cfg(0) <= flag_RE;
80 Rec.FIFO_Cfg(2) <= empty;
81
82
83 CONVERTER : entity Work.Top_FifoRead
84 generic map(Data_sz,Addr_sz,addr_max_int)
85 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,Rec.FIFO_AddrR,full,Waddr,Rec.FIFO_DataR);
86
87
88 process(rst,clk)
89 begin
90 if(rst='0')then
91 Rec.FIFO_AddrR <= (others => '0');
92
93 elsif(clk'event and clk='1')then
94
95 --APB Write OP
96 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
97 case apbi.paddr(abits-1 downto 2) is
98 when others =>
99 null;
100 end case;
101 end if;
102
103 --APB Read OP
104 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
105 case apbi.paddr(abits-1 downto 2) is
106 when "000000" =>
107 Rdata(31 downto 16) <= X"DDDD";
108 Rdata(15 downto 0) <= Rec.FIFO_DataR;
109 when "000001" =>
110 Rdata(31 downto 8) <= X"AAAAAA";
111 Rdata(7 downto 0) <= Rec.FIFO_AddrR;
112 when "000010" =>
113 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
114 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
115 Rdata(31 downto 8) <= X"CCCCCC";
116 when others =>
117 Rdata <= (others => '0');
118 end case;
119 end if;
120
121 end if;
122 apbo.pconfig <= pconfig;
123 end process;
124
125 apbo.prdata <= Rdata when apbi.penable = '1';
126
127 end ar_APB_FifoReade; No newline at end of file
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@@ -0,0 +1,131
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
35 entity APB_FifoWrite is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
45 port (
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
49 Flag_RE : in std_logic; --! Demande de lecture de la mοΏ½moire, gοΏ½rοΏ½ hors de l'IP
50 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture dans la mοΏ½moire
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 );
53 end APB_FifoWrite;
54
55
56 architecture ar_APB_FifoWrite of APB_FifoWrite is
57
58 constant REVISION : integer := 1;
59
60 constant pconfig : apb_config_type := (
61 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0),
62 1 => apb_iobar(paddr, pmask));
63
64 type FIFO_ctrlr_Reg is record
65 FIFO_Cfg : std_logic_vector(1 downto 0);
66 FIFO_DataW : std_logic_vector(15 downto 0);
67 FIFO_DataR : std_logic_vector(15 downto 0);
68 FIFO_AddrW : std_logic_vector(7 downto 0);
69 end record;
70
71 signal Rec : FIFO_ctrlr_Reg;
72 signal Rdata : std_logic_vector(31 downto 0);
73
74 signal flag_WR : std_logic;
75 signal full : std_logic;
76
77 begin
78
79 Rec.FIFO_Cfg(0) <= flag_WR;
80 Rec.FIFO_Cfg(1) <= full;
81
82 CONVERTER : entity Work.Top_FifoWrite
83 generic map(Data_sz,Addr_sz,addr_max_int)
84 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,Raddr,full,Rec.FIFO_AddrW,Rec.FIFO_DataR);
85
86
87 process(rst,clk)
88 begin
89 if(rst='0')then
90 Rec.FIFO_DataW <= (others => '0');
91
92 elsif(clk'event and clk='1')then
93
94 --APB Write OP
95 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
96 case apbi.paddr(abits-1 downto 2) is
97 when "000000" =>
98 flag_WR <= '1';
99 Rec.FIFO_DataW <= apbi.pwdata(15 downto 0);
100 when others =>
101 null;
102 end case;
103 else
104 flag_WR <= '0';
105 end if;
106
107 --APB Read OP
108 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
109 case apbi.paddr(abits-1 downto 2) is
110 when "000000" =>
111 Rdata(31 downto 16) <= X"DDDD";
112 Rdata(15 downto 0) <= Rec.FIFO_DataR;
113 when "000001" =>
114 Rdata(31 downto 8) <= X"AAAAAA";
115 Rdata(7 downto 0) <= Rec.FIFO_AddrW;
116 when "000010" =>
117 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
118 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
119 Rdata(31 downto 8) <= X"CCCCCC";
120 when others =>
121 Rdata <= (others => '0');
122 end case;
123 end if;
124
125 end if;
126 apbo.pconfig <= pconfig;
127 end process;
128
129 apbo.prdata <= Rdata when apbi.penable = '1';
130
131 end ar_APB_FifoWrite; No newline at end of file
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@@ -0,0 +1,103
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FIFO_Config.all;
26
27 --! Programme qui va permettre de "pipeliner" la FIFO, donnοΏ½e disponible en sortie dοΏ½ son οΏ½criture en entrοΏ½e de la FIFO
28
29 entity Link_Reg is
30 generic(Data_sz : integer := 16);
31 port(
32 clk,raz : in std_logic; --! Horloge et reset general du composant
33 Data_one : in std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½e en entrοΏ½e de la FIFO, cotοΏ½ οΏ½criture
34 Data_two : in std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½e en sortie de la FIFO, cotοΏ½ lecture
35 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
36 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
37 empty : in std_logic; --! Flag, MοΏ½moire vide
38 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! DonnοΏ½e en sortie, pipelinοΏ½e
39 );
40 end Link_Reg;
41
42 architecture ar_Link_Reg of Link_Reg is
43
44 type etat is (e0,e1,e2,e3);
45 signal ect : etat;
46
47 begin
48 process (clk,raz)
49 begin
50 if(raz='0')then
51 Data_out <= (others => 'X');
52 ect <= e0;
53
54 elsif(clk' event and clk='1')then
55 case ect is
56 when e0 =>
57 if(flag_WR='1')then
58 Data_out <= Data_one;
59 ect <= e1;
60 end if;
61
62 when e1 =>
63 if(flag_RE='1')then
64 Data_out <= Data_two;
65 ect <= e2;
66 end if;
67
68 when e2 =>
69 if(empty='1')then
70 ect <= e3;
71 else
72 Data_out <= Data_two;
73 ect <= e2;
74 end if;
75
76 when e3 =>
77 Data_out <= Data_two;
78 ect <= e0;
79
80 end case;
81 end if;
82 end process;
83
84 end ar_Link_Reg;
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
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@@ -0,0 +1,104
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library techmap;
26 use techmap.gencomp.all;
27 use work.config.all;
28
29 --! Programme de la FIFO
30
31 entity Top_FifoRead is
32 generic(
33 Data_sz : integer := 16;
34 Addr_sz : integer := 8;
35 addr_max_int : integer := 256);
36 port(
37 clk,raz : in std_logic; --! Horloge et reset general du composant
38 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
39 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
40 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrοΏ½e du composant
41 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'οΏ½criture dans la mοΏ½moire
42 full : out std_logic; --! Flag, MοΏ½moire pleine
43 empty : out std_logic; --! Flag, MοΏ½moire vide
44 Raddr : out std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la mοΏ½moire
45 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
46 );
47 end Top_FifoRead;
48
49 --! @details Une mοΏ½moire SRAM de chez Gaisler est utilisοΏ½e,
50 --! associοΏ½e a une fifo, utilisοΏ½ pour la lecture
51
52 architecture ar_Top_FifoRead of Top_FifoRead is
53
54 component syncram_2p
55 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
56 port (
57 rclk : in std_ulogic;
58 renable : in std_ulogic;
59 raddress : in std_logic_vector((abits -1) downto 0);
60 dataout : out std_logic_vector((dbits -1) downto 0);
61 wclk : in std_ulogic;
62 write : in std_ulogic;
63 waddress : in std_logic_vector((abits -1) downto 0);
64 datain : in std_logic_vector((dbits -1) downto 0));
65 end component;
66
67 signal Raddr_int : std_logic_vector(addr_sz-1 downto 0);
68 signal s_flag_RE : std_logic;
69 signal s_empty : std_logic;
70
71 begin
72
73 SRAM : syncram_2p
74 generic map(CFG_MEMTECH,addr_sz,Data_sz)
75 port map(clk,s_flag_RE,Waddr,Data_int,clk,flag_WR,Raddr_int,Data_in);
76
77
78 RE : entity work.Fifo_Read
79 generic map(Addr_sz,addr_max_int)
80 port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr_int);
81
82 link : entity work.Link_Reg
83 generic map(Data_sz)
84 port map(clk,raz,Data_in,Data_int,s_flag_RE,flag_WR,s_empty,Data_out);
85
86 process(clk,raz)
87 begin
88 if(raz='0')then
89 s_flag_RE <= '0';
90
91 elsif(clk'event and clk='1')then
92 if(s_empty='0')then
93 s_flag_RE <= Flag_RE;
94 else
95 s_flag_RE <= '0';
96 end if;
97
98 end if;
99 end process;
100
101 empty <= s_empty;
102 Raddr <= Raddr_int;
103
104 end ar_Top_FifoRead; No newline at end of file
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@@ -0,0 +1,101
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library techmap;
26 use techmap.gencomp.all;
27 use work.config.all;
28
29 --! Programme de la FIFO
30
31 entity Top_FifoWrite is
32 generic(
33 Data_sz : integer := 16;
34 Addr_sz : integer := 8;
35 addr_max_int : integer := 256);
36 port(
37 clk,raz : in std_logic; --! Horloge et reset general du composant
38 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
39 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
40 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrοΏ½e du composant
41 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'οΏ½criture dans la mοΏ½moire
42 full : out std_logic; --! Flag, MοΏ½moire pleine
43 Waddr : out std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la mοΏ½moire
44 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
45 );
46 end Top_FifoWrite;
47
48 --! @details Une mοΏ½moire SRAM de chez Gaisler est utilisοΏ½e,
49 --! associοΏ½e a un Driver, utilisοΏ½e pour οΏ½crire dans celle-ci
50
51 architecture ar_Top_FifoWrite of Top_FifoWrite is
52
53 component syncram_2p
54 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
55 port (
56 rclk : in std_ulogic;
57 renable : in std_ulogic;
58 raddress : in std_logic_vector((abits -1) downto 0);
59 dataout : out std_logic_vector((dbits -1) downto 0);
60 wclk : in std_ulogic;
61 write : in std_ulogic;
62 waddress : in std_logic_vector((abits -1) downto 0);
63 datain : in std_logic_vector((dbits -1) downto 0));
64 end component;
65
66 signal Waddr_int : std_logic_vector(addr_sz-1 downto 0);
67 signal s_flag_WR : std_logic;
68 signal s_full : std_logic;
69
70 begin
71
72
73 WR : entity work.Fifo_Write
74 generic map(Addr_sz,addr_max_int)
75 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr_int);
76
77
78 SRAM : syncram_2p
79 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
80 port map(clk,flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr_int,Data_in);
81
82
83 process(clk,raz)
84 begin
85 if(raz='0')then
86 s_flag_WR <= '0';
87
88 elsif(clk'event and clk='1')then
89 if(s_full='0')then
90 s_flag_WR <= Flag_WR;
91 else
92 s_flag_WR <= '0';
93 end if;
94
95 end if;
96 end process;
97
98 Waddr <= Waddr_int;
99 full <= s_full;
100
101 end ar_Top_FifoWrite; No newline at end of file
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@@ -11,3 +11,4 device LPP_APB_ADC 8
11 device LPP_CHENILLARD 9
11 device LPP_CHENILLARD 9
12 device LPP_IIR_CEL_FILTER 10
12 device LPP_IIR_CEL_FILTER 10
13 device LPP_FIFO 11
13 device LPP_FIFO 11
14 device LPP_FFT 12
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@@ -22,4 +22,5
22 all:
22 all:
23 make all -C ScanAPB
23 make all -C ScanAPB
24 make all -C APB_lcd_ctrlr
24 make all -C APB_lcd_ctrlr
25 make all -C BenchFIFO
25
26
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@@ -25,10 +25,12 all:
25 make all -C AMBA
25 make all -C AMBA
26 make all -C LCD
26 make all -C LCD
27 make all -C DAC
27 make all -C DAC
28 make all -C FIFO
28
29
29
30
30 cleanall:
31 cleanall:
31 make clean -C AMBA
32 make clean -C AMBA
32 make clean -C LCD
33 make clean -C LCD
33 make clean -C DAC
34 make clean -C DAC
35 make clean -C FIFO
34
36
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@@ -1,1 +1,1
1 load bin/APB_lcd_ctrlr.bin
1 load bin/BenchFIFO.bin
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@@ -34,11 +34,14 use lpp.lpp_fifo.all;
34
34
35 entity APB_FIFO is
35 entity APB_FIFO is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0;
41 abits : integer := 8);
41 abits : integer := 8;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
42 port (
45 port (
43 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
44 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
@@ -60,6 +63,8 type FIFO_ctrlr_Reg is record
60 FIFO_Cfg : std_logic_vector(3 downto 0);
63 FIFO_Cfg : std_logic_vector(3 downto 0);
61 FIFO_DataW : std_logic_vector(15 downto 0);
64 FIFO_DataW : std_logic_vector(15 downto 0);
62 FIFO_DataR : std_logic_vector(15 downto 0);
65 FIFO_DataR : std_logic_vector(15 downto 0);
66 FIFO_AddrW : std_logic_vector(7 downto 0);
67 FIFO_AddrR : std_logic_vector(7 downto 0);
63 end record;
68 end record;
64
69
65 signal Rec : FIFO_ctrlr_Reg;
70 signal Rec : FIFO_ctrlr_Reg;
@@ -71,54 +76,62 signal full : std_logic;
71 signal empty : std_logic;
76 signal empty : std_logic;
72 begin
77 begin
73
78
74 flag_RE <= Rec.FIFO_Cfg(0);
79 Rec.FIFO_Cfg(0) <= flag_RE;
75 flag_WR <= Rec.FIFO_Cfg(1);
80 Rec.FIFO_Cfg(1) <= flag_WR;
76 Rec.FIFO_Cfg(2) <= empty;
81 Rec.FIFO_Cfg(2) <= empty;
77 Rec.FIFO_Cfg(3) <= full;
82 Rec.FIFO_Cfg(3) <= full;
78
83
79 CONVERTER : entity Work.Top_FIFO
84 CONVERTER : entity Work.Top_FIFO
80 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,full,empty,Rec.FIFO_DataR);
85 generic map(Data_sz,Addr_sz,addr_max_int)
86 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,Rec.FIFO_AddrR,Rec.FIFO_AddrW,full,empty,Rec.FIFO_DataR);
81
87
82
88
83 process(rst,clk)
89 process(rst,clk)
84 begin
90 begin
85 if(rst='0')then
91 if(rst='0')then
86 Rec.FIFO_DataW <= (others => '0');
92 Rec.FIFO_DataW <= (others => '0');
93 flag_WR <= '0';
94 flag_RE <= '0';
87
95
88 elsif(clk'event and clk='1')then
96 elsif(clk'event and clk='1')then
89
90
97
91 --APB Write OP
98 --APB Write OP
92 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
99 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
93 case apbi.paddr(abits-1 downto 2) is
100 case apbi.paddr(abits-1 downto 2) is
94 when "000000" =>
101 when "000000" =>
95 Rec.FIFO_Cfg(0) <= apbi.pwdata(0);
102 flag_WR <= '1';
96 Rec.FIFO_Cfg(1) <= apbi.pwdata(4);
103 Rec.FIFO_DataW <= apbi.pwdata(15 downto 0);
97 when "000001" =>
98 Rec.FIFO_DataW <= apbi.pwdata(15 downto 0);
99 when others =>
104 when others =>
100 null;
105 null;
101 end case;
106 end case;
107 else
108 flag_WR <= '0';
102 end if;
109 end if;
103
110
104 --APB READ OP
111 --APB Read OP
105 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
112 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
106 case apbi.paddr(abits-1 downto 2) is
113 case apbi.paddr(abits-1 downto 2) is
107 when "000000" =>
114 when "000000" =>
108 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
115 flag_RE <= '1';
109 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
116 Rdata(31 downto 16) <= X"DDDD";
110 Rdata(11 downto 8) <= "000" & Rec.FIFO_Cfg(2);
117 Rdata(15 downto 0) <= Rec.FIFO_DataR;
111 Rdata(15 downto 12) <= "000" & Rec.FIFO_Cfg(3);
112 Rdata(31 downto 16) <= X"AAAA";
113 when "000001" =>
118 when "000001" =>
114 Rdata(31 downto 16) <= X"AAAA";
119 Rdata(31 downto 8) <= X"AAAAAA";
115 Rdata(15 downto 0) <= Rec.FIFO_DataW;
120 Rdata(7 downto 0) <= Rec.FIFO_AddrR;
121 when "000101" =>
122 Rdata(31 downto 8) <= X"AAAAAA";
123 Rdata(7 downto 0) <= Rec.FIFO_AddrW;
116 when "000010" =>
124 when "000010" =>
117 Rdata(31 downto 16) <= X"AAAA";
125 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
118 Rdata(15 downto 0) <= Rec.FIFO_DataR;
126 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
127 Rdata(11 downto 8) <= "000" & Rec.FIFO_Cfg(2);
128 Rdata(15 downto 12) <= "000" & Rec.FIFO_Cfg(3);
129 Rdata(31 downto 16) <= X"CCCC";
119 when others =>
130 when others =>
120 Rdata <= (others => '0');
131 Rdata <= (others => '0');
121 end case;
132 end case;
133 else
134 flag_RE <= '0';
122 end if;
135 end if;
123
136
124 end if;
137 end if;
@@ -126,4 +139,5 Rec.FIFO_Cfg(3) <= full;
126 end process;
139 end process;
127
140
128 apbo.prdata <= Rdata when apbi.penable = '1';
141 apbo.prdata <= Rdata when apbi.penable = '1';
129 end ar_APB_FIFO;
142
143 end ar_APB_FIFO; No newline at end of file
Show file before | Show file after | Hide comments
@@ -22,18 +22,19
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use work.FIFO_Config.all;
26
25
27 --! Programme de la FIFO de lecture
26 --! Programme de la FIFO de lecture
28
27
29 entity Fifo_Read is
28 entity Fifo_Read is
29 generic(
30 Addr_sz : integer := 8;
31 addr_max_int : integer := 256);
30 port(
32 port(
31 clk,raz : in std_logic; --! Horloge et reset general du composant
33 clk,raz : in std_logic; --! Horloge et reset general du composant
32 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
34 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
33 WAD : in integer range 0 to addr_max_int; --! Adresse du registre d'οΏ½criture dans la mοΏ½moire (forme entiοΏ½re)
35 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'οΏ½criture dans la mοΏ½moire
34 empty : out std_logic; --! Flag, MοΏ½moire vide
36 empty : out std_logic; --! Flag, MοΏ½moire vide
35 RAD : out integer range 0 to addr_max_int; --! Adresse du registre de lecture de la mοΏ½moire (forme entiοΏ½re)
37 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la mοΏ½moire
36 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la mοΏ½moire (forme vectorielle)
37 );
38 );
38 end Fifo_Read;
39 end Fifo_Read;
39
40
@@ -41,7 +42,11 end Fifo_Read;
41
42
42 architecture ar_Fifo_Read of Fifo_Read is
43 architecture ar_Fifo_Read of Fifo_Read is
43
44
44 signal Rad_int : integer range 0 to addr_max_int;
45 signal Rad_int : integer range 0 to addr_max_int;
46 signal Rad_int_reg : integer range 0 to addr_max_int;
47 signal Wad_int : integer range 0 to addr_max_int;
48 signal Wad_int_reg : integer range 0 to addr_max_int;
49 signal flag_reg : std_logic;
45
50
46 begin
51 begin
47 process (clk,raz)
52 process (clk,raz)
@@ -49,23 +54,33 begin
49 if(raz='0')then
54 if(raz='0')then
50 Rad_int <= 0;
55 Rad_int <= 0;
51 empty <= '1';
56 empty <= '1';
52
57
53 elsif(clk' event and clk='1')then
58 elsif(clk' event and clk='1')then
54 if(flag_RE='1')then
59 Wad_int_reg <= Wad_int;
55 if(Rad_int=addr_max_int)then
60 Rad_int_reg <= Rad_int;
61 flag_reg <= flag_RE;
62
63 if(flag_reg ='0' and flag_RE='1')then
64 if(Rad_int=addr_max_int-1)then
56 Rad_int <= 0;
65 Rad_int <= 0;
57 else
66 else
58 Rad_int <= Rad_int+1;
67 Rad_int <= Rad_int+1;
59 end if;
68 end if;
60 end if;
69 end if;
61 if(Rad_int=WAD)then
70
62 empty <= '1';
71 if(Rad_int_reg /= Rad_int)then
63 else
72 if(Rad_int=Wad_int)then
73 empty <= '1';
74 else
75 empty <= '0';
76 end if;
77 elsif(Wad_int_reg /= Wad_int)then
64 empty <= '0';
78 empty <= '0';
65 end if;
79 end if;
66 end if;
80 end if;
67 end process;
81 end process;
68
82
69 RAD <= Rad_int;
83 Wad_int <= to_integer(unsigned(Waddr));
70 Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz));
84 Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz));
85
71 end ar_Fifo_Read; No newline at end of file
86 end ar_Fifo_Read;
Show file before | Show file after | Hide comments
@@ -22,18 +22,19
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use work.FIFO_Config.all;
26
25
27 --! Programme de la FIFO d'οΏ½criture
26 --! Programme de la FIFO d'οΏ½criture
28
27
29 entity Fifo_Write is
28 entity Fifo_Write is
29 generic(
30 Addr_sz : integer := 8;
31 addr_max_int : integer := 256);
30 port(
32 port(
31 clk,raz : in std_logic; --! Horloge et reset general du composant
33 clk,raz : in std_logic; --! Horloge et reset general du composant
32 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
34 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
33 RAD : in integer range 0 to addr_max_int; --! Adresse du registre de lecture de la mοΏ½moire (forme entiοΏ½re)
35 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la mοΏ½moire
34 full : out std_logic; --! Flag, MοΏ½moire pleine
36 full : out std_logic; --! Flag, MοΏ½moire pleine
35 WAD : out integer range 0 to addr_max_int; --! Adresse du registre d'οΏ½criture dans la mοΏ½moire (forme entiοΏ½re)
37 Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'οΏ½criture dans la mοΏ½moire
36 Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'οΏ½criture dans la mοΏ½moire (forme vectorielle)
37 );
38 );
38 end Fifo_Write;
39 end Fifo_Write;
39
40
@@ -41,35 +42,45 end Fifo_Write;
41
42
42 architecture ar_Fifo_Write of Fifo_Write is
43 architecture ar_Fifo_Write of Fifo_Write is
43
44
44 signal Wad_int : integer range 0 to addr_max_int;
45 signal Wad_int : integer range 0 to addr_max_int;
45 signal full_int : std_logic;
46 signal Wad_int_reg : integer range 0 to addr_max_int;
47 signal Rad_int : integer range 0 to addr_max_int;
48 signal Rad_int_reg : integer range 0 to addr_max_int;
46
49
47 begin
50 begin
48 process (clk,raz)
51 process (clk,raz)
49 begin
52 begin
50 if(raz='0')then
53 if(raz='0')then
51 Wad_int <= 0;
54 Wad_int <= 0;
52 full_int <= '0';
55 full <= '0';
53
56
54 elsif(clk' event and clk='1')then
57 elsif(clk' event and clk='1')then
58 Wad_int_reg <= Wad_int;
59 Rad_int_reg <= Rad_int;
60
61
55 if(flag_WR='1')then
62 if(flag_WR='1')then
56 if(Wad_int=addr_max_int)then
63 if(Wad_int=addr_max_int-1)then
57 Wad_int <= 0;
64 Wad_int <= 0;
58 elsif(full_int='1')then
59 Wad_int <= Wad_int;
60 else
65 else
61 Wad_int <= Wad_int+1;
66 Wad_int <= Wad_int+1;
62 end if;
67 end if;
63 end if;
68 end if;
64 if(Wad_int=RAD-1 or (Wad_int=addr_max_int and RAD=0))then
69
65 full_int <= '1';
70 if(Wad_int_reg /= Wad_int)then
66 else
71 if(Wad_int=Rad_int)then
67 full_int <= '0';
72 full <= '1';
73 else
74 full <= '0';
75 end if;
76 elsif(Rad_int_reg /= Rad_int)then
77 full <= '0';
68 end if;
78 end if;
79
69 end if;
80 end if;
70 end process;
81 end process;
71
82
72 full <= full_int;
83 Rad_int <= to_integer(unsigned(Raddr));
73 WAD <= Wad_int;
84 Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz));
74 Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz));
85
75 end ar_Fifo_Write; No newline at end of file
86 end ar_Fifo_Write;
Show file before | Show file after | Hide comments
@@ -24,17 +24,23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library techmap;
25 library techmap;
26 use techmap.gencomp.all;
26 use techmap.gencomp.all;
27 use work.FIFO_Config.all;
28 use work.config.all;
27 use work.config.all;
29
28
30 --! Programme de la FIFO
29 --! Programme de la FIFO
31
30
32 entity Top_FIFO is
31 entity Top_FIFO is
32 generic(
33 Data_sz : integer := 16;
34 Addr_sz : integer := 8;
35 addr_max_int : integer := 256
36 );
33 port(
37 port(
34 clk,raz : in std_logic; --! Horloge et reset general du composant
38 clk,raz : in std_logic; --! Horloge et reset general du composant
35 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
39 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
36 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
40 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
37 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrοΏ½e du composant
41 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrοΏ½e du composant
42 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'οΏ½criture
43 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
38 full : out std_logic; --! Flag, MοΏ½moire pleine
44 full : out std_logic; --! Flag, MοΏ½moire pleine
39 empty : out std_logic; --! Flag, MοΏ½moire vide
45 empty : out std_logic; --! Flag, MοΏ½moire vide
40 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
46 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
@@ -42,42 +48,76 entity Top_FIFO is
42 end Top_FIFO;
48 end Top_FIFO;
43
49
44 --! @details Une mοΏ½moire SRAM de chez Gaisler est utilisοΏ½e,
50 --! @details Une mοΏ½moire SRAM de chez Gaisler est utilisοΏ½e,
45 --! associοΏ½e a deux fifos, une pour οΏ½crire l'autre pour lire cette mοΏ½moire
51 --! associοΏ½e a deux Drivers, un pour οΏ½crire l'autre pour lire cette mοΏ½moire
46
52
47 architecture ar_Top_FIFO of Top_FIFO is
53 architecture ar_Top_FIFO of Top_FIFO is
48
54
49 component syncram_2p
55 component syncram_2p
50 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer
56 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
51 := 0);
52 port (
57 port (
53 rclk : in std_ulogic;
58 rclk : in std_ulogic;
54 renable : in std_ulogic;
59 renable : in std_ulogic;
55 raddress : in std_logic_vector((abits -1) downto 0);
60 raddress : in std_logic_vector((abits -1) downto 0);
56 dataout : out std_logic_vector((dbits -1) downto 0);
61 dataout : out std_logic_vector((dbits -1) downto 0);
57 wclk : in std_ulogic;
62 wclk : in std_ulogic;
58 write : in std_ulogic;
63 write : in std_ulogic;
59 waddress : in std_logic_vector((abits -1) downto 0);
64 waddress : in std_logic_vector((abits -1) downto 0);
60 datain : in std_logic_vector((dbits -1) downto 0));
65 datain : in std_logic_vector((dbits -1) downto 0));
61 end component;
66 end component;
62
67
63 signal RAD : integer range 0 to addr_max_int;
68 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
64 signal WAD : integer range 0 to addr_max_int;
69 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
65 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
70 signal Data_int : std_logic_vector(Data_sz-1 downto 0);
66 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
71 signal s_empty : std_logic;
72 signal s_full : std_logic;
73 signal s_flag_RE : std_logic;
74 signal s_flag_WR : std_logic;
67
75
68 begin
76 begin
77
78 WR : entity work.Fifo_Write
79 generic map(Addr_sz,addr_max_int)
80 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr);
81
69
82
70 SRAM : syncram_2p
83 SRAM : syncram_2p
71 generic map(CFG_MEMTECH,addr_sz,Data_sz)
84 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
72 port map(clk,flag_RE,Raddr,Data_out,clk,flag_WR,Waddr,Data_in);
85 port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in);
73
74
75 WR : entity work.Fifo_Write
76 port map(clk,raz,flag_WR,RAD,full,WAD,Waddr);
77
86
78
87
88 link : entity work.Link_Reg
89 generic map(Data_sz)
90 port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
91
79 RE : entity work.Fifo_Read
92 RE : entity work.Fifo_Read
80 port map(clk,raz,flag_RE,WAD,empty,RAD,Raddr);
93 generic map(Addr_sz,addr_max_int)
94 port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr);
95
96 process(clk,raz)
97 begin
98 if(raz='0')then
99 s_flag_RE <= '0';
100 s_flag_WR <= '0';
81
101
102 elsif(clk'event and clk='1')then
103 if(s_full='0')then
104 s_flag_WR <= Flag_WR;
105 else
106 s_flag_WR <= '0';
107 end if;
82
108
83 end ar_Top_FIFO; No newline at end of file
109 if(s_empty='0')then
110 s_flag_RE <= Flag_RE;
111 else
112 s_flag_RE <= '0';
113 end if;
114
115 end if;
116 end process;
117
118 full <= s_full;
119 empty <= s_empty;
120 Addr_RE <= Raddr;
121 Addr_WR <= Waddr;
122
123 end ar_Top_FIFO; No newline at end of file
Show file before | Show file after | Hide comments
@@ -32,58 +32,173 use work.FIFO_Config.all;
32
32
33 package lpp_fifo is
33 package lpp_fifo is
34
34
35 --===========================================================|
36 --================= FIFOW SRAM FIFOR ========================|
37 --===========================================================|
38
35 component APB_FIFO is
39 component APB_FIFO is
36 generic (
40 generic (
37 pindex : integer := 0;
41 pindex : integer := 0;
38 paddr : integer := 0;
42 paddr : integer := 0;
39 pmask : integer := 16#fff#;
43 pmask : integer := 16#fff#;
40 pirq : integer := 0;
44 pirq : integer := 0;
41 abits : integer := 8);
45 abits : integer := 8;
46 Addr_sz : integer := 8;
47 Data_sz : integer := 16;
48 addr_max_int : integer := 256);
42 port (
49 port (
43 clk : in std_logic;
50 clk : in std_logic;
44 rst : in std_logic;
51 rst : in std_logic;
45 apbi : in apb_slv_in_type;
52 apbi : in apb_slv_in_type;
46 apbo : out apb_slv_out_type
53 apbo : out apb_slv_out_type
47 );
54 );
48 end component;
55 end component;
49
56
50
57
51 component Top_FIFO is
58 component Top_FIFO is
59 generic(
60 Addr_sz : integer := 8;
61 Data_sz : integer := 16;
62 addr_max_int : integer := 256);
52 port(
63 port(
53 clk : in std_logic;
64 clk : in std_logic;
54 raz : in std_logic;
65 raz : in std_logic;
55 flag_RE : in std_logic;
66 Send_RE : in std_logic;
56 flag_WR : in std_logic;
67 Send_WR : in std_logic;
57 Data_in : in std_logic_vector(Data_sz-1 downto 0);
68 Data_in : in std_logic_vector(Data_sz-1 downto 0);
58 full : out std_logic;
69 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
59 empty : out std_logic;
70 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
60 Data_out : out std_logic_vector(Data_sz-1 downto 0)
71 full : out std_logic;
72 empty : out std_logic;
73 Data_out : out std_logic_vector(Data_sz-1 downto 0)
61 );
74 );
62 end component;
75 end component;
63
76
64
77
65 component Fifo_Read is
78 component Fifo_Read is
79 generic(
80 Addr_sz : integer := 8;
81 addr_max_int : integer := 256);
66 port(
82 port(
67 clk : in std_logic;
83 clk : in std_logic;
68 raz : in std_logic;
84 raz : in std_logic;
69 flag_RE : in std_logic;
85 flag_RE : in std_logic;
70 WAD : in integer range 0 to addr_max_int;
86 Waddr : in std_logic_vector(addr_sz-1 downto 0);
71 empty : out std_logic;
87 empty : out std_logic;
72 RAD : out integer range 0 to addr_max_int;
88 Raddr : out std_logic_vector(addr_sz-1 downto 0)
73 Raddr : out std_logic_vector(addr_sz-1 downto 0)
74 );
89 );
75 end component;
90 end component;
76
91
77
92
78 component Fifo_Write is
93 component Fifo_Write is
94 generic(
95 Addr_sz : integer := 8;
96 addr_max_int : integer := 256);
79 port(
97 port(
80 clk : in std_logic;
98 clk : in std_logic;
81 raz : in std_logic;
99 raz : in std_logic;
82 flag_WR : in std_logic;
100 flag_WR : in std_logic;
83 RAD : in integer range 0 to addr_max_int;
101 Raddr : in std_logic_vector(addr_sz-1 downto 0);
84 full : out std_logic;
102 full : out std_logic;
85 WAD : out integer range 0 to addr_max_int;
103 Waddr : out std_logic_vector(addr_sz-1 downto 0)
86 Waddr : out std_logic_vector(addr_sz-1 downto 0)
104 );
105 end component;
106
107
108 component Link_Reg is
109 generic(Data_sz : integer := 16);
110 port(
111 clk,raz : in std_logic;
112 Data_one : in std_logic_vector(Data_sz-1 downto 0);
113 Data_two : in std_logic_vector(Data_sz-1 downto 0);
114 flag_RE : in std_logic;
115 flag_WR : in std_logic;
116 empty : in std_logic;
117 Data_out : out std_logic_vector(Data_sz-1 downto 0)
118 );
119 end component;
120
121 --===========================================================|
122 --===================== FIFOW SRAM ==========================|
123 --===========================================================|
124
125 component APB_FifoWrite is
126 generic (
127 pindex : integer := 0;
128 paddr : integer := 0;
129 pmask : integer := 16#fff#;
130 pirq : integer := 0;
131 abits : integer := 8;
132 Data_sz : integer := 16;
133 Addr_sz : integer := 8;
134 addr_max_int : integer := 256);
135 port (
136 clk : in std_logic;
137 rst : in std_logic;
138 apbi : in apb_slv_in_type;
139 apbo : out apb_slv_out_type
140 );
141 end component;
142
143
144 component Top_FifoWrite is
145 generic(
146 Data_sz : integer := 16;
147 Addr_sz : integer := 8;
148 addr_max_int : integer := 256);
149 port(
150 clk : in std_logic;
151 raz : in std_logic;
152 flag_RE : in std_logic;
153 flag_WR : in std_logic;
154 Data_in : in std_logic_vector(Data_sz-1 downto 0);
155 Raddr : in std_logic_vector(addr_sz-1 downto 0);
156 full : out std_logic;
157 empty : out std_logic;
158 Waddr : out std_logic_vector(addr_sz-1 downto 0);
159 Data_out : out std_logic_vector(Data_sz-1 downto 0)
160 );
161 end component;
162
163 --===========================================================|
164 --===================== SRAM FIFOR ==========================|
165 --===========================================================|
166
167 component APB_FifoRead is
168 generic (
169 pindex : integer := 0;
170 paddr : integer := 0;
171 pmask : integer := 16#fff#;
172 pirq : integer := 0;
173 abits : integer := 8;
174 Data_sz : integer := 16;
175 Addr_sz : integer := 8;
176 addr_max_int : integer := 256);
177 port (
178 clk : in std_logic;
179 rst : in std_logic;
180 apbi : in apb_slv_in_type;
181 apbo : out apb_slv_out_type
182 );
183 end component;
184
185
186 component Top_FifoRead is
187 generic(
188 Data_sz : integer := 16;
189 Addr_sz : integer := 8;
190 addr_max_int : integer := 256);
191 port(
192 clk : in std_logic;
193 raz : in std_logic;
194 flag_RE : in std_logic;
195 flag_WR : in std_logic;
196 Data_in : in std_logic_vector(Data_sz-1 downto 0);
197 Waddr : in std_logic_vector(addr_sz-1 downto 0);
198 full : out std_logic;
199 empty : out std_logic;
200 Raddr : out std_logic_vector(addr_sz-1 downto 0);
201 Data_out : out std_logic_vector(Data_sz-1 downto 0)
87 );
202 );
88 end component;
203 end component;
89
204
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