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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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--! Programme de la FIFO d'�criture
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entity Fifo_Write is
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generic(
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Addr_sz : integer := 8;
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addr_max_int : integer := 256);
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port(
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clk,raz : in std_logic; --! Horloge et reset general du composant
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flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
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Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la m�moire
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full : out std_logic; --! Flag, M�moire pleine
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Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'�criture dans la m�moire
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);
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end Fifo_Write;
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--! @details En amont de la SRAM Gaisler
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architecture ar_Fifo_Write of Fifo_Write is
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signal Wad_int : integer range 0 to addr_max_int;
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signal Wad_int_reg : integer range 0 to addr_max_int;
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signal Rad_int : integer range 0 to addr_max_int;
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signal Rad_int_reg : integer range 0 to addr_max_int;
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begin
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process (clk,raz)
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begin
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if(raz='0')then
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Wad_int <= 0;
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full <= '0';
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elsif(clk' event and clk='1')then
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Wad_int_reg <= Wad_int;
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Rad_int_reg <= Rad_int;
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if(flag_WR='1')then
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if(Wad_int=addr_max_int-1)then
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Wad_int <= 0;
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else
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Wad_int <= Wad_int+1;
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end if;
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end if;
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if(Wad_int_reg /= Wad_int)then
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if(Wad_int=Rad_int)then
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full <= '1';
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else
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full <= '0';
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end if;
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elsif(Rad_int_reg /= Rad_int)then
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full <= '0';
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end if;
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end if;
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end process;
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Rad_int <= to_integer(unsigned(Raddr));
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Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz));
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end ar_Fifo_Write;
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