diff --git a/lib/lpp/lpp_matrix/APB_Matrix.vhd b/lib/lpp/lpp_matrix/APB_Matrix.vhd --- a/lib/lpp/lpp_matrix/APB_Matrix.vhd +++ b/lib/lpp/lpp_matrix/APB_Matrix.vhd @@ -52,13 +52,14 @@ entity APB_Matrix is WriteFIFO : out std_logic; Result : out std_logic_vector(Result_SZ-1 downto 0); Start : out std_logic; --- Read : out std_logic; --- Take : out std_logic; --- Valid : out std_logic; + Read : out std_logic; + Take : out std_logic; + Valid : out std_logic; + Received : out std_logic; Res : out std_logic_vector(Result_SZ-1 downto 0); -- Conjugate : out std_logic; --- OP1 : out std_logic_vector(3 downto 0); --- OP2 : out std_logic_vector(3 downto 0); + OP1 : out std_logic_vector(3 downto 0); + OP2 : out std_logic_vector(3 downto 0); apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); @@ -84,7 +85,7 @@ begin Mspec0 : SpectralMatrix generic map (Input_SZ,Result_SZ) - port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Res,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2 + port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Read,Take,Valid,Received,Res,OP1,OP2,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2 process(rst,clk) begin diff --git a/lib/lpp/lpp_matrix/Matrix.vhd b/lib/lpp/lpp_matrix/Matrix.vhd --- a/lib/lpp/lpp_matrix/Matrix.vhd +++ b/lib/lpp/lpp_matrix/Matrix.vhd @@ -39,8 +39,8 @@ entity Matrix is Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugué Valid : out std_logic; --! Flag, Résultat disponible Read : out std_logic; --! Flag, opérande disponible --- OPin1 : out std_logic_vector(3 downto 0); --- OPin2 : out std_logic_vector(3 downto 0); + OPin1 : out std_logic_vector(3 downto 0); + OPin2 : out std_logic_vector(3 downto 0); Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! Résultat du calcul ); end Matrix; @@ -53,8 +53,8 @@ signal OP1 : std_logic_vector(Input_SZ signal OP2 : std_logic_vector(Input_SZ-1 downto 0); begin ---OPin1 <= OP1(3 downto 0); ---OPin2 <= OP1(3 downto 0); +OPin1 <= OP1(3 downto 0); +OPin2 <= OP1(3 downto 0); DRIVE : ALU_Driver diff --git a/lib/lpp/lpp_matrix/SpectralMatrix.vhd b/lib/lpp/lpp_matrix/SpectralMatrix.vhd --- a/lib/lpp/lpp_matrix/SpectralMatrix.vhd +++ b/lib/lpp/lpp_matrix/SpectralMatrix.vhd @@ -39,14 +39,14 @@ port( ReadFIFO : out std_logic_vector(1 downto 0); WriteFIFO : out std_logic; Start : out std_logic; --- Read : out std_logic; --- Take : out std_logic; --- Valid : out std_logic; - Res : out std_logic_vector(Result_SZ-1 downto 0); --- Received : out std_logic; + Read : out std_logic; + Take : out std_logic; + Valid : out std_logic; + Received : out std_logic; + Res : out std_logic_vector(Result_SZ-1 downto 0); -- Conjugate : out std_logic; --- OP1 : out std_logic_vector(3 downto 0); --- OP2 : out std_logic_vector(3 downto 0); + OP1 : out std_logic_vector(3 downto 0); + OP2 : out std_logic_vector(3 downto 0); Result : out std_logic_vector(Result_SZ-1 downto 0) ); end SpectralMatrix; @@ -82,7 +82,7 @@ IN1 : DriveInputs CALC0 : Matrix generic map(Input_SZ) - port map(clk,Start_int,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat); + port map(clk,Start_int,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,OP1,OP2,Resultat); RES0 : GetResult @@ -99,10 +99,10 @@ With Statu select '0' when others; Start <= Start_int; ---Read <= Read_int; ---Take <= Take_int; ---Received <= Received_int; ---Valid <= Valid_int; +Read <= Read_int; +Take <= Take_int; +Received <= Received_int; +Valid <= Valid_int; --Conjugate <= Conjugate_int; Res <= Resultat; diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -51,7 +51,14 @@ component APB_Matrix is WriteFIFO : out std_logic; Result : out std_logic_vector(Result_SZ-1 downto 0); Start : out std_logic; - Res : out std_logic_vector(Result_SZ-1 downto 0); + Read : out std_logic; + Take : out std_logic; + Valid : out std_logic; + Received : out std_logic; +Res : out std_logic_vector(Result_SZ-1 downto 0); +-- Conjugate : out std_logic; + OP1 : out std_logic_vector(3 downto 0); + OP2 : out std_logic_vector(3 downto 0); apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); @@ -72,8 +79,15 @@ port( Statu : in std_logic_vector(3 downto 0); ReadFIFO : out std_logic_vector(1 downto 0); WriteFIFO : out std_logic; - Start : out std_logic; + Start : out std_logic; + Read : out std_logic; + Take : out std_logic; + Valid : out std_logic; + Received : out std_logic; Res : out std_logic_vector(Result_SZ-1 downto 0); +-- Conjugate : out std_logic; + OP1 : out std_logic_vector(3 downto 0); + OP2 : out std_logic_vector(3 downto 0); Result : out std_logic_vector(Result_SZ-1 downto 0) ); end component; @@ -92,6 +106,8 @@ component Matrix is Conjugate : in std_logic; Valid : out std_logic; Read : out std_logic; + OPin1 : out std_logic_vector(3 downto 0); + OPin2 : out std_logic_vector(3 downto 0); Result : out std_logic_vector(2*Input_SZ-1 downto 0) ); end component; diff --git a/lib/lpp/lpp_memory/APB_FIFO.vhd b/lib/lpp/lpp_memory/APB_FIFO.vhd --- a/lib/lpp/lpp_memory/APB_FIFO.vhd +++ b/lib/lpp/lpp_memory/APB_FIFO.vhd @@ -63,7 +63,7 @@ signal FlagEmpty : std_logic; signal FlagFull : std_logic; --signal ReUse : std_logic; --signal Lock : std_logic; ---signal RstMem : std_logic; +signal RstMem : std_logic; signal DataIn : std_logic_vector(Data_sz-1 downto 0); signal DataOut : std_logic_vector(Data_sz-1 downto 0); signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); @@ -73,12 +73,12 @@ begin APB : ApbDriver generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); + port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); DEVICE : Top_FIFO generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); + port map(clk,rst,ReadEnable,WriteEnable,RstMem,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); Empty <= FlagEmpty; Full <= FlagFull; diff --git a/lib/lpp/lpp_memory/APB_FifoRead.vhd b/lib/lpp/lpp_memory/APB_FifoRead.vhd --- a/lib/lpp/lpp_memory/APB_FifoRead.vhd +++ b/lib/lpp/lpp_memory/APB_FifoRead.vhd @@ -51,6 +51,7 @@ entity APB_FifoRead is Full : out std_logic; --! Flag, Memoire pleine Empty : out std_logic; --! Flag, Memoire vide DATA : in std_logic_vector(Data_sz-1 downto 0); --! Données en entrée de la mémoire + dataTEST : out std_logic_vector(Data_sz-1 downto 0); apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); end APB_FifoRead; @@ -65,7 +66,7 @@ signal FlagEmpty : std_logic; signal FlagFull : std_logic; --signal ReUse : std_logic; --signal Lock : std_logic; ---signal RstMem : std_logic; +signal RstMem : std_logic; signal DataIn : std_logic_vector(Data_sz-1 downto 0); signal DataOut : std_logic_vector(Data_sz-1 downto 0); signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); @@ -75,15 +76,16 @@ begin APB : ApbDriver generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); + port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); FIFO : Top_FIFO generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); + port map(clk,rst,ReadEnable,WriteEnable,RstMem,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); Empty <= FlagEmpty; Full <= FlagFull; RE <= ReadEnable; +dataTEST <= DataOut; end ar_APB_FifoRead; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/APB_FifoWrite.vhd b/lib/lpp/lpp_memory/APB_FifoWrite.vhd --- a/lib/lpp/lpp_memory/APB_FifoWrite.vhd +++ b/lib/lpp/lpp_memory/APB_FifoWrite.vhd @@ -64,7 +64,7 @@ signal FlagEmpty : std_logic; signal FlagFull : std_logic; --signal ReUse : std_logic; --signal Lock : std_logic; ---signal RstMem : std_logic; +signal RstMem : std_logic; signal DataIn : std_logic_vector(Data_sz-1 downto 0); signal DataOut : std_logic_vector(Data_sz-1 downto 0); signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); @@ -74,12 +74,12 @@ begin APB : ApbDriver generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); + port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); FIFO : Top_FIFO generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); + port map(clk,rst,ReadEnable,WriteEnable,RstMem,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); DATA <= DataOut; Empty <= FlagEmpty; diff --git a/lib/lpp/lpp_memory/ApbDriver.vhd b/lib/lpp/lpp_memory/ApbDriver.vhd --- a/lib/lpp/lpp_memory/ApbDriver.vhd +++ b/lib/lpp/lpp_memory/ApbDriver.vhd @@ -51,7 +51,7 @@ entity ApbDriver is FlagFull : in std_logic; --! Flag, Mémoire pleine -- ReUse : out std_logic; --! Flag, Permet de relire la mémoire en boucle sans nouvelle données -- Lock : out std_logic; --! Flag, Permet de bloquer l'écriture dans la mémoire --- RstMem : out std_logic; --! Flag, Reset "manuel" spécifique au composant + RstMem : out std_logic; --! Flag, Reset "manuel" spécifique au composant DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de données en entrée DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de données en sortie AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (écriture) @@ -72,7 +72,7 @@ constant pconfig : apb_config_type := ( 1 => apb_iobar(paddr, pmask)); type DEVICE_ctrlr_Reg is record - DEVICE_Cfg : std_logic_vector(3 downto 0); + DEVICE_Cfg : std_logic_vector(4 downto 0); DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); @@ -87,13 +87,13 @@ signal FlagWR : std_logic; begin -Rec.DEVICE_Cfg(0) <= FlagRE; +Rec.DEVICE_Cfg(2) <= FlagRE; Rec.DEVICE_Cfg(1) <= FlagWR; -Rec.DEVICE_Cfg(2) <= FlagEmpty; -Rec.DEVICE_Cfg(3) <= FlagFull; +Rec.DEVICE_Cfg(3) <= FlagEmpty; +Rec.DEVICE_Cfg(4) <= FlagFull; --ReUse <= Rec.DEVICE_Cfg(4); --Lock <= Rec.DEVICE_Cfg(5); ---RstMem <= Rec.DEVICE_Cfg(7); +RstMem <= Rec.DEVICE_Cfg(0); DataIn <= Rec.DEVICE_DataW; Rec.DEVICE_DataR <= DataOut; @@ -108,7 +108,7 @@ Rec.DEVICE_AddrR <= AddrOut; Rec.DEVICE_DataW <= (others => '0'); FlagWR <= '0'; FlagRE <= '0'; --- Rec.DEVICE_Cfg(4) <= '0'; + Rec.DEVICE_Cfg(0) <= '0'; -- Rec.DEVICE_Cfg(5) <= '0'; -- Rec.DEVICE_Cfg(7) <= '0'; @@ -120,8 +120,8 @@ Rec.DEVICE_AddrR <= AddrOut; when "000000" => FlagWR <= '1'; Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); --- when "000010" => --- Rec.DEVICE_Cfg(7) <= apbi.pwdata(28); + when "000010" => + Rec.DEVICE_Cfg(0) <= apbi.pwdata(0); -- Rec.DEVICE_Cfg(5) <= apbi.pwdata(20); -- Rec.DEVICE_Cfg(6) <= apbi.pwdata(24); when others => @@ -150,11 +150,11 @@ Rec.DEVICE_AddrR <= AddrOut; Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); --- Rdata(27 downto 16) <= X"000"; + Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); -- Rdata(31 downto 28) <= "000" & Rec.DEVICE_Cfg(7); -- Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5); -- Rdata(27 downto 24) <= "000" & Rec.DEVICE_Cfg(6); - Rdata(31 downto 16) <= X"CCCC"; + Rdata(31 downto 20) <= X"CCC"; when others => Rdata <= (others => '0'); end case; diff --git a/lib/lpp/lpp_memory/Fifo_Read.vhd b/lib/lpp/lpp_memory/Fifo_Read.vhd --- a/lib/lpp/lpp_memory/Fifo_Read.vhd +++ b/lib/lpp/lpp_memory/Fifo_Read.vhd @@ -32,6 +32,7 @@ generic( port( clk,raz : in std_logic; --! Horloge et reset general du composant flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire +-- flag_WR : in std_logic; -- ReUse : in std_logic; --! Flag, Permet de relire la mémoire du début Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'écriture dans la mémoire empty : out std_logic; --! Flag, Mémoire vide @@ -47,48 +48,54 @@ signal Rad_int : integer range 0 to signal Rad_int_reg : integer range 0 to addr_max_int; signal Wad_int : integer range 0 to addr_max_int; signal Wad_int_reg : integer range 0 to addr_max_int; -signal flag_reg : std_logic; +signal s_empty : std_logic; begin process (clk,raz) begin if(raz='0')then - Rad_int <= 0; - empty <= '1'; - flag_reg <= '0'; + Rad_int <= 0; + s_empty <= '1'; elsif(clk' event and clk='1')then Wad_int_reg <= Wad_int; Rad_int_reg <= Rad_int; - flag_reg <= flag_RE; - if(flag_reg ='0' and flag_RE='1')then - if(Rad_int=addr_max_int-1)then - Rad_int <= 0; - else - Rad_int <= Rad_int+1; + if(flag_RE='1')then + + if(s_empty = '0')then + if(Rad_int=addr_max_int-1)then + Rad_int <= 0; +-- elsif(Rad_int=Wad_int-1)then +-- Rad_int <= Rad_int+1; +-- s_empty <= '1'; + else + Rad_int <= Rad_int+1; + end if; + end if; + + if(Rad_int=Wad_int-1)then + s_empty <= '1'; + elsif(Rad_int=addr_max_int-1 and Wad_int=0)then + s_empty <= '1'; + end if; + + end if; + + + if(Wad_int_reg /= Wad_int)then + if(s_empty='1')then + s_empty <= '0'; end if; end if; + + end if; --- if(ReUse='1')then --- empty <= '0'; --- else - if(Rad_int_reg /= Rad_int)then - if(Rad_int=Wad_int)then - empty <= '1'; - else - empty <= '0'; - end if; - elsif(Wad_int_reg /= Wad_int)then - empty <= '0'; - end if; - end if; - --- end if; end process; Wad_int <= to_integer(unsigned(Waddr)); Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz)); +empty <= s_empty; end ar_Fifo_Read; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/Fifo_Write.vhd b/lib/lpp/lpp_memory/Fifo_Write.vhd --- a/lib/lpp/lpp_memory/Fifo_Write.vhd +++ b/lib/lpp/lpp_memory/Fifo_Write.vhd @@ -32,6 +32,7 @@ generic( port( clk,raz : in std_logic; --! Horloge et reset general du composant flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire +-- flag_RE : in std_logic; Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la mémoire full : out std_logic; --! Flag, Mémoire pleine Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'écriture dans la mémoire @@ -46,38 +47,44 @@ signal Wad_int : integer range 0 to signal Wad_int_reg : integer range 0 to addr_max_int; signal Rad_int : integer range 0 to addr_max_int; signal Rad_int_reg : integer range 0 to addr_max_int; -signal flag_reg : std_logic; +signal s_full : std_logic; begin process (clk,raz) begin if(raz='0')then Wad_int <= 0; - full <= '0'; - flag_reg <= '0'; - + s_full <= '0'; + elsif(clk' event and clk='1')then Wad_int_reg <= Wad_int; - Rad_int_reg <= Rad_int; - flag_reg <= flag_WR; - + Rad_int_reg <= Rad_int; + + if(flag_WR='1')then - if(flag_reg ='0' and flag_WR='1')then - if(Wad_int=addr_max_int-1)then - Wad_int <= 0; - else - Wad_int <= Wad_int+1; + if(s_full = '0')then + if(Wad_int=addr_max_int-1)then + Wad_int <= 0; +-- elsif(Wad_int=Rad_int-1)then +-- Wad_int <= Wad_int+1; +-- s_full <= '1'; + else + Wad_int <= Wad_int+1; + end if; end if; + + if(Wad_int=Rad_int-1)then + s_full <= '1'; + elsif(Wad_int=addr_max_int-1 and Rad_int=0)then + s_full <= '1'; + end if; + end if; - if(Wad_int_reg /= Wad_int)then - if(Wad_int=Rad_int)then - full <= '1'; - else - full <= '0'; + if(Rad_int_reg /= Rad_int)then + if(s_full='1')then + s_full <= '0'; end if; - elsif(Rad_int_reg /= Rad_int)then - full <= '0'; end if; end if; @@ -85,5 +92,6 @@ begin Rad_int <= to_integer(unsigned(Raddr)); Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz)); +full <= s_full; end ar_Fifo_Write; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/LocalReset.vhd b/lib/lpp/lpp_memory/LocalReset.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/LocalReset.vhd @@ -0,0 +1,70 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, Write_int to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity LocalReset is + port( + clk : in std_logic; + raz : in std_logic; + Rz : in std_logic; + rstf : out std_logic + ); +end LocalReset; + + +architecture ar_LocalReset of LocalReset is + +signal Rz_reg : std_logic; + +type state is (st0); +signal ect : state; + +begin + process(clk,raz) + begin + + if(raz='0')then + rstf <= '0'; + ect <= st0; + + elsif(clk'event and clk='1')then + Rz_reg <= Rz; + + case ect is + + when st0 => + rstf <= '1'; + if(Rz_reg='0' and Rz='1')then + rstf <= '0'; + ect <= st0; + elsif(Rz_reg='1' and Rz='0')then + rstf <= '0'; + ect <= st0; + end if; + + end case; + end if; + end process; + +end ar_LocalReset; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/Pipeline.vhd b/lib/lpp/lpp_memory/Pipeline.vhd --- a/lib/lpp/lpp_memory/Pipeline.vhd +++ b/lib/lpp/lpp_memory/Pipeline.vhd @@ -22,71 +22,78 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; +use work.FIFO_Config.all; --! Programme qui va permettre de "pipeliner" la FIFO, donnée disponible en sortie dé son écriture en entrée de la FIFO -entity Pipeline is +entity PipeLine is generic(Data_sz : integer := 16); port( clk,raz : in std_logic; --! Horloge et reset general du composant - Data_one : in std_logic_vector(Data_sz-1 downto 0); --! Donnée en entrée de la FIFO, coté écriture - Data_two : in std_logic_vector(Data_sz-1 downto 0); --! Donnée en sortie de la FIFO, coté lecture --- ReUse : in std_logic; --! Flag, Permet de relire la mémoire du début + Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Donnée en entrée de la FIFO, coté écriture flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire empty : in std_logic; --! Flag, Mémoire vide - Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Donnée en sortie, pipelinée + Data_svg : out std_logic_vector(Data_sz-1 downto 0); + Data1 : out std_logic; + Data2 : out std_logic ); -end Pipeline; +end PipeLine; -architecture ar_Pipeline of Pipeline is +architecture ar_PipeLine of PipeLine is -type etat is (e0,e1,e2,eX); +type etat is (e0,e1,e2,st0,st1,st2); signal ect : etat; begin process (clk,raz) begin if(raz='0')then - Data_out <= (others => 'X'); + Data1 <= '0'; + Data2 <= '0'; ect <= e0; elsif(clk' event and clk='1')then + Data_svg <= Data_in; + case ect is when e0 => + Data2 <= '0'; if(flag_WR='1')then - Data_out <= Data_one; - ect <= e1; - -- elsif(ReUse='1')then - -- ect <= e1; + Data1 <= '1'; + ect <= st2; end if; - when e1 => + when st2 => + Data1 <= '0'; + ect <= e1; + + when e1 => if(flag_RE='1')then - --Data_out <= Data_two; - ect <= eX; - end if; + ect <= st0; + end if; - when eX => - --Data_out <= Data_two; - ect <= e2; + when st0 => + ect <= st1; - when e2 => - Data_out <= Data_two; + when st1 => + Data2 <= '1'; + ect <= e2; + + + when e2 => if(empty='1')then ect <= e0; else - --Data_out <= Data_two; ect <= e2; end if; - end case; end if; end process; -end ar_Pipeline; +end ar_PipeLine; diff --git a/lib/lpp/lpp_memory/Top_FIFO.vhd b/lib/lpp/lpp_memory/Top_FIFO.vhd --- a/lib/lpp/lpp_memory/Top_FIFO.vhd +++ b/lib/lpp/lpp_memory/Top_FIFO.vhd @@ -39,9 +39,7 @@ entity Top_FIFO is clk,raz : in std_logic; --! Horloge et reset general du composant flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire --- ReUse : in std_logic; --! Flag, Permet de relire la mémoire en boucle sans nouvelle données --- Lock : in std_logic; --! Permet de bloquer l'écriture dans la mémoire --- RstMem : in std_logic; --! Flag, Reset "manuel" spécifique au composant + RstMem : in std_logic; Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrée du composant Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'écriture Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture @@ -72,78 +70,49 @@ end component; signal Raddr : std_logic_vector(addr_sz-1 downto 0); signal Waddr : std_logic_vector(addr_sz-1 downto 0); signal Data_int : std_logic_vector(Data_sz-1 downto 0); +signal Data_svg : std_logic_vector(Data_sz-1 downto 0); signal s_empty : std_logic; signal s_full : std_logic; ---signal s_full2 : std_logic; +signal Data1 : std_logic; +signal Data2 : std_logic; signal s_flag_RE : std_logic; signal s_flag_WR : std_logic; -signal Flag_WR_reg : std_logic; ---signal rst : std_logic; ---signal RstMem_inv : std_logic; +signal rstf : std_logic; begin ---RstMem_inv <= not RstMem; ---rst <= raz and RstMem_inv; + Reset : entity LocalReset + port map(clk,raz,RstMem,rstf); - WR : Fifo_Write - generic map(Addr_sz,addr_max_int) - port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr); - + WR : entity Fifo_Write + generic map(Addr_sz,addr_max_int) + port map(clk,rstf,s_flag_WR,Raddr,s_full,Waddr); SRAM : syncram_2p - generic map(CFG_MEMTECH,Addr_sz,Data_sz) - port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in); - + generic map(CFG_MEMTECH,Addr_sz,Data_sz) + port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in); + + RE : entity Fifo_Read + generic map(Addr_sz,addr_max_int) + port map(clk,rstf,s_flag_RE,Waddr,s_empty,Raddr); - Pipe : Pipeline - generic map(Data_sz) - port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out); + PIPE : entity PipeLine + generic map(Data_sz) + port map(clk,rstf,Data_in,s_flag_RE,s_flag_WR,s_empty,Data_svg,Data1,Data2); - RE : Fifo_Read - generic map(Addr_sz,addr_max_int) - port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr); - - process(clk,raz) - begin - if(raz='0')then - s_flag_RE <= '0'; - s_flag_WR <= '0'; --- s_full2 <= s_full; - Flag_WR_reg <= '0'; - - elsif(clk'event and clk='1')then - Flag_WR_reg <= Flag_WR; +Data_out <= Data_svg when Data1='1' else + Data_int when Data2='1'; - if(s_full='0')then --2 - if(s_empty='1')then - s_flag_WR <= Flag_WR_reg; - else - s_flag_WR <= Flag_WR; - end if; - else - s_flag_WR <= '0'; - end if; - - if(s_empty='0')then - s_flag_RE <= Flag_RE; - else - s_flag_RE <= '0'; - end if; - --- if(Lock='1')then --- s_full2 <= '1'; --- else --- s_full2 <= s_full; --- end if; - - end if; - end process; - -full <= s_full; --2 +full <= s_full; empty <= s_empty; Addr_RE <= Raddr; Addr_WR <= Waddr; +s_flag_WR <= Flag_WR when s_full='0' else + '0'; + +s_flag_RE <= Flag_RE when s_empty='0' else + '0'; + end ar_Top_FIFO; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -78,7 +78,7 @@ component ApbDriver is FlagFull : in std_logic; -- ReUse : out std_logic; -- Lock : out std_logic; --- RstMem : out std_logic; + RstMem : out std_logic; DataIn : out std_logic_vector(Data_sz-1 downto 0); DataOut : in std_logic_vector(Data_sz-1 downto 0); AddrIn : in std_logic_vector(Addr_sz-1 downto 0); @@ -92,7 +92,7 @@ end component; component Top_FIFO is generic( Data_sz : integer := 16; - Addr_sz : integer := 8; + Addr_sz : integer := 8; addr_max_int : integer := 256 ); port( @@ -101,7 +101,7 @@ component Top_FIFO is flag_WR : in std_logic; -- ReUse : in std_logic; -- Lock : in std_logic; --- RstMem : in std_logic; + RstMem : in std_logic; Data_in : in std_logic_vector(Data_sz-1 downto 0); Addr_RE : out std_logic_vector(addr_sz-1 downto 0); Addr_WR : out std_logic_vector(addr_sz-1 downto 0); @@ -120,7 +120,6 @@ component Fifo_Read is clk : in std_logic; raz : in std_logic; flag_RE : in std_logic; --- ReUse : in std_logic; Waddr : in std_logic_vector(addr_sz-1 downto 0); empty : out std_logic; Raddr : out std_logic_vector(addr_sz-1 downto 0) @@ -143,20 +142,29 @@ component Fifo_Write is end component; -component Pipeline is +component PipeLine is generic(Data_sz : integer := 16); port( - clk,raz : in std_logic; - Data_one : in std_logic_vector(Data_sz-1 downto 0); - Data_two : in std_logic_vector(Data_sz-1 downto 0); --- ReUse : in std_logic; - flag_RE : in std_logic; - flag_WR : in std_logic; - empty : in std_logic; - Data_out : out std_logic_vector(Data_sz-1 downto 0) + clk,raz : in std_logic; --! Horloge et reset general du composant + Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Donnée en entrée de la FIFO, coté écriture + flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire + flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire + empty : in std_logic; --! Flag, Mémoire vide + Data_svg : out std_logic_vector(Data_sz-1 downto 0); + Data1 : out std_logic; + Data2 : out std_logic ); end component; + +component LocalReset is + port( + clk : in std_logic; + raz : in std_logic; + Rz : in std_logic; + rstf : out std_logic + ); +end component; --===========================================================| --================= Demi FIFO Ecriture ======================| --===========================================================| @@ -226,6 +234,7 @@ component APB_FifoRead is Full : out std_logic; Empty : out std_logic; DATA : in std_logic_vector(Data_sz-1 downto 0); + dataTEST : out std_logic_vector(Data_sz-1 downto 0); apbo : out apb_slv_out_type ); end component;