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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.FIFO_Config.all;
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--! Programme qui va permettre de "pipeliner" la FIFO, donn�e disponible en sortie d� son �criture en entr�e de la FIFO
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entity PipeLine is
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generic(Data_sz : integer := 16);
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port(
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clk,raz : in std_logic; --! Horloge et reset general du composant
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Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Donn�e en entr�e de la FIFO, cot� �criture
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flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
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flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
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empty : in std_logic; --! Flag, M�moire vide
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Data_svg : out std_logic_vector(Data_sz-1 downto 0);
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Data1 : out std_logic;
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Data2 : out std_logic
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);
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end PipeLine;
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architecture ar_PipeLine of PipeLine is
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type etat is (e0,e1,e2,st0,st1,st2);
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signal ect : etat;
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begin
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process (clk,raz)
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begin
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if(raz='0')then
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Data1 <= '0';
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Data2 <= '0';
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ect <= e0;
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elsif(clk' event and clk='1')then
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Data_svg <= Data_in;
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case ect is
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when e0 =>
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Data2 <= '0';
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if(flag_WR='1')then
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Data1 <= '1';
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ect <= st2;
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end if;
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when st2 =>
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Data1 <= '0';
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ect <= e1;
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when e1 =>
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if(flag_RE='1')then
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ect <= st0;
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end if;
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when st0 =>
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ect <= st1;
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when st1 =>
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Data2 <= '1';
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ect <= e2;
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when e2 =>
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if(empty='1')then
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ect <= e0;
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else
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ect <= e2;
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end if;
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end case;
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end if;
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end process;
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end ar_PipeLine;
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