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modif APB_fifo
modif APB_fifo
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Pipeline.vhd
115 lines | 3.5 KiB | text/x-vhdl | VhdlLexer
/ lib / lpp / lpp_memory / Pipeline.vhd
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martin
update delay function
 r87 ------------------------------------------------------------------------------
-- This file is a part of the LPP VHDL IP LIBRARY
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Author : Martin Morlot
-- Mail : martin.morlot@lpp.polytechnique.fr
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
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modif APB_fifo
 r91 use work.FIFO_Config.all;
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update delay function
 r87
--! Programme qui va permettre de "pipeliner" la FIFO, donn�e disponible en sortie d� son �criture en entr�e de la FIFO
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modif APB_fifo
 r91 entity PipeLine is
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update delay function
 r87 generic(Data_sz : integer := 16);
port(
clk,raz : in std_logic; --! Horloge et reset general du composant
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modif APB_fifo
 r91 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Donn�e en entr�e de la FIFO, cot� �criture
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update delay function
 r87 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
empty : in std_logic; --! Flag, M�moire vide
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modif APB_fifo
 r91 Data_svg : out std_logic_vector(Data_sz-1 downto 0);
Data1 : out std_logic;
Data2 : out std_logic
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update delay function
 r87 );
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modif APB_fifo
 r91 end PipeLine;
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update delay function
 r87
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modif APB_fifo
 r91 architecture ar_PipeLine of PipeLine is
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update delay function
 r87
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modif APB_fifo
 r91 type etat is (e0,e1,e2,st0,st1,st2);
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update delay function
 r87 signal ect : etat;
begin
process (clk,raz)
begin
if(raz='0')then
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modif APB_fifo
 r91 Data1 <= '0';
Data2 <= '0';
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update delay function
 r87 ect <= e0;
elsif(clk' event and clk='1')then
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modif APB_fifo
 r91 Data_svg <= Data_in;
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update delay function
 r87 case ect is
when e0 =>
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modif APB_fifo
 r91 Data2 <= '0';
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update delay function
 r87 if(flag_WR='1')then
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modif APB_fifo
 r91 Data1 <= '1';
ect <= st2;
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update delay function
 r87 end if;
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modif APB_fifo
 r91 when st2 =>
Data1 <= '0';
ect <= e1;
when e1 =>
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update delay function
 r87 if(flag_RE='1')then
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modif APB_fifo
 r91 ect <= st0;
end if;
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update delay function
 r87
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modif APB_fifo
 r91 when st0 =>
ect <= st1;
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update delay function
 r87
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modif APB_fifo
 r91 when st1 =>
Data2 <= '1';
ect <= e2;
when e2 =>
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update delay function
 r87 if(empty='1')then
ect <= e0;
else
ect <= e2;
end if;
end case;
end if;
end process;
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modif APB_fifo
 r91 end ar_PipeLine;
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update delay function
 r87