@@ -0,0 +1,70 | |||
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1 | ------------------------------------------------------------------------------ | |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
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8 | -- (at your option) any later version. | |
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9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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13 | -- GNU General Public License for more details. | |
|
14 | -- | |
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15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, Write_int to the Free Software | |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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18 | ------------------------------------------------------------------------------- | |
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19 | -- Author : Martin Morlot | |
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20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
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21 | ------------------------------------------------------------------------------- | |
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22 | library IEEE; | |
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23 | use IEEE.numeric_std.all; | |
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24 | use IEEE.std_logic_1164.all; | |
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25 | ||
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26 | entity LocalReset is | |
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27 | port( | |
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28 | clk : in std_logic; | |
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29 | raz : in std_logic; | |
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30 | Rz : in std_logic; | |
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31 | rstf : out std_logic | |
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32 | ); | |
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33 | end LocalReset; | |
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34 | ||
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35 | ||
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36 | architecture ar_LocalReset of LocalReset is | |
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37 | ||
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38 | signal Rz_reg : std_logic; | |
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39 | ||
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40 | type state is (st0); | |
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41 | signal ect : state; | |
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42 | ||
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43 | begin | |
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44 | process(clk,raz) | |
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45 | begin | |
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46 | ||
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47 | if(raz='0')then | |
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48 | rstf <= '0'; | |
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49 | ect <= st0; | |
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50 | ||
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51 | elsif(clk'event and clk='1')then | |
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52 | Rz_reg <= Rz; | |
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53 | ||
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54 | case ect is | |
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55 | ||
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56 | when st0 => | |
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57 | rstf <= '1'; | |
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58 | if(Rz_reg='0' and Rz='1')then | |
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59 | rstf <= '0'; | |
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60 | ect <= st0; | |
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61 | elsif(Rz_reg='1' and Rz='0')then | |
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62 | rstf <= '0'; | |
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63 | ect <= st0; | |
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64 | end if; | |
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65 | ||
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66 | end case; | |
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67 | end if; | |
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68 | end process; | |
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69 | ||
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70 | end ar_LocalReset; No newline at end of file |
@@ -52,13 +52,14 entity APB_Matrix is | |||
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52 | 52 | WriteFIFO : out std_logic; |
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53 | 53 | Result : out std_logic_vector(Result_SZ-1 downto 0); |
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54 | 54 | Start : out std_logic; |
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55 |
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56 |
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57 |
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55 | Read : out std_logic; | |
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56 | Take : out std_logic; | |
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57 | Valid : out std_logic; | |
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58 | Received : out std_logic; | |
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58 | 59 | Res : out std_logic_vector(Result_SZ-1 downto 0); |
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59 | 60 | -- Conjugate : out std_logic; |
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60 |
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61 |
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61 | OP1 : out std_logic_vector(3 downto 0); | |
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62 | OP2 : out std_logic_vector(3 downto 0); | |
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62 | 63 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus |
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63 | 64 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
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64 | 65 | ); |
@@ -84,7 +85,7 begin | |||
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84 | 85 | |
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85 | 86 | Mspec0 : SpectralMatrix |
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86 | 87 | generic map (Input_SZ,Result_SZ) |
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87 | port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Res,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2 | |
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88 | port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Read,Take,Valid,Received,Res,OP1,OP2,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2 | |
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88 | 89 | |
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89 | 90 | process(rst,clk) |
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90 | 91 | begin |
@@ -39,8 +39,8 entity Matrix is | |||
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39 | 39 | Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu� |
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40 | 40 | Valid : out std_logic; --! Flag, R�sultat disponible |
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41 | 41 | Read : out std_logic; --! Flag, op�rande disponible |
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42 |
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43 |
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42 | OPin1 : out std_logic_vector(3 downto 0); | |
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43 | OPin2 : out std_logic_vector(3 downto 0); | |
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44 | 44 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! R�sultat du calcul |
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45 | 45 | ); |
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46 | 46 | end Matrix; |
@@ -53,8 +53,8 signal OP1 : std_logic_vector(Input_SZ | |||
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53 | 53 | signal OP2 : std_logic_vector(Input_SZ-1 downto 0); |
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54 | 54 | |
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55 | 55 | begin |
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56 |
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57 |
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56 | OPin1 <= OP1(3 downto 0); | |
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57 | OPin2 <= OP1(3 downto 0); | |
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58 | 58 | |
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59 | 59 | |
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60 | 60 | DRIVE : ALU_Driver |
@@ -39,14 +39,14 port( | |||
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39 | 39 | ReadFIFO : out std_logic_vector(1 downto 0); |
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40 | 40 | WriteFIFO : out std_logic; |
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41 | 41 | Start : out std_logic; |
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42 |
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43 |
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44 |
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45 | Res : out std_logic_vector(Result_SZ-1 downto 0); | |
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46 | -- Received : out std_logic; | |
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42 | Read : out std_logic; | |
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43 | Take : out std_logic; | |
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44 | Valid : out std_logic; | |
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45 | Received : out std_logic; | |
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46 | Res : out std_logic_vector(Result_SZ-1 downto 0); | |
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47 | 47 | -- Conjugate : out std_logic; |
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48 |
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49 |
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48 | OP1 : out std_logic_vector(3 downto 0); | |
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49 | OP2 : out std_logic_vector(3 downto 0); | |
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50 | 50 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
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51 | 51 | ); |
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52 | 52 | end SpectralMatrix; |
@@ -82,7 +82,7 IN1 : DriveInputs | |||
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82 | 82 | |
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83 | 83 | CALC0 : Matrix |
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84 | 84 | generic map(Input_SZ) |
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85 | port map(clk,Start_int,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat); | |
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85 | port map(clk,Start_int,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,OP1,OP2,Resultat); | |
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86 | 86 | |
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87 | 87 | |
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88 | 88 | RES0 : GetResult |
@@ -99,10 +99,10 With Statu select | |||
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99 | 99 | '0' when others; |
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100 | 100 | |
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101 | 101 | Start <= Start_int; |
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102 |
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103 |
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104 |
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105 |
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102 | Read <= Read_int; | |
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103 | Take <= Take_int; | |
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104 | Received <= Received_int; | |
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105 | Valid <= Valid_int; | |
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106 | 106 | --Conjugate <= Conjugate_int; |
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107 | 107 | Res <= Resultat; |
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108 | 108 |
@@ -51,7 +51,14 component APB_Matrix is | |||
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51 | 51 | WriteFIFO : out std_logic; |
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52 | 52 | Result : out std_logic_vector(Result_SZ-1 downto 0); |
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53 | 53 | Start : out std_logic; |
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54 | Res : out std_logic_vector(Result_SZ-1 downto 0); | |
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54 | Read : out std_logic; | |
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55 | Take : out std_logic; | |
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56 | Valid : out std_logic; | |
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57 | Received : out std_logic; | |
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58 | Res : out std_logic_vector(Result_SZ-1 downto 0); | |
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59 | -- Conjugate : out std_logic; | |
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60 | OP1 : out std_logic_vector(3 downto 0); | |
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61 | OP2 : out std_logic_vector(3 downto 0); | |
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55 | 62 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus |
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56 | 63 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
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57 | 64 | ); |
@@ -72,8 +79,15 port( | |||
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72 | 79 | Statu : in std_logic_vector(3 downto 0); |
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73 | 80 | ReadFIFO : out std_logic_vector(1 downto 0); |
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74 | 81 | WriteFIFO : out std_logic; |
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75 | Start : out std_logic; | |
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82 | Start : out std_logic; | |
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83 | Read : out std_logic; | |
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84 | Take : out std_logic; | |
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85 | Valid : out std_logic; | |
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86 | Received : out std_logic; | |
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76 | 87 | Res : out std_logic_vector(Result_SZ-1 downto 0); |
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88 | -- Conjugate : out std_logic; | |
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89 | OP1 : out std_logic_vector(3 downto 0); | |
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90 | OP2 : out std_logic_vector(3 downto 0); | |
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77 | 91 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
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78 | 92 | ); |
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79 | 93 | end component; |
@@ -92,6 +106,8 component Matrix is | |||
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92 | 106 | Conjugate : in std_logic; |
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93 | 107 | Valid : out std_logic; |
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94 | 108 | Read : out std_logic; |
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109 | OPin1 : out std_logic_vector(3 downto 0); | |
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110 | OPin2 : out std_logic_vector(3 downto 0); | |
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95 | 111 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) |
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96 | 112 | ); |
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97 | 113 | end component; |
@@ -63,7 +63,7 signal FlagEmpty : std_logic; | |||
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63 | 63 | signal FlagFull : std_logic; |
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64 | 64 | --signal ReUse : std_logic; |
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65 | 65 | --signal Lock : std_logic; |
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66 |
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66 | signal RstMem : std_logic; | |
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67 | 67 | signal DataIn : std_logic_vector(Data_sz-1 downto 0); |
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68 | 68 | signal DataOut : std_logic_vector(Data_sz-1 downto 0); |
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69 | 69 | signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); |
@@ -73,12 +73,12 begin | |||
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73 | 73 | |
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74 | 74 | APB : ApbDriver |
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75 | 75 | generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) |
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76 | port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); | |
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76 | port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); | |
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77 | 77 | |
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78 | 78 | |
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79 | 79 | DEVICE : Top_FIFO |
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80 | 80 | generic map(Data_sz,Addr_sz,addr_max_int) |
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81 | port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); | |
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81 | port map(clk,rst,ReadEnable,WriteEnable,RstMem,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); | |
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82 | 82 | |
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83 | 83 | Empty <= FlagEmpty; |
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84 | 84 | Full <= FlagFull; |
@@ -51,6 +51,7 entity APB_FifoRead is | |||
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51 | 51 | Full : out std_logic; --! Flag, Memoire pleine |
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52 | 52 | Empty : out std_logic; --! Flag, Memoire vide |
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53 | 53 | DATA : in std_logic_vector(Data_sz-1 downto 0); --! Donn�es en entr�e de la m�moire |
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54 | dataTEST : out std_logic_vector(Data_sz-1 downto 0); | |
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54 | 55 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
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55 | 56 | ); |
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56 | 57 | end APB_FifoRead; |
@@ -65,7 +66,7 signal FlagEmpty : std_logic; | |||
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65 | 66 | signal FlagFull : std_logic; |
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66 | 67 | --signal ReUse : std_logic; |
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67 | 68 | --signal Lock : std_logic; |
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68 |
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69 | signal RstMem : std_logic; | |
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69 | 70 | signal DataIn : std_logic_vector(Data_sz-1 downto 0); |
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70 | 71 | signal DataOut : std_logic_vector(Data_sz-1 downto 0); |
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71 | 72 | signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); |
@@ -75,15 +76,16 begin | |||
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75 | 76 | |
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76 | 77 | APB : ApbDriver |
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77 | 78 | generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) |
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78 | port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); | |
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79 | port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); | |
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79 | 80 | |
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80 | 81 | |
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81 | 82 | FIFO : Top_FIFO |
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82 | 83 | generic map(Data_sz,Addr_sz,addr_max_int) |
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83 | port map(clk,rst,ReadEnable,WriteEnable,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); | |
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84 | port map(clk,rst,ReadEnable,WriteEnable,RstMem,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); | |
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84 | 85 | |
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85 | 86 | Empty <= FlagEmpty; |
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86 | 87 | Full <= FlagFull; |
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87 | 88 | RE <= ReadEnable; |
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89 | dataTEST <= DataOut; | |
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88 | 90 | |
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89 | 91 | end ar_APB_FifoRead; No newline at end of file |
@@ -64,7 +64,7 signal FlagEmpty : std_logic; | |||
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64 | 64 | signal FlagFull : std_logic; |
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65 | 65 | --signal ReUse : std_logic; |
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66 | 66 | --signal Lock : std_logic; |
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67 |
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67 | signal RstMem : std_logic; | |
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68 | 68 | signal DataIn : std_logic_vector(Data_sz-1 downto 0); |
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69 | 69 | signal DataOut : std_logic_vector(Data_sz-1 downto 0); |
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70 | 70 | signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); |
@@ -74,12 +74,12 begin | |||
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74 | 74 | |
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75 | 75 | APB : ApbDriver |
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76 | 76 | generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) |
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77 | port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); | |
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77 | port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,RstMem,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); | |
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78 | 78 | |
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79 | 79 | |
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80 | 80 | FIFO : Top_FIFO |
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81 | 81 | generic map(Data_sz,Addr_sz,addr_max_int) |
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82 | port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); | |
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82 | port map(clk,rst,ReadEnable,WriteEnable,RstMem,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); | |
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83 | 83 | |
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84 | 84 | DATA <= DataOut; |
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85 | 85 | Empty <= FlagEmpty; |
@@ -51,7 +51,7 entity ApbDriver is | |||
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51 | 51 | FlagFull : in std_logic; --! Flag, M�moire pleine |
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52 | 52 | -- ReUse : out std_logic; --! Flag, Permet de relire la m�moire en boucle sans nouvelle donn�es |
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53 | 53 | -- Lock : out std_logic; --! Flag, Permet de bloquer l'�criture dans la m�moire |
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54 |
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54 | RstMem : out std_logic; --! Flag, Reset "manuel" sp�cifique au composant | |
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55 | 55 | DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e |
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56 | 56 | DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie |
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57 | 57 | AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture) |
@@ -72,7 +72,7 constant pconfig : apb_config_type := ( | |||
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72 | 72 | 1 => apb_iobar(paddr, pmask)); |
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73 | 73 | |
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74 | 74 | type DEVICE_ctrlr_Reg is record |
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75 |
DEVICE_Cfg : std_logic_vector( |
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75 | DEVICE_Cfg : std_logic_vector(4 downto 0); | |
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76 | 76 | DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); |
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77 | 77 | DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); |
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78 | 78 | DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); |
@@ -87,13 +87,13 signal FlagWR : std_logic; | |||
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87 | 87 | |
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88 | 88 | begin |
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89 | 89 | |
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90 |
Rec.DEVICE_Cfg( |
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90 | Rec.DEVICE_Cfg(2) <= FlagRE; | |
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91 | 91 | Rec.DEVICE_Cfg(1) <= FlagWR; |
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92 |
Rec.DEVICE_Cfg( |
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93 |
Rec.DEVICE_Cfg( |
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92 | Rec.DEVICE_Cfg(3) <= FlagEmpty; | |
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93 | Rec.DEVICE_Cfg(4) <= FlagFull; | |
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94 | 94 | --ReUse <= Rec.DEVICE_Cfg(4); |
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95 | 95 | --Lock <= Rec.DEVICE_Cfg(5); |
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96 |
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96 | RstMem <= Rec.DEVICE_Cfg(0); | |
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97 | 97 | |
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98 | 98 | DataIn <= Rec.DEVICE_DataW; |
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99 | 99 | Rec.DEVICE_DataR <= DataOut; |
@@ -108,7 +108,7 Rec.DEVICE_AddrR <= AddrOut; | |||
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108 | 108 | Rec.DEVICE_DataW <= (others => '0'); |
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109 | 109 | FlagWR <= '0'; |
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110 | 110 | FlagRE <= '0'; |
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111 |
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111 | Rec.DEVICE_Cfg(0) <= '0'; | |
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112 | 112 | -- Rec.DEVICE_Cfg(5) <= '0'; |
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113 | 113 | -- Rec.DEVICE_Cfg(7) <= '0'; |
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114 | 114 | |
@@ -120,8 +120,8 Rec.DEVICE_AddrR <= AddrOut; | |||
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120 | 120 | when "000000" => |
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121 | 121 | FlagWR <= '1'; |
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122 | 122 | Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); |
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123 |
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124 |
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123 | when "000010" => | |
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124 | Rec.DEVICE_Cfg(0) <= apbi.pwdata(0); | |
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125 | 125 | -- Rec.DEVICE_Cfg(5) <= apbi.pwdata(20); |
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126 | 126 | -- Rec.DEVICE_Cfg(6) <= apbi.pwdata(24); |
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127 | 127 | when others => |
@@ -150,11 +150,11 Rec.DEVICE_AddrR <= AddrOut; | |||
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150 | 150 | Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); |
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151 | 151 | Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); |
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152 | 152 | Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); |
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153 |
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153 | Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); | |
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154 | 154 | -- Rdata(31 downto 28) <= "000" & Rec.DEVICE_Cfg(7); |
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155 | 155 | -- Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5); |
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156 | 156 | -- Rdata(27 downto 24) <= "000" & Rec.DEVICE_Cfg(6); |
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157 |
Rdata(31 downto |
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157 | Rdata(31 downto 20) <= X"CCC"; | |
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158 | 158 | when others => |
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159 | 159 | Rdata <= (others => '0'); |
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160 | 160 | end case; |
@@ -32,6 +32,7 generic( | |||
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32 | 32 | port( |
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33 | 33 | clk,raz : in std_logic; --! Horloge et reset general du composant |
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34 | 34 | flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire |
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35 | -- flag_WR : in std_logic; | |
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35 | 36 | -- ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but |
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36 | 37 | Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire |
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37 | 38 | empty : out std_logic; --! Flag, M�moire vide |
@@ -47,48 +48,54 signal Rad_int : integer range 0 to | |||
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47 | 48 | signal Rad_int_reg : integer range 0 to addr_max_int; |
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48 | 49 | signal Wad_int : integer range 0 to addr_max_int; |
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49 | 50 | signal Wad_int_reg : integer range 0 to addr_max_int; |
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50 |
signal |
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51 | signal s_empty : std_logic; | |
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51 | 52 | |
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52 | 53 | begin |
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53 | 54 | process (clk,raz) |
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54 | 55 | begin |
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55 | 56 | if(raz='0')then |
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56 |
Rad_int |
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57 |
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58 | flag_reg <= '0'; | |
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57 | Rad_int <= 0; | |
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58 | s_empty <= '1'; | |
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59 | 59 | |
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60 | 60 | elsif(clk' event and clk='1')then |
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61 | 61 | Wad_int_reg <= Wad_int; |
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62 | 62 | Rad_int_reg <= Rad_int; |
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63 | flag_reg <= flag_RE; | |
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64 | 63 | |
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65 | 64 | |
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66 |
if( |
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67 | if(Rad_int=addr_max_int-1)then | |
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68 | Rad_int <= 0; | |
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69 | else | |
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70 |
Rad_int <= |
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65 | if(flag_RE='1')then | |
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66 | ||
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67 | if(s_empty = '0')then | |
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68 | if(Rad_int=addr_max_int-1)then | |
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69 | Rad_int <= 0; | |
|
70 | -- elsif(Rad_int=Wad_int-1)then | |
|
71 | -- Rad_int <= Rad_int+1; | |
|
72 | -- s_empty <= '1'; | |
|
73 | else | |
|
74 | Rad_int <= Rad_int+1; | |
|
75 | end if; | |
|
76 | end if; | |
|
77 | ||
|
78 | if(Rad_int=Wad_int-1)then | |
|
79 | s_empty <= '1'; | |
|
80 | elsif(Rad_int=addr_max_int-1 and Wad_int=0)then | |
|
81 | s_empty <= '1'; | |
|
82 | end if; | |
|
83 | ||
|
84 | end if; | |
|
85 | ||
|
86 | ||
|
87 | if(Wad_int_reg /= Wad_int)then | |
|
88 | if(s_empty='1')then | |
|
89 | s_empty <= '0'; | |
|
71 | 90 | end if; |
|
72 | 91 | end if; |
|
92 | ||
|
93 | end if; | |
|
73 | 94 | |
|
74 | -- if(ReUse='1')then | |
|
75 | -- empty <= '0'; | |
|
76 | -- else | |
|
77 | if(Rad_int_reg /= Rad_int)then | |
|
78 | if(Rad_int=Wad_int)then | |
|
79 | empty <= '1'; | |
|
80 | else | |
|
81 | empty <= '0'; | |
|
82 | end if; | |
|
83 | elsif(Wad_int_reg /= Wad_int)then | |
|
84 | empty <= '0'; | |
|
85 | end if; | |
|
86 | end if; | |
|
87 | ||
|
88 | -- end if; | |
|
89 | 95 | end process; |
|
90 | 96 | |
|
91 | 97 | Wad_int <= to_integer(unsigned(Waddr)); |
|
92 | 98 | Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz)); |
|
99 | empty <= s_empty; | |
|
93 | 100 | |
|
94 | 101 | end ar_Fifo_Read; No newline at end of file |
@@ -32,6 +32,7 generic( | |||
|
32 | 32 | port( |
|
33 | 33 | clk,raz : in std_logic; --! Horloge et reset general du composant |
|
34 | 34 | flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire |
|
35 | -- flag_RE : in std_logic; | |
|
35 | 36 | Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la m�moire |
|
36 | 37 | full : out std_logic; --! Flag, M�moire pleine |
|
37 | 38 | Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'�criture dans la m�moire |
@@ -46,38 +47,44 signal Wad_int : integer range 0 to | |||
|
46 | 47 | signal Wad_int_reg : integer range 0 to addr_max_int; |
|
47 | 48 | signal Rad_int : integer range 0 to addr_max_int; |
|
48 | 49 | signal Rad_int_reg : integer range 0 to addr_max_int; |
|
49 |
signal |
|
|
50 | signal s_full : std_logic; | |
|
50 | 51 | |
|
51 | 52 | begin |
|
52 | 53 | process (clk,raz) |
|
53 | 54 | begin |
|
54 | 55 | if(raz='0')then |
|
55 | 56 | Wad_int <= 0; |
|
56 | full <= '0'; | |
|
57 | flag_reg <= '0'; | |
|
58 | ||
|
57 | s_full <= '0'; | |
|
58 | ||
|
59 | 59 | elsif(clk' event and clk='1')then |
|
60 | 60 | Wad_int_reg <= Wad_int; |
|
61 | Rad_int_reg <= Rad_int; | |
|
62 | flag_reg <= flag_WR; | |
|
63 | ||
|
61 | Rad_int_reg <= Rad_int; | |
|
62 | ||
|
63 | if(flag_WR='1')then | |
|
64 | 64 | |
|
65 |
if( |
|
|
66 | if(Wad_int=addr_max_int-1)then | |
|
67 | Wad_int <= 0; | |
|
68 | else | |
|
69 | Wad_int <= Wad_int+1; | |
|
65 | if(s_full = '0')then | |
|
66 | if(Wad_int=addr_max_int-1)then | |
|
67 | Wad_int <= 0; | |
|
68 | -- elsif(Wad_int=Rad_int-1)then | |
|
69 | -- Wad_int <= Wad_int+1; | |
|
70 | -- s_full <= '1'; | |
|
71 | else | |
|
72 | Wad_int <= Wad_int+1; | |
|
73 | end if; | |
|
70 | 74 | end if; |
|
75 | ||
|
76 | if(Wad_int=Rad_int-1)then | |
|
77 | s_full <= '1'; | |
|
78 | elsif(Wad_int=addr_max_int-1 and Rad_int=0)then | |
|
79 | s_full <= '1'; | |
|
80 | end if; | |
|
81 | ||
|
71 | 82 | end if; |
|
72 | 83 | |
|
73 |
if( |
|
|
74 |
if( |
|
|
75 |
full <= ' |
|
|
76 | else | |
|
77 | full <= '0'; | |
|
84 | if(Rad_int_reg /= Rad_int)then | |
|
85 | if(s_full='1')then | |
|
86 | s_full <= '0'; | |
|
78 | 87 | end if; |
|
79 | elsif(Rad_int_reg /= Rad_int)then | |
|
80 | full <= '0'; | |
|
81 | 88 | end if; |
|
82 | 89 | |
|
83 | 90 | end if; |
@@ -85,5 +92,6 begin | |||
|
85 | 92 | |
|
86 | 93 | Rad_int <= to_integer(unsigned(Raddr)); |
|
87 | 94 | Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz)); |
|
95 | full <= s_full; | |
|
88 | 96 | |
|
89 | 97 | end ar_Fifo_Write; No newline at end of file |
@@ -22,71 +22,78 | |||
|
22 | 22 | library IEEE; |
|
23 | 23 | use IEEE.std_logic_1164.all; |
|
24 | 24 | use IEEE.numeric_std.all; |
|
25 | use work.FIFO_Config.all; | |
|
25 | 26 | |
|
26 | 27 | --! Programme qui va permettre de "pipeliner" la FIFO, donn�e disponible en sortie d� son �criture en entr�e de la FIFO |
|
27 | 28 | |
|
28 |
entity Pipe |
|
|
29 | entity PipeLine is | |
|
29 | 30 | generic(Data_sz : integer := 16); |
|
30 | 31 | port( |
|
31 | 32 | clk,raz : in std_logic; --! Horloge et reset general du composant |
|
32 |
Data_ |
|
|
33 | Data_two : in std_logic_vector(Data_sz-1 downto 0); --! Donn�e en sortie de la FIFO, cot� lecture | |
|
34 | -- ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but | |
|
33 | Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Donn�e en entr�e de la FIFO, cot� �criture | |
|
35 | 34 | flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire |
|
36 | 35 | flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire |
|
37 | 36 | empty : in std_logic; --! Flag, M�moire vide |
|
38 |
Data_ |
|
|
37 | Data_svg : out std_logic_vector(Data_sz-1 downto 0); | |
|
38 | Data1 : out std_logic; | |
|
39 | Data2 : out std_logic | |
|
39 | 40 |
|
|
40 |
end Pipe |
|
|
41 | end PipeLine; | |
|
41 | 42 | |
|
42 |
architecture ar_Pipe |
|
|
43 | architecture ar_PipeLine of PipeLine is | |
|
43 | 44 | |
|
44 |
type etat is (e0,e1,e2, |
|
|
45 | type etat is (e0,e1,e2,st0,st1,st2); | |
|
45 | 46 | signal ect : etat; |
|
46 | 47 | |
|
47 | 48 | begin |
|
48 | 49 | process (clk,raz) |
|
49 | 50 | begin |
|
50 | 51 | if(raz='0')then |
|
51 |
Data |
|
|
52 | Data1 <= '0'; | |
|
53 | Data2 <= '0'; | |
|
52 | 54 | ect <= e0; |
|
53 | 55 | |
|
54 | 56 | elsif(clk' event and clk='1')then |
|
57 | Data_svg <= Data_in; | |
|
58 | ||
|
55 | 59 | case ect is |
|
56 | 60 | when e0 => |
|
61 | Data2 <= '0'; | |
|
57 | 62 |
|
|
58 |
Data |
|
|
59 |
|
|
|
60 | -- elsif(ReUse='1')then | |
|
61 | -- ect <= e1; | |
|
63 | Data1 <= '1'; | |
|
64 | ect <= st2; | |
|
62 | 65 |
|
|
63 | 66 | |
|
64 |
when |
|
|
67 | when st2 => | |
|
68 | Data1 <= '0'; | |
|
69 | ect <= e1; | |
|
70 | ||
|
71 | when e1 => | |
|
65 | 72 |
|
|
66 |
|
|
|
67 |
|
|
|
68 | end if; | |
|
73 | ect <= st0; | |
|
74 | end if; | |
|
69 | 75 |
|
|
70 |
|
|
|
71 |
|
|
|
72 | ect <= e2; | |
|
76 | when st0 => | |
|
77 | ect <= st1; | |
|
73 | 78 | |
|
74 |
when |
|
|
75 |
Data |
|
|
79 | when st1 => | |
|
80 | Data2 <= '1'; | |
|
81 | ect <= e2; | |
|
82 | ||
|
83 | ||
|
84 | when e2 => | |
|
76 | 85 |
|
|
77 | 86 | ect <= e0; |
|
78 | 87 | else |
|
79 | --Data_out <= Data_two; | |
|
80 | 88 | ect <= e2; |
|
81 | 89 | end if; |
|
82 | 90 | |
|
83 | 91 | |
|
84 | ||
|
85 | 92 | end case; |
|
86 | 93 | end if; |
|
87 | 94 | end process; |
|
88 | 95 | |
|
89 |
end ar_Pipe |
|
|
96 | end ar_PipeLine; | |
|
90 | 97 | |
|
91 | 98 | |
|
92 | 99 |
@@ -39,9 +39,7 entity Top_FIFO is | |||
|
39 | 39 | clk,raz : in std_logic; --! Horloge et reset general du composant |
|
40 | 40 | flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire |
|
41 | 41 | flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire |
|
42 | -- ReUse : in std_logic; --! Flag, Permet de relire la m�moire en boucle sans nouvelle donn�es | |
|
43 | -- Lock : in std_logic; --! Permet de bloquer l'�criture dans la m�moire | |
|
44 | -- RstMem : in std_logic; --! Flag, Reset "manuel" sp�cifique au composant | |
|
42 | RstMem : in std_logic; | |
|
45 | 43 | Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant |
|
46 | 44 | Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture |
|
47 | 45 | Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture |
@@ -72,78 +70,49 end component; | |||
|
72 | 70 | signal Raddr : std_logic_vector(addr_sz-1 downto 0); |
|
73 | 71 | signal Waddr : std_logic_vector(addr_sz-1 downto 0); |
|
74 | 72 | signal Data_int : std_logic_vector(Data_sz-1 downto 0); |
|
73 | signal Data_svg : std_logic_vector(Data_sz-1 downto 0); | |
|
75 | 74 | signal s_empty : std_logic; |
|
76 | 75 | signal s_full : std_logic; |
|
77 |
|
|
|
76 | signal Data1 : std_logic; | |
|
77 | signal Data2 : std_logic; | |
|
78 | 78 | signal s_flag_RE : std_logic; |
|
79 | 79 | signal s_flag_WR : std_logic; |
|
80 |
signal |
|
|
81 | --signal rst : std_logic; | |
|
82 | --signal RstMem_inv : std_logic; | |
|
80 | signal rstf : std_logic; | |
|
83 | 81 | |
|
84 | 82 | begin |
|
85 | 83 | |
|
86 | --RstMem_inv <= not RstMem; | |
|
87 | --rst <= raz and RstMem_inv; | |
|
84 | Reset : entity LocalReset | |
|
85 | port map(clk,raz,RstMem,rstf); | |
|
88 | 86 | |
|
89 | WR : Fifo_Write | |
|
90 | generic map(Addr_sz,addr_max_int) | |
|
91 |
port map(clk,r |
|
|
92 | ||
|
87 | WR : entity Fifo_Write | |
|
88 | generic map(Addr_sz,addr_max_int) | |
|
89 | port map(clk,rstf,s_flag_WR,Raddr,s_full,Waddr); | |
|
93 | 90 | |
|
94 | 91 | SRAM : syncram_2p |
|
95 | generic map(CFG_MEMTECH,Addr_sz,Data_sz) | |
|
96 | port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in); | |
|
97 | ||
|
92 | generic map(CFG_MEMTECH,Addr_sz,Data_sz) | |
|
93 | port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in); | |
|
94 | ||
|
95 | RE : entity Fifo_Read | |
|
96 | generic map(Addr_sz,addr_max_int) | |
|
97 | port map(clk,rstf,s_flag_RE,Waddr,s_empty,Raddr); | |
|
98 | 98 | |
|
99 |
P |
|
|
100 | generic map(Data_sz) | |
|
101 |
port map(clk,r |
|
|
99 | PIPE : entity PipeLine | |
|
100 | generic map(Data_sz) | |
|
101 | port map(clk,rstf,Data_in,s_flag_RE,s_flag_WR,s_empty,Data_svg,Data1,Data2); | |
|
102 | 102 | |
|
103 | 103 | |
|
104 | RE : Fifo_Read | |
|
105 | generic map(Addr_sz,addr_max_int) | |
|
106 | port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr); | |
|
107 | ||
|
108 | process(clk,raz) | |
|
109 | begin | |
|
110 | if(raz='0')then | |
|
111 | s_flag_RE <= '0'; | |
|
112 | s_flag_WR <= '0'; | |
|
113 | -- s_full2 <= s_full; | |
|
114 | Flag_WR_reg <= '0'; | |
|
115 | ||
|
116 | elsif(clk'event and clk='1')then | |
|
117 | Flag_WR_reg <= Flag_WR; | |
|
104 | Data_out <= Data_svg when Data1='1' else | |
|
105 | Data_int when Data2='1'; | |
|
118 | 106 | |
|
119 | if(s_full='0')then --2 | |
|
120 | if(s_empty='1')then | |
|
121 | s_flag_WR <= Flag_WR_reg; | |
|
122 | else | |
|
123 | s_flag_WR <= Flag_WR; | |
|
124 | end if; | |
|
125 | else | |
|
126 | s_flag_WR <= '0'; | |
|
127 | end if; | |
|
128 | ||
|
129 | if(s_empty='0')then | |
|
130 | s_flag_RE <= Flag_RE; | |
|
131 | else | |
|
132 | s_flag_RE <= '0'; | |
|
133 | end if; | |
|
134 | ||
|
135 | -- if(Lock='1')then | |
|
136 | -- s_full2 <= '1'; | |
|
137 | -- else | |
|
138 | -- s_full2 <= s_full; | |
|
139 | -- end if; | |
|
140 | ||
|
141 | end if; | |
|
142 | end process; | |
|
143 | ||
|
144 | full <= s_full; --2 | |
|
107 | full <= s_full; | |
|
145 | 108 | empty <= s_empty; |
|
146 | 109 | Addr_RE <= Raddr; |
|
147 | 110 | Addr_WR <= Waddr; |
|
148 | 111 | |
|
112 | s_flag_WR <= Flag_WR when s_full='0' else | |
|
113 | '0'; | |
|
114 | ||
|
115 | s_flag_RE <= Flag_RE when s_empty='0' else | |
|
116 | '0'; | |
|
117 | ||
|
149 | 118 | end ar_Top_FIFO; No newline at end of file |
@@ -78,7 +78,7 component ApbDriver is | |||
|
78 | 78 | FlagFull : in std_logic; |
|
79 | 79 | -- ReUse : out std_logic; |
|
80 | 80 | -- Lock : out std_logic; |
|
81 |
|
|
|
81 | RstMem : out std_logic; | |
|
82 | 82 | DataIn : out std_logic_vector(Data_sz-1 downto 0); |
|
83 | 83 | DataOut : in std_logic_vector(Data_sz-1 downto 0); |
|
84 | 84 | AddrIn : in std_logic_vector(Addr_sz-1 downto 0); |
@@ -92,7 +92,7 end component; | |||
|
92 | 92 | component Top_FIFO is |
|
93 | 93 | generic( |
|
94 | 94 | Data_sz : integer := 16; |
|
95 |
Addr_sz : integer := 8; |
|
|
95 | Addr_sz : integer := 8; | |
|
96 | 96 | addr_max_int : integer := 256 |
|
97 | 97 | ); |
|
98 | 98 | port( |
@@ -101,7 +101,7 component Top_FIFO is | |||
|
101 | 101 | flag_WR : in std_logic; |
|
102 | 102 | -- ReUse : in std_logic; |
|
103 | 103 | -- Lock : in std_logic; |
|
104 |
|
|
|
104 | RstMem : in std_logic; | |
|
105 | 105 | Data_in : in std_logic_vector(Data_sz-1 downto 0); |
|
106 | 106 | Addr_RE : out std_logic_vector(addr_sz-1 downto 0); |
|
107 | 107 | Addr_WR : out std_logic_vector(addr_sz-1 downto 0); |
@@ -120,7 +120,6 component Fifo_Read is | |||
|
120 | 120 | clk : in std_logic; |
|
121 | 121 | raz : in std_logic; |
|
122 | 122 | flag_RE : in std_logic; |
|
123 | -- ReUse : in std_logic; | |
|
124 | 123 | Waddr : in std_logic_vector(addr_sz-1 downto 0); |
|
125 | 124 | empty : out std_logic; |
|
126 | 125 | Raddr : out std_logic_vector(addr_sz-1 downto 0) |
@@ -143,20 +142,29 component Fifo_Write is | |||
|
143 | 142 | end component; |
|
144 | 143 | |
|
145 | 144 | |
|
146 |
component Pipe |
|
|
145 | component PipeLine is | |
|
147 | 146 | generic(Data_sz : integer := 16); |
|
148 | 147 | port( |
|
149 | clk,raz : in std_logic; | |
|
150 |
Data_ |
|
|
151 | Data_two : in std_logic_vector(Data_sz-1 downto 0); | |
|
152 | -- ReUse : in std_logic; | |
|
153 | flag_RE : in std_logic; | |
|
154 | flag_WR : in std_logic; | |
|
155 |
|
|
|
156 | Data_out : out std_logic_vector(Data_sz-1 downto 0) | |
|
148 | clk,raz : in std_logic; --! Horloge et reset general du composant | |
|
149 | Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Donn�e en entr�e de la FIFO, cot� �criture | |
|
150 | flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire | |
|
151 | flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire | |
|
152 | empty : in std_logic; --! Flag, M�moire vide | |
|
153 | Data_svg : out std_logic_vector(Data_sz-1 downto 0); | |
|
154 | Data1 : out std_logic; | |
|
155 | Data2 : out std_logic | |
|
157 | 156 | ); |
|
158 | 157 | end component; |
|
159 | 158 | |
|
159 | ||
|
160 | component LocalReset is | |
|
161 | port( | |
|
162 | clk : in std_logic; | |
|
163 | raz : in std_logic; | |
|
164 | Rz : in std_logic; | |
|
165 | rstf : out std_logic | |
|
166 | ); | |
|
167 | end component; | |
|
160 | 168 | --===========================================================| |
|
161 | 169 | --================= Demi FIFO Ecriture ======================| |
|
162 | 170 | --===========================================================| |
@@ -226,6 +234,7 component APB_FifoRead is | |||
|
226 | 234 | Full : out std_logic; |
|
227 | 235 | Empty : out std_logic; |
|
228 | 236 | DATA : in std_logic_vector(Data_sz-1 downto 0); |
|
237 | dataTEST : out std_logic_vector(Data_sz-1 downto 0); | |
|
229 | 238 | apbo : out apb_slv_out_type |
|
230 | 239 | ); |
|
231 | 240 | end component; |
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