HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r328:057b3542e4d7

MINI_LFR-WFP_MS-0.1.5.pdb

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r328:057b3542e4d7 JC

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r328:057b3542e4d7

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designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +1 -1

                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"000104")  -- aa.bb.cc version
+                  top_lfr_version        => X"000105")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => reset,

lib/lpp/dsp/lpp_fft/FFT.vhd +7 -2

                     PTS         => gPTS,
                     HALFPTS     => gHALFPTS,
                     inBuf_RWDLY => gInBuf_RWDLY)
-                    port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
+                    port map(clkm,start,rstn,
+                             Drive_Write,Link_Read,
+                             Drive_DataIM,Drive_DataRE,
+                             FFT_Load,open,
+                             FFT_DataIM,FFT_DataRE,
+                             FFT_Valid,FFT_Ready);
                 LINK : Linker_FFT
                     port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
-            end architecture;
  No newline at end of file
+            end architecture;

lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +544 -544

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	@@ -1,544 +1,544
	1	------------------------------------------------------------------------------	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--	4	--
	5	-- This program is free software; you can redistribute it and/or modify	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.	8	-- (at your option) any later version.
	9	--	9	--
	10	-- This program is distributed in the hope that it will be useful,	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.	13	-- GNU General Public License for more details.
	14	--	14	--
	15	-- You should have received a copy of the GNU General Public License	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------	18	-------------------------------------------------------------------------------
	19	-- Author : Jean-christophe Pellion	19	-- Author : Jean-christophe Pellion
	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
	21	-- jean-christophe.pellion@easii-ic.com	21	-- jean-christophe.pellion@easii-ic.com
	22	----------------------------------------------------------------------------	22	----------------------------------------------------------------------------
	23	LIBRARY ieee;	23	LIBRARY ieee;
	24	USE ieee.std_logic_1164.ALL;	24	USE ieee.std_logic_1164.ALL;
	25	USE ieee.numeric_std.ALL;	25	USE ieee.numeric_std.ALL;
	26	LIBRARY grlib;	26	LIBRARY grlib;
	27	USE grlib.amba.ALL;	27	USE grlib.amba.ALL;
	28	USE grlib.stdlib.ALL;	28	USE grlib.stdlib.ALL;
	29	USE grlib.devices.ALL;	29	USE grlib.devices.ALL;
	30	LIBRARY lpp;	30	LIBRARY lpp;
	31	USE lpp.lpp_amba.ALL;	31	USE lpp.lpp_amba.ALL;
	32	USE lpp.apb_devices_list.ALL;	32	USE lpp.apb_devices_list.ALL;
	33	USE lpp.lpp_memory.ALL;	33	USE lpp.lpp_memory.ALL;
	34	LIBRARY techmap;	34	LIBRARY techmap;
	35	USE techmap.gencomp.ALL;	35	USE techmap.gencomp.ALL;
	36		36
	37	ENTITY lpp_lfr_apbreg IS	37	ENTITY lpp_lfr_apbreg IS
	38	GENERIC (	38	GENERIC (
	39	nb_data_by_buffer_size : INTEGER := 11;	39	nb_data_by_buffer_size : INTEGER := 11;
	40	nb_word_by_buffer_size : INTEGER := 11;	40	nb_word_by_buffer_size : INTEGER := 11;
	41	nb_snapshot_param_size : INTEGER := 11;	41	nb_snapshot_param_size : INTEGER := 11;
	42	delta_vector_size : INTEGER := 20;	42	delta_vector_size : INTEGER := 20;
	43	delta_vector_size_f0_2 : INTEGER := 3;	43	delta_vector_size_f0_2 : INTEGER := 3;
	44		44
	45	pindex : INTEGER := 4;	45	pindex : INTEGER := 4;
	46	paddr : INTEGER := 4;	46	paddr : INTEGER := 4;
	47	pmask : INTEGER := 16#fff#;	47	pmask : INTEGER := 16#fff#;
	48	pirq_ms : INTEGER := 0;	48	pirq_ms : INTEGER := 0;
	49	pirq_wfp : INTEGER := 1;	49	pirq_wfp : INTEGER := 1;
	50	top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));	50	top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
	51	PORT (	51	PORT (
	52	-- AMBA AHB system signals	52	-- AMBA AHB system signals
	53	HCLK : IN STD_ULOGIC;	53	HCLK : IN STD_ULOGIC;
	54	HRESETn : IN STD_ULOGIC;	54	HRESETn : IN STD_ULOGIC;
	55		55
	56	-- AMBA APB Slave Interface	56	-- AMBA APB Slave Interface
	57	apbi : IN apb_slv_in_type;	57	apbi : IN apb_slv_in_type;
	58	apbo : OUT apb_slv_out_type;	58	apbo : OUT apb_slv_out_type;
	59		59
	60	---------------------------------------------------------------------------	60	---------------------------------------------------------------------------
	61	-- Spectral Matrix Reg	61	-- Spectral Matrix Reg
	62	run_ms : OUT STD_LOGIC;	62	run_ms : OUT STD_LOGIC;
	63	-- IN	63	-- IN
	64	ready_matrix_f0_0 : IN STD_LOGIC;	64	ready_matrix_f0_0 : IN STD_LOGIC;
	65	ready_matrix_f0_1 : IN STD_LOGIC;	65	ready_matrix_f0_1 : IN STD_LOGIC;
	66	ready_matrix_f1 : IN STD_LOGIC;	66	ready_matrix_f1 : IN STD_LOGIC;
	67	ready_matrix_f2 : IN STD_LOGIC;	67	ready_matrix_f2 : IN STD_LOGIC;
	68	error_anticipating_empty_fifo : IN STD_LOGIC;	68	error_anticipating_empty_fifo : IN STD_LOGIC;
	69	error_bad_component_error : IN STD_LOGIC;	69	error_bad_component_error : IN STD_LOGIC;
	70	debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	70	debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	71		71
	72	-- OUT	72	-- OUT
	73	status_ready_matrix_f0_0 : OUT STD_LOGIC;	73	status_ready_matrix_f0_0 : OUT STD_LOGIC;
	74	status_ready_matrix_f0_1 : OUT STD_LOGIC;	74	status_ready_matrix_f0_1 : OUT STD_LOGIC;
	75	status_ready_matrix_f1 : OUT STD_LOGIC;	75	status_ready_matrix_f1 : OUT STD_LOGIC;
	76	status_ready_matrix_f2 : OUT STD_LOGIC;	76	status_ready_matrix_f2 : OUT STD_LOGIC;
	77	status_error_anticipating_empty_fifo : OUT STD_LOGIC;	77	status_error_anticipating_empty_fifo : OUT STD_LOGIC;
	78	status_error_bad_component_error : OUT STD_LOGIC;	78	status_error_bad_component_error : OUT STD_LOGIC;
	79		79
	80	config_active_interruption_onNewMatrix : OUT STD_LOGIC;	80	config_active_interruption_onNewMatrix : OUT STD_LOGIC;
	81	config_active_interruption_onError : OUT STD_LOGIC;	81	config_active_interruption_onError : OUT STD_LOGIC;
	82		82
	83	addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	83	addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	84	addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	84	addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	85	addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	85	addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	86	addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	86	addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	87		87
	88	matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	88	matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	89	matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	89	matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	90	matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	90	matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	91	matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	91	matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	92		92
	93	---------------------------------------------------------------------------	93	---------------------------------------------------------------------------
	94	---------------------------------------------------------------------------	94	---------------------------------------------------------------------------
	95	-- WaveForm picker Reg	95	-- WaveForm picker Reg
	96	status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	96	status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	97	status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);	97	status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	98	status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	98	status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	99	status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	99	status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	100		100
	101	-- OUT	101	-- OUT
	102	data_shaping_BW : OUT STD_LOGIC;	102	data_shaping_BW : OUT STD_LOGIC;
	103	data_shaping_SP0 : OUT STD_LOGIC;	103	data_shaping_SP0 : OUT STD_LOGIC;
	104	data_shaping_SP1 : OUT STD_LOGIC;	104	data_shaping_SP1 : OUT STD_LOGIC;
	105	data_shaping_R0 : OUT STD_LOGIC;	105	data_shaping_R0 : OUT STD_LOGIC;
	106	data_shaping_R1 : OUT STD_LOGIC;	106	data_shaping_R1 : OUT STD_LOGIC;
	107		107
	108	delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	108	delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	109	delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	109	delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	110	delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);	110	delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
	111	delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	111	delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	112	delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	112	delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	113	nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);	113	nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
	114	nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);	114	nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
	115	nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);	115	nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
	116		116
	117	enable_f0 : OUT STD_LOGIC;	117	enable_f0 : OUT STD_LOGIC;
	118	enable_f1 : OUT STD_LOGIC;	118	enable_f1 : OUT STD_LOGIC;
	119	enable_f2 : OUT STD_LOGIC;	119	enable_f2 : OUT STD_LOGIC;
	120	enable_f3 : OUT STD_LOGIC;	120	enable_f3 : OUT STD_LOGIC;
	121		121
	122	burst_f0 : OUT STD_LOGIC;	122	burst_f0 : OUT STD_LOGIC;
	123	burst_f1 : OUT STD_LOGIC;	123	burst_f1 : OUT STD_LOGIC;
	124	burst_f2 : OUT STD_LOGIC;	124	burst_f2 : OUT STD_LOGIC;
	125		125
	126	run : OUT STD_LOGIC;	126	run : OUT STD_LOGIC;
	127		127
	128	addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	128	addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	129	addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	129	addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	130	addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	130	addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	131	addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	131	addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	132	start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);	132	start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
	133	---------------------------------------------------------------------------	133	---------------------------------------------------------------------------
	134	debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	134	debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	135	debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	135	debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	136	debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	136	debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	137	debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	137	debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	138	debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	138	debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	139	debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	139	debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	140	debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	140	debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	141	debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)	141	debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
	142		142
	143	---------------------------------------------------------------------------	143	---------------------------------------------------------------------------
	144	);	144	);
	145		145
	146	END lpp_lfr_apbreg;	146	END lpp_lfr_apbreg;
	147		147
	148	ARCHITECTURE beh OF lpp_lfr_apbreg IS	148	ARCHITECTURE beh OF lpp_lfr_apbreg IS
	149		149
	150	CONSTANT REVISION : INTEGER := 1;	150	CONSTANT REVISION : INTEGER := 1;
	151		151
	152	CONSTANT pconfig : apb_config_type := (	152	CONSTANT pconfig : apb_config_type := (
	153	0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),	153	0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
	154	1 => apb_iobar(paddr, pmask));	154	1 => apb_iobar(paddr, pmask));
	155		155
	156	TYPE lpp_SpectralMatrix_regs IS RECORD	156	TYPE lpp_SpectralMatrix_regs IS RECORD
	157	config_active_interruption_onNewMatrix : STD_LOGIC;	157	config_active_interruption_onNewMatrix : STD_LOGIC;
	158	config_active_interruption_onError : STD_LOGIC;	158	config_active_interruption_onError : STD_LOGIC;
	159	config_ms_run : STD_LOGIC;	159	config_ms_run : STD_LOGIC;
	160	status_ready_matrix_f0_0 : STD_LOGIC;	160	status_ready_matrix_f0_0 : STD_LOGIC;
	161	status_ready_matrix_f0_1 : STD_LOGIC;	161	status_ready_matrix_f0_1 : STD_LOGIC;
	162	status_ready_matrix_f1 : STD_LOGIC;	162	status_ready_matrix_f1 : STD_LOGIC;
	163	status_ready_matrix_f2 : STD_LOGIC;	163	status_ready_matrix_f2 : STD_LOGIC;
	164	status_error_anticipating_empty_fifo : STD_LOGIC;	164	status_error_anticipating_empty_fifo : STD_LOGIC;
	165	status_error_bad_component_error : STD_LOGIC;	165	status_error_bad_component_error : STD_LOGIC;
	166	addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);	166	addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	167	addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	167	addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	168	addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	168	addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	169	addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);	169	addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	170		170
	171	coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);	171	coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	172	coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	172	coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	173	coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	173	coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	174	coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);	174	coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	175		175
	176	-- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);	176	-- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	177	-- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);	177	-- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	178	-- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);	178	-- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	179	-- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);	179	-- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	180	END RECORD;	180	END RECORD;
	181	SIGNAL reg_sp : lpp_SpectralMatrix_regs;	181	SIGNAL reg_sp : lpp_SpectralMatrix_regs;
	182		182
	183	TYPE lpp_WaveformPicker_regs IS RECORD	183	TYPE lpp_WaveformPicker_regs IS RECORD
	184	status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);	184	status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
	185	status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);	185	status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
	186	status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);	186	status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
	187	data_shaping_BW : STD_LOGIC;	187	data_shaping_BW : STD_LOGIC;
	188	data_shaping_SP0 : STD_LOGIC;	188	data_shaping_SP0 : STD_LOGIC;
	189	data_shaping_SP1 : STD_LOGIC;	189	data_shaping_SP1 : STD_LOGIC;
	190	data_shaping_R0 : STD_LOGIC;	190	data_shaping_R0 : STD_LOGIC;
	191	data_shaping_R1 : STD_LOGIC;	191	data_shaping_R1 : STD_LOGIC;
	192	delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	192	delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	193	delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	193	delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	194	delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);	194	delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
	195	delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	195	delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	196	delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	196	delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	197	nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);	197	nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
	198	nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);	198	nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
	199	nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);	199	nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
	200	enable_f0 : STD_LOGIC;	200	enable_f0 : STD_LOGIC;
	201	enable_f1 : STD_LOGIC;	201	enable_f1 : STD_LOGIC;
	202	enable_f2 : STD_LOGIC;	202	enable_f2 : STD_LOGIC;
	203	enable_f3 : STD_LOGIC;	203	enable_f3 : STD_LOGIC;
	204	burst_f0 : STD_LOGIC;	204	burst_f0 : STD_LOGIC;
	205	burst_f1 : STD_LOGIC;	205	burst_f1 : STD_LOGIC;
	206	burst_f2 : STD_LOGIC;	206	burst_f2 : STD_LOGIC;
	207	run : STD_LOGIC;	207	run : STD_LOGIC;
	208	addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);	208	addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	209	addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	209	addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	210	addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);	210	addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	211	addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);	211	addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	212	start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);	212	start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
	213	END RECORD;	213	END RECORD;
	214	SIGNAL reg_wp : lpp_WaveformPicker_regs;	214	SIGNAL reg_wp : lpp_WaveformPicker_regs;
	215		215
	216	SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);	216	SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
	217		217
	218	-----------------------------------------------------------------------------	218	-----------------------------------------------------------------------------
	219	-- IRQ	219	-- IRQ
	220	-----------------------------------------------------------------------------	220	-----------------------------------------------------------------------------
	221	CONSTANT IRQ_WFP_SIZE : INTEGER := 12;	221	CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
	222	SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);	222	SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
	223	SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);	223	SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
	224	SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);	224	SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
	225	SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);	225	SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
	226	SIGNAL ored_irq_wfp : STD_LOGIC;	226	SIGNAL ored_irq_wfp : STD_LOGIC;
	227		227
	228	BEGIN -- beh	228	BEGIN -- beh
	229		229
	230	status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;	230	status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
	231	status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;	231	status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
	232	status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;	232	status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
	233	status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;	233	status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
	234	status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;	234	status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
	235	status_error_bad_component_error <= reg_sp.status_error_bad_component_error;	235	status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
	236		236
	237	config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;	237	config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
	238	config_active_interruption_onError <= reg_sp.config_active_interruption_onError;	238	config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
	239	addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;	239	addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
	240	addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;	240	addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
	241	addr_matrix_f1 <= reg_sp.addr_matrix_f1;	241	addr_matrix_f1 <= reg_sp.addr_matrix_f1;
	242	addr_matrix_f2 <= reg_sp.addr_matrix_f2;	242	addr_matrix_f2 <= reg_sp.addr_matrix_f2;
	243		243
	244		244
	245	data_shaping_BW <= NOT reg_wp.data_shaping_BW;	245	data_shaping_BW <= NOT reg_wp.data_shaping_BW;
	246	data_shaping_SP0 <= reg_wp.data_shaping_SP0;	246	data_shaping_SP0 <= reg_wp.data_shaping_SP0;
	247	data_shaping_SP1 <= reg_wp.data_shaping_SP1;	247	data_shaping_SP1 <= reg_wp.data_shaping_SP1;
	248	data_shaping_R0 <= reg_wp.data_shaping_R0;	248	data_shaping_R0 <= reg_wp.data_shaping_R0;
	249	data_shaping_R1 <= reg_wp.data_shaping_R1;	249	data_shaping_R1 <= reg_wp.data_shaping_R1;
	250		250
	251	delta_snapshot <= reg_wp.delta_snapshot;	251	delta_snapshot <= reg_wp.delta_snapshot;
	252	delta_f0 <= reg_wp.delta_f0;	252	delta_f0 <= reg_wp.delta_f0;
	253	delta_f0_2 <= reg_wp.delta_f0_2;	253	delta_f0_2 <= reg_wp.delta_f0_2;
	254	delta_f1 <= reg_wp.delta_f1;	254	delta_f1 <= reg_wp.delta_f1;
	255	delta_f2 <= reg_wp.delta_f2;	255	delta_f2 <= reg_wp.delta_f2;
	256	nb_data_by_buffer <= reg_wp.nb_data_by_buffer;	256	nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
	257	nb_word_by_buffer <= reg_wp.nb_word_by_buffer;	257	nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
	258	nb_snapshot_param <= reg_wp.nb_snapshot_param;	258	nb_snapshot_param <= reg_wp.nb_snapshot_param;
	259		259
	260	enable_f0 <= reg_wp.enable_f0;	260	enable_f0 <= reg_wp.enable_f0;
	261	enable_f1 <= reg_wp.enable_f1;	261	enable_f1 <= reg_wp.enable_f1;
	262	enable_f2 <= reg_wp.enable_f2;	262	enable_f2 <= reg_wp.enable_f2;
	263	enable_f3 <= reg_wp.enable_f3;	263	enable_f3 <= reg_wp.enable_f3;
	264		264
	265	burst_f0 <= reg_wp.burst_f0;	265	burst_f0 <= reg_wp.burst_f0;
	266	burst_f1 <= reg_wp.burst_f1;	266	burst_f1 <= reg_wp.burst_f1;
	267	burst_f2 <= reg_wp.burst_f2;	267	burst_f2 <= reg_wp.burst_f2;
	268		268
	269	run <= reg_wp.run;	269	run <= reg_wp.run;
	270		270
	271	addr_data_f0 <= reg_wp.addr_data_f0;	271	addr_data_f0 <= reg_wp.addr_data_f0;
	272	addr_data_f1 <= reg_wp.addr_data_f1;	272	addr_data_f1 <= reg_wp.addr_data_f1;
	273	addr_data_f2 <= reg_wp.addr_data_f2;	273	addr_data_f2 <= reg_wp.addr_data_f2;
	274	addr_data_f3 <= reg_wp.addr_data_f3;	274	addr_data_f3 <= reg_wp.addr_data_f3;
	275		275
	276	start_date <= reg_wp.start_date;	276	start_date <= reg_wp.start_date;
	277		277
	278	lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)	278	lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
	279	VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);	279	VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
	280	BEGIN -- PROCESS lpp_dma_top	280	BEGIN -- PROCESS lpp_dma_top
	281	IF HRESETn = '0' THEN -- asynchronous reset (active low)	281	IF HRESETn = '0' THEN -- asynchronous reset (active low)
	282	reg_sp.config_active_interruption_onNewMatrix <= '0';	282	reg_sp.config_active_interruption_onNewMatrix <= '0';
	283	reg_sp.config_active_interruption_onError <= '0';	283	reg_sp.config_active_interruption_onError <= '0';
	284	reg_sp.config_ms_run <= '1';	284	reg_sp.config_ms_run <= '1';
	285	reg_sp.status_ready_matrix_f0_0 <= '0';	285	reg_sp.status_ready_matrix_f0_0 <= '0';
	286	reg_sp.status_ready_matrix_f0_1 <= '0';	286	reg_sp.status_ready_matrix_f0_1 <= '0';
	287	reg_sp.status_ready_matrix_f1 <= '0';	287	reg_sp.status_ready_matrix_f1 <= '0';
	288	reg_sp.status_ready_matrix_f2 <= '0';	288	reg_sp.status_ready_matrix_f2 <= '0';
	289	reg_sp.status_error_anticipating_empty_fifo <= '0';	289	reg_sp.status_error_anticipating_empty_fifo <= '0';
	290	reg_sp.status_error_bad_component_error <= '0';	290	reg_sp.status_error_bad_component_error <= '0';
	291	reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');	291	reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
	292	reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');	292	reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
	293	reg_sp.addr_matrix_f1 <= (OTHERS => '0');	293	reg_sp.addr_matrix_f1 <= (OTHERS => '0');
	294	reg_sp.addr_matrix_f2 <= (OTHERS => '0');	294	reg_sp.addr_matrix_f2 <= (OTHERS => '0');
	295		295
	296	reg_sp.coarse_time_f0_0 <= (OTHERS => '0');	296	reg_sp.coarse_time_f0_0 <= (OTHERS => '0');
	297	reg_sp.coarse_time_f0_1 <= (OTHERS => '0');	297	reg_sp.coarse_time_f0_1 <= (OTHERS => '0');
	298	reg_sp.coarse_time_f1 <= (OTHERS => '0');	298	reg_sp.coarse_time_f1 <= (OTHERS => '0');
	299	reg_sp.coarse_time_f2 <= (OTHERS => '0');	299	reg_sp.coarse_time_f2 <= (OTHERS => '0');
	300	--reg_sp.fine_time_f0_0 <= (OTHERS => '0');	300	--reg_sp.fine_time_f0_0 <= (OTHERS => '0');
	301	--reg_sp.fine_time_f0_1 <= (OTHERS => '0');	301	--reg_sp.fine_time_f0_1 <= (OTHERS => '0');
	302	--reg_sp.fine_time_f1 <= (OTHERS => '0');	302	--reg_sp.fine_time_f1 <= (OTHERS => '0');
	303	--reg_sp.fine_time_f2 <= (OTHERS => '0');	303	--reg_sp.fine_time_f2 <= (OTHERS => '0');
	304		304
	305	prdata <= (OTHERS => '0');	305	prdata <= (OTHERS => '0');
	306		306
	307	apbo.pirq <= (OTHERS => '0');	307	apbo.pirq <= (OTHERS => '0');
	308		308
	309	status_full_ack <= (OTHERS => '0');	309	status_full_ack <= (OTHERS => '0');
	310		310
	311	reg_wp.data_shaping_BW <= '0';	311	reg_wp.data_shaping_BW <= '0';
	312	reg_wp.data_shaping_SP0 <= '0';	312	reg_wp.data_shaping_SP0 <= '0';
	313	reg_wp.data_shaping_SP1 <= '0';	313	reg_wp.data_shaping_SP1 <= '0';
	314	reg_wp.data_shaping_R0 <= '0';	314	reg_wp.data_shaping_R0 <= '0';
	315	reg_wp.data_shaping_R1 <= '0';	315	reg_wp.data_shaping_R1 <= '0';
	316	reg_wp.enable_f0 <= '0';	316	reg_wp.enable_f0 <= '0';
	317	reg_wp.enable_f1 <= '0';	317	reg_wp.enable_f1 <= '0';
	318	reg_wp.enable_f2 <= '0';	318	reg_wp.enable_f2 <= '0';
	319	reg_wp.enable_f3 <= '0';	319	reg_wp.enable_f3 <= '0';
	320	reg_wp.burst_f0 <= '0';	320	reg_wp.burst_f0 <= '0';
	321	reg_wp.burst_f1 <= '0';	321	reg_wp.burst_f1 <= '0';
	322	reg_wp.burst_f2 <= '0';	322	reg_wp.burst_f2 <= '0';
	323	reg_wp.run <= '0';	323	reg_wp.run <= '0';
	324	reg_wp.addr_data_f0 <= (OTHERS => '0');	324	reg_wp.addr_data_f0 <= (OTHERS => '0');
	325	reg_wp.addr_data_f1 <= (OTHERS => '0');	325	reg_wp.addr_data_f1 <= (OTHERS => '0');
	326	reg_wp.addr_data_f2 <= (OTHERS => '0');	326	reg_wp.addr_data_f2 <= (OTHERS => '0');
	327	reg_wp.addr_data_f3 <= (OTHERS => '0');	327	reg_wp.addr_data_f3 <= (OTHERS => '0');
	328	reg_wp.status_full <= (OTHERS => '0');	328	reg_wp.status_full <= (OTHERS => '0');
	329	reg_wp.status_full_err <= (OTHERS => '0');	329	reg_wp.status_full_err <= (OTHERS => '0');
	330	reg_wp.status_new_err <= (OTHERS => '0');	330	reg_wp.status_new_err <= (OTHERS => '0');
	331	reg_wp.delta_snapshot <= (OTHERS => '0');	331	reg_wp.delta_snapshot <= (OTHERS => '0');
	332	reg_wp.delta_f0 <= (OTHERS => '0');	332	reg_wp.delta_f0 <= (OTHERS => '0');
	333	reg_wp.delta_f0_2 <= (OTHERS => '0');	333	reg_wp.delta_f0_2 <= (OTHERS => '0');
	334	reg_wp.delta_f1 <= (OTHERS => '0');	334	reg_wp.delta_f1 <= (OTHERS => '0');
	335	reg_wp.delta_f2 <= (OTHERS => '0');	335	reg_wp.delta_f2 <= (OTHERS => '0');
	336	reg_wp.nb_data_by_buffer <= (OTHERS => '0');	336	reg_wp.nb_data_by_buffer <= (OTHERS => '0');
	337	reg_wp.nb_snapshot_param <= (OTHERS => '0');	337	reg_wp.nb_snapshot_param <= (OTHERS => '0');
	338	reg_wp.start_date <= (OTHERS => '0');	338	reg_wp.start_date <= (OTHERS => '0');
	339		339
	340	ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge	340	ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
	341		341
	342	reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0);	342	reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0);
	343	reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0);	343	reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0);
	344	reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0);	344	reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0);
	345	reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0);	345	reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0);
	346		346
	347	--reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0);	347	--reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0);
	348	--reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0);	348	--reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0);
	349	--reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0);	349	--reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0);
	350	--reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0);	350	--reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0);
	351		351
	352	status_full_ack <= (OTHERS => '0');	352	status_full_ack <= (OTHERS => '0');
	353		353
	354	reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;	354	reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
	355	reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;	355	reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
	356	reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;	356	reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
	357	reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;	357	reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
	358		358
	359	reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;	359	reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
	360	reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;	360	reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
	361	all_status: FOR I IN 3 DOWNTO 0 LOOP	361	all_status: FOR I IN 3 DOWNTO 0 LOOP
	362	--reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;	362	--reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
	363	--reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;	363	--reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
	364	--reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;	364	--reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
	365	reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;	365	reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
	366	reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;	366	reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
	367	reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;	367	reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
	368	END LOOP all_status;	368	END LOOP all_status;
	369		369
	370	paddr := "000000";	370	paddr := "000000";
	371	paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);	371	paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
	372	prdata <= (OTHERS => '0');	372	prdata <= (OTHERS => '0');
	373	IF apbi.psel(pindex) = '1' THEN	373	IF apbi.psel(pindex) = '1' THEN
	374	-- APB DMA READ --	374	-- APB DMA READ --
	375	CASE paddr(7 DOWNTO 2) IS	375	CASE paddr(7 DOWNTO 2) IS
	376	--	376	--
	377	WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;	377	WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
	378	prdata(1) <= reg_sp.config_active_interruption_onError;	378	prdata(1) <= reg_sp.config_active_interruption_onError;
	379	prdata(2) <= reg_sp.config_ms_run;	379	prdata(2) <= reg_sp.config_ms_run;
	380	WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;	380	WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
	381	prdata(1) <= reg_sp.status_ready_matrix_f0_1;	381	prdata(1) <= reg_sp.status_ready_matrix_f0_1;
	382	prdata(2) <= reg_sp.status_ready_matrix_f1;	382	prdata(2) <= reg_sp.status_ready_matrix_f1;
	383	prdata(3) <= reg_sp.status_ready_matrix_f2;	383	prdata(3) <= reg_sp.status_ready_matrix_f2;
	384	prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;	384	prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
	385	prdata(5) <= reg_sp.status_error_bad_component_error;	385	prdata(5) <= reg_sp.status_error_bad_component_error;
	386	WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;	386	WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
	387	WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;	387	WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
	388	WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;	388	WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
	389	WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;	389	WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
	390		390
	391	WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0;	391	WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0;
	392	WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1;	392	WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1;
	393	WHEN "001000" => prdata <= reg_sp.coarse_time_f1;	393	WHEN "001000" => prdata <= reg_sp.coarse_time_f1;
	394	WHEN "001001" => prdata <= reg_sp.coarse_time_f2;	394	WHEN "001001" => prdata <= reg_sp.coarse_time_f2;
	395	WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0;	395	WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0;
	396	WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1;	396	WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1;
	397	WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1;	397	WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1;
	398	WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2;	398	WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2;
	399		399
	400	WHEN "001111" => prdata <= debug_reg;	400	WHEN "001111" => prdata <= debug_reg;
	401	---------------------------------------------------------------------	401	---------------------------------------------------------------------
	402	WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW;	402	WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW;
	403	prdata(1) <= reg_wp.data_shaping_SP0;	403	prdata(1) <= reg_wp.data_shaping_SP0;
	404	prdata(2) <= reg_wp.data_shaping_SP1;	404	prdata(2) <= reg_wp.data_shaping_SP1;
	405	prdata(3) <= reg_wp.data_shaping_R0;	405	prdata(3) <= reg_wp.data_shaping_R0;
	406	prdata(4) <= reg_wp.data_shaping_R1;	406	prdata(4) <= reg_wp.data_shaping_R1;
	407	WHEN "010001" => prdata(0) <= reg_wp.enable_f0;	407	WHEN "010001" => prdata(0) <= reg_wp.enable_f0;
	408	prdata(1) <= reg_wp.enable_f1;	408	prdata(1) <= reg_wp.enable_f1;
	409	prdata(2) <= reg_wp.enable_f2;	409	prdata(2) <= reg_wp.enable_f2;
	410	prdata(3) <= reg_wp.enable_f3;	410	prdata(3) <= reg_wp.enable_f3;
	411	prdata(4) <= reg_wp.burst_f0;	411	prdata(4) <= reg_wp.burst_f0;
	412	prdata(5) <= reg_wp.burst_f1;	412	prdata(5) <= reg_wp.burst_f1;
	413	prdata(6) <= reg_wp.burst_f2;	413	prdata(6) <= reg_wp.burst_f2;
	414	prdata(7) <= reg_wp.run;	414	prdata(7) <= reg_wp.run;
	415	WHEN "010010" => prdata <= reg_wp.addr_data_f0;	415	WHEN "010010" => prdata <= reg_wp.addr_data_f0;
	416	WHEN "010011" => prdata <= reg_wp.addr_data_f1;	416	WHEN "010011" => prdata <= reg_wp.addr_data_f1;
	417	WHEN "010100" => prdata <= reg_wp.addr_data_f2;	417	WHEN "010100" => prdata <= reg_wp.addr_data_f2;
	418	WHEN "010101" => prdata <= reg_wp.addr_data_f3;	418	WHEN "010101" => prdata <= reg_wp.addr_data_f3;
	419	WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;	419	WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
	420	prdata(7 DOWNTO 4) <= reg_wp.status_full_err;	420	prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
	421	prdata(11 DOWNTO 8) <= reg_wp.status_new_err;	421	prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
	422	WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;	422	WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
	423	WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;	423	WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
	424	WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;	424	WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
	425	WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;	425	WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
	426	WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;	426	WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
	427	WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;	427	WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
	428	WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;	428	WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
	429	WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;	429	WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
	430	WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;	430	WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
	431	----------------------------------------------------	431	----------------------------------------------------
	432	WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);	432	WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
	433	WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);	433	WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
	434	WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);	434	WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
	435	WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);	435	WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
	436	WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);	436	WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
	437	WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);	437	WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
	438	WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);	438	WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
	439	WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);	439	WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
	440	----------------------------------------------------	440	----------------------------------------------------
	441	WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);	441	WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
	442	WHEN OTHERS => NULL;	442	WHEN OTHERS => NULL;
	443		443
	444	END CASE;	444	END CASE;
	445	IF (apbi.pwrite AND apbi.penable) = '1' THEN	445	IF (apbi.pwrite AND apbi.penable) = '1' THEN
	446	-- APB DMA WRITE --	446	-- APB DMA WRITE --
	447	CASE paddr(7 DOWNTO 2) IS	447	CASE paddr(7 DOWNTO 2) IS
	448	--	448	--
	449	WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);	449	WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
	450	reg_sp.config_active_interruption_onError <= apbi.pwdata(1);	450	reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
	451	reg_sp.config_ms_run <= apbi.pwdata(2);	451	reg_sp.config_ms_run <= apbi.pwdata(2);
	452	WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);	452	WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
	453	reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);	453	reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
	454	reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);	454	reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
	455	reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);	455	reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
	456	reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);	456	reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
	457	reg_sp.status_error_bad_component_error <= apbi.pwdata(5);	457	reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
	458	WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;	458	WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
	459	WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;	459	WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
	460	WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;	460	WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
	461	WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;	461	WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
	462	--	462	--
	463	WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);	463	WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
	464	reg_wp.data_shaping_SP0 <= apbi.pwdata(1);	464	reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
	465	reg_wp.data_shaping_SP1 <= apbi.pwdata(2);	465	reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
	466	reg_wp.data_shaping_R0 <= apbi.pwdata(3);	466	reg_wp.data_shaping_R0 <= apbi.pwdata(3);
	467	reg_wp.data_shaping_R1 <= apbi.pwdata(4);	467	reg_wp.data_shaping_R1 <= apbi.pwdata(4);
	468	WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0);	468	WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0);
	469	reg_wp.enable_f1 <= apbi.pwdata(1);	469	reg_wp.enable_f1 <= apbi.pwdata(1);
	470	reg_wp.enable_f2 <= apbi.pwdata(2);	470	reg_wp.enable_f2 <= apbi.pwdata(2);
	471	reg_wp.enable_f3 <= apbi.pwdata(3);	471	reg_wp.enable_f3 <= apbi.pwdata(3);
	472	reg_wp.burst_f0 <= apbi.pwdata(4);	472	reg_wp.burst_f0 <= apbi.pwdata(4);
	473	reg_wp.burst_f1 <= apbi.pwdata(5);	473	reg_wp.burst_f1 <= apbi.pwdata(5);
	474	reg_wp.burst_f2 <= apbi.pwdata(6);	474	reg_wp.burst_f2 <= apbi.pwdata(6);
	475	reg_wp.run <= apbi.pwdata(7);	475	reg_wp.run <= apbi.pwdata(7);
	476	WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata;	476	WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata;
	477	WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata;	477	WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata;
	478	WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata;	478	WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata;
	479	WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata;	479	WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata;
	480	WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);	480	WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
	481	reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);	481	reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
	482	reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);	482	reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
	483	status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);	483	status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
	484	status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);	484	status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
	485	status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);	485	status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
	486	status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);	486	status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
	487	WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);	487	WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
	488	WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);	488	WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
	489	WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);	489	WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
	490	WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);	490	WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
	491	WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);	491	WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
	492	WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);	492	WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
	493	WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);	493	WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
	494	WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);	494	WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
	495	WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);	495	WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
	496	--	496	--
	497	WHEN OTHERS => NULL;	497	WHEN OTHERS => NULL;
	498	END CASE;	498	END CASE;
	499	END IF;	499	END IF;
	500	END IF;	500	END IF;
	501		501
	502	apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR	502	apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
	503	ready_matrix_f0_1 OR	503	ready_matrix_f0_1 OR
	504	ready_matrix_f1 OR	504	ready_matrix_f1 OR
	505	ready_matrix_f2)	505	ready_matrix_f2)
	506	)	506	)
	507	OR	507	OR
	508	(reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR	508	(reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
	509	error_bad_component_error)	509	error_bad_component_error)
	510	));	510	));
	511		511
	512	apbo.pirq(pirq_wfp) <= ored_irq_wfp;	512	apbo.pirq(pirq_wfp) <= ored_irq_wfp;
	513		513
	514	END IF;	514	END IF;
	515	END PROCESS lpp_lfr_apbreg;	515	END PROCESS lpp_lfr_apbreg;
	516		516
	517	apbo.pindex <= pindex;	517	apbo.pindex <= pindex;
	518	apbo.pconfig <= pconfig;	518	apbo.pconfig <= pconfig;
	519	apbo.prdata <= prdata;	519	apbo.prdata <= prdata;
	520		520
	521	-----------------------------------------------------------------------------	521	-----------------------------------------------------------------------------
	522	-- IRQ	522	-- IRQ
	523	-----------------------------------------------------------------------------	523	-----------------------------------------------------------------------------
	524	irq_wfp_reg_s <= status_full & status_full_err & status_new_err;	524	irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
	525		525
	526	PROCESS (HCLK, HRESETn)	526	PROCESS (HCLK, HRESETn)
	527	BEGIN -- PROCESS	527	BEGIN -- PROCESS
	528	IF HRESETn = '0' THEN -- asynchronous reset (active low)	528	IF HRESETn = '0' THEN -- asynchronous reset (active low)
	529	irq_wfp_reg <= (OTHERS => '0');	529	irq_wfp_reg <= (OTHERS => '0');
	530	ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge	530	ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
	531	irq_wfp_reg <= irq_wfp_reg_s;	531	irq_wfp_reg <= irq_wfp_reg_s;
	532	END IF;	532	END IF;
	533	END PROCESS;	533	END PROCESS;
	534		534
	535	all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE	535	all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
	536	irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);	536	irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
	537	END GENERATE all_irq_wfp;	537	END GENERATE all_irq_wfp;
	538		538
	539	irq_wfp_ZERO <= (OTHERS => '0');	539	irq_wfp_ZERO <= (OTHERS => '0');
	540	ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';	540	ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
	541		541
	542	run_ms <= reg_sp.config_ms_run;	542	run_ms <= reg_sp.config_ms_run;
	543		543
	544	END beh;	544	END beh; No newline at end of file

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +394 -374

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	@@ -1,374 +1,394
	1	LIBRARY ieee;	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;	2	USE ieee.std_logic_1164.ALL;
	3		3
	4	LIBRARY lpp;	4	LIBRARY lpp;
	5	USE lpp.lpp_amba.ALL;	5	USE lpp.lpp_amba.ALL;
	6	USE lpp.lpp_memory.ALL;	6	USE lpp.lpp_memory.ALL;
	7	--USE lpp.lpp_uart.ALL;	7	--USE lpp.lpp_uart.ALL;
	8	USE lpp.lpp_matrix.ALL;	8	USE lpp.lpp_matrix.ALL;
	9	--USE lpp.lpp_delay.ALL;	9	--USE lpp.lpp_delay.ALL;
	10	USE lpp.lpp_fft.ALL;	10	USE lpp.lpp_fft.ALL;
	11	USE lpp.fft_components.ALL;	11	USE lpp.fft_components.ALL;
	12	USE lpp.lpp_ad_conv.ALL;	12	USE lpp.lpp_ad_conv.ALL;
	13	USE lpp.iir_filter.ALL;	13	USE lpp.iir_filter.ALL;
	14	USE lpp.general_purpose.ALL;	14	USE lpp.general_purpose.ALL;
	15	USE lpp.Filtercfg.ALL;	15	USE lpp.Filtercfg.ALL;
	16	USE lpp.lpp_demux.ALL;	16	USE lpp.lpp_demux.ALL;
	17	USE lpp.lpp_top_lfr_pkg.ALL;	17	USE lpp.lpp_top_lfr_pkg.ALL;
	18	USE lpp.lpp_dma_pkg.ALL;	18	USE lpp.lpp_dma_pkg.ALL;
	19	USE lpp.lpp_Header.ALL;	19	USE lpp.lpp_Header.ALL;
	20	USE lpp.lpp_lfr_pkg.ALL;	20	USE lpp.lpp_lfr_pkg.ALL;
	21		21
	22	LIBRARY grlib;	22	LIBRARY grlib;
	23	USE grlib.amba.ALL;	23	USE grlib.amba.ALL;
	24	USE grlib.stdlib.ALL;	24	USE grlib.stdlib.ALL;
	25	USE grlib.devices.ALL;	25	USE grlib.devices.ALL;
	26	USE GRLIB.DMA2AHB_Package.ALL;	26	USE GRLIB.DMA2AHB_Package.ALL;
	27		27
	28		28
	29	ENTITY lpp_lfr_ms IS	29	ENTITY lpp_lfr_ms IS
	30	GENERIC (	30	GENERIC (
	31	Mem_use : INTEGER	31	Mem_use : INTEGER := use_RAM
	32	);	32	);
	33	PORT (	33	PORT (
	34	clk : IN STD_LOGIC;	34	clk : IN STD_LOGIC;
	35	rstn : IN STD_LOGIC;	35	rstn : IN STD_LOGIC;
	36		36
	37	---------------------------------------------------------------------------	37	---------------------------------------------------------------------------
	38	-- DATA INPUT	38	-- DATA INPUT
	39	---------------------------------------------------------------------------	39	---------------------------------------------------------------------------
	40	-- TIME	40	-- TIME
	41	coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo	41	coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
	42	fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo	42	fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
	43	--	43	--
	44	sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	44	sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	45	sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	45	sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	46	--	46	--
	47	sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	47	sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	48	sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	48	sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	49	--	49	--
	50	sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	50	sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	51	sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	51	sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	52		52
	53	---------------------------------------------------------------------------	53	---------------------------------------------------------------------------
	54	-- DMA	54	-- DMA
	55	---------------------------------------------------------------------------	55	---------------------------------------------------------------------------
	56	dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	56	dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	57	dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	57	dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	58	dma_valid : OUT STD_LOGIC;	58	dma_valid : OUT STD_LOGIC;
	59	dma_valid_burst : OUT STD_LOGIC;	59	dma_valid_burst : OUT STD_LOGIC;
	60	dma_ren : IN STD_LOGIC;	60	dma_ren : IN STD_LOGIC;
	61	dma_done : IN STD_LOGIC;	61	dma_done : IN STD_LOGIC;
	62		62
	63	-- Reg out	63	-- Reg out
	64	ready_matrix_f0_0 : OUT STD_LOGIC;	64	ready_matrix_f0_0 : OUT STD_LOGIC;
	65	ready_matrix_f0_1 : OUT STD_LOGIC;	65	ready_matrix_f0_1 : OUT STD_LOGIC;
	66	ready_matrix_f1 : OUT STD_LOGIC;	66	ready_matrix_f1 : OUT STD_LOGIC;
	67	ready_matrix_f2 : OUT STD_LOGIC;	67	ready_matrix_f2 : OUT STD_LOGIC;
	68	error_anticipating_empty_fifo : OUT STD_LOGIC;	68	error_anticipating_empty_fifo : OUT STD_LOGIC;
	69	error_bad_component_error : OUT STD_LOGIC;	69	error_bad_component_error : OUT STD_LOGIC;
	70	debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	70	debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	71		71
	72	-- Reg In	72	-- Reg In
	73	status_ready_matrix_f0_0 :IN STD_LOGIC;	73	status_ready_matrix_f0_0 :IN STD_LOGIC;
	74	status_ready_matrix_f0_1 :IN STD_LOGIC;	74	status_ready_matrix_f0_1 :IN STD_LOGIC;
	75	status_ready_matrix_f1 :IN STD_LOGIC;	75	status_ready_matrix_f1 :IN STD_LOGIC;
	76	status_ready_matrix_f2 :IN STD_LOGIC;	76	status_ready_matrix_f2 :IN STD_LOGIC;
	77	status_error_anticipating_empty_fifo :IN STD_LOGIC;	77	status_error_anticipating_empty_fifo :IN STD_LOGIC;
	78	status_error_bad_component_error :IN STD_LOGIC;	78	status_error_bad_component_error :IN STD_LOGIC;
	79		79
	80	config_active_interruption_onNewMatrix : IN STD_LOGIC;	80	config_active_interruption_onNewMatrix : IN STD_LOGIC;
	81	config_active_interruption_onError : IN STD_LOGIC;	81	config_active_interruption_onError : IN STD_LOGIC;
	82	addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	82	addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	83	addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	83	addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	84	addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	84	addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	85	addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	85	addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	86		86
	87	matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);	87	matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	88	matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);	88	matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	89	matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);	89	matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	90	matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)	90	matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
	91		91
	92	);	92	);
	93	END;	93	END;
	94		94
	95	ARCHITECTURE Behavioral OF lpp_lfr_ms IS	95	ARCHITECTURE Behavioral OF lpp_lfr_ms IS
	96	-----------------------------------------------------------------------------	96	-----------------------------------------------------------------------------
	97	SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);	97	SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
	98	SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);	98	SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
	99	SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);	99	SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
	100	SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);	100	SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
	101	SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);	101	SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
	102	SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);	102	SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
	103		103
	104	-----------------------------------------------------------------------------	104	-----------------------------------------------------------------------------
	105	SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);	105	SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
	106	SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);	106	SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
	107	SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);	107	SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
	108	SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);	108	SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
	109		109
	110	-----------------------------------------------------------------------------	110	-----------------------------------------------------------------------------
	111	SIGNAL FFT_Load : STD_LOGIC;	111	SIGNAL FFT_Load : STD_LOGIC;
	112	SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);	112	SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
	113	SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);	113	SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
	114	SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);	114	SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
	115	SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);	115	SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
	116		116
	117	-----------------------------------------------------------------------------	117	-----------------------------------------------------------------------------
	118	SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);	118	SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
	119	SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);	119	SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
	120		120
	121	-----------------------------------------------------------------------------	121	-----------------------------------------------------------------------------
	122	SIGNAL SM_FlagError : STD_LOGIC;	122	SIGNAL SM_FlagError : STD_LOGIC;
	123	-- SIGNAL SM_Pong : STD_LOGIC;	123	-- SIGNAL SM_Pong : STD_LOGIC;
	124	SIGNAL SM_Wen : STD_LOGIC;	124	SIGNAL SM_Wen : STD_LOGIC;
	125	SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);	125	SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
	126	SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);	126	SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
	127	SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);	127	SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
	128	SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);	128	SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
	129	SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);	129	SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
	130		130
	131	-----------------------------------------------------------------------------	131	-----------------------------------------------------------------------------
	132	SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);	132	SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
	133	SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);	133	SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
	134	SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);	134	SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
	135		135
	136	-----------------------------------------------------------------------------	136	-----------------------------------------------------------------------------
	137	SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);	137	SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
	138	SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);	138	SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
	139	SIGNAL Head_Empty : STD_LOGIC;	139	SIGNAL Head_Empty : STD_LOGIC;
	140	SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);	140	SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
	141	SIGNAL Head_Valid : STD_LOGIC;	141	SIGNAL Head_Valid : STD_LOGIC;
	142	SIGNAL Head_Val : STD_LOGIC;	142	SIGNAL Head_Val : STD_LOGIC;
	143		143
	144	-----------------------------------------------------------------------------	144	-----------------------------------------------------------------------------
	145	SIGNAL DMA_Read : STD_LOGIC;	145	SIGNAL DMA_Read : STD_LOGIC;
	146	SIGNAL DMA_ack : STD_LOGIC;	146	SIGNAL DMA_ack : STD_LOGIC;
	147		147
	148	-----------------------------------------------------------------------------	148	-----------------------------------------------------------------------------
	149	SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0);	149	SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
	150		150
	151	BEGIN	151	SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
	152		152	SIGNAL dma_valid_s : STD_LOGIC;
	153	-----------------------------------------------------------------------------	153	SIGNAL dma_valid_burst_s : STD_LOGIC;
	154	Memf0: lppFIFOxN	154
	155	GENERIC MAP (	155	BEGIN
	156	tech => 0, Mem_use => Mem_use, Data_sz => 16,	156
	157	Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')	157	-----------------------------------------------------------------------------
	158	PORT MAP (	158	Memf0: lppFIFOxN
	159	rstn => rstn, wclk => clk, rclk => clk,	159	GENERIC MAP (
	160	ReUse => (OTHERS => '0'),	160	tech => 0, Mem_use => Mem_use, Data_sz => 16,
	161	wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),	161	Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
	162	wdata => sample_f0_wdata, rdata => FifoF0_Data,	162	PORT MAP (
	163	full => OPEN, empty => FifoF0_Empty);	163	rstn => rstn, wclk => clk, rclk => clk,
	164		164	ReUse => (OTHERS => '0'),
	165	Memf1: lppFIFOxN	165	wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
	166	GENERIC MAP (	166	wdata => sample_f0_wdata, rdata => FifoF0_Data,
	167	tech => 0, Mem_use => Mem_use, Data_sz => 16,	167	full => OPEN, empty => FifoF0_Empty);
	168	Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')	168
	169	PORT MAP (	169	Memf1: lppFIFOxN
	170	rstn => rstn, wclk => clk, rclk => clk,	170	GENERIC MAP (
	171	ReUse => (OTHERS => '0'),	171	tech => 0, Mem_use => Mem_use, Data_sz => 16,
	172	wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),	172	Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
	173	wdata => sample_f1_wdata, rdata => FifoF1_Data,	173	PORT MAP (
	174	full => OPEN, empty => FifoF1_Empty);	174	rstn => rstn, wclk => clk, rclk => clk,
	175		175	ReUse => (OTHERS => '0'),
	176		176	wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
	177	Memf2: lppFIFOxN	177	wdata => sample_f1_wdata, rdata => FifoF1_Data,
	178	GENERIC MAP (	178	full => OPEN, empty => FifoF1_Empty);
	179	tech => 0, Mem_use => Mem_use, Data_sz => 16,	179
	180	Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')	180
	181	PORT MAP (	181	Memf2: lppFIFOxN
	182	rstn => rstn, wclk => clk, rclk => clk,	182	GENERIC MAP (
	183	ReUse => (OTHERS => '0'),	183	tech => 0, Mem_use => Mem_use, Data_sz => 16,
	184	wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),	184	Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
	185	wdata => sample_f3_wdata, rdata => FifoF3_Data,	185	PORT MAP (
	186	full => OPEN, empty => FifoF3_Empty);	186	rstn => rstn, wclk => clk, rclk => clk,
	187	-----------------------------------------------------------------------------	187	ReUse => (OTHERS => '0'),
	188		188	wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
	189		189	wdata => sample_f3_wdata, rdata => FifoF3_Data,
	190	-----------------------------------------------------------------------------	190	full => OPEN, empty => FifoF3_Empty);
	191	DMUX0 : DEMUX	191	-----------------------------------------------------------------------------
	192	GENERIC MAP (	192
	193	Data_sz => 16)	193
	194	PORT MAP (	194	-----------------------------------------------------------------------------
	195	clk => clk,	195	DMUX0 : DEMUX
	196	rstn => rstn,	196	GENERIC MAP (
	197	Read => FFT_Read,	197	Data_sz => 16)
	198	Load => FFT_Load,	198	PORT MAP (
	199	EmptyF0 => FifoF0_Empty,	199	clk => clk,
	200	EmptyF1 => FifoF1_Empty,	200	rstn => rstn,
	201	EmptyF2 => FifoF3_Empty,	201	Read => FFT_Read,
	202	~~DataF0~~ => F~~ifoF0_Data~~,	202	Load => FFT_Load,
	203	~~DataF1~~ => FifoF~~1_Data~~,	203	EmptyF0 => FifoF0_Empty,
	204	~~DataF2~~ => FifoF~~3_Data~~,	204	EmptyF1 => FifoF1_Empty,
	205	WorkFreq => DMUX_WorkFreq,	205	EmptyF2 => FifoF3_Empty,
	206	Read_DEMUX => DMUX_Read,	206	DataF0 => FifoF0_Data,
	207	Empty => DMUX_Empty,	207	DataF1 => FifoF1_Data,
	208	Data => ~~DMUX_Data~~);	208	DataF2 => FifoF3_Data,
	209	-----------------------------------------------------------------------------	209	WorkFreq => DMUX_WorkFreq,
	210		210	Read_DEMUX => DMUX_Read,
	211		211	Empty => DMUX_Empty,
	212	-----------------------------------------------------------------------------	212	Data => DMUX_Data);
	213	FFT0: FFT	213	-----------------------------------------------------------------------------
	214	GENERIC MAP (	214
	215	Data_sz => 16,	215
	216	NbData => 256)	216	-----------------------------------------------------------------------------
	217	PORT MAP (	217	FFT0: FFT
	218	clkm => clk,	218	GENERIC MAP (
	219	rstn => rstn,	219	Data_sz => 16,
	220	FifoIN_Empty => DMUX_Empty,	220	NbData => 256)
	221	FifoIN_Data => DMUX_Data,	221	PORT MAP (
	222	FifoOUT_Full => FifoINT_Full,	222	clkm => clk,
	223	~~Load~~ => ~~FFT_Load~~,	223	rstn => rstn,
	224	Read => FFT_Read,	224	FifoIN_Empty => DMUX_Empty,
	225	Write => FFT_Write,	225	FifoIN_Data => DMUX_Data,
	226	ReUse => FFT_ReUse,	226	FifoOUT_Full => FifoINT_Full,
	227	~~Data~~ => FFT_~~Data~~);	227	Load => FFT_Load,
	228	-----------------------------------------------------------------------------	228	Read => FFT_Read,
	229		229	Write => FFT_Write,
	230		230	ReUse => FFT_ReUse,
	231	-----------------------------------------------------------------------------	231	Data => FFT_Data);
	232	MemInt : lppFIFOxN	232	-----------------------------------------------------------------------------
	233	GENERIC MAP (	233
	234	tech => 0,	234
	235	Mem_use => Mem_use,	235	-----------------------------------------------------------------------------
	236	Data_sz => 16,	236	MemInt : lppFIFOxN
	237	Addr_sz => 8,	237	GENERIC MAP (
	238	~~FifoCn~~t => 5,	238	tech => 0,
	239	Enable_ReUse => '1')	239	Mem_use => Mem_use,
	240	PORT MAP (	240	Data_sz => 16,
	241	~~rstn~~ => ~~rstn~~,	241	Addr_sz => 8,
	242	wclk => clk,	242	FifoCnt => 5,
	243	rclk => clk,	243	Enable_ReUse => '1')
	244	ReUse => SM_ReUse,	244	PORT MAP (
	245	wen => ~~FFT_Write~~,	245	rstn => rstn,
	246	ren => SM_Read,	246	wclk => clk,
	247	wdata => FFT_Data,	247	rclk => clk,
	248	rdata => FifoINT_Data,	248	ReUse => SM_ReUse,
	249	full => FifoINT_Full,	249	wen => FFT_Write,
	250	empty => OPEN);	250	ren => SM_Read,
	251	-----------------------------------------------------------------------------	251	wdata => FFT_Data,
	252		252	rdata => FifoINT_Data,
	253	-----------------------------------------------------------------------------	253	full => FifoINT_Full,
	254	SM0 : MatriceSpectrale	254	empty => OPEN);
	255	GENERIC MAP (	255	-----------------------------------------------------------------------------
	256	Input_SZ => 16,	256
	257	Result_SZ => 32)	257	-----------------------------------------------------------------------------
	258	PORT MAP (	258	SM0 : MatriceSpectrale
	259	clkm => clk,	259	GENERIC MAP (
	260	rstn => rstn,	260	Input_SZ => 16,
	261	FifoIN_Full => FifoINT_Full,	261	Result_SZ => 32)
	262	SetReUse => FFT_ReUse,	262	PORT MAP (
	263	~~Valid~~ => ~~Head_Valid~~,	263	clkm => clk,
	264	Data_IN => FifoINT_Data,	264	rstn => rstn,
	265	ACK => DMA_ack,	265	FifoIN_Full => FifoINT_Full,
	266	SM_Write => SM_Wen,	266	SetReUse => FFT_ReUse,
	267	FlagError => SM_FlagError,	267	Valid => Head_Valid,
	268	-- Pong => SM_Pong,	268	Data_IN => FifoINT_Data,
	269	~~Statu~~ => ~~SM_Param~~,	269	ACK => DMA_ack,
	270	Write => SM_W~~rit~~e,	270	SM_Write => SM_Wen,
	271	Read => SM_Read,	271	FlagError => SM_FlagError,
	272	ReUse => SM_ReUse,	272	-- Pong => SM_Pong,
	273	~~Data_OUT~~ => SM_~~Data~~);	273	Statu => SM_Param,
	274	-----------------------------------------------------------------------------	274	Write => SM_Write,
	275		275	Read => SM_Read,
	276	-----------------------------------------------------------------------------	276	ReUse => SM_ReUse,
	277	MemOut : lppFIFOxN	277	Data_OUT => SM_Data);
	278	GENERIC MAP (	278	-----------------------------------------------------------------------------
	279	tech => 0,	279
	280	Mem_use => Mem_use,	280	-----------------------------------------------------------------------------
	281	Data_sz => 32,	281	MemOut : lppFIFOxN
	282	Addr_sz => 8,	282	GENERIC MAP (
	283	~~FifoCn~~t => 2,	283	tech => 0,
	284	Enable_ReUse => '0')	284	Mem_use => Mem_use,
	285	PORT MAP (	285	Data_sz => 32,
	286	~~rstn~~ => ~~rstn~~,	286	Addr_sz => 8,
	287	wclk => clk,	287	FifoCnt => 2,
	288	rclk => clk,	288	Enable_ReUse => '0')
	289	ReUse => (OTHERS => '0'),	289	PORT MAP (
	290	wen => ~~SM_Write~~,	290	rstn => rstn,
	291	ren => Head_Read,	291	wclk => clk,
	292	wdata => SM_Data,	292	rclk => clk,
	293	rdata => FifoOUT_Data,	293	ReUse => (OTHERS => '0'),
	294	full => FifoOUT_Full,	294	wen => SM_Write,
	295	empty => FifoOUT_Empty);	295	ren => Head_Read,
	296	-----------------------------------------------------------------------------	296	wdata => SM_Data,
	297		297	rdata => FifoOUT_Data,
	298	-----------------------------------------------------------------------------	298	full => FifoOUT_Full,
	299	Head0 : HeaderBuilder	299	empty => FifoOUT_Empty);
	300	GENERIC MAP (	300	-----------------------------------------------------------------------------
	301	Data_sz => 32)	301
	302	PORT MAP (	302	-----------------------------------------------------------------------------
	303	clkm => clk,	303	Head0 : HeaderBuilder
	304	rstn => rstn,	304	GENERIC MAP (
	305	-- pong => SM_Pong,	305	Data_sz => 32)
	306	Statu => SM_Param,	306	PORT MAP (
	307	Matrix_Type => DMUX_WorkFreq,	307	clkm => clk,
	308	Matrix_Write => SM_Wen,	308	rstn => rstn,
	309	Valid => Head_Valid,	309	-- pong => SM_Pong,
	310		310	Statu => SM_Param,
	311	dataIN => FifoOUT_Data,	311	Matrix_Type => DMUX_WorkFreq,
	312	emptyIN => FifoOUT_Empty,	312	Matrix_Write => SM_Wen,
	313	~~RenOUT~~ => Head_~~Rea~~d,	313	Valid => Head_Valid,
	314		314
	315	data~~OUT~~ => ~~Head~~_Data,	315	dataIN => FifoOUT_Data,
	316	empty~~OUT~~ => ~~Head~~_Empty,	316	emptyIN => FifoOUT_Empty,
	317	RenIN => ~~DMA~~_Read,	317	RenOUT => Head_Read,
	318		318
	319	~~header~~ => Head_~~Header~~,	319	dataOUT => Head_Data,
	320	header_val => Head_Val,	320	emptyOUT => Head_Empty,
	321	header_ack => DMA_ack );	321	RenIN => DMA_Read,
	322	-----------------------------------------------------------------------------	322
	323	data_time(31 DOWNTO 0) <= coarse_time;	323	header => Head_Header,
	324	data_time(47 DOWNTO 32) <= fine_time;	324	header_val => Head_Val,
	325		325	header_ack => DMA_ack );
	326	lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma	326	-----------------------------------------------------------------------------
	327	PORT MAP (	327	data_time(31 DOWNTO 0) <= coarse_time;
	328	HCLK => clk,	328	data_time(47 DOWNTO 32) <= fine_time;
	329	HRESETn => rstn,	329
	330		330	lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
	331	data_time => data_time,	331	PORT MAP (
	332		332	HCLK => clk,
	333	~~fifo_data~~ => ~~Head_Data~~,	333	HRESETn => rstn,
	334	fifo_empty => Head_Empty,	334
	335	~~fifo_ren~~ => ~~DMA_Read~~,	335	data_time => data_time,
	336		336
	337	~~header~~ => Head_~~Header~~,	337	fifo_data => Head_Data,
	338	~~header_val~~ => Head_~~Val~~,	338	fifo_empty => Head_Empty,
	339	~~header_ack~~ => DMA_~~ack~~,	339	fifo_ren => DMA_Read,
	340		340
	341	~~dma_addr~~ => ~~dma_add~~r,	341	header => Head_Header,
	342	~~dma_data~~ => ~~dma_data~~,	342	header_val => Head_Val,
	343	~~dma_valid~~ => ~~dma_valid~~,	343	header_ack => DMA_ack,
	344	dma_valid_burst => dma_valid_burst,	344
	345	dma_ren => dma_ren,	345	dma_addr => dma_addr,
	346	dma_d~~one~~ => dma_d~~one~~,	346	dma_data => dma_data,
	347		347	dma_valid => dma_valid_s,
	348	~~ready_matrix_f0_0~~ => ~~ready_matrix_f0_0~~,	348	dma_valid_burst => dma_valid_burst_s,
	349	ready_matrix_f0_1 => ready_matrix_f0_1,	349	dma_ren => dma_ren,
	350	~~ready_matrix_f1~~ => ~~ready_matrix_f1~~,	350	dma_done => dma_done,
	351	ready_matrix_f2 => ready_matrix_f2,	351
	352	error_anticipating_empty_fifo => error_anticipating_empty_fifo,	352	ready_matrix_f0_0 => ready_matrix_f0_0,
	353	error_bad_component_error => error_bad_component_error,	353	ready_matrix_f0_1 => ready_matrix_f0_1,
	354	~~debug_reg~~ => ~~debug_reg~~,	354	ready_matrix_f1 => ready_matrix_f1,
	355	~~status_~~ready_matrix_f~~0_0~~ => ~~status_~~ready_matrix_f~~0_0~~,	355	ready_matrix_f2 => ready_matrix_f2,
	356	status_ready_matrix_f0_1 => status_ready_matrix_f0_1,	356	error_anticipating_empty_fifo => error_anticipating_empty_fifo,
	357	status_ready_matrix_f1 => status_ready_matrix_f1,	357	error_bad_component_error => error_bad_component_error,
	358	status_ready_matrix_f2 => status_ready_matrix_f2,	358	debug_reg => debug_reg_s,
	359	status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,	359	status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
	360	status_error_bad_component_error => status_error_bad_component_error,	360	status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
	361	config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,	361	status_ready_matrix_f1 => status_ready_matrix_f1,
	362	config_active_interruption_onError => config_active_interruption_onError,	362	status_ready_matrix_f2 => status_ready_matrix_f2,
	363	addr_matrix_f0_0 => addr_matrix_f0_0,	363	status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
	364	addr_matrix_f0_1 => addr_matrix_f0_1,	364	status_error_bad_component_error => status_error_bad_component_error,
	365	addr_matrix_f1 => addr_matrix_f1,	365	config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
	366	addr_matrix_f2 => addr_matrix_f2,	366	config_active_interruption_onError => config_active_interruption_onError,
	367		367	addr_matrix_f0_0 => addr_matrix_f0_0,
	368	matrix_~~time_f0_0~~ => matrix_~~time_f0_0~~,	368	addr_matrix_f0_1 => addr_matrix_f0_1,
	369	matrix_~~time_~~f0_1 => matrix_~~time_~~f0_1,	369	addr_matrix_f1 => addr_matrix_f1,
	370	matrix_~~time_f1~~ => matrix_~~time_f1~~,	370	addr_matrix_f2 => addr_matrix_f2,
	371	matrix_time_f2 => matrix_time_f2	371
	372	);	372	matrix_time_f0_0 => matrix_time_f0_0,
	373		373	matrix_time_f0_1 => matrix_time_f0_1,
	374	END Behavioral;	374	matrix_time_f1 => matrix_time_f1,
			375	matrix_time_f2 => matrix_time_f2
			376	);
			377
			378	dma_valid <= dma_valid_s;
			379	dma_valid_burst <= dma_valid_burst_s;
			380
			381	debug_reg(9 DOWNTO 0) <= debug_reg_s(9 DOWNTO 0);
			382	debug_reg(10) <= Head_Empty;
			383	debug_reg(11) <= DMA_Read;
			384	debug_reg(12) <= Head_Val;
			385	debug_reg(13) <= DMA_ack;
			386	debug_reg(14) <= dma_ren;
			387	debug_reg(15) <= dma_done;
			388	debug_reg(16) <= dma_valid_s;
			389	debug_reg(17) <= dma_valid_burst_s;
			390	debug_reg(31 DOWNTO 18) <= (OTHERS => '0');
			391
			392
			393
			394	END Behavioral;

lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd +6 -3

                   debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0');
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
+                  debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
                   CASE state IS
                     WHEN IDLE =>
                       debug_reg_s(2 DOWNTO 0) <= "000";
                       ready_matrix_f2           <= '0';
                       error_bad_component_error <= '0';
                       header_select             <= '1';
+                      IF header_val = '1' THEN
+                        header_ack  <= '1';
+                      END IF;
                       IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
                         debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0);
                         debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2);
                     WHEN CHECK_COMPONENT_TYPE =>
                       debug_reg_s(2 DOWNTO 0) <= "001";
+                      header_ack              <= '0';
                       IF header_check_ok = '1' THEN
-                        header_ack  <= '1';
                         header_send <= '0';
                         --
                         IF component_type = "0000" THEN
                       ELSE
                         error_bad_component_error <= '1';
                         component_type_pre        <= "0000";
-                        header_ack                <= '1';
                         state                     <= TRASH_FIFO;
                       END IF;

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