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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library lpp;
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use lpp.lpp_fft.all;
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use lpp.fft_components.all;
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-- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "cr�neau"
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entity FFT is
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generic(
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Data_sz : integer := 16;
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NbData : integer := 256);
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port(
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clkm : in std_logic;
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rstn : in std_logic;
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FifoIN_Empty : in std_logic_vector(4 downto 0);
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FifoIN_Data : in std_logic_vector(79 downto 0);
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FifoOUT_Full : in std_logic_vector(4 downto 0);
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Load : out std_logic;
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Read : out std_logic_vector(4 downto 0);
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Write : out std_logic_vector(4 downto 0);
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ReUse : out std_logic_vector(4 downto 0);
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Data : out std_logic_vector(79 downto 0)
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);
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end entity;
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architecture ar_FFT of FFT is
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signal Drive_Write : std_logic;
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signal Drive_DataRE : std_logic_vector(15 downto 0);
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signal Drive_DataIM : std_logic_vector(15 downto 0);
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signal Start : std_logic;
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signal FFT_Load : std_logic;
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signal FFT_Ready : std_logic;
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signal FFT_Valid : std_logic;
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signal FFT_DataRE : std_logic_vector(15 downto 0);
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signal FFT_DataIM : std_logic_vector(15 downto 0);
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signal Link_Read : std_logic;
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begin
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Start <= '0';
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Load <= FFT_Load;
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DRIVE : Driver_FFT
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generic map(Data_sz,NbData)
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port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
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FFT0 : CoreFFT
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generic map(
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LOGPTS => gLOGPTS,
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LOGLOGPTS => gLOGLOGPTS,
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WSIZE => gWSIZE,
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TWIDTH => gTWIDTH,
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DWIDTH => gDWIDTH,
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TDWIDTH => gTDWIDTH,
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RND_MODE => gRND_MODE,
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SCALE_MODE => gSCALE_MODE,
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PTS => gPTS,
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HALFPTS => gHALFPTS,
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inBuf_RWDLY => gInBuf_RWDLY)
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port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
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LINK : Linker_FFT
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generic map(Data_sz,NbData)
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port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
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end architecture;
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