HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r328:057b3542e4d7

MINI_LFR-WFP_MS-0.1.5.pdb

pellion -

r328:057b3542e4d7 JC

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r328:057b3542e4d7

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designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +1 -1

                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"000104")  -- aa.bb.cc version
+                  top_lfr_version        => X"000105")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => reset,

lib/lpp/dsp/lpp_fft/FFT.vhd +7 -2

                     PTS         => gPTS,
                     HALFPTS     => gHALFPTS,
                     inBuf_RWDLY => gInBuf_RWDLY)
-                    port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
+                    port map(clkm,start,rstn,
+                             Drive_Write,Link_Read,
+                             Drive_DataIM,Drive_DataRE,
+                             FFT_Load,open,
+                             FFT_DataIM,FFT_DataRE,
+                             FFT_Valid,FFT_Ready);
                 LINK : Linker_FFT
                     port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
-            end architecture;
  No newline at end of file
+            end architecture;

lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +2 -2

                 pmask    : INTEGER := 16#fff#;
                 pirq_ms  : INTEGER := 0;
                 pirq_wfp : INTEGER := 1;
-                top_lfr_version    : STD_LOGIC_VECTOR(23 DOWNTO 0));
+                top_lfr_version    : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
               PORT (
                 -- AMBA AHB system signals
                 HCLK    : IN STD_ULOGIC;
               run_ms <= reg_sp.config_ms_run;
-            END beh;
+            END beh;
  No newline at end of file

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +24 -4

             ENTITY lpp_lfr_ms IS
               GENERIC (
-                Mem_use : INTEGER
+                Mem_use : INTEGER := use_RAM
                 );
               PORT (
                 clk  : IN STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL data_time   : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
+              SIGNAL dma_valid_s       : STD_LOGIC;
+              SIGNAL dma_valid_burst_s : STD_LOGIC;
             BEGIN
               -----------------------------------------------------------------------------
                   dma_addr                               => dma_addr,
                   dma_data                               => dma_data,
-                  dma_valid                              => dma_valid,
+                  dma_valid                              => dma_valid_s,
-                  dma_valid_burst                        => dma_valid_burst,
+                  dma_valid_burst                        => dma_valid_burst_s,
                   dma_ren                                => dma_ren,
                   dma_done                               => dma_done,
                   ready_matrix_f2                        => ready_matrix_f2,
                   error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
                   error_bad_component_error              => error_bad_component_error,
-                  debug_reg                              => debug_reg,
+                  debug_reg                              => debug_reg_s,
                   status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
                   status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   matrix_time_f2                         => matrix_time_f2
                   );
+              dma_valid       <= dma_valid_s;
+              dma_valid_burst <= dma_valid_burst_s;
+              debug_reg(9 DOWNTO 0)   <= debug_reg_s(9 DOWNTO 0);
+              debug_reg(10)           <= Head_Empty;
+              debug_reg(11)           <= DMA_Read;
+              debug_reg(12)           <= Head_Val;
+              debug_reg(13)           <= DMA_ack;
+              debug_reg(14)           <= dma_ren;
+              debug_reg(15)           <= dma_done;
+              debug_reg(16)           <= dma_valid_s;
+              debug_reg(17)           <= dma_valid_burst_s;
+              debug_reg(31 DOWNTO 18) <= (OTHERS => '0');
             END Behavioral;

lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd +5 -2

                   debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0');
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
+                  debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
                   CASE state IS
                     WHEN IDLE =>
                       ready_matrix_f2           <= '0';
                       error_bad_component_error <= '0';
                       header_select             <= '1';
+                      IF header_val = '1' THEN
+                        header_ack  <= '1';
+                      END IF;
                       IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
                         debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0);
                         debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2);
                     WHEN CHECK_COMPONENT_TYPE =>
                       debug_reg_s(2 DOWNTO 0) <= "001";
+                      header_ack              <= '0';
                       IF header_check_ok = '1' THEN
-                        header_ack  <= '1';
                         header_send <= '0';
                         --
                         IF component_type = "0000" THEN
                       ELSE
                         error_bad_component_error <= '1';
                         component_type_pre        <= "0000";
-                        header_ack                <= '1';
                         state                     <= TRASH_FIFO;
                       END IF;

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