diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -425,7 +425,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000104") -- aa.bb.cc version + top_lfr_version => X"000105") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => reset, diff --git a/lib/lpp/dsp/lpp_fft/FFT.vhd b/lib/lpp/dsp/lpp_fft/FFT.vhd --- a/lib/lpp/dsp/lpp_fft/FFT.vhd +++ b/lib/lpp/dsp/lpp_fft/FFT.vhd @@ -84,7 +84,12 @@ Load <= FFT_Load; PTS => gPTS, HALFPTS => gHALFPTS, inBuf_RWDLY => gInBuf_RWDLY) - port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); + port map(clkm,start,rstn, + Drive_Write,Link_Read, + Drive_DataIM,Drive_DataRE, + FFT_Load,open, + FFT_DataIM,FFT_DataRE, + FFT_Valid,FFT_Ready); LINK : Linker_FFT @@ -92,4 +97,4 @@ Load <= FFT_Load; port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data); -end architecture; \ No newline at end of file +end architecture; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -1,544 +1,544 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com ----------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -LIBRARY lpp; -USE lpp.lpp_amba.ALL; -USE lpp.apb_devices_list.ALL; -USE lpp.lpp_memory.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -ENTITY lpp_lfr_apbreg IS - GENERIC ( - nb_data_by_buffer_size : INTEGER := 11; - nb_word_by_buffer_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_vector_size : INTEGER := 20; - delta_vector_size_f0_2 : INTEGER := 3; - - pindex : INTEGER := 4; - paddr : INTEGER := 4; - pmask : INTEGER := 16#fff#; - pirq_ms : INTEGER := 0; - pirq_wfp : INTEGER := 1; - top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); - PORT ( - -- AMBA AHB system signals - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - - -- AMBA APB Slave Interface - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - - --------------------------------------------------------------------------- - -- Spectral Matrix Reg - run_ms : OUT STD_LOGIC; - -- IN - ready_matrix_f0_0 : IN STD_LOGIC; - ready_matrix_f0_1 : IN STD_LOGIC; - ready_matrix_f1 : IN STD_LOGIC; - ready_matrix_f2 : IN STD_LOGIC; - error_anticipating_empty_fifo : IN STD_LOGIC; - error_bad_component_error : IN STD_LOGIC; - debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - - -- OUT - status_ready_matrix_f0_0 : OUT STD_LOGIC; - status_ready_matrix_f0_1 : OUT STD_LOGIC; - status_ready_matrix_f1 : OUT STD_LOGIC; - status_ready_matrix_f2 : OUT STD_LOGIC; - status_error_anticipating_empty_fifo : OUT STD_LOGIC; - status_error_bad_component_error : OUT STD_LOGIC; - - config_active_interruption_onNewMatrix : OUT STD_LOGIC; - config_active_interruption_onError : OUT STD_LOGIC; - - addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - - --------------------------------------------------------------------------- - --------------------------------------------------------------------------- - -- WaveForm picker Reg - status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - - -- OUT - data_shaping_BW : OUT STD_LOGIC; - data_shaping_SP0 : OUT STD_LOGIC; - data_shaping_SP1 : OUT STD_LOGIC; - data_shaping_R0 : OUT STD_LOGIC; - data_shaping_R1 : OUT STD_LOGIC; - - delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); - delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); - nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - - enable_f0 : OUT STD_LOGIC; - enable_f1 : OUT STD_LOGIC; - enable_f2 : OUT STD_LOGIC; - enable_f3 : OUT STD_LOGIC; - - burst_f0 : OUT STD_LOGIC; - burst_f1 : OUT STD_LOGIC; - burst_f2 : OUT STD_LOGIC; - - run : OUT STD_LOGIC; - - addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); - --------------------------------------------------------------------------- - debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - - --------------------------------------------------------------------------- - ); - -END lpp_lfr_apbreg; - -ARCHITECTURE beh OF lpp_lfr_apbreg IS - - CONSTANT REVISION : INTEGER := 1; - - CONSTANT pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), - 1 => apb_iobar(paddr, pmask)); - - TYPE lpp_SpectralMatrix_regs IS RECORD - config_active_interruption_onNewMatrix : STD_LOGIC; - config_active_interruption_onError : STD_LOGIC; - config_ms_run : STD_LOGIC; - status_ready_matrix_f0_0 : STD_LOGIC; - status_ready_matrix_f0_1 : STD_LOGIC; - status_ready_matrix_f1 : STD_LOGIC; - status_ready_matrix_f2 : STD_LOGIC; - status_error_anticipating_empty_fifo : STD_LOGIC; - status_error_bad_component_error : STD_LOGIC; - addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - - coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - --- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); --- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); --- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); --- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); - END RECORD; - SIGNAL reg_sp : lpp_SpectralMatrix_regs; - - TYPE lpp_WaveformPicker_regs IS RECORD - status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - data_shaping_BW : STD_LOGIC; - data_shaping_SP0 : STD_LOGIC; - data_shaping_SP1 : STD_LOGIC; - data_shaping_R0 : STD_LOGIC; - data_shaping_R1 : STD_LOGIC; - delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); - delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); - nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - enable_f0 : STD_LOGIC; - enable_f1 : STD_LOGIC; - enable_f2 : STD_LOGIC; - enable_f3 : STD_LOGIC; - burst_f0 : STD_LOGIC; - burst_f1 : STD_LOGIC; - burst_f2 : STD_LOGIC; - run : STD_LOGIC; - addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); - start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); - END RECORD; - SIGNAL reg_wp : lpp_WaveformPicker_regs; - - SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - - ----------------------------------------------------------------------------- - -- IRQ - ----------------------------------------------------------------------------- - CONSTANT IRQ_WFP_SIZE : INTEGER := 12; - SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); - SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); - SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); - SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); - SIGNAL ored_irq_wfp : STD_LOGIC; - -BEGIN -- beh - - status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; - status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; - status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; - status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; - status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; - status_error_bad_component_error <= reg_sp.status_error_bad_component_error; - - config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; - config_active_interruption_onError <= reg_sp.config_active_interruption_onError; - addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; - addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; - addr_matrix_f1 <= reg_sp.addr_matrix_f1; - addr_matrix_f2 <= reg_sp.addr_matrix_f2; - - - data_shaping_BW <= NOT reg_wp.data_shaping_BW; - data_shaping_SP0 <= reg_wp.data_shaping_SP0; - data_shaping_SP1 <= reg_wp.data_shaping_SP1; - data_shaping_R0 <= reg_wp.data_shaping_R0; - data_shaping_R1 <= reg_wp.data_shaping_R1; - - delta_snapshot <= reg_wp.delta_snapshot; - delta_f0 <= reg_wp.delta_f0; - delta_f0_2 <= reg_wp.delta_f0_2; - delta_f1 <= reg_wp.delta_f1; - delta_f2 <= reg_wp.delta_f2; - nb_data_by_buffer <= reg_wp.nb_data_by_buffer; - nb_word_by_buffer <= reg_wp.nb_word_by_buffer; - nb_snapshot_param <= reg_wp.nb_snapshot_param; - - enable_f0 <= reg_wp.enable_f0; - enable_f1 <= reg_wp.enable_f1; - enable_f2 <= reg_wp.enable_f2; - enable_f3 <= reg_wp.enable_f3; - - burst_f0 <= reg_wp.burst_f0; - burst_f1 <= reg_wp.burst_f1; - burst_f2 <= reg_wp.burst_f2; - - run <= reg_wp.run; - - addr_data_f0 <= reg_wp.addr_data_f0; - addr_data_f1 <= reg_wp.addr_data_f1; - addr_data_f2 <= reg_wp.addr_data_f2; - addr_data_f3 <= reg_wp.addr_data_f3; - - start_date <= reg_wp.start_date; - - lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) - VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); - BEGIN -- PROCESS lpp_dma_top - IF HRESETn = '0' THEN -- asynchronous reset (active low) - reg_sp.config_active_interruption_onNewMatrix <= '0'; - reg_sp.config_active_interruption_onError <= '0'; - reg_sp.config_ms_run <= '1'; - reg_sp.status_ready_matrix_f0_0 <= '0'; - reg_sp.status_ready_matrix_f0_1 <= '0'; - reg_sp.status_ready_matrix_f1 <= '0'; - reg_sp.status_ready_matrix_f2 <= '0'; - reg_sp.status_error_anticipating_empty_fifo <= '0'; - reg_sp.status_error_bad_component_error <= '0'; - reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); - reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); - reg_sp.addr_matrix_f1 <= (OTHERS => '0'); - reg_sp.addr_matrix_f2 <= (OTHERS => '0'); - - reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); - reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); - reg_sp.coarse_time_f1 <= (OTHERS => '0'); - reg_sp.coarse_time_f2 <= (OTHERS => '0'); - --reg_sp.fine_time_f0_0 <= (OTHERS => '0'); - --reg_sp.fine_time_f0_1 <= (OTHERS => '0'); - --reg_sp.fine_time_f1 <= (OTHERS => '0'); - --reg_sp.fine_time_f2 <= (OTHERS => '0'); - - prdata <= (OTHERS => '0'); - - apbo.pirq <= (OTHERS => '0'); - - status_full_ack <= (OTHERS => '0'); - - reg_wp.data_shaping_BW <= '0'; - reg_wp.data_shaping_SP0 <= '0'; - reg_wp.data_shaping_SP1 <= '0'; - reg_wp.data_shaping_R0 <= '0'; - reg_wp.data_shaping_R1 <= '0'; - reg_wp.enable_f0 <= '0'; - reg_wp.enable_f1 <= '0'; - reg_wp.enable_f2 <= '0'; - reg_wp.enable_f3 <= '0'; - reg_wp.burst_f0 <= '0'; - reg_wp.burst_f1 <= '0'; - reg_wp.burst_f2 <= '0'; - reg_wp.run <= '0'; - reg_wp.addr_data_f0 <= (OTHERS => '0'); - reg_wp.addr_data_f1 <= (OTHERS => '0'); - reg_wp.addr_data_f2 <= (OTHERS => '0'); - reg_wp.addr_data_f3 <= (OTHERS => '0'); - reg_wp.status_full <= (OTHERS => '0'); - reg_wp.status_full_err <= (OTHERS => '0'); - reg_wp.status_new_err <= (OTHERS => '0'); - reg_wp.delta_snapshot <= (OTHERS => '0'); - reg_wp.delta_f0 <= (OTHERS => '0'); - reg_wp.delta_f0_2 <= (OTHERS => '0'); - reg_wp.delta_f1 <= (OTHERS => '0'); - reg_wp.delta_f2 <= (OTHERS => '0'); - reg_wp.nb_data_by_buffer <= (OTHERS => '0'); - reg_wp.nb_snapshot_param <= (OTHERS => '0'); - reg_wp.start_date <= (OTHERS => '0'); - - ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge - - reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); - reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); - reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); - reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); - - --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); - --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); - --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); - --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); - - status_full_ack <= (OTHERS => '0'); - - reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; - reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; - reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; - reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; - - reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; - reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; - all_status: FOR I IN 3 DOWNTO 0 LOOP - --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; - --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; - --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; - reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; - reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; - reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; - END LOOP all_status; - - paddr := "000000"; - paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); - prdata <= (OTHERS => '0'); - IF apbi.psel(pindex) = '1' THEN - -- APB DMA READ -- - CASE paddr(7 DOWNTO 2) IS - -- - WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; - prdata(1) <= reg_sp.config_active_interruption_onError; - prdata(2) <= reg_sp.config_ms_run; - WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; - prdata(1) <= reg_sp.status_ready_matrix_f0_1; - prdata(2) <= reg_sp.status_ready_matrix_f1; - prdata(3) <= reg_sp.status_ready_matrix_f2; - prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; - prdata(5) <= reg_sp.status_error_bad_component_error; - WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; - WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; - WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; - WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; - - WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; - WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; - WHEN "001000" => prdata <= reg_sp.coarse_time_f1; - WHEN "001001" => prdata <= reg_sp.coarse_time_f2; - WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; - WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; - WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; - WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; - - WHEN "001111" => prdata <= debug_reg; - --------------------------------------------------------------------- - WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; - prdata(1) <= reg_wp.data_shaping_SP0; - prdata(2) <= reg_wp.data_shaping_SP1; - prdata(3) <= reg_wp.data_shaping_R0; - prdata(4) <= reg_wp.data_shaping_R1; - WHEN "010001" => prdata(0) <= reg_wp.enable_f0; - prdata(1) <= reg_wp.enable_f1; - prdata(2) <= reg_wp.enable_f2; - prdata(3) <= reg_wp.enable_f3; - prdata(4) <= reg_wp.burst_f0; - prdata(5) <= reg_wp.burst_f1; - prdata(6) <= reg_wp.burst_f2; - prdata(7) <= reg_wp.run; - WHEN "010010" => prdata <= reg_wp.addr_data_f0; - WHEN "010011" => prdata <= reg_wp.addr_data_f1; - WHEN "010100" => prdata <= reg_wp.addr_data_f2; - WHEN "010101" => prdata <= reg_wp.addr_data_f3; - WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; - prdata(7 DOWNTO 4) <= reg_wp.status_full_err; - prdata(11 DOWNTO 8) <= reg_wp.status_new_err; - WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; - WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; - WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; - WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; - WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; - WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; - WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; - WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; - WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; - ---------------------------------------------------- - WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); - WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); - WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); - WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); - WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); - WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); - WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); - WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); - ---------------------------------------------------- - WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); - WHEN OTHERS => NULL; - - END CASE; - IF (apbi.pwrite AND apbi.penable) = '1' THEN - -- APB DMA WRITE -- - CASE paddr(7 DOWNTO 2) IS - -- - WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); - reg_sp.config_active_interruption_onError <= apbi.pwdata(1); - reg_sp.config_ms_run <= apbi.pwdata(2); - WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); - reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); - reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); - reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); - reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); - reg_sp.status_error_bad_component_error <= apbi.pwdata(5); - WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; - WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; - WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; - WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; - -- - WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); - reg_wp.data_shaping_SP0 <= apbi.pwdata(1); - reg_wp.data_shaping_SP1 <= apbi.pwdata(2); - reg_wp.data_shaping_R0 <= apbi.pwdata(3); - reg_wp.data_shaping_R1 <= apbi.pwdata(4); - WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); - reg_wp.enable_f1 <= apbi.pwdata(1); - reg_wp.enable_f2 <= apbi.pwdata(2); - reg_wp.enable_f3 <= apbi.pwdata(3); - reg_wp.burst_f0 <= apbi.pwdata(4); - reg_wp.burst_f1 <= apbi.pwdata(5); - reg_wp.burst_f2 <= apbi.pwdata(6); - reg_wp.run <= apbi.pwdata(7); - WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; - WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; - WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; - WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; - WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); - reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); - reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); - status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); - status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); - status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); - status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); - WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); - WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); - WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); - WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); - WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); - -- - WHEN OTHERS => NULL; - END CASE; - END IF; - END IF; - - apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR - ready_matrix_f0_1 OR - ready_matrix_f1 OR - ready_matrix_f2) - ) - OR - (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR - error_bad_component_error) - )); - - apbo.pirq(pirq_wfp) <= ored_irq_wfp; - - END IF; - END PROCESS lpp_lfr_apbreg; - - apbo.pindex <= pindex; - apbo.pconfig <= pconfig; - apbo.prdata <= prdata; - - ----------------------------------------------------------------------------- - -- IRQ - ----------------------------------------------------------------------------- - irq_wfp_reg_s <= status_full & status_full_err & status_new_err; - - PROCESS (HCLK, HRESETn) - BEGIN -- PROCESS - IF HRESETn = '0' THEN -- asynchronous reset (active low) - irq_wfp_reg <= (OTHERS => '0'); - ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge - irq_wfp_reg <= irq_wfp_reg_s; - END IF; - END PROCESS; - - all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE - irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); - END GENERATE all_irq_wfp; - - irq_wfp_ZERO <= (OTHERS => '0'); - ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; - - run_ms <= reg_sp.config_ms_run; - -END beh; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_lfr_apbreg IS + GENERIC ( + nb_data_by_buffer_size : INTEGER := 11; + nb_word_by_buffer_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_vector_size : INTEGER := 20; + delta_vector_size_f0_2 : INTEGER := 3; + + pindex : INTEGER := 4; + paddr : INTEGER := 4; + pmask : INTEGER := 16#fff#; + pirq_ms : INTEGER := 0; + pirq_wfp : INTEGER := 1; + top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000"); + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- AMBA APB Slave Interface + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + + --------------------------------------------------------------------------- + -- Spectral Matrix Reg + run_ms : OUT STD_LOGIC; + -- IN + ready_matrix_f0_0 : IN STD_LOGIC; + ready_matrix_f0_1 : IN STD_LOGIC; + ready_matrix_f1 : IN STD_LOGIC; + ready_matrix_f2 : IN STD_LOGIC; + error_anticipating_empty_fifo : IN STD_LOGIC; + error_bad_component_error : IN STD_LOGIC; + debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- OUT + status_ready_matrix_f0_0 : OUT STD_LOGIC; + status_ready_matrix_f0_1 : OUT STD_LOGIC; + status_ready_matrix_f1 : OUT STD_LOGIC; + status_ready_matrix_f2 : OUT STD_LOGIC; + status_error_anticipating_empty_fifo : OUT STD_LOGIC; + status_error_bad_component_error : OUT STD_LOGIC; + + config_active_interruption_onNewMatrix : OUT STD_LOGIC; + config_active_interruption_onError : OUT STD_LOGIC; + + addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + + --------------------------------------------------------------------------- + --------------------------------------------------------------------------- + -- WaveForm picker Reg + status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- OUT + data_shaping_BW : OUT STD_LOGIC; + data_shaping_SP0 : OUT STD_LOGIC; + data_shaping_SP1 : OUT STD_LOGIC; + data_shaping_R0 : OUT STD_LOGIC; + data_shaping_R1 : OUT STD_LOGIC; + + delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); + nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + + enable_f0 : OUT STD_LOGIC; + enable_f1 : OUT STD_LOGIC; + enable_f2 : OUT STD_LOGIC; + enable_f3 : OUT STD_LOGIC; + + burst_f0 : OUT STD_LOGIC; + burst_f1 : OUT STD_LOGIC; + burst_f2 : OUT STD_LOGIC; + + run : OUT STD_LOGIC; + + addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); + --------------------------------------------------------------------------- + debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + + --------------------------------------------------------------------------- + ); + +END lpp_lfr_apbreg; + +ARCHITECTURE beh OF lpp_lfr_apbreg IS + + CONSTANT REVISION : INTEGER := 1; + + CONSTANT pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), + 1 => apb_iobar(paddr, pmask)); + + TYPE lpp_SpectralMatrix_regs IS RECORD + config_active_interruption_onNewMatrix : STD_LOGIC; + config_active_interruption_onError : STD_LOGIC; + config_ms_run : STD_LOGIC; + status_ready_matrix_f0_0 : STD_LOGIC; + status_ready_matrix_f0_1 : STD_LOGIC; + status_ready_matrix_f1 : STD_LOGIC; + status_ready_matrix_f2 : STD_LOGIC; + status_error_anticipating_empty_fifo : STD_LOGIC; + status_error_bad_component_error : STD_LOGIC; + addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + +-- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); +-- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); +-- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); +-- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + END RECORD; + SIGNAL reg_sp : lpp_SpectralMatrix_regs; + + TYPE lpp_WaveformPicker_regs IS RECORD + status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + data_shaping_BW : STD_LOGIC; + data_shaping_SP0 : STD_LOGIC; + data_shaping_SP1 : STD_LOGIC; + data_shaping_R0 : STD_LOGIC; + data_shaping_R1 : STD_LOGIC; + delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); + nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + enable_f0 : STD_LOGIC; + enable_f1 : STD_LOGIC; + enable_f2 : STD_LOGIC; + enable_f3 : STD_LOGIC; + burst_f0 : STD_LOGIC; + burst_f1 : STD_LOGIC; + burst_f2 : STD_LOGIC; + run : STD_LOGIC; + addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); + END RECORD; + SIGNAL reg_wp : lpp_WaveformPicker_regs; + + SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- IRQ + ----------------------------------------------------------------------------- + CONSTANT IRQ_WFP_SIZE : INTEGER := 12; + SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); + SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); + SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); + SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); + SIGNAL ored_irq_wfp : STD_LOGIC; + +BEGIN -- beh + + status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; + status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; + status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; + status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; + status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; + status_error_bad_component_error <= reg_sp.status_error_bad_component_error; + + config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; + config_active_interruption_onError <= reg_sp.config_active_interruption_onError; + addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; + addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; + addr_matrix_f1 <= reg_sp.addr_matrix_f1; + addr_matrix_f2 <= reg_sp.addr_matrix_f2; + + + data_shaping_BW <= NOT reg_wp.data_shaping_BW; + data_shaping_SP0 <= reg_wp.data_shaping_SP0; + data_shaping_SP1 <= reg_wp.data_shaping_SP1; + data_shaping_R0 <= reg_wp.data_shaping_R0; + data_shaping_R1 <= reg_wp.data_shaping_R1; + + delta_snapshot <= reg_wp.delta_snapshot; + delta_f0 <= reg_wp.delta_f0; + delta_f0_2 <= reg_wp.delta_f0_2; + delta_f1 <= reg_wp.delta_f1; + delta_f2 <= reg_wp.delta_f2; + nb_data_by_buffer <= reg_wp.nb_data_by_buffer; + nb_word_by_buffer <= reg_wp.nb_word_by_buffer; + nb_snapshot_param <= reg_wp.nb_snapshot_param; + + enable_f0 <= reg_wp.enable_f0; + enable_f1 <= reg_wp.enable_f1; + enable_f2 <= reg_wp.enable_f2; + enable_f3 <= reg_wp.enable_f3; + + burst_f0 <= reg_wp.burst_f0; + burst_f1 <= reg_wp.burst_f1; + burst_f2 <= reg_wp.burst_f2; + + run <= reg_wp.run; + + addr_data_f0 <= reg_wp.addr_data_f0; + addr_data_f1 <= reg_wp.addr_data_f1; + addr_data_f2 <= reg_wp.addr_data_f2; + addr_data_f3 <= reg_wp.addr_data_f3; + + start_date <= reg_wp.start_date; + + lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) + VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); + BEGIN -- PROCESS lpp_dma_top + IF HRESETn = '0' THEN -- asynchronous reset (active low) + reg_sp.config_active_interruption_onNewMatrix <= '0'; + reg_sp.config_active_interruption_onError <= '0'; + reg_sp.config_ms_run <= '1'; + reg_sp.status_ready_matrix_f0_0 <= '0'; + reg_sp.status_ready_matrix_f0_1 <= '0'; + reg_sp.status_ready_matrix_f1 <= '0'; + reg_sp.status_ready_matrix_f2 <= '0'; + reg_sp.status_error_anticipating_empty_fifo <= '0'; + reg_sp.status_error_bad_component_error <= '0'; + reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); + reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); + reg_sp.addr_matrix_f1 <= (OTHERS => '0'); + reg_sp.addr_matrix_f2 <= (OTHERS => '0'); + + reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); + reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); + reg_sp.coarse_time_f1 <= (OTHERS => '0'); + reg_sp.coarse_time_f2 <= (OTHERS => '0'); + --reg_sp.fine_time_f0_0 <= (OTHERS => '0'); + --reg_sp.fine_time_f0_1 <= (OTHERS => '0'); + --reg_sp.fine_time_f1 <= (OTHERS => '0'); + --reg_sp.fine_time_f2 <= (OTHERS => '0'); + + prdata <= (OTHERS => '0'); + + apbo.pirq <= (OTHERS => '0'); + + status_full_ack <= (OTHERS => '0'); + + reg_wp.data_shaping_BW <= '0'; + reg_wp.data_shaping_SP0 <= '0'; + reg_wp.data_shaping_SP1 <= '0'; + reg_wp.data_shaping_R0 <= '0'; + reg_wp.data_shaping_R1 <= '0'; + reg_wp.enable_f0 <= '0'; + reg_wp.enable_f1 <= '0'; + reg_wp.enable_f2 <= '0'; + reg_wp.enable_f3 <= '0'; + reg_wp.burst_f0 <= '0'; + reg_wp.burst_f1 <= '0'; + reg_wp.burst_f2 <= '0'; + reg_wp.run <= '0'; + reg_wp.addr_data_f0 <= (OTHERS => '0'); + reg_wp.addr_data_f1 <= (OTHERS => '0'); + reg_wp.addr_data_f2 <= (OTHERS => '0'); + reg_wp.addr_data_f3 <= (OTHERS => '0'); + reg_wp.status_full <= (OTHERS => '0'); + reg_wp.status_full_err <= (OTHERS => '0'); + reg_wp.status_new_err <= (OTHERS => '0'); + reg_wp.delta_snapshot <= (OTHERS => '0'); + reg_wp.delta_f0 <= (OTHERS => '0'); + reg_wp.delta_f0_2 <= (OTHERS => '0'); + reg_wp.delta_f1 <= (OTHERS => '0'); + reg_wp.delta_f2 <= (OTHERS => '0'); + reg_wp.nb_data_by_buffer <= (OTHERS => '0'); + reg_wp.nb_snapshot_param <= (OTHERS => '0'); + reg_wp.start_date <= (OTHERS => '0'); + + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + + reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); + reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); + reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); + reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); + + --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); + --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); + --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); + --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); + + status_full_ack <= (OTHERS => '0'); + + reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; + reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; + reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; + reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; + + reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; + reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; + all_status: FOR I IN 3 DOWNTO 0 LOOP + --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; + --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; + --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; + reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; + reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; + reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; + END LOOP all_status; + + paddr := "000000"; + paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); + prdata <= (OTHERS => '0'); + IF apbi.psel(pindex) = '1' THEN + -- APB DMA READ -- + CASE paddr(7 DOWNTO 2) IS + -- + WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; + prdata(1) <= reg_sp.config_active_interruption_onError; + prdata(2) <= reg_sp.config_ms_run; + WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; + prdata(1) <= reg_sp.status_ready_matrix_f0_1; + prdata(2) <= reg_sp.status_ready_matrix_f1; + prdata(3) <= reg_sp.status_ready_matrix_f2; + prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; + prdata(5) <= reg_sp.status_error_bad_component_error; + WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; + WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; + WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; + WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; + + WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; + WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; + WHEN "001000" => prdata <= reg_sp.coarse_time_f1; + WHEN "001001" => prdata <= reg_sp.coarse_time_f2; + WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; + WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; + WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; + WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; + + WHEN "001111" => prdata <= debug_reg; + --------------------------------------------------------------------- + WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; + prdata(1) <= reg_wp.data_shaping_SP0; + prdata(2) <= reg_wp.data_shaping_SP1; + prdata(3) <= reg_wp.data_shaping_R0; + prdata(4) <= reg_wp.data_shaping_R1; + WHEN "010001" => prdata(0) <= reg_wp.enable_f0; + prdata(1) <= reg_wp.enable_f1; + prdata(2) <= reg_wp.enable_f2; + prdata(3) <= reg_wp.enable_f3; + prdata(4) <= reg_wp.burst_f0; + prdata(5) <= reg_wp.burst_f1; + prdata(6) <= reg_wp.burst_f2; + prdata(7) <= reg_wp.run; + WHEN "010010" => prdata <= reg_wp.addr_data_f0; + WHEN "010011" => prdata <= reg_wp.addr_data_f1; + WHEN "010100" => prdata <= reg_wp.addr_data_f2; + WHEN "010101" => prdata <= reg_wp.addr_data_f3; + WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; + prdata(7 DOWNTO 4) <= reg_wp.status_full_err; + prdata(11 DOWNTO 8) <= reg_wp.status_new_err; + WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; + WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; + WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; + WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; + WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; + WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; + WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; + WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; + WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; + ---------------------------------------------------- + WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); + WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); + WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); + WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); + WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); + WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); + WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); + WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); + ---------------------------------------------------- + WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); + WHEN OTHERS => NULL; + + END CASE; + IF (apbi.pwrite AND apbi.penable) = '1' THEN + -- APB DMA WRITE -- + CASE paddr(7 DOWNTO 2) IS + -- + WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); + reg_sp.config_active_interruption_onError <= apbi.pwdata(1); + reg_sp.config_ms_run <= apbi.pwdata(2); + WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); + reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); + reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); + reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); + reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); + reg_sp.status_error_bad_component_error <= apbi.pwdata(5); + WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; + WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; + WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; + WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; + -- + WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); + reg_wp.data_shaping_SP0 <= apbi.pwdata(1); + reg_wp.data_shaping_SP1 <= apbi.pwdata(2); + reg_wp.data_shaping_R0 <= apbi.pwdata(3); + reg_wp.data_shaping_R1 <= apbi.pwdata(4); + WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); + reg_wp.enable_f1 <= apbi.pwdata(1); + reg_wp.enable_f2 <= apbi.pwdata(2); + reg_wp.enable_f3 <= apbi.pwdata(3); + reg_wp.burst_f0 <= apbi.pwdata(4); + reg_wp.burst_f1 <= apbi.pwdata(5); + reg_wp.burst_f2 <= apbi.pwdata(6); + reg_wp.run <= apbi.pwdata(7); + WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; + WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; + WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; + WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; + WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); + reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); + reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); + status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); + status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); + status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); + status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); + WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); + WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); + WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); + WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); + WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); + -- + WHEN OTHERS => NULL; + END CASE; + END IF; + END IF; + + apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR + ready_matrix_f0_1 OR + ready_matrix_f1 OR + ready_matrix_f2) + ) + OR + (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR + error_bad_component_error) + )); + + apbo.pirq(pirq_wfp) <= ored_irq_wfp; + + END IF; + END PROCESS lpp_lfr_apbreg; + + apbo.pindex <= pindex; + apbo.pconfig <= pconfig; + apbo.prdata <= prdata; + + ----------------------------------------------------------------------------- + -- IRQ + ----------------------------------------------------------------------------- + irq_wfp_reg_s <= status_full & status_full_err & status_new_err; + + PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS + IF HRESETn = '0' THEN -- asynchronous reset (active low) + irq_wfp_reg <= (OTHERS => '0'); + ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge + irq_wfp_reg <= irq_wfp_reg_s; + END IF; + END PROCESS; + + all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE + irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); + END GENERATE all_irq_wfp; + + irq_wfp_ZERO <= (OTHERS => '0'); + ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; + + run_ms <= reg_sp.config_ms_run; + +END beh; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd @@ -1,374 +1,394 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - -LIBRARY lpp; -USE lpp.lpp_amba.ALL; -USE lpp.lpp_memory.ALL; ---USE lpp.lpp_uart.ALL; -USE lpp.lpp_matrix.ALL; ---USE lpp.lpp_delay.ALL; -USE lpp.lpp_fft.ALL; -USE lpp.fft_components.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.Filtercfg.ALL; -USE lpp.lpp_demux.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_Header.ALL; -USE lpp.lpp_lfr_pkg.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - - -ENTITY lpp_lfr_ms IS - GENERIC ( - Mem_use : INTEGER - ); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - --------------------------------------------------------------------------- - -- DATA INPUT - --------------------------------------------------------------------------- - -- TIME - coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo - -- - sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - --------------------------------------------------------------------------- - -- DMA - --------------------------------------------------------------------------- - dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dma_valid : OUT STD_LOGIC; - dma_valid_burst : OUT STD_LOGIC; - dma_ren : IN STD_LOGIC; - dma_done : IN STD_LOGIC; - - -- Reg out - ready_matrix_f0_0 : OUT STD_LOGIC; - ready_matrix_f0_1 : OUT STD_LOGIC; - ready_matrix_f1 : OUT STD_LOGIC; - ready_matrix_f2 : OUT STD_LOGIC; - error_anticipating_empty_fifo : OUT STD_LOGIC; - error_bad_component_error : OUT STD_LOGIC; - debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - -- Reg In - status_ready_matrix_f0_0 :IN STD_LOGIC; - status_ready_matrix_f0_1 :IN STD_LOGIC; - status_ready_matrix_f1 :IN STD_LOGIC; - status_ready_matrix_f2 :IN STD_LOGIC; - status_error_anticipating_empty_fifo :IN STD_LOGIC; - status_error_bad_component_error :IN STD_LOGIC; - - config_active_interruption_onNewMatrix : IN STD_LOGIC; - config_active_interruption_onError : IN STD_LOGIC; - addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - - matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) - - ); -END; - -ARCHITECTURE Behavioral OF lpp_lfr_ms IS - ----------------------------------------------------------------------------- - SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); - SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL FFT_Load : STD_LOGIC; - SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL SM_FlagError : STD_LOGIC; --- SIGNAL SM_Pong : STD_LOGIC; - SIGNAL SM_Wen : STD_LOGIC; - SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL Head_Empty : STD_LOGIC; - SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL Head_Valid : STD_LOGIC; - SIGNAL Head_Val : STD_LOGIC; - - ----------------------------------------------------------------------------- - SIGNAL DMA_Read : STD_LOGIC; - SIGNAL DMA_ack : STD_LOGIC; - - ----------------------------------------------------------------------------- - SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); - -BEGIN - - ----------------------------------------------------------------------------- - Memf0: lppFIFOxN - GENERIC MAP ( - tech => 0, Mem_use => Mem_use, Data_sz => 16, - Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') - PORT MAP ( - rstn => rstn, wclk => clk, rclk => clk, - ReUse => (OTHERS => '0'), - wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), - wdata => sample_f0_wdata, rdata => FifoF0_Data, - full => OPEN, empty => FifoF0_Empty); - - Memf1: lppFIFOxN - GENERIC MAP ( - tech => 0, Mem_use => Mem_use, Data_sz => 16, - Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - PORT MAP ( - rstn => rstn, wclk => clk, rclk => clk, - ReUse => (OTHERS => '0'), - wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), - wdata => sample_f1_wdata, rdata => FifoF1_Data, - full => OPEN, empty => FifoF1_Empty); - - - Memf2: lppFIFOxN - GENERIC MAP ( - tech => 0, Mem_use => Mem_use, Data_sz => 16, - Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - PORT MAP ( - rstn => rstn, wclk => clk, rclk => clk, - ReUse => (OTHERS => '0'), - wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), - wdata => sample_f3_wdata, rdata => FifoF3_Data, - full => OPEN, empty => FifoF3_Empty); - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - DMUX0 : DEMUX - GENERIC MAP ( - Data_sz => 16) - PORT MAP ( - clk => clk, - rstn => rstn, - Read => FFT_Read, - Load => FFT_Load, - EmptyF0 => FifoF0_Empty, - EmptyF1 => FifoF1_Empty, - EmptyF2 => FifoF3_Empty, - DataF0 => FifoF0_Data, - DataF1 => FifoF1_Data, - DataF2 => FifoF3_Data, - WorkFreq => DMUX_WorkFreq, - Read_DEMUX => DMUX_Read, - Empty => DMUX_Empty, - Data => DMUX_Data); - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - FFT0: FFT - GENERIC MAP ( - Data_sz => 16, - NbData => 256) - PORT MAP ( - clkm => clk, - rstn => rstn, - FifoIN_Empty => DMUX_Empty, - FifoIN_Data => DMUX_Data, - FifoOUT_Full => FifoINT_Full, - Load => FFT_Load, - Read => FFT_Read, - Write => FFT_Write, - ReUse => FFT_ReUse, - Data => FFT_Data); - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - MemInt : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5, - Enable_ReUse => '1') - PORT MAP ( - rstn => rstn, - wclk => clk, - rclk => clk, - ReUse => SM_ReUse, - wen => FFT_Write, - ren => SM_Read, - wdata => FFT_Data, - rdata => FifoINT_Data, - full => FifoINT_Full, - empty => OPEN); - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - SM0 : MatriceSpectrale - GENERIC MAP ( - Input_SZ => 16, - Result_SZ => 32) - PORT MAP ( - clkm => clk, - rstn => rstn, - FifoIN_Full => FifoINT_Full, - SetReUse => FFT_ReUse, - Valid => Head_Valid, - Data_IN => FifoINT_Data, - ACK => DMA_ack, - SM_Write => SM_Wen, - FlagError => SM_FlagError, --- Pong => SM_Pong, - Statu => SM_Param, - Write => SM_Write, - Read => SM_Read, - ReUse => SM_ReUse, - Data_OUT => SM_Data); - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - MemOut : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 32, - Addr_sz => 8, - FifoCnt => 2, - Enable_ReUse => '0') - PORT MAP ( - rstn => rstn, - wclk => clk, - rclk => clk, - ReUse => (OTHERS => '0'), - wen => SM_Write, - ren => Head_Read, - wdata => SM_Data, - rdata => FifoOUT_Data, - full => FifoOUT_Full, - empty => FifoOUT_Empty); - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - Head0 : HeaderBuilder - GENERIC MAP ( - Data_sz => 32) - PORT MAP ( - clkm => clk, - rstn => rstn, --- pong => SM_Pong, - Statu => SM_Param, - Matrix_Type => DMUX_WorkFreq, - Matrix_Write => SM_Wen, - Valid => Head_Valid, - - dataIN => FifoOUT_Data, - emptyIN => FifoOUT_Empty, - RenOUT => Head_Read, - - dataOUT => Head_Data, - emptyOUT => Head_Empty, - RenIN => DMA_Read, - - header => Head_Header, - header_val => Head_Val, - header_ack => DMA_ack ); - ----------------------------------------------------------------------------- - data_time(31 DOWNTO 0) <= coarse_time; - data_time(47 DOWNTO 32) <= fine_time; - - lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma - PORT MAP ( - HCLK => clk, - HRESETn => rstn, - - data_time => data_time, - - fifo_data => Head_Data, - fifo_empty => Head_Empty, - fifo_ren => DMA_Read, - - header => Head_Header, - header_val => Head_Val, - header_ack => DMA_ack, - - dma_addr => dma_addr, - dma_data => dma_data, - dma_valid => dma_valid, - dma_valid_burst => dma_valid_burst, - dma_ren => dma_ren, - dma_done => dma_done, - - ready_matrix_f0_0 => ready_matrix_f0_0, - ready_matrix_f0_1 => ready_matrix_f0_1, - ready_matrix_f1 => ready_matrix_f1, - ready_matrix_f2 => ready_matrix_f2, - error_anticipating_empty_fifo => error_anticipating_empty_fifo, - error_bad_component_error => error_bad_component_error, - debug_reg => debug_reg, - status_ready_matrix_f0_0 => status_ready_matrix_f0_0, - status_ready_matrix_f0_1 => status_ready_matrix_f0_1, - status_ready_matrix_f1 => status_ready_matrix_f1, - status_ready_matrix_f2 => status_ready_matrix_f2, - status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, - status_error_bad_component_error => status_error_bad_component_error, - config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, - config_active_interruption_onError => config_active_interruption_onError, - addr_matrix_f0_0 => addr_matrix_f0_0, - addr_matrix_f0_1 => addr_matrix_f0_1, - addr_matrix_f1 => addr_matrix_f1, - addr_matrix_f2 => addr_matrix_f2, - - matrix_time_f0_0 => matrix_time_f0_0, - matrix_time_f0_1 => matrix_time_f0_1, - matrix_time_f1 => matrix_time_f1, - matrix_time_f2 => matrix_time_f2 - ); - -END Behavioral; +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.lpp_memory.ALL; +--USE lpp.lpp_uart.ALL; +USE lpp.lpp_matrix.ALL; +--USE lpp.lpp_delay.ALL; +USE lpp.lpp_fft.ALL; +USE lpp.fft_components.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.Filtercfg.ALL; +USE lpp.lpp_demux.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_Header.ALL; +USE lpp.lpp_lfr_pkg.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + + +ENTITY lpp_lfr_ms IS + GENERIC ( + Mem_use : INTEGER := use_RAM + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + --------------------------------------------------------------------------- + -- DATA INPUT + --------------------------------------------------------------------------- + -- TIME + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo + -- + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + --------------------------------------------------------------------------- + -- DMA + --------------------------------------------------------------------------- + dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_valid : OUT STD_LOGIC; + dma_valid_burst : OUT STD_LOGIC; + dma_ren : IN STD_LOGIC; + dma_done : IN STD_LOGIC; + + -- Reg out + ready_matrix_f0_0 : OUT STD_LOGIC; + ready_matrix_f0_1 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + error_anticipating_empty_fifo : OUT STD_LOGIC; + error_bad_component_error : OUT STD_LOGIC; + debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- Reg In + status_ready_matrix_f0_0 :IN STD_LOGIC; + status_ready_matrix_f0_1 :IN STD_LOGIC; + status_ready_matrix_f1 :IN STD_LOGIC; + status_ready_matrix_f2 :IN STD_LOGIC; + status_error_anticipating_empty_fifo :IN STD_LOGIC; + status_error_bad_component_error :IN STD_LOGIC; + + config_active_interruption_onNewMatrix : IN STD_LOGIC; + config_active_interruption_onError : IN STD_LOGIC; + addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + + ); +END; + +ARCHITECTURE Behavioral OF lpp_lfr_ms IS + ----------------------------------------------------------------------------- + SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); + SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL FFT_Load : STD_LOGIC; + SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL SM_FlagError : STD_LOGIC; +-- SIGNAL SM_Pong : STD_LOGIC; + SIGNAL SM_Wen : STD_LOGIC; + SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL Head_Empty : STD_LOGIC; + SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL Head_Valid : STD_LOGIC; + SIGNAL Head_Val : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL DMA_Read : STD_LOGIC; + SIGNAL DMA_ack : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); + + SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL dma_valid_s : STD_LOGIC; + SIGNAL dma_valid_burst_s : STD_LOGIC; + +BEGIN + + ----------------------------------------------------------------------------- + Memf0: lppFIFOxN + GENERIC MAP ( + tech => 0, Mem_use => Mem_use, Data_sz => 16, + Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') + PORT MAP ( + rstn => rstn, wclk => clk, rclk => clk, + ReUse => (OTHERS => '0'), + wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), + wdata => sample_f0_wdata, rdata => FifoF0_Data, + full => OPEN, empty => FifoF0_Empty); + + Memf1: lppFIFOxN + GENERIC MAP ( + tech => 0, Mem_use => Mem_use, Data_sz => 16, + Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') + PORT MAP ( + rstn => rstn, wclk => clk, rclk => clk, + ReUse => (OTHERS => '0'), + wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), + wdata => sample_f1_wdata, rdata => FifoF1_Data, + full => OPEN, empty => FifoF1_Empty); + + + Memf2: lppFIFOxN + GENERIC MAP ( + tech => 0, Mem_use => Mem_use, Data_sz => 16, + Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') + PORT MAP ( + rstn => rstn, wclk => clk, rclk => clk, + ReUse => (OTHERS => '0'), + wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), + wdata => sample_f3_wdata, rdata => FifoF3_Data, + full => OPEN, empty => FifoF3_Empty); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + DMUX0 : DEMUX + GENERIC MAP ( + Data_sz => 16) + PORT MAP ( + clk => clk, + rstn => rstn, + Read => FFT_Read, + Load => FFT_Load, + EmptyF0 => FifoF0_Empty, + EmptyF1 => FifoF1_Empty, + EmptyF2 => FifoF3_Empty, + DataF0 => FifoF0_Data, + DataF1 => FifoF1_Data, + DataF2 => FifoF3_Data, + WorkFreq => DMUX_WorkFreq, + Read_DEMUX => DMUX_Read, + Empty => DMUX_Empty, + Data => DMUX_Data); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + FFT0: FFT + GENERIC MAP ( + Data_sz => 16, + NbData => 256) + PORT MAP ( + clkm => clk, + rstn => rstn, + FifoIN_Empty => DMUX_Empty, + FifoIN_Data => DMUX_Data, + FifoOUT_Full => FifoINT_Full, + Load => FFT_Load, + Read => FFT_Read, + Write => FFT_Write, + ReUse => FFT_ReUse, + Data => FFT_Data); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + MemInt : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5, + Enable_ReUse => '1') + PORT MAP ( + rstn => rstn, + wclk => clk, + rclk => clk, + ReUse => SM_ReUse, + wen => FFT_Write, + ren => SM_Read, + wdata => FFT_Data, + rdata => FifoINT_Data, + full => FifoINT_Full, + empty => OPEN); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + SM0 : MatriceSpectrale + GENERIC MAP ( + Input_SZ => 16, + Result_SZ => 32) + PORT MAP ( + clkm => clk, + rstn => rstn, + FifoIN_Full => FifoINT_Full, + SetReUse => FFT_ReUse, + Valid => Head_Valid, + Data_IN => FifoINT_Data, + ACK => DMA_ack, + SM_Write => SM_Wen, + FlagError => SM_FlagError, +-- Pong => SM_Pong, + Statu => SM_Param, + Write => SM_Write, + Read => SM_Read, + ReUse => SM_ReUse, + Data_OUT => SM_Data); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + MemOut : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 32, + Addr_sz => 8, + FifoCnt => 2, + Enable_ReUse => '0') + PORT MAP ( + rstn => rstn, + wclk => clk, + rclk => clk, + ReUse => (OTHERS => '0'), + wen => SM_Write, + ren => Head_Read, + wdata => SM_Data, + rdata => FifoOUT_Data, + full => FifoOUT_Full, + empty => FifoOUT_Empty); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + Head0 : HeaderBuilder + GENERIC MAP ( + Data_sz => 32) + PORT MAP ( + clkm => clk, + rstn => rstn, +-- pong => SM_Pong, + Statu => SM_Param, + Matrix_Type => DMUX_WorkFreq, + Matrix_Write => SM_Wen, + Valid => Head_Valid, + + dataIN => FifoOUT_Data, + emptyIN => FifoOUT_Empty, + RenOUT => Head_Read, + + dataOUT => Head_Data, + emptyOUT => Head_Empty, + RenIN => DMA_Read, + + header => Head_Header, + header_val => Head_Val, + header_ack => DMA_ack ); + ----------------------------------------------------------------------------- + data_time(31 DOWNTO 0) <= coarse_time; + data_time(47 DOWNTO 32) <= fine_time; + + lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + + data_time => data_time, + + fifo_data => Head_Data, + fifo_empty => Head_Empty, + fifo_ren => DMA_Read, + + header => Head_Header, + header_val => Head_Val, + header_ack => DMA_ack, + + dma_addr => dma_addr, + dma_data => dma_data, + dma_valid => dma_valid_s, + dma_valid_burst => dma_valid_burst_s, + dma_ren => dma_ren, + dma_done => dma_done, + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg_s, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + + matrix_time_f0_0 => matrix_time_f0_0, + matrix_time_f0_1 => matrix_time_f0_1, + matrix_time_f1 => matrix_time_f1, + matrix_time_f2 => matrix_time_f2 + ); + + dma_valid <= dma_valid_s; + dma_valid_burst <= dma_valid_burst_s; + + debug_reg(9 DOWNTO 0) <= debug_reg_s(9 DOWNTO 0); + debug_reg(10) <= Head_Empty; + debug_reg(11) <= DMA_Read; + debug_reg(12) <= Head_Val; + debug_reg(13) <= DMA_ack; + debug_reg(14) <= dma_ren; + debug_reg(15) <= dma_done; + debug_reg(16) <= dma_valid_s; + debug_reg(17) <= dma_valid_burst_s; + debug_reg(31 DOWNTO 18) <= (OTHERS => '0'); + + + +END Behavioral; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd @@ -200,7 +200,8 @@ BEGIN debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge - + debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); + CASE state IS WHEN IDLE => debug_reg_s(2 DOWNTO 0) <= "000"; @@ -214,6 +215,9 @@ BEGIN ready_matrix_f2 <= '0'; error_bad_component_error <= '0'; header_select <= '1'; + IF header_val = '1' THEN + header_ack <= '1'; + END IF; IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0); debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2); @@ -226,9 +230,9 @@ BEGIN WHEN CHECK_COMPONENT_TYPE => debug_reg_s(2 DOWNTO 0) <= "001"; + header_ack <= '0'; IF header_check_ok = '1' THEN - header_ack <= '1'; header_send <= '0'; -- IF component_type = "0000" THEN @@ -256,7 +260,6 @@ BEGIN ELSE error_bad_component_error <= '1'; component_type_pre <= "0000"; - header_ack <= '1'; state <= TRASH_FIFO; END IF;