@@ -425,7 +425,7 BEGIN -- beh | |||
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425 | 425 | pirq_ms => 6, |
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426 | 426 | pirq_wfp => 14, |
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427 | 427 | hindex => 2, |
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428 |
top_lfr_version => X"00010 |
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428 | top_lfr_version => X"000105") -- aa.bb.cc version | |
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429 | 429 | PORT MAP ( |
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430 | 430 | clk => clk_25, |
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431 | 431 | rstn => reset, |
@@ -84,7 +84,12 Load <= FFT_Load; | |||
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84 | 84 | PTS => gPTS, |
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85 | 85 | HALFPTS => gHALFPTS, |
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86 | 86 | inBuf_RWDLY => gInBuf_RWDLY) |
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87 | port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); | |
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87 | port map(clkm,start,rstn, | |
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88 | Drive_Write,Link_Read, | |
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89 | Drive_DataIM,Drive_DataRE, | |
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90 | FFT_Load,open, | |
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91 | FFT_DataIM,FFT_DataRE, | |
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92 | FFT_Valid,FFT_Ready); | |
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88 | 93 | |
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89 | 94 | |
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90 | 95 | LINK : Linker_FFT |
@@ -92,4 +97,4 Load <= FFT_Load; | |||
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92 | 97 | port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data); |
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93 | 98 | |
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94 | 99 | |
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95 | end architecture; No newline at end of file | |
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100 | end architecture; |
This diff has been collapsed as it changes many lines, (1088 lines changed) Show them Hide them | |||
@@ -1,544 +1,544 | |||
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1 | ------------------------------------------------------------------------------ | |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
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21 | -- jean-christophe.pellion@easii-ic.com | |
|
22 | ---------------------------------------------------------------------------- | |
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23 | LIBRARY ieee; | |
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24 | USE ieee.std_logic_1164.ALL; | |
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25 | USE ieee.numeric_std.ALL; | |
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26 | LIBRARY grlib; | |
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27 | USE grlib.amba.ALL; | |
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28 | USE grlib.stdlib.ALL; | |
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29 | USE grlib.devices.ALL; | |
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30 | LIBRARY lpp; | |
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31 | USE lpp.lpp_amba.ALL; | |
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32 | USE lpp.apb_devices_list.ALL; | |
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33 | USE lpp.lpp_memory.ALL; | |
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34 | LIBRARY techmap; | |
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35 | USE techmap.gencomp.ALL; | |
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36 | ||
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37 | ENTITY lpp_lfr_apbreg IS | |
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38 | GENERIC ( | |
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39 | nb_data_by_buffer_size : INTEGER := 11; | |
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40 | nb_word_by_buffer_size : INTEGER := 11; | |
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41 | nb_snapshot_param_size : INTEGER := 11; | |
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42 | delta_vector_size : INTEGER := 20; | |
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43 | delta_vector_size_f0_2 : INTEGER := 3; | |
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44 | ||
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45 | pindex : INTEGER := 4; | |
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46 | paddr : INTEGER := 4; | |
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47 | pmask : INTEGER := 16#fff#; | |
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48 | pirq_ms : INTEGER := 0; | |
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49 | pirq_wfp : INTEGER := 1; | |
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50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
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51 | PORT ( | |
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52 | -- AMBA AHB system signals | |
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53 | HCLK : IN STD_ULOGIC; | |
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54 | HRESETn : IN STD_ULOGIC; | |
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55 | ||
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56 | -- AMBA APB Slave Interface | |
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57 | apbi : IN apb_slv_in_type; | |
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58 | apbo : OUT apb_slv_out_type; | |
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59 | ||
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60 | --------------------------------------------------------------------------- | |
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61 | -- Spectral Matrix Reg | |
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62 | run_ms : OUT STD_LOGIC; | |
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63 | -- IN | |
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64 | ready_matrix_f0_0 : IN STD_LOGIC; | |
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65 | ready_matrix_f0_1 : IN STD_LOGIC; | |
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66 | ready_matrix_f1 : IN STD_LOGIC; | |
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67 | ready_matrix_f2 : IN STD_LOGIC; | |
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68 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
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69 | error_bad_component_error : IN STD_LOGIC; | |
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70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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71 | ||
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72 | -- OUT | |
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73 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
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74 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
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75 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
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76 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
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77 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
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78 | status_error_bad_component_error : OUT STD_LOGIC; | |
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79 | ||
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80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
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81 | config_active_interruption_onError : OUT STD_LOGIC; | |
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82 | ||
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83 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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84 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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85 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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86 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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87 | ||
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88 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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89 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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90 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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91 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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92 | ||
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93 | --------------------------------------------------------------------------- | |
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94 | --------------------------------------------------------------------------- | |
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95 | -- WaveForm picker Reg | |
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96 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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97 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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98 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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99 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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100 | ||
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101 | -- OUT | |
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102 | data_shaping_BW : OUT STD_LOGIC; | |
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103 | data_shaping_SP0 : OUT STD_LOGIC; | |
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104 | data_shaping_SP1 : OUT STD_LOGIC; | |
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105 | data_shaping_R0 : OUT STD_LOGIC; | |
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106 | data_shaping_R1 : OUT STD_LOGIC; | |
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107 | ||
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108 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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109 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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110 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
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111 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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112 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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113 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
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114 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
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115 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
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116 | ||
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117 | enable_f0 : OUT STD_LOGIC; | |
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118 | enable_f1 : OUT STD_LOGIC; | |
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119 | enable_f2 : OUT STD_LOGIC; | |
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120 | enable_f3 : OUT STD_LOGIC; | |
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121 | ||
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122 | burst_f0 : OUT STD_LOGIC; | |
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123 | burst_f1 : OUT STD_LOGIC; | |
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124 | burst_f2 : OUT STD_LOGIC; | |
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125 | ||
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126 | run : OUT STD_LOGIC; | |
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127 | ||
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128 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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129 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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130 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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131 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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132 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
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133 | --------------------------------------------------------------------------- | |
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134 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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135 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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136 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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137 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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138 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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139 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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140 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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141 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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142 | ||
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143 | --------------------------------------------------------------------------- | |
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144 | ); | |
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145 | ||
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146 | END lpp_lfr_apbreg; | |
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147 | ||
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148 | ARCHITECTURE beh OF lpp_lfr_apbreg IS | |
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149 | ||
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150 | CONSTANT REVISION : INTEGER := 1; | |
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151 | ||
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152 | CONSTANT pconfig : apb_config_type := ( | |
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153 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), | |
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154 | 1 => apb_iobar(paddr, pmask)); | |
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155 | ||
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156 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
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157 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
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158 | config_active_interruption_onError : STD_LOGIC; | |
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159 | config_ms_run : STD_LOGIC; | |
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160 | status_ready_matrix_f0_0 : STD_LOGIC; | |
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161 | status_ready_matrix_f0_1 : STD_LOGIC; | |
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162 | status_ready_matrix_f1 : STD_LOGIC; | |
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163 | status_ready_matrix_f2 : STD_LOGIC; | |
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164 | status_error_anticipating_empty_fifo : STD_LOGIC; | |
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165 | status_error_bad_component_error : STD_LOGIC; | |
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166 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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168 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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169 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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170 | ||
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171 | coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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172 | coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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173 | coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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174 | coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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175 | ||
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176 | -- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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177 | -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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178 | -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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179 | -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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180 | END RECORD; | |
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181 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
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182 | ||
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183 | TYPE lpp_WaveformPicker_regs IS RECORD | |
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184 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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185 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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186 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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187 | data_shaping_BW : STD_LOGIC; | |
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188 | data_shaping_SP0 : STD_LOGIC; | |
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189 | data_shaping_SP1 : STD_LOGIC; | |
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190 | data_shaping_R0 : STD_LOGIC; | |
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191 | data_shaping_R1 : STD_LOGIC; | |
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192 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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193 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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194 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
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195 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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196 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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197 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
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198 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
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199 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
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200 | enable_f0 : STD_LOGIC; | |
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201 | enable_f1 : STD_LOGIC; | |
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202 | enable_f2 : STD_LOGIC; | |
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203 | enable_f3 : STD_LOGIC; | |
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204 | burst_f0 : STD_LOGIC; | |
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205 | burst_f1 : STD_LOGIC; | |
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206 | burst_f2 : STD_LOGIC; | |
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207 | run : STD_LOGIC; | |
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208 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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209 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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210 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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211 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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212 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
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213 | END RECORD; | |
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214 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
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215 | ||
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216 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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217 | ||
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218 | ----------------------------------------------------------------------------- | |
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219 | -- IRQ | |
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220 | ----------------------------------------------------------------------------- | |
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221 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
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222 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
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223 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
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224 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
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225 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
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226 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
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227 | ||
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228 | BEGIN -- beh | |
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229 | ||
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230 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; | |
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231 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | |
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232 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
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233 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
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234 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
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235 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
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236 | ||
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237 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |
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238 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |
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239 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |
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240 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |
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241 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
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242 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |
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243 | ||
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244 | ||
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245 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |
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246 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
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247 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
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248 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
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249 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |
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250 | ||
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251 | delta_snapshot <= reg_wp.delta_snapshot; | |
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252 | delta_f0 <= reg_wp.delta_f0; | |
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253 | delta_f0_2 <= reg_wp.delta_f0_2; | |
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254 | delta_f1 <= reg_wp.delta_f1; | |
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255 | delta_f2 <= reg_wp.delta_f2; | |
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256 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; | |
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257 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; | |
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258 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
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259 | ||
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260 | enable_f0 <= reg_wp.enable_f0; | |
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261 | enable_f1 <= reg_wp.enable_f1; | |
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262 | enable_f2 <= reg_wp.enable_f2; | |
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263 | enable_f3 <= reg_wp.enable_f3; | |
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264 | ||
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265 | burst_f0 <= reg_wp.burst_f0; | |
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266 | burst_f1 <= reg_wp.burst_f1; | |
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267 | burst_f2 <= reg_wp.burst_f2; | |
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268 | ||
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269 | run <= reg_wp.run; | |
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270 | ||
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271 | addr_data_f0 <= reg_wp.addr_data_f0; | |
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272 | addr_data_f1 <= reg_wp.addr_data_f1; | |
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273 | addr_data_f2 <= reg_wp.addr_data_f2; | |
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274 | addr_data_f3 <= reg_wp.addr_data_f3; | |
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275 | ||
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276 | start_date <= reg_wp.start_date; | |
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277 | ||
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278 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
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279 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
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280 | BEGIN -- PROCESS lpp_dma_top | |
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281 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
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282 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
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283 | reg_sp.config_active_interruption_onError <= '0'; | |
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284 | reg_sp.config_ms_run <= '1'; | |
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285 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
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286 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
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287 | reg_sp.status_ready_matrix_f1 <= '0'; | |
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288 | reg_sp.status_ready_matrix_f2 <= '0'; | |
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289 | reg_sp.status_error_anticipating_empty_fifo <= '0'; | |
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290 | reg_sp.status_error_bad_component_error <= '0'; | |
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291 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
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292 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
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293 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); | |
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294 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
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295 | ||
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296 | reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); | |
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297 | reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); | |
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298 | reg_sp.coarse_time_f1 <= (OTHERS => '0'); | |
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299 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); | |
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300 | --reg_sp.fine_time_f0_0 <= (OTHERS => '0'); | |
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301 | --reg_sp.fine_time_f0_1 <= (OTHERS => '0'); | |
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302 | --reg_sp.fine_time_f1 <= (OTHERS => '0'); | |
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303 | --reg_sp.fine_time_f2 <= (OTHERS => '0'); | |
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304 | ||
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305 | prdata <= (OTHERS => '0'); | |
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306 | ||
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307 | apbo.pirq <= (OTHERS => '0'); | |
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308 | ||
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309 | status_full_ack <= (OTHERS => '0'); | |
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310 | ||
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311 | reg_wp.data_shaping_BW <= '0'; | |
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312 | reg_wp.data_shaping_SP0 <= '0'; | |
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313 | reg_wp.data_shaping_SP1 <= '0'; | |
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314 | reg_wp.data_shaping_R0 <= '0'; | |
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315 | reg_wp.data_shaping_R1 <= '0'; | |
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316 | reg_wp.enable_f0 <= '0'; | |
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317 | reg_wp.enable_f1 <= '0'; | |
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318 | reg_wp.enable_f2 <= '0'; | |
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319 | reg_wp.enable_f3 <= '0'; | |
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320 | reg_wp.burst_f0 <= '0'; | |
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321 | reg_wp.burst_f1 <= '0'; | |
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322 | reg_wp.burst_f2 <= '0'; | |
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323 | reg_wp.run <= '0'; | |
|
324 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
|
325 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
|
326 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
|
327 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
|
328 | reg_wp.status_full <= (OTHERS => '0'); | |
|
329 | reg_wp.status_full_err <= (OTHERS => '0'); | |
|
330 | reg_wp.status_new_err <= (OTHERS => '0'); | |
|
331 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
|
332 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
|
333 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
|
334 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
|
335 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
|
336 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
|
337 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
|
338 | reg_wp.start_date <= (OTHERS => '0'); | |
|
339 | ||
|
340 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
341 | ||
|
342 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); | |
|
343 | reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |
|
344 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); | |
|
345 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); | |
|
346 | ||
|
347 | --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); | |
|
348 | --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); | |
|
349 | --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); | |
|
350 | --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); | |
|
351 | ||
|
352 | status_full_ack <= (OTHERS => '0'); | |
|
353 | ||
|
354 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; | |
|
355 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
|
356 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; | |
|
357 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
|
358 | ||
|
359 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
|
360 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
|
361 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
|
362 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
|
363 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
|
364 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
|
365 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
|
366 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
|
367 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; | |
|
368 | END LOOP all_status; | |
|
369 | ||
|
370 | paddr := "000000"; | |
|
371 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
|
372 | prdata <= (OTHERS => '0'); | |
|
373 | IF apbi.psel(pindex) = '1' THEN | |
|
374 | -- APB DMA READ -- | |
|
375 | CASE paddr(7 DOWNTO 2) IS | |
|
376 | -- | |
|
377 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
|
378 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
|
379 | prdata(2) <= reg_sp.config_ms_run; | |
|
380 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
|
381 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
|
382 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
|
383 | prdata(3) <= reg_sp.status_ready_matrix_f2; | |
|
384 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |
|
385 | prdata(5) <= reg_sp.status_error_bad_component_error; | |
|
386 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
|
387 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
|
388 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; | |
|
389 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
|
390 | ||
|
391 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; | |
|
392 | WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; | |
|
393 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; | |
|
394 | WHEN "001001" => prdata <= reg_sp.coarse_time_f2; | |
|
395 | WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; | |
|
396 | WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; | |
|
397 | WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; | |
|
398 | WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; | |
|
399 | ||
|
400 | WHEN "001111" => prdata <= debug_reg; | |
|
401 | --------------------------------------------------------------------- | |
|
402 | WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; | |
|
403 | prdata(1) <= reg_wp.data_shaping_SP0; | |
|
404 | prdata(2) <= reg_wp.data_shaping_SP1; | |
|
405 | prdata(3) <= reg_wp.data_shaping_R0; | |
|
406 | prdata(4) <= reg_wp.data_shaping_R1; | |
|
407 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; | |
|
408 | prdata(1) <= reg_wp.enable_f1; | |
|
409 | prdata(2) <= reg_wp.enable_f2; | |
|
410 | prdata(3) <= reg_wp.enable_f3; | |
|
411 | prdata(4) <= reg_wp.burst_f0; | |
|
412 | prdata(5) <= reg_wp.burst_f1; | |
|
413 | prdata(6) <= reg_wp.burst_f2; | |
|
414 | prdata(7) <= reg_wp.run; | |
|
415 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; | |
|
416 | WHEN "010011" => prdata <= reg_wp.addr_data_f1; | |
|
417 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; | |
|
418 | WHEN "010101" => prdata <= reg_wp.addr_data_f3; | |
|
419 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
|
420 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
|
421 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |
|
422 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
|
423 | WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
|
424 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
|
425 | WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
|
426 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
|
427 | WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
|
428 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
|
429 | WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
|
430 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
|
431 | ---------------------------------------------------- | |
|
432 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); | |
|
433 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); | |
|
434 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); | |
|
435 | WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); | |
|
436 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); | |
|
437 | WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); | |
|
438 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); | |
|
439 | WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); | |
|
440 | ---------------------------------------------------- | |
|
441 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
|
442 | WHEN OTHERS => NULL; | |
|
443 | ||
|
444 | END CASE; | |
|
445 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
|
446 | -- APB DMA WRITE -- | |
|
447 | CASE paddr(7 DOWNTO 2) IS | |
|
448 | -- | |
|
449 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
|
450 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
|
451 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
|
452 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
|
453 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
|
454 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
|
455 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); | |
|
456 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |
|
457 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); | |
|
458 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
|
459 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
460 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |
|
461 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |
|
462 | -- | |
|
463 | WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
|
464 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |
|
465 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |
|
466 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
|
467 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |
|
468 | WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
|
469 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
|
470 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
|
471 | reg_wp.enable_f3 <= apbi.pwdata(3); | |
|
472 | reg_wp.burst_f0 <= apbi.pwdata(4); | |
|
473 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
|
474 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
|
475 | reg_wp.run <= apbi.pwdata(7); | |
|
476 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
|
477 | WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
|
478 | WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
|
479 | WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
|
480 | WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
|
481 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
|
482 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
|
483 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
|
484 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
|
485 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
|
486 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
|
487 | WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
488 | WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
489 | WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
490 | WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
491 | WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
492 | WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
493 | WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
|
494 | WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
|
495 | WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
496 | -- | |
|
497 | WHEN OTHERS => NULL; | |
|
498 | END CASE; | |
|
499 | END IF; | |
|
500 | END IF; | |
|
501 | ||
|
502 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |
|
503 | ready_matrix_f0_1 OR | |
|
504 | ready_matrix_f1 OR | |
|
505 | ready_matrix_f2) | |
|
506 | ) | |
|
507 | OR | |
|
508 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR | |
|
509 | error_bad_component_error) | |
|
510 | )); | |
|
511 | ||
|
512 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; | |
|
513 | ||
|
514 | END IF; | |
|
515 | END PROCESS lpp_lfr_apbreg; | |
|
516 | ||
|
517 | apbo.pindex <= pindex; | |
|
518 | apbo.pconfig <= pconfig; | |
|
519 | apbo.prdata <= prdata; | |
|
520 | ||
|
521 | ----------------------------------------------------------------------------- | |
|
522 | -- IRQ | |
|
523 | ----------------------------------------------------------------------------- | |
|
524 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; | |
|
525 | ||
|
526 | PROCESS (HCLK, HRESETn) | |
|
527 | BEGIN -- PROCESS | |
|
528 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
529 | irq_wfp_reg <= (OTHERS => '0'); | |
|
530 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
|
531 | irq_wfp_reg <= irq_wfp_reg_s; | |
|
532 | END IF; | |
|
533 | END PROCESS; | |
|
534 | ||
|
535 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
|
536 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); | |
|
537 | END GENERATE all_irq_wfp; | |
|
538 | ||
|
539 | irq_wfp_ZERO <= (OTHERS => '0'); | |
|
540 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; | |
|
541 | ||
|
542 | run_ms <= reg_sp.config_ms_run; | |
|
543 | ||
|
544 |
END beh; |
|
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
|
22 | ---------------------------------------------------------------------------- | |
|
23 | LIBRARY ieee; | |
|
24 | USE ieee.std_logic_1164.ALL; | |
|
25 | USE ieee.numeric_std.ALL; | |
|
26 | LIBRARY grlib; | |
|
27 | USE grlib.amba.ALL; | |
|
28 | USE grlib.stdlib.ALL; | |
|
29 | USE grlib.devices.ALL; | |
|
30 | LIBRARY lpp; | |
|
31 | USE lpp.lpp_amba.ALL; | |
|
32 | USE lpp.apb_devices_list.ALL; | |
|
33 | USE lpp.lpp_memory.ALL; | |
|
34 | LIBRARY techmap; | |
|
35 | USE techmap.gencomp.ALL; | |
|
36 | ||
|
37 | ENTITY lpp_lfr_apbreg IS | |
|
38 | GENERIC ( | |
|
39 | nb_data_by_buffer_size : INTEGER := 11; | |
|
40 | nb_word_by_buffer_size : INTEGER := 11; | |
|
41 | nb_snapshot_param_size : INTEGER := 11; | |
|
42 | delta_vector_size : INTEGER := 20; | |
|
43 | delta_vector_size_f0_2 : INTEGER := 3; | |
|
44 | ||
|
45 | pindex : INTEGER := 4; | |
|
46 | paddr : INTEGER := 4; | |
|
47 | pmask : INTEGER := 16#fff#; | |
|
48 | pirq_ms : INTEGER := 0; | |
|
49 | pirq_wfp : INTEGER := 1; | |
|
50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000"); | |
|
51 | PORT ( | |
|
52 | -- AMBA AHB system signals | |
|
53 | HCLK : IN STD_ULOGIC; | |
|
54 | HRESETn : IN STD_ULOGIC; | |
|
55 | ||
|
56 | -- AMBA APB Slave Interface | |
|
57 | apbi : IN apb_slv_in_type; | |
|
58 | apbo : OUT apb_slv_out_type; | |
|
59 | ||
|
60 | --------------------------------------------------------------------------- | |
|
61 | -- Spectral Matrix Reg | |
|
62 | run_ms : OUT STD_LOGIC; | |
|
63 | -- IN | |
|
64 | ready_matrix_f0_0 : IN STD_LOGIC; | |
|
65 | ready_matrix_f0_1 : IN STD_LOGIC; | |
|
66 | ready_matrix_f1 : IN STD_LOGIC; | |
|
67 | ready_matrix_f2 : IN STD_LOGIC; | |
|
68 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
69 | error_bad_component_error : IN STD_LOGIC; | |
|
70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
71 | ||
|
72 | -- OUT | |
|
73 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
|
74 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
75 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
|
76 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
|
77 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
78 | status_error_bad_component_error : OUT STD_LOGIC; | |
|
79 | ||
|
80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
|
81 | config_active_interruption_onError : OUT STD_LOGIC; | |
|
82 | ||
|
83 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
87 | ||
|
88 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
89 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
91 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
92 | ||
|
93 | --------------------------------------------------------------------------- | |
|
94 | --------------------------------------------------------------------------- | |
|
95 | -- WaveForm picker Reg | |
|
96 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
97 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
98 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
99 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
100 | ||
|
101 | -- OUT | |
|
102 | data_shaping_BW : OUT STD_LOGIC; | |
|
103 | data_shaping_SP0 : OUT STD_LOGIC; | |
|
104 | data_shaping_SP1 : OUT STD_LOGIC; | |
|
105 | data_shaping_R0 : OUT STD_LOGIC; | |
|
106 | data_shaping_R1 : OUT STD_LOGIC; | |
|
107 | ||
|
108 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
109 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
110 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
111 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
112 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
113 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
114 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
115 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
116 | ||
|
117 | enable_f0 : OUT STD_LOGIC; | |
|
118 | enable_f1 : OUT STD_LOGIC; | |
|
119 | enable_f2 : OUT STD_LOGIC; | |
|
120 | enable_f3 : OUT STD_LOGIC; | |
|
121 | ||
|
122 | burst_f0 : OUT STD_LOGIC; | |
|
123 | burst_f1 : OUT STD_LOGIC; | |
|
124 | burst_f2 : OUT STD_LOGIC; | |
|
125 | ||
|
126 | run : OUT STD_LOGIC; | |
|
127 | ||
|
128 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
129 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
130 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
131 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
132 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
133 | --------------------------------------------------------------------------- | |
|
134 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
135 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
136 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
137 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
138 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
139 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
140 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
141 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
142 | ||
|
143 | --------------------------------------------------------------------------- | |
|
144 | ); | |
|
145 | ||
|
146 | END lpp_lfr_apbreg; | |
|
147 | ||
|
148 | ARCHITECTURE beh OF lpp_lfr_apbreg IS | |
|
149 | ||
|
150 | CONSTANT REVISION : INTEGER := 1; | |
|
151 | ||
|
152 | CONSTANT pconfig : apb_config_type := ( | |
|
153 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), | |
|
154 | 1 => apb_iobar(paddr, pmask)); | |
|
155 | ||
|
156 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
|
157 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
|
158 | config_active_interruption_onError : STD_LOGIC; | |
|
159 | config_ms_run : STD_LOGIC; | |
|
160 | status_ready_matrix_f0_0 : STD_LOGIC; | |
|
161 | status_ready_matrix_f0_1 : STD_LOGIC; | |
|
162 | status_ready_matrix_f1 : STD_LOGIC; | |
|
163 | status_ready_matrix_f2 : STD_LOGIC; | |
|
164 | status_error_anticipating_empty_fifo : STD_LOGIC; | |
|
165 | status_error_bad_component_error : STD_LOGIC; | |
|
166 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
168 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
169 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
170 | ||
|
171 | coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
172 | coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
173 | coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
174 | coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
175 | ||
|
176 | -- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
177 | -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
178 | -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
179 | -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
180 | END RECORD; | |
|
181 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
|
182 | ||
|
183 | TYPE lpp_WaveformPicker_regs IS RECORD | |
|
184 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
185 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
186 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
187 | data_shaping_BW : STD_LOGIC; | |
|
188 | data_shaping_SP0 : STD_LOGIC; | |
|
189 | data_shaping_SP1 : STD_LOGIC; | |
|
190 | data_shaping_R0 : STD_LOGIC; | |
|
191 | data_shaping_R1 : STD_LOGIC; | |
|
192 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
193 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
194 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
195 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
196 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
197 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
198 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
199 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
200 | enable_f0 : STD_LOGIC; | |
|
201 | enable_f1 : STD_LOGIC; | |
|
202 | enable_f2 : STD_LOGIC; | |
|
203 | enable_f3 : STD_LOGIC; | |
|
204 | burst_f0 : STD_LOGIC; | |
|
205 | burst_f1 : STD_LOGIC; | |
|
206 | burst_f2 : STD_LOGIC; | |
|
207 | run : STD_LOGIC; | |
|
208 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
209 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
210 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
211 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
212 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
213 | END RECORD; | |
|
214 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
|
215 | ||
|
216 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
217 | ||
|
218 | ----------------------------------------------------------------------------- | |
|
219 | -- IRQ | |
|
220 | ----------------------------------------------------------------------------- | |
|
221 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
|
222 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
223 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
224 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
225 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
226 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
|
227 | ||
|
228 | BEGIN -- beh | |
|
229 | ||
|
230 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; | |
|
231 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | |
|
232 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
|
233 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
|
234 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
|
235 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
|
236 | ||
|
237 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |
|
238 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |
|
239 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |
|
240 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |
|
241 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
|
242 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |
|
243 | ||
|
244 | ||
|
245 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |
|
246 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
|
247 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
|
248 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
|
249 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |
|
250 | ||
|
251 | delta_snapshot <= reg_wp.delta_snapshot; | |
|
252 | delta_f0 <= reg_wp.delta_f0; | |
|
253 | delta_f0_2 <= reg_wp.delta_f0_2; | |
|
254 | delta_f1 <= reg_wp.delta_f1; | |
|
255 | delta_f2 <= reg_wp.delta_f2; | |
|
256 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; | |
|
257 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; | |
|
258 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
|
259 | ||
|
260 | enable_f0 <= reg_wp.enable_f0; | |
|
261 | enable_f1 <= reg_wp.enable_f1; | |
|
262 | enable_f2 <= reg_wp.enable_f2; | |
|
263 | enable_f3 <= reg_wp.enable_f3; | |
|
264 | ||
|
265 | burst_f0 <= reg_wp.burst_f0; | |
|
266 | burst_f1 <= reg_wp.burst_f1; | |
|
267 | burst_f2 <= reg_wp.burst_f2; | |
|
268 | ||
|
269 | run <= reg_wp.run; | |
|
270 | ||
|
271 | addr_data_f0 <= reg_wp.addr_data_f0; | |
|
272 | addr_data_f1 <= reg_wp.addr_data_f1; | |
|
273 | addr_data_f2 <= reg_wp.addr_data_f2; | |
|
274 | addr_data_f3 <= reg_wp.addr_data_f3; | |
|
275 | ||
|
276 | start_date <= reg_wp.start_date; | |
|
277 | ||
|
278 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
|
279 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
|
280 | BEGIN -- PROCESS lpp_dma_top | |
|
281 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
282 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
|
283 | reg_sp.config_active_interruption_onError <= '0'; | |
|
284 | reg_sp.config_ms_run <= '1'; | |
|
285 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
|
286 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
|
287 | reg_sp.status_ready_matrix_f1 <= '0'; | |
|
288 | reg_sp.status_ready_matrix_f2 <= '0'; | |
|
289 | reg_sp.status_error_anticipating_empty_fifo <= '0'; | |
|
290 | reg_sp.status_error_bad_component_error <= '0'; | |
|
291 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
|
292 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
|
293 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); | |
|
294 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
|
295 | ||
|
296 | reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); | |
|
297 | reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); | |
|
298 | reg_sp.coarse_time_f1 <= (OTHERS => '0'); | |
|
299 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); | |
|
300 | --reg_sp.fine_time_f0_0 <= (OTHERS => '0'); | |
|
301 | --reg_sp.fine_time_f0_1 <= (OTHERS => '0'); | |
|
302 | --reg_sp.fine_time_f1 <= (OTHERS => '0'); | |
|
303 | --reg_sp.fine_time_f2 <= (OTHERS => '0'); | |
|
304 | ||
|
305 | prdata <= (OTHERS => '0'); | |
|
306 | ||
|
307 | apbo.pirq <= (OTHERS => '0'); | |
|
308 | ||
|
309 | status_full_ack <= (OTHERS => '0'); | |
|
310 | ||
|
311 | reg_wp.data_shaping_BW <= '0'; | |
|
312 | reg_wp.data_shaping_SP0 <= '0'; | |
|
313 | reg_wp.data_shaping_SP1 <= '0'; | |
|
314 | reg_wp.data_shaping_R0 <= '0'; | |
|
315 | reg_wp.data_shaping_R1 <= '0'; | |
|
316 | reg_wp.enable_f0 <= '0'; | |
|
317 | reg_wp.enable_f1 <= '0'; | |
|
318 | reg_wp.enable_f2 <= '0'; | |
|
319 | reg_wp.enable_f3 <= '0'; | |
|
320 | reg_wp.burst_f0 <= '0'; | |
|
321 | reg_wp.burst_f1 <= '0'; | |
|
322 | reg_wp.burst_f2 <= '0'; | |
|
323 | reg_wp.run <= '0'; | |
|
324 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
|
325 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
|
326 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
|
327 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
|
328 | reg_wp.status_full <= (OTHERS => '0'); | |
|
329 | reg_wp.status_full_err <= (OTHERS => '0'); | |
|
330 | reg_wp.status_new_err <= (OTHERS => '0'); | |
|
331 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
|
332 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
|
333 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
|
334 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
|
335 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
|
336 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
|
337 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
|
338 | reg_wp.start_date <= (OTHERS => '0'); | |
|
339 | ||
|
340 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
341 | ||
|
342 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); | |
|
343 | reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |
|
344 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); | |
|
345 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); | |
|
346 | ||
|
347 | --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); | |
|
348 | --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); | |
|
349 | --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); | |
|
350 | --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); | |
|
351 | ||
|
352 | status_full_ack <= (OTHERS => '0'); | |
|
353 | ||
|
354 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; | |
|
355 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
|
356 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; | |
|
357 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
|
358 | ||
|
359 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
|
360 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
|
361 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
|
362 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
|
363 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
|
364 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
|
365 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
|
366 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
|
367 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; | |
|
368 | END LOOP all_status; | |
|
369 | ||
|
370 | paddr := "000000"; | |
|
371 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
|
372 | prdata <= (OTHERS => '0'); | |
|
373 | IF apbi.psel(pindex) = '1' THEN | |
|
374 | -- APB DMA READ -- | |
|
375 | CASE paddr(7 DOWNTO 2) IS | |
|
376 | -- | |
|
377 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
|
378 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
|
379 | prdata(2) <= reg_sp.config_ms_run; | |
|
380 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
|
381 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
|
382 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
|
383 | prdata(3) <= reg_sp.status_ready_matrix_f2; | |
|
384 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |
|
385 | prdata(5) <= reg_sp.status_error_bad_component_error; | |
|
386 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
|
387 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
|
388 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; | |
|
389 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
|
390 | ||
|
391 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; | |
|
392 | WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; | |
|
393 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; | |
|
394 | WHEN "001001" => prdata <= reg_sp.coarse_time_f2; | |
|
395 | WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; | |
|
396 | WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; | |
|
397 | WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; | |
|
398 | WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; | |
|
399 | ||
|
400 | WHEN "001111" => prdata <= debug_reg; | |
|
401 | --------------------------------------------------------------------- | |
|
402 | WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; | |
|
403 | prdata(1) <= reg_wp.data_shaping_SP0; | |
|
404 | prdata(2) <= reg_wp.data_shaping_SP1; | |
|
405 | prdata(3) <= reg_wp.data_shaping_R0; | |
|
406 | prdata(4) <= reg_wp.data_shaping_R1; | |
|
407 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; | |
|
408 | prdata(1) <= reg_wp.enable_f1; | |
|
409 | prdata(2) <= reg_wp.enable_f2; | |
|
410 | prdata(3) <= reg_wp.enable_f3; | |
|
411 | prdata(4) <= reg_wp.burst_f0; | |
|
412 | prdata(5) <= reg_wp.burst_f1; | |
|
413 | prdata(6) <= reg_wp.burst_f2; | |
|
414 | prdata(7) <= reg_wp.run; | |
|
415 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; | |
|
416 | WHEN "010011" => prdata <= reg_wp.addr_data_f1; | |
|
417 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; | |
|
418 | WHEN "010101" => prdata <= reg_wp.addr_data_f3; | |
|
419 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
|
420 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
|
421 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |
|
422 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
|
423 | WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
|
424 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
|
425 | WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
|
426 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
|
427 | WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
|
428 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
|
429 | WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
|
430 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
|
431 | ---------------------------------------------------- | |
|
432 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); | |
|
433 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); | |
|
434 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); | |
|
435 | WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); | |
|
436 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); | |
|
437 | WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); | |
|
438 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); | |
|
439 | WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); | |
|
440 | ---------------------------------------------------- | |
|
441 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
|
442 | WHEN OTHERS => NULL; | |
|
443 | ||
|
444 | END CASE; | |
|
445 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
|
446 | -- APB DMA WRITE -- | |
|
447 | CASE paddr(7 DOWNTO 2) IS | |
|
448 | -- | |
|
449 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
|
450 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
|
451 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
|
452 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
|
453 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
|
454 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
|
455 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); | |
|
456 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |
|
457 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); | |
|
458 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
|
459 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
460 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |
|
461 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |
|
462 | -- | |
|
463 | WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
|
464 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |
|
465 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |
|
466 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
|
467 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |
|
468 | WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
|
469 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
|
470 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
|
471 | reg_wp.enable_f3 <= apbi.pwdata(3); | |
|
472 | reg_wp.burst_f0 <= apbi.pwdata(4); | |
|
473 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
|
474 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
|
475 | reg_wp.run <= apbi.pwdata(7); | |
|
476 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
|
477 | WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
|
478 | WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
|
479 | WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
|
480 | WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
|
481 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
|
482 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
|
483 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
|
484 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
|
485 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
|
486 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
|
487 | WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
488 | WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
489 | WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
490 | WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
491 | WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
492 | WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
493 | WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
|
494 | WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
|
495 | WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
496 | -- | |
|
497 | WHEN OTHERS => NULL; | |
|
498 | END CASE; | |
|
499 | END IF; | |
|
500 | END IF; | |
|
501 | ||
|
502 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |
|
503 | ready_matrix_f0_1 OR | |
|
504 | ready_matrix_f1 OR | |
|
505 | ready_matrix_f2) | |
|
506 | ) | |
|
507 | OR | |
|
508 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR | |
|
509 | error_bad_component_error) | |
|
510 | )); | |
|
511 | ||
|
512 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; | |
|
513 | ||
|
514 | END IF; | |
|
515 | END PROCESS lpp_lfr_apbreg; | |
|
516 | ||
|
517 | apbo.pindex <= pindex; | |
|
518 | apbo.pconfig <= pconfig; | |
|
519 | apbo.prdata <= prdata; | |
|
520 | ||
|
521 | ----------------------------------------------------------------------------- | |
|
522 | -- IRQ | |
|
523 | ----------------------------------------------------------------------------- | |
|
524 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; | |
|
525 | ||
|
526 | PROCESS (HCLK, HRESETn) | |
|
527 | BEGIN -- PROCESS | |
|
528 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
529 | irq_wfp_reg <= (OTHERS => '0'); | |
|
530 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
|
531 | irq_wfp_reg <= irq_wfp_reg_s; | |
|
532 | END IF; | |
|
533 | END PROCESS; | |
|
534 | ||
|
535 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
|
536 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); | |
|
537 | END GENERATE all_irq_wfp; | |
|
538 | ||
|
539 | irq_wfp_ZERO <= (OTHERS => '0'); | |
|
540 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; | |
|
541 | ||
|
542 | run_ms <= reg_sp.config_ms_run; | |
|
543 | ||
|
544 | END beh; No newline at end of file |
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@@ -1,374 +1,394 | |||
|
1 | LIBRARY ieee; | |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
3 | ||
|
4 | LIBRARY lpp; | |
|
5 | USE lpp.lpp_amba.ALL; | |
|
6 | USE lpp.lpp_memory.ALL; | |
|
7 | --USE lpp.lpp_uart.ALL; | |
|
8 | USE lpp.lpp_matrix.ALL; | |
|
9 | --USE lpp.lpp_delay.ALL; | |
|
10 | USE lpp.lpp_fft.ALL; | |
|
11 | USE lpp.fft_components.ALL; | |
|
12 | USE lpp.lpp_ad_conv.ALL; | |
|
13 | USE lpp.iir_filter.ALL; | |
|
14 | USE lpp.general_purpose.ALL; | |
|
15 | USE lpp.Filtercfg.ALL; | |
|
16 | USE lpp.lpp_demux.ALL; | |
|
17 | USE lpp.lpp_top_lfr_pkg.ALL; | |
|
18 | USE lpp.lpp_dma_pkg.ALL; | |
|
19 | USE lpp.lpp_Header.ALL; | |
|
20 | USE lpp.lpp_lfr_pkg.ALL; | |
|
21 | ||
|
22 | LIBRARY grlib; | |
|
23 | USE grlib.amba.ALL; | |
|
24 | USE grlib.stdlib.ALL; | |
|
25 | USE grlib.devices.ALL; | |
|
26 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
27 | ||
|
28 | ||
|
29 | ENTITY lpp_lfr_ms IS | |
|
30 | GENERIC ( | |
|
31 | Mem_use : INTEGER | |
|
32 | ); | |
|
33 | PORT ( | |
|
34 | clk : IN STD_LOGIC; | |
|
35 | rstn : IN STD_LOGIC; | |
|
36 | ||
|
37 | --------------------------------------------------------------------------- | |
|
38 | -- DATA INPUT | |
|
39 | --------------------------------------------------------------------------- | |
|
40 | -- TIME | |
|
41 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
|
42 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
|
43 | -- | |
|
44 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
45 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
46 | -- | |
|
47 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
48 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
49 | -- | |
|
50 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
51 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
52 | ||
|
53 | --------------------------------------------------------------------------- | |
|
54 | -- DMA | |
|
55 | --------------------------------------------------------------------------- | |
|
56 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
57 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
58 | dma_valid : OUT STD_LOGIC; | |
|
59 | dma_valid_burst : OUT STD_LOGIC; | |
|
60 | dma_ren : IN STD_LOGIC; | |
|
61 | dma_done : IN STD_LOGIC; | |
|
62 | ||
|
63 | -- Reg out | |
|
64 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
|
65 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
66 | ready_matrix_f1 : OUT STD_LOGIC; | |
|
67 | ready_matrix_f2 : OUT STD_LOGIC; | |
|
68 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
69 | error_bad_component_error : OUT STD_LOGIC; | |
|
70 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
71 | ||
|
72 | -- Reg In | |
|
73 | status_ready_matrix_f0_0 :IN STD_LOGIC; | |
|
74 | status_ready_matrix_f0_1 :IN STD_LOGIC; | |
|
75 | status_ready_matrix_f1 :IN STD_LOGIC; | |
|
76 | status_ready_matrix_f2 :IN STD_LOGIC; | |
|
77 | status_error_anticipating_empty_fifo :IN STD_LOGIC; | |
|
78 | status_error_bad_component_error :IN STD_LOGIC; | |
|
79 | ||
|
80 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
|
81 | config_active_interruption_onError : IN STD_LOGIC; | |
|
82 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
83 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | ||
|
87 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
88 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
89 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
|
91 | ||
|
92 | ); | |
|
93 | END; | |
|
94 | ||
|
95 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |
|
96 | ----------------------------------------------------------------------------- | |
|
97 | SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
98 | SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
99 | SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
100 | SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
101 | SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
102 | SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
103 | ||
|
104 | ----------------------------------------------------------------------------- | |
|
105 | SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); | |
|
106 | SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
107 | SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
108 | SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
109 | ||
|
110 | ----------------------------------------------------------------------------- | |
|
111 | SIGNAL FFT_Load : STD_LOGIC; | |
|
112 | SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
113 | SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
114 | SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
115 | SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
116 | ||
|
117 | ----------------------------------------------------------------------------- | |
|
118 | SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
119 | SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
120 | ||
|
121 | ----------------------------------------------------------------------------- | |
|
122 | SIGNAL SM_FlagError : STD_LOGIC; | |
|
123 | -- SIGNAL SM_Pong : STD_LOGIC; | |
|
124 | SIGNAL SM_Wen : STD_LOGIC; | |
|
125 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
126 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
127 | SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
128 | SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
129 | SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
|
130 | ||
|
131 | ----------------------------------------------------------------------------- | |
|
132 | SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
133 | SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
134 | SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
|
135 | ||
|
136 | ----------------------------------------------------------------------------- | |
|
137 | SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
138 | SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
139 | SIGNAL Head_Empty : STD_LOGIC; | |
|
140 | SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
141 | SIGNAL Head_Valid : STD_LOGIC; | |
|
142 | SIGNAL Head_Val : STD_LOGIC; | |
|
143 | ||
|
144 | ----------------------------------------------------------------------------- | |
|
145 | SIGNAL DMA_Read : STD_LOGIC; | |
|
146 | SIGNAL DMA_ack : STD_LOGIC; | |
|
147 | ||
|
148 | ----------------------------------------------------------------------------- | |
|
149 | SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
150 | ||
|
151 | BEGIN | |
|
152 | ||
|
153 | ----------------------------------------------------------------------------- | |
|
154 | Memf0: lppFIFOxN | |
|
155 | GENERIC MAP ( | |
|
156 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
|
157 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') | |
|
158 | PORT MAP ( | |
|
159 | rstn => rstn, wclk => clk, rclk => clk, | |
|
160 | ReUse => (OTHERS => '0'), | |
|
161 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), | |
|
162 | wdata => sample_f0_wdata, rdata => FifoF0_Data, | |
|
163 | full => OPEN, empty => FifoF0_Empty); | |
|
164 | ||
|
165 | Memf1: lppFIFOxN | |
|
166 | GENERIC MAP ( | |
|
167 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
|
168 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
|
169 | PORT MAP ( | |
|
170 | rstn => rstn, wclk => clk, rclk => clk, | |
|
171 | ReUse => (OTHERS => '0'), | |
|
172 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), | |
|
173 | wdata => sample_f1_wdata, rdata => FifoF1_Data, | |
|
174 | full => OPEN, empty => FifoF1_Empty); | |
|
175 | ||
|
176 | ||
|
177 | Memf2: lppFIFOxN | |
|
178 | GENERIC MAP ( | |
|
179 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
|
180 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
|
181 | PORT MAP ( | |
|
182 | rstn => rstn, wclk => clk, rclk => clk, | |
|
183 | ReUse => (OTHERS => '0'), | |
|
184 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), | |
|
185 | wdata => sample_f3_wdata, rdata => FifoF3_Data, | |
|
186 | full => OPEN, empty => FifoF3_Empty); | |
|
187 | ----------------------------------------------------------------------------- | |
|
188 | ||
|
189 | ||
|
190 | ----------------------------------------------------------------------------- | |
|
191 | DMUX0 : DEMUX | |
|
192 | GENERIC MAP ( | |
|
193 | Data_sz => 16) | |
|
194 | PORT MAP ( | |
|
195 | clk => clk, | |
|
196 | rstn => rstn, | |
|
197 | Read => FFT_Read, | |
|
198 | Load => FFT_Load, | |
|
199 | EmptyF0 => FifoF0_Empty, | |
|
200 | EmptyF1 => FifoF1_Empty, | |
|
201 | EmptyF2 => FifoF3_Empty, | |
|
202 |
|
|
|
203 |
|
|
|
204 |
|
|
|
205 | WorkFreq => DMUX_WorkFreq, | |
|
206 | Read_DEMUX => DMUX_Read, | |
|
207 | Empty => DMUX_Empty, | |
|
208 |
Data |
|
|
209 | ----------------------------------------------------------------------------- | |
|
210 | ||
|
211 | ||
|
212 | ----------------------------------------------------------------------------- | |
|
213 | FFT0: FFT | |
|
214 | GENERIC MAP ( | |
|
215 | Data_sz => 16, | |
|
216 | NbData => 256) | |
|
217 | PORT MAP ( | |
|
218 | clkm => clk, | |
|
219 | rstn => rstn, | |
|
220 | FifoIN_Empty => DMUX_Empty, | |
|
221 | FifoIN_Data => DMUX_Data, | |
|
222 | FifoOUT_Full => FifoINT_Full, | |
|
223 |
|
|
|
224 | Read => FFT_Read, | |
|
225 | Write => FFT_Write, | |
|
226 | ReUse => FFT_ReUse, | |
|
227 |
|
|
|
228 | ----------------------------------------------------------------------------- | |
|
229 | ||
|
230 | ||
|
231 | ----------------------------------------------------------------------------- | |
|
232 | MemInt : lppFIFOxN | |
|
233 | GENERIC MAP ( | |
|
234 | tech => 0, | |
|
235 | Mem_use => Mem_use, | |
|
236 | Data_sz => 16, | |
|
237 | Addr_sz => 8, | |
|
238 |
|
|
|
239 | Enable_ReUse => '1') | |
|
240 | PORT MAP ( | |
|
241 |
|
|
|
242 | wclk => clk, | |
|
243 | rclk => clk, | |
|
244 | ReUse => SM_ReUse, | |
|
245 |
|
|
|
246 | ren => SM_Read, | |
|
247 | wdata => FFT_Data, | |
|
248 | rdata => FifoINT_Data, | |
|
249 | full => FifoINT_Full, | |
|
250 | empty => OPEN); | |
|
251 | ----------------------------------------------------------------------------- | |
|
252 | ||
|
253 | ----------------------------------------------------------------------------- | |
|
254 | SM0 : MatriceSpectrale | |
|
255 | GENERIC MAP ( | |
|
256 | Input_SZ => 16, | |
|
257 | Result_SZ => 32) | |
|
258 | PORT MAP ( | |
|
259 | clkm => clk, | |
|
260 | rstn => rstn, | |
|
261 | FifoIN_Full => FifoINT_Full, | |
|
262 | SetReUse => FFT_ReUse, | |
|
263 |
|
|
|
264 | Data_IN => FifoINT_Data, | |
|
265 | ACK => DMA_ack, | |
|
266 | SM_Write => SM_Wen, | |
|
267 | FlagError => SM_FlagError, | |
|
268 | -- Pong => SM_Pong, | |
|
269 |
|
|
|
270 |
Write |
|
|
271 | Read => SM_Read, | |
|
272 | ReUse => SM_ReUse, | |
|
273 |
|
|
|
274 | ----------------------------------------------------------------------------- | |
|
275 | ||
|
276 | ----------------------------------------------------------------------------- | |
|
277 | MemOut : lppFIFOxN | |
|
278 | GENERIC MAP ( | |
|
279 | tech => 0, | |
|
280 | Mem_use => Mem_use, | |
|
281 | Data_sz => 32, | |
|
282 | Addr_sz => 8, | |
|
283 |
|
|
|
284 | Enable_ReUse => '0') | |
|
285 | PORT MAP ( | |
|
286 |
|
|
|
287 | wclk => clk, | |
|
288 | rclk => clk, | |
|
289 | ReUse => (OTHERS => '0'), | |
|
290 |
|
|
|
291 | ren => Head_Read, | |
|
292 | wdata => SM_Data, | |
|
293 | rdata => FifoOUT_Data, | |
|
294 | full => FifoOUT_Full, | |
|
295 | empty => FifoOUT_Empty); | |
|
296 | ----------------------------------------------------------------------------- | |
|
297 | ||
|
298 | ----------------------------------------------------------------------------- | |
|
299 | Head0 : HeaderBuilder | |
|
300 | GENERIC MAP ( | |
|
301 | Data_sz => 32) | |
|
302 | PORT MAP ( | |
|
303 | clkm => clk, | |
|
304 | rstn => rstn, | |
|
305 | -- pong => SM_Pong, | |
|
306 | Statu => SM_Param, | |
|
307 | Matrix_Type => DMUX_WorkFreq, | |
|
308 | Matrix_Write => SM_Wen, | |
|
309 | Valid => Head_Valid, | |
|
310 | ||
|
311 | dataIN => FifoOUT_Data, | |
|
312 | emptyIN => FifoOUT_Empty, | |
|
313 |
|
|
|
314 | ||
|
315 |
data |
|
|
316 |
empty |
|
|
317 |
Ren |
|
|
318 | ||
|
319 |
|
|
|
320 | header_val => Head_Val, | |
|
321 | header_ack => DMA_ack ); | |
|
322 | ----------------------------------------------------------------------------- | |
|
323 | data_time(31 DOWNTO 0) <= coarse_time; | |
|
324 | data_time(47 DOWNTO 32) <= fine_time; | |
|
325 | ||
|
326 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma | |
|
327 | PORT MAP ( | |
|
328 | HCLK => clk, | |
|
329 | HRESETn => rstn, | |
|
330 | ||
|
331 | data_time => data_time, | |
|
332 | ||
|
333 |
|
|
|
334 | fifo_empty => Head_Empty, | |
|
335 |
|
|
|
336 | ||
|
337 |
|
|
|
338 |
|
|
|
339 |
|
|
|
340 | ||
|
341 |
|
|
|
342 |
|
|
|
343 |
|
|
|
344 | dma_valid_burst => dma_valid_burst, | |
|
345 |
|
|
|
346 |
dma_d |
|
|
347 | ||
|
348 |
|
|
|
349 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
350 |
|
|
|
351 | ready_matrix_f2 => ready_matrix_f2, | |
|
352 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
353 | error_bad_component_error => error_bad_component_error, | |
|
354 |
|
|
|
355 |
|
|
|
356 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
357 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
358 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
359 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
360 | status_error_bad_component_error => status_error_bad_component_error, | |
|
361 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
362 | config_active_interruption_onError => config_active_interruption_onError, | |
|
363 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
|
364 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
365 | addr_matrix_f1 => addr_matrix_f1, | |
|
366 | addr_matrix_f2 => addr_matrix_f2, | |
|
367 | ||
|
368 |
matrix_ |
|
|
369 |
matrix_ |
|
|
370 |
matrix_ |
|
|
371 | matrix_time_f2 => matrix_time_f2 | |
|
372 | ); | |
|
373 | ||
|
374 | END Behavioral; | |
|
1 | LIBRARY ieee; | |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
3 | ||
|
4 | LIBRARY lpp; | |
|
5 | USE lpp.lpp_amba.ALL; | |
|
6 | USE lpp.lpp_memory.ALL; | |
|
7 | --USE lpp.lpp_uart.ALL; | |
|
8 | USE lpp.lpp_matrix.ALL; | |
|
9 | --USE lpp.lpp_delay.ALL; | |
|
10 | USE lpp.lpp_fft.ALL; | |
|
11 | USE lpp.fft_components.ALL; | |
|
12 | USE lpp.lpp_ad_conv.ALL; | |
|
13 | USE lpp.iir_filter.ALL; | |
|
14 | USE lpp.general_purpose.ALL; | |
|
15 | USE lpp.Filtercfg.ALL; | |
|
16 | USE lpp.lpp_demux.ALL; | |
|
17 | USE lpp.lpp_top_lfr_pkg.ALL; | |
|
18 | USE lpp.lpp_dma_pkg.ALL; | |
|
19 | USE lpp.lpp_Header.ALL; | |
|
20 | USE lpp.lpp_lfr_pkg.ALL; | |
|
21 | ||
|
22 | LIBRARY grlib; | |
|
23 | USE grlib.amba.ALL; | |
|
24 | USE grlib.stdlib.ALL; | |
|
25 | USE grlib.devices.ALL; | |
|
26 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
27 | ||
|
28 | ||
|
29 | ENTITY lpp_lfr_ms IS | |
|
30 | GENERIC ( | |
|
31 | Mem_use : INTEGER := use_RAM | |
|
32 | ); | |
|
33 | PORT ( | |
|
34 | clk : IN STD_LOGIC; | |
|
35 | rstn : IN STD_LOGIC; | |
|
36 | ||
|
37 | --------------------------------------------------------------------------- | |
|
38 | -- DATA INPUT | |
|
39 | --------------------------------------------------------------------------- | |
|
40 | -- TIME | |
|
41 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
|
42 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
|
43 | -- | |
|
44 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
45 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
46 | -- | |
|
47 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
48 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
49 | -- | |
|
50 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
51 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
52 | ||
|
53 | --------------------------------------------------------------------------- | |
|
54 | -- DMA | |
|
55 | --------------------------------------------------------------------------- | |
|
56 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
57 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
58 | dma_valid : OUT STD_LOGIC; | |
|
59 | dma_valid_burst : OUT STD_LOGIC; | |
|
60 | dma_ren : IN STD_LOGIC; | |
|
61 | dma_done : IN STD_LOGIC; | |
|
62 | ||
|
63 | -- Reg out | |
|
64 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
|
65 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
66 | ready_matrix_f1 : OUT STD_LOGIC; | |
|
67 | ready_matrix_f2 : OUT STD_LOGIC; | |
|
68 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
69 | error_bad_component_error : OUT STD_LOGIC; | |
|
70 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
71 | ||
|
72 | -- Reg In | |
|
73 | status_ready_matrix_f0_0 :IN STD_LOGIC; | |
|
74 | status_ready_matrix_f0_1 :IN STD_LOGIC; | |
|
75 | status_ready_matrix_f1 :IN STD_LOGIC; | |
|
76 | status_ready_matrix_f2 :IN STD_LOGIC; | |
|
77 | status_error_anticipating_empty_fifo :IN STD_LOGIC; | |
|
78 | status_error_bad_component_error :IN STD_LOGIC; | |
|
79 | ||
|
80 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
|
81 | config_active_interruption_onError : IN STD_LOGIC; | |
|
82 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
83 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | ||
|
87 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
88 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
89 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
|
91 | ||
|
92 | ); | |
|
93 | END; | |
|
94 | ||
|
95 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |
|
96 | ----------------------------------------------------------------------------- | |
|
97 | SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
98 | SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
99 | SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
100 | SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
101 | SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
102 | SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
103 | ||
|
104 | ----------------------------------------------------------------------------- | |
|
105 | SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); | |
|
106 | SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
107 | SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
108 | SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
109 | ||
|
110 | ----------------------------------------------------------------------------- | |
|
111 | SIGNAL FFT_Load : STD_LOGIC; | |
|
112 | SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
113 | SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
114 | SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
115 | SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
116 | ||
|
117 | ----------------------------------------------------------------------------- | |
|
118 | SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
119 | SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
|
120 | ||
|
121 | ----------------------------------------------------------------------------- | |
|
122 | SIGNAL SM_FlagError : STD_LOGIC; | |
|
123 | -- SIGNAL SM_Pong : STD_LOGIC; | |
|
124 | SIGNAL SM_Wen : STD_LOGIC; | |
|
125 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
126 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
127 | SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
128 | SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
129 | SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
|
130 | ||
|
131 | ----------------------------------------------------------------------------- | |
|
132 | SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
133 | SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
134 | SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
|
135 | ||
|
136 | ----------------------------------------------------------------------------- | |
|
137 | SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
138 | SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
139 | SIGNAL Head_Empty : STD_LOGIC; | |
|
140 | SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
141 | SIGNAL Head_Valid : STD_LOGIC; | |
|
142 | SIGNAL Head_Val : STD_LOGIC; | |
|
143 | ||
|
144 | ----------------------------------------------------------------------------- | |
|
145 | SIGNAL DMA_Read : STD_LOGIC; | |
|
146 | SIGNAL DMA_ack : STD_LOGIC; | |
|
147 | ||
|
148 | ----------------------------------------------------------------------------- | |
|
149 | SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
150 | ||
|
151 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
152 | SIGNAL dma_valid_s : STD_LOGIC; | |
|
153 | SIGNAL dma_valid_burst_s : STD_LOGIC; | |
|
154 | ||
|
155 | BEGIN | |
|
156 | ||
|
157 | ----------------------------------------------------------------------------- | |
|
158 | Memf0: lppFIFOxN | |
|
159 | GENERIC MAP ( | |
|
160 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
|
161 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') | |
|
162 | PORT MAP ( | |
|
163 | rstn => rstn, wclk => clk, rclk => clk, | |
|
164 | ReUse => (OTHERS => '0'), | |
|
165 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), | |
|
166 | wdata => sample_f0_wdata, rdata => FifoF0_Data, | |
|
167 | full => OPEN, empty => FifoF0_Empty); | |
|
168 | ||
|
169 | Memf1: lppFIFOxN | |
|
170 | GENERIC MAP ( | |
|
171 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
|
172 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
|
173 | PORT MAP ( | |
|
174 | rstn => rstn, wclk => clk, rclk => clk, | |
|
175 | ReUse => (OTHERS => '0'), | |
|
176 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), | |
|
177 | wdata => sample_f1_wdata, rdata => FifoF1_Data, | |
|
178 | full => OPEN, empty => FifoF1_Empty); | |
|
179 | ||
|
180 | ||
|
181 | Memf2: lppFIFOxN | |
|
182 | GENERIC MAP ( | |
|
183 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
|
184 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
|
185 | PORT MAP ( | |
|
186 | rstn => rstn, wclk => clk, rclk => clk, | |
|
187 | ReUse => (OTHERS => '0'), | |
|
188 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), | |
|
189 | wdata => sample_f3_wdata, rdata => FifoF3_Data, | |
|
190 | full => OPEN, empty => FifoF3_Empty); | |
|
191 | ----------------------------------------------------------------------------- | |
|
192 | ||
|
193 | ||
|
194 | ----------------------------------------------------------------------------- | |
|
195 | DMUX0 : DEMUX | |
|
196 | GENERIC MAP ( | |
|
197 | Data_sz => 16) | |
|
198 | PORT MAP ( | |
|
199 | clk => clk, | |
|
200 | rstn => rstn, | |
|
201 | Read => FFT_Read, | |
|
202 | Load => FFT_Load, | |
|
203 | EmptyF0 => FifoF0_Empty, | |
|
204 | EmptyF1 => FifoF1_Empty, | |
|
205 | EmptyF2 => FifoF3_Empty, | |
|
206 | DataF0 => FifoF0_Data, | |
|
207 | DataF1 => FifoF1_Data, | |
|
208 | DataF2 => FifoF3_Data, | |
|
209 | WorkFreq => DMUX_WorkFreq, | |
|
210 | Read_DEMUX => DMUX_Read, | |
|
211 | Empty => DMUX_Empty, | |
|
212 | Data => DMUX_Data); | |
|
213 | ----------------------------------------------------------------------------- | |
|
214 | ||
|
215 | ||
|
216 | ----------------------------------------------------------------------------- | |
|
217 | FFT0: FFT | |
|
218 | GENERIC MAP ( | |
|
219 | Data_sz => 16, | |
|
220 | NbData => 256) | |
|
221 | PORT MAP ( | |
|
222 | clkm => clk, | |
|
223 | rstn => rstn, | |
|
224 | FifoIN_Empty => DMUX_Empty, | |
|
225 | FifoIN_Data => DMUX_Data, | |
|
226 | FifoOUT_Full => FifoINT_Full, | |
|
227 | Load => FFT_Load, | |
|
228 | Read => FFT_Read, | |
|
229 | Write => FFT_Write, | |
|
230 | ReUse => FFT_ReUse, | |
|
231 | Data => FFT_Data); | |
|
232 | ----------------------------------------------------------------------------- | |
|
233 | ||
|
234 | ||
|
235 | ----------------------------------------------------------------------------- | |
|
236 | MemInt : lppFIFOxN | |
|
237 | GENERIC MAP ( | |
|
238 | tech => 0, | |
|
239 | Mem_use => Mem_use, | |
|
240 | Data_sz => 16, | |
|
241 | Addr_sz => 8, | |
|
242 | FifoCnt => 5, | |
|
243 | Enable_ReUse => '1') | |
|
244 | PORT MAP ( | |
|
245 | rstn => rstn, | |
|
246 | wclk => clk, | |
|
247 | rclk => clk, | |
|
248 | ReUse => SM_ReUse, | |
|
249 | wen => FFT_Write, | |
|
250 | ren => SM_Read, | |
|
251 | wdata => FFT_Data, | |
|
252 | rdata => FifoINT_Data, | |
|
253 | full => FifoINT_Full, | |
|
254 | empty => OPEN); | |
|
255 | ----------------------------------------------------------------------------- | |
|
256 | ||
|
257 | ----------------------------------------------------------------------------- | |
|
258 | SM0 : MatriceSpectrale | |
|
259 | GENERIC MAP ( | |
|
260 | Input_SZ => 16, | |
|
261 | Result_SZ => 32) | |
|
262 | PORT MAP ( | |
|
263 | clkm => clk, | |
|
264 | rstn => rstn, | |
|
265 | FifoIN_Full => FifoINT_Full, | |
|
266 | SetReUse => FFT_ReUse, | |
|
267 | Valid => Head_Valid, | |
|
268 | Data_IN => FifoINT_Data, | |
|
269 | ACK => DMA_ack, | |
|
270 | SM_Write => SM_Wen, | |
|
271 | FlagError => SM_FlagError, | |
|
272 | -- Pong => SM_Pong, | |
|
273 | Statu => SM_Param, | |
|
274 | Write => SM_Write, | |
|
275 | Read => SM_Read, | |
|
276 | ReUse => SM_ReUse, | |
|
277 | Data_OUT => SM_Data); | |
|
278 | ----------------------------------------------------------------------------- | |
|
279 | ||
|
280 | ----------------------------------------------------------------------------- | |
|
281 | MemOut : lppFIFOxN | |
|
282 | GENERIC MAP ( | |
|
283 | tech => 0, | |
|
284 | Mem_use => Mem_use, | |
|
285 | Data_sz => 32, | |
|
286 | Addr_sz => 8, | |
|
287 | FifoCnt => 2, | |
|
288 | Enable_ReUse => '0') | |
|
289 | PORT MAP ( | |
|
290 | rstn => rstn, | |
|
291 | wclk => clk, | |
|
292 | rclk => clk, | |
|
293 | ReUse => (OTHERS => '0'), | |
|
294 | wen => SM_Write, | |
|
295 | ren => Head_Read, | |
|
296 | wdata => SM_Data, | |
|
297 | rdata => FifoOUT_Data, | |
|
298 | full => FifoOUT_Full, | |
|
299 | empty => FifoOUT_Empty); | |
|
300 | ----------------------------------------------------------------------------- | |
|
301 | ||
|
302 | ----------------------------------------------------------------------------- | |
|
303 | Head0 : HeaderBuilder | |
|
304 | GENERIC MAP ( | |
|
305 | Data_sz => 32) | |
|
306 | PORT MAP ( | |
|
307 | clkm => clk, | |
|
308 | rstn => rstn, | |
|
309 | -- pong => SM_Pong, | |
|
310 | Statu => SM_Param, | |
|
311 | Matrix_Type => DMUX_WorkFreq, | |
|
312 | Matrix_Write => SM_Wen, | |
|
313 | Valid => Head_Valid, | |
|
314 | ||
|
315 | dataIN => FifoOUT_Data, | |
|
316 | emptyIN => FifoOUT_Empty, | |
|
317 | RenOUT => Head_Read, | |
|
318 | ||
|
319 | dataOUT => Head_Data, | |
|
320 | emptyOUT => Head_Empty, | |
|
321 | RenIN => DMA_Read, | |
|
322 | ||
|
323 | header => Head_Header, | |
|
324 | header_val => Head_Val, | |
|
325 | header_ack => DMA_ack ); | |
|
326 | ----------------------------------------------------------------------------- | |
|
327 | data_time(31 DOWNTO 0) <= coarse_time; | |
|
328 | data_time(47 DOWNTO 32) <= fine_time; | |
|
329 | ||
|
330 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma | |
|
331 | PORT MAP ( | |
|
332 | HCLK => clk, | |
|
333 | HRESETn => rstn, | |
|
334 | ||
|
335 | data_time => data_time, | |
|
336 | ||
|
337 | fifo_data => Head_Data, | |
|
338 | fifo_empty => Head_Empty, | |
|
339 | fifo_ren => DMA_Read, | |
|
340 | ||
|
341 | header => Head_Header, | |
|
342 | header_val => Head_Val, | |
|
343 | header_ack => DMA_ack, | |
|
344 | ||
|
345 | dma_addr => dma_addr, | |
|
346 | dma_data => dma_data, | |
|
347 | dma_valid => dma_valid_s, | |
|
348 | dma_valid_burst => dma_valid_burst_s, | |
|
349 | dma_ren => dma_ren, | |
|
350 | dma_done => dma_done, | |
|
351 | ||
|
352 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
|
353 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
354 | ready_matrix_f1 => ready_matrix_f1, | |
|
355 | ready_matrix_f2 => ready_matrix_f2, | |
|
356 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
357 | error_bad_component_error => error_bad_component_error, | |
|
358 | debug_reg => debug_reg_s, | |
|
359 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
|
360 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
361 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
362 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
363 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
364 | status_error_bad_component_error => status_error_bad_component_error, | |
|
365 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
366 | config_active_interruption_onError => config_active_interruption_onError, | |
|
367 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
|
368 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
369 | addr_matrix_f1 => addr_matrix_f1, | |
|
370 | addr_matrix_f2 => addr_matrix_f2, | |
|
371 | ||
|
372 | matrix_time_f0_0 => matrix_time_f0_0, | |
|
373 | matrix_time_f0_1 => matrix_time_f0_1, | |
|
374 | matrix_time_f1 => matrix_time_f1, | |
|
375 | matrix_time_f2 => matrix_time_f2 | |
|
376 | ); | |
|
377 | ||
|
378 | dma_valid <= dma_valid_s; | |
|
379 | dma_valid_burst <= dma_valid_burst_s; | |
|
380 | ||
|
381 | debug_reg(9 DOWNTO 0) <= debug_reg_s(9 DOWNTO 0); | |
|
382 | debug_reg(10) <= Head_Empty; | |
|
383 | debug_reg(11) <= DMA_Read; | |
|
384 | debug_reg(12) <= Head_Val; | |
|
385 | debug_reg(13) <= DMA_ack; | |
|
386 | debug_reg(14) <= dma_ren; | |
|
387 | debug_reg(15) <= dma_done; | |
|
388 | debug_reg(16) <= dma_valid_s; | |
|
389 | debug_reg(17) <= dma_valid_burst_s; | |
|
390 | debug_reg(31 DOWNTO 18) <= (OTHERS => '0'); | |
|
391 | ||
|
392 | ||
|
393 | ||
|
394 | END Behavioral; |
@@ -200,7 +200,8 BEGIN | |||
|
200 | 200 | debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); |
|
201 | 201 | |
|
202 | 202 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
203 | ||
|
203 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); | |
|
204 | ||
|
204 | 205 |
|
|
205 | 206 | WHEN IDLE => |
|
206 | 207 | debug_reg_s(2 DOWNTO 0) <= "000"; |
@@ -214,6 +215,9 BEGIN | |||
|
214 | 215 | ready_matrix_f2 <= '0'; |
|
215 | 216 | error_bad_component_error <= '0'; |
|
216 | 217 | header_select <= '1'; |
|
218 | IF header_val = '1' THEN | |
|
219 | header_ack <= '1'; | |
|
220 | END IF; | |
|
217 | 221 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN |
|
218 | 222 | debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0); |
|
219 | 223 | debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2); |
@@ -226,9 +230,9 BEGIN | |||
|
226 | 230 | |
|
227 | 231 | WHEN CHECK_COMPONENT_TYPE => |
|
228 | 232 | debug_reg_s(2 DOWNTO 0) <= "001"; |
|
233 | header_ack <= '0'; | |
|
229 | 234 | |
|
230 | 235 | IF header_check_ok = '1' THEN |
|
231 | header_ack <= '1'; | |
|
232 | 236 | header_send <= '0'; |
|
233 | 237 | -- |
|
234 | 238 | IF component_type = "0000" THEN |
@@ -256,7 +260,6 BEGIN | |||
|
256 | 260 | ELSE |
|
257 | 261 | error_bad_component_error <= '1'; |
|
258 | 262 | component_type_pre <= "0000"; |
|
259 | header_ack <= '1'; | |
|
260 | 263 | state <= TRASH_FIFO; |
|
261 | 264 | END IF; |
|
262 | 265 |
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