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MINI_LFR-WFP_MS-0.1.5.pdb
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_val : STD_LOGIC;
166 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170
170
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172
172
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
175
175
176 BEGIN -- beh
176 BEGIN -- beh
177
177
178 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
179 -- CLK
179 -- CLK
180 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
181
181
182 PROCESS(clk_50)
182 PROCESS(clk_50)
183 BEGIN
183 BEGIN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
185 clk_50_s <= NOT clk_50_s;
185 clk_50_s <= NOT clk_50_s;
186 END IF;
186 END IF;
187 END PROCESS;
187 END PROCESS;
188
188
189 PROCESS(clk_50_s)
189 PROCESS(clk_50_s)
190 BEGIN
190 BEGIN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 clk_25 <= NOT clk_25;
192 clk_25 <= NOT clk_25;
193 END IF;
193 END IF;
194 END PROCESS;
194 END PROCESS;
195
195
196 PROCESS(clk_49)
196 PROCESS(clk_49)
197 BEGIN
197 BEGIN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
199 clk_24 <= NOT clk_24;
199 clk_24 <= NOT clk_24;
200 END IF;
200 END IF;
201 END PROCESS;
201 END PROCESS;
202
202
203 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
204
204
205 PROCESS (clk_25, reset)
205 PROCESS (clk_25, reset)
206 BEGIN -- PROCESS
206 BEGIN -- PROCESS
207 IF reset = '0' THEN -- asynchronous reset (active low)
207 IF reset = '0' THEN -- asynchronous reset (active low)
208 LED0 <= '0';
208 LED0 <= '0';
209 LED1 <= '0';
209 LED1 <= '0';
210 LED2 <= '0';
210 LED2 <= '0';
211 --IO1 <= '0';
211 --IO1 <= '0';
212 --IO2 <= '1';
212 --IO2 <= '1';
213 --IO3 <= '0';
213 --IO3 <= '0';
214 --IO4 <= '0';
214 --IO4 <= '0';
215 --IO5 <= '0';
215 --IO5 <= '0';
216 --IO6 <= '0';
216 --IO6 <= '0';
217 --IO7 <= '0';
217 --IO7 <= '0';
218 --IO8 <= '0';
218 --IO8 <= '0';
219 --IO9 <= '0';
219 --IO9 <= '0';
220 --IO10 <= '0';
220 --IO10 <= '0';
221 --IO11 <= '0';
221 --IO11 <= '0';
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 LED0 <= '0';
223 LED0 <= '0';
224 LED1 <= '1';
224 LED1 <= '1';
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 --IO1 <= '1';
226 --IO1 <= '1';
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 --IO3 <= ADC_SDO(0);
228 --IO3 <= ADC_SDO(0);
229 --IO4 <= ADC_SDO(1);
229 --IO4 <= ADC_SDO(1);
230 --IO5 <= ADC_SDO(2);
230 --IO5 <= ADC_SDO(2);
231 --IO6 <= ADC_SDO(3);
231 --IO6 <= ADC_SDO(3);
232 --IO7 <= ADC_SDO(4);
232 --IO7 <= ADC_SDO(4);
233 --IO8 <= ADC_SDO(5);
233 --IO8 <= ADC_SDO(5);
234 --IO9 <= ADC_SDO(6);
234 --IO9 <= ADC_SDO(6);
235 --IO10 <= ADC_SDO(7);
235 --IO10 <= ADC_SDO(7);
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
237 END IF;
237 END IF;
238 END PROCESS;
238 END PROCESS;
239
239
240 PROCESS (clk_24, reset)
240 PROCESS (clk_24, reset)
241 BEGIN -- PROCESS
241 BEGIN -- PROCESS
242 IF reset = '0' THEN -- asynchronous reset (active low)
242 IF reset = '0' THEN -- asynchronous reset (active low)
243 I00_s <= '0';
243 I00_s <= '0';
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 I00_s <= NOT I00_s ;
245 I00_s <= NOT I00_s ;
246 END IF;
246 END IF;
247 END PROCESS;
247 END PROCESS;
248 -- IO0 <= I00_s;
248 -- IO0 <= I00_s;
249
249
250 --UARTs
250 --UARTs
251 nCTS1 <= '1';
251 nCTS1 <= '1';
252 nCTS2 <= '1';
252 nCTS2 <= '1';
253 nDCD2 <= '1';
253 nDCD2 <= '1';
254
254
255 --EXT CONNECTOR
255 --EXT CONNECTOR
256
256
257 --SPACE WIRE
257 --SPACE WIRE
258
258
259 leon3_soc_1 : leon3_soc
259 leon3_soc_1 : leon3_soc
260 GENERIC MAP (
260 GENERIC MAP (
261 fabtech => apa3e,
261 fabtech => apa3e,
262 memtech => apa3e,
262 memtech => apa3e,
263 padtech => inferred,
263 padtech => inferred,
264 clktech => inferred,
264 clktech => inferred,
265 disas => 0,
265 disas => 0,
266 dbguart => 0,
266 dbguart => 0,
267 pclow => 2,
267 pclow => 2,
268 clk_freq => 25000,
268 clk_freq => 25000,
269 NB_CPU => 1,
269 NB_CPU => 1,
270 ENABLE_FPU => 1,
270 ENABLE_FPU => 1,
271 FPU_NETLIST => 0,
271 FPU_NETLIST => 0,
272 ENABLE_DSU => 1,
272 ENABLE_DSU => 1,
273 ENABLE_AHB_UART => 1,
273 ENABLE_AHB_UART => 1,
274 ENABLE_APB_UART => 1,
274 ENABLE_APB_UART => 1,
275 ENABLE_IRQMP => 1,
275 ENABLE_IRQMP => 1,
276 ENABLE_GPT => 1,
276 ENABLE_GPT => 1,
277 NB_AHB_MASTER => NB_AHB_MASTER,
277 NB_AHB_MASTER => NB_AHB_MASTER,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 NB_APB_SLAVE => NB_APB_SLAVE)
279 NB_APB_SLAVE => NB_APB_SLAVE)
280 PORT MAP (
280 PORT MAP (
281 clk => clk_25,
281 clk => clk_25,
282 reset => reset,
282 reset => reset,
283 errorn => errorn,
283 errorn => errorn,
284 ahbrxd => TXD1,
284 ahbrxd => TXD1,
285 ahbtxd => RXD1,
285 ahbtxd => RXD1,
286 urxd1 => TXD2,
286 urxd1 => TXD2,
287 utxd1 => RXD2,
287 utxd1 => RXD2,
288 address => SRAM_A,
288 address => SRAM_A,
289 data => SRAM_DQ,
289 data => SRAM_DQ,
290 nSRAM_BE0 => SRAM_nBE(0),
290 nSRAM_BE0 => SRAM_nBE(0),
291 nSRAM_BE1 => SRAM_nBE(1),
291 nSRAM_BE1 => SRAM_nBE(1),
292 nSRAM_BE2 => SRAM_nBE(2),
292 nSRAM_BE2 => SRAM_nBE(2),
293 nSRAM_BE3 => SRAM_nBE(3),
293 nSRAM_BE3 => SRAM_nBE(3),
294 nSRAM_WE => SRAM_nWE,
294 nSRAM_WE => SRAM_nWE,
295 nSRAM_CE => SRAM_CE,
295 nSRAM_CE => SRAM_CE,
296 nSRAM_OE => SRAM_nOE,
296 nSRAM_OE => SRAM_nOE,
297
297
298 apbi_ext => apbi_ext,
298 apbi_ext => apbi_ext,
299 apbo_ext => apbo_ext,
299 apbo_ext => apbo_ext,
300 ahbi_s_ext => ahbi_s_ext,
300 ahbi_s_ext => ahbi_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
302 ahbi_m_ext => ahbi_m_ext,
302 ahbi_m_ext => ahbi_m_ext,
303 ahbo_m_ext => ahbo_m_ext);
303 ahbo_m_ext => ahbo_m_ext);
304
304
305 -------------------------------------------------------------------------------
305 -------------------------------------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 -------------------------------------------------------------------------------
307 -------------------------------------------------------------------------------
308 apb_lfr_time_management_1 : apb_lfr_time_management
308 apb_lfr_time_management_1 : apb_lfr_time_management
309 GENERIC MAP (
309 GENERIC MAP (
310 pindex => 6,
310 pindex => 6,
311 paddr => 6,
311 paddr => 6,
312 pmask => 16#fff#,
312 pmask => 16#fff#,
313 pirq => 12,
313 pirq => 12,
314 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
314 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
315 PORT MAP (
315 PORT MAP (
316 clk25MHz => clk_25,
316 clk25MHz => clk_25,
317 clk49_152MHz => clk_24, -- 49.152MHz/2
317 clk49_152MHz => clk_24, -- 49.152MHz/2
318 resetn => reset,
318 resetn => reset,
319 grspw_tick => swno.tickout,
319 grspw_tick => swno.tickout,
320 apbi => apbi_ext,
320 apbi => apbi_ext,
321 apbo => apbo_ext(6),
321 apbo => apbo_ext(6),
322 coarse_time => coarse_time,
322 coarse_time => coarse_time,
323 fine_time => fine_time);
323 fine_time => fine_time);
324
324
325 -----------------------------------------------------------------------
325 -----------------------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
327 -----------------------------------------------------------------------
327 -----------------------------------------------------------------------
328
328
329 SPW_EN <= '1';
329 SPW_EN <= '1';
330
330
331 spw_clk <= clk_50_s;
331 spw_clk <= clk_50_s;
332 spw_rxtxclk <= spw_clk;
332 spw_rxtxclk <= spw_clk;
333 spw_rxclkn <= NOT spw_rxtxclk;
333 spw_rxclkn <= NOT spw_rxtxclk;
334
334
335 -- PADS for SPW1
335 -- PADS for SPW1
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 PORT MAP (SPW_NOM_SIN, stmp(0));
339 PORT MAP (SPW_NOM_SIN, stmp(0));
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 -- PADS FOR SPW2
344 -- PADS FOR SPW2
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 PORT MAP (SPW_RED_SIN, dtmp(1));
346 PORT MAP (SPW_RED_SIN, dtmp(1));
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 PORT MAP (SPW_RED_DIN, stmp(1));
348 PORT MAP (SPW_RED_DIN, stmp(1));
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
353
353
354 -- GRSPW PHY
354 -- GRSPW PHY
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 spw_phy0 : grspw_phy
357 spw_phy0 : grspw_phy
358 GENERIC MAP(
358 GENERIC MAP(
359 tech => apa3e,
359 tech => apa3e,
360 rxclkbuftype => 1,
360 rxclkbuftype => 1,
361 scantest => 0)
361 scantest => 0)
362 PORT MAP(
362 PORT MAP(
363 rxrst => swno.rxrst,
363 rxrst => swno.rxrst,
364 di => dtmp(j),
364 di => dtmp(j),
365 si => stmp(j),
365 si => stmp(j),
366 rxclko => spw_rxclk(j),
366 rxclko => spw_rxclk(j),
367 do => swni.d(j),
367 do => swni.d(j),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 END GENERATE spw_inputloop;
370 END GENERATE spw_inputloop;
371
371
372 -- SPW core
372 -- SPW core
373 sw0 : grspwm GENERIC MAP(
373 sw0 : grspwm GENERIC MAP(
374 tech => apa3e,
374 tech => apa3e,
375 hindex => 1,
375 hindex => 1,
376 pindex => 5,
376 pindex => 5,
377 paddr => 5,
377 paddr => 5,
378 pirq => 11,
378 pirq => 11,
379 sysfreq => 25000, -- CPU_FREQ
379 sysfreq => 25000, -- CPU_FREQ
380 rmap => 1,
380 rmap => 1,
381 rmapcrc => 1,
381 rmapcrc => 1,
382 fifosize1 => 16,
382 fifosize1 => 16,
383 fifosize2 => 16,
383 fifosize2 => 16,
384 rxclkbuftype => 1,
384 rxclkbuftype => 1,
385 rxunaligned => 0,
385 rxunaligned => 0,
386 rmapbufs => 4,
386 rmapbufs => 4,
387 ft => 0,
387 ft => 0,
388 netlist => 0,
388 netlist => 0,
389 ports => 2,
389 ports => 2,
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 memtech => apa3e,
391 memtech => apa3e,
392 destkey => 2,
392 destkey => 2,
393 spwcore => 1
393 spwcore => 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 )
397 )
398 PORT MAP(reset, clk_25, spw_rxclk(0),
398 PORT MAP(reset, clk_25, spw_rxclk(0),
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 swni, swno);
401 swni, swno);
402
402
403 swni.tickin <= '0';
403 swni.tickin <= '0';
404 swni.rmapen <= '1';
404 swni.rmapen <= '1';
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 swni.tickinraw <= '0';
406 swni.tickinraw <= '0';
407 swni.timein <= (OTHERS => '0');
407 swni.timein <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
410
410
411 -------------------------------------------------------------------------------
411 -------------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
414 lpp_lfr_1 : lpp_lfr
414 lpp_lfr_1 : lpp_lfr
415 GENERIC MAP (
415 GENERIC MAP (
416 Mem_use => use_RAM,
416 Mem_use => use_RAM,
417 nb_data_by_buffer_size => 32,
417 nb_data_by_buffer_size => 32,
418 nb_word_by_buffer_size => 30,
418 nb_word_by_buffer_size => 30,
419 nb_snapshot_param_size => 32,
419 nb_snapshot_param_size => 32,
420 delta_vector_size => 32,
420 delta_vector_size => 32,
421 delta_vector_size_f0_2 => 7, -- log2(96)
421 delta_vector_size_f0_2 => 7, -- log2(96)
422 pindex => 15,
422 pindex => 15,
423 paddr => 15,
423 paddr => 15,
424 pmask => 16#fff#,
424 pmask => 16#fff#,
425 pirq_ms => 6,
425 pirq_ms => 6,
426 pirq_wfp => 14,
426 pirq_wfp => 14,
427 hindex => 2,
427 hindex => 2,
428 top_lfr_version => X"000104") -- aa.bb.cc version
428 top_lfr_version => X"000105") -- aa.bb.cc version
429 PORT MAP (
429 PORT MAP (
430 clk => clk_25,
430 clk => clk_25,
431 rstn => reset,
431 rstn => reset,
432 sample_B => sample(2 DOWNTO 0),
432 sample_B => sample(2 DOWNTO 0),
433 sample_E => sample(7 DOWNTO 3),
433 sample_E => sample(7 DOWNTO 3),
434 sample_val => sample_val,
434 sample_val => sample_val,
435 apbi => apbi_ext,
435 apbi => apbi_ext,
436 apbo => apbo_ext(15),
436 apbo => apbo_ext(15),
437 ahbi => ahbi_m_ext,
437 ahbi => ahbi_m_ext,
438 ahbo => ahbo_m_ext(2),
438 ahbo => ahbo_m_ext(2),
439 coarse_time => coarse_time,
439 coarse_time => coarse_time,
440 fine_time => fine_time,
440 fine_time => fine_time,
441 data_shaping_BW => bias_fail_sw_sig,
441 data_shaping_BW => bias_fail_sw_sig,
442 observation_reg => observation_reg);
442 observation_reg => observation_reg);
443
443
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
445 GENERIC MAP(
445 GENERIC MAP(
446 ChannelCount => 8,
446 ChannelCount => 8,
447 SampleNbBits => 14,
447 SampleNbBits => 14,
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
450 PORT MAP (
450 PORT MAP (
451 -- CONV
451 -- CONV
452 cnv_clk => clk_24,
452 cnv_clk => clk_24,
453 cnv_rstn => reset,
453 cnv_rstn => reset,
454 cnv => ADC_nCS_sig,
454 cnv => ADC_nCS_sig,
455 -- DATA
455 -- DATA
456 clk => clk_25,
456 clk => clk_25,
457 rstn => reset,
457 rstn => reset,
458 sck => ADC_CLK_sig,
458 sck => ADC_CLK_sig,
459 sdo => ADC_SDO_sig,
459 sdo => ADC_SDO_sig,
460 -- SAMPLE
460 -- SAMPLE
461 sample => sample,
461 sample => sample,
462 sample_val => sample_val);
462 sample_val => sample_val);
463
463
464 --IO10 <= ADC_SDO_sig(5);
464 --IO10 <= ADC_SDO_sig(5);
465 --IO9 <= ADC_SDO_sig(4);
465 --IO9 <= ADC_SDO_sig(4);
466 --IO8 <= ADC_SDO_sig(3);
466 --IO8 <= ADC_SDO_sig(3);
467
467
468 ADC_nCS <= ADC_nCS_sig;
468 ADC_nCS <= ADC_nCS_sig;
469 ADC_CLK <= ADC_CLK_sig;
469 ADC_CLK <= ADC_CLK_sig;
470 ADC_SDO_sig <= ADC_SDO;
470 ADC_SDO_sig <= ADC_SDO;
471
471
472 ----------------------------------------------------------------------
472 ----------------------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
474 ----------------------------------------------------------------------
474 ----------------------------------------------------------------------
475
475
476 grgpio0 : grgpio
476 grgpio0 : grgpio
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
479
479
480 --pio_pad_0 : iopad
480 --pio_pad_0 : iopad
481 -- GENERIC MAP (tech => CFG_PADTECH)
481 -- GENERIC MAP (tech => CFG_PADTECH)
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
483 --pio_pad_1 : iopad
483 --pio_pad_1 : iopad
484 -- GENERIC MAP (tech => CFG_PADTECH)
484 -- GENERIC MAP (tech => CFG_PADTECH)
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
486 --pio_pad_2 : iopad
486 --pio_pad_2 : iopad
487 -- GENERIC MAP (tech => CFG_PADTECH)
487 -- GENERIC MAP (tech => CFG_PADTECH)
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
489 --pio_pad_3 : iopad
489 --pio_pad_3 : iopad
490 -- GENERIC MAP (tech => CFG_PADTECH)
490 -- GENERIC MAP (tech => CFG_PADTECH)
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
492 --pio_pad_4 : iopad
492 --pio_pad_4 : iopad
493 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- GENERIC MAP (tech => CFG_PADTECH)
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
495 --pio_pad_5 : iopad
495 --pio_pad_5 : iopad
496 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- GENERIC MAP (tech => CFG_PADTECH)
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
498 --pio_pad_6 : iopad
498 --pio_pad_6 : iopad
499 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- GENERIC MAP (tech => CFG_PADTECH)
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
501 --pio_pad_7 : iopad
501 --pio_pad_7 : iopad
502 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- GENERIC MAP (tech => CFG_PADTECH)
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
504
504
505 PROCESS (clk_25, reset)
505 PROCESS (clk_25, reset)
506 BEGIN -- PROCESS
506 BEGIN -- PROCESS
507 IF reset = '0' THEN -- asynchronous reset (active low)
507 IF reset = '0' THEN -- asynchronous reset (active low)
508 IO0 <= '0';
508 IO0 <= '0';
509 IO1 <= '0';
509 IO1 <= '0';
510 IO2 <= '0';
510 IO2 <= '0';
511 IO3 <= '0';
511 IO3 <= '0';
512 IO4 <= '0';
512 IO4 <= '0';
513 IO5 <= '0';
513 IO5 <= '0';
514 IO6 <= '0';
514 IO6 <= '0';
515 IO7 <= '0';
515 IO7 <= '0';
516 IO8 <= '0';
516 IO8 <= '0';
517 IO9 <= '0';
517 IO9 <= '0';
518 IO10 <= '0';
518 IO10 <= '0';
519 IO11 <= '0';
519 IO11 <= '0';
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 CASE gpioo.dout(1 DOWNTO 0) IS
521 CASE gpioo.dout(1 DOWNTO 0) IS
522 WHEN "00" =>
522 WHEN "00" =>
523 IO0 <= observation_reg(0 );
523 IO0 <= observation_reg(0 );
524 IO1 <= observation_reg(1 );
524 IO1 <= observation_reg(1 );
525 IO2 <= observation_reg(2 );
525 IO2 <= observation_reg(2 );
526 IO3 <= observation_reg(3 );
526 IO3 <= observation_reg(3 );
527 IO4 <= observation_reg(4 );
527 IO4 <= observation_reg(4 );
528 IO5 <= observation_reg(5 );
528 IO5 <= observation_reg(5 );
529 IO6 <= observation_reg(6 );
529 IO6 <= observation_reg(6 );
530 IO7 <= observation_reg(7 );
530 IO7 <= observation_reg(7 );
531 IO8 <= observation_reg(8 );
531 IO8 <= observation_reg(8 );
532 IO9 <= observation_reg(9 );
532 IO9 <= observation_reg(9 );
533 IO10 <= observation_reg(10);
533 IO10 <= observation_reg(10);
534 IO11 <= observation_reg(11);
534 IO11 <= observation_reg(11);
535 WHEN "01" =>
535 WHEN "01" =>
536 IO0 <= observation_reg(0 + 12);
536 IO0 <= observation_reg(0 + 12);
537 IO1 <= observation_reg(1 + 12);
537 IO1 <= observation_reg(1 + 12);
538 IO2 <= observation_reg(2 + 12);
538 IO2 <= observation_reg(2 + 12);
539 IO3 <= observation_reg(3 + 12);
539 IO3 <= observation_reg(3 + 12);
540 IO4 <= observation_reg(4 + 12);
540 IO4 <= observation_reg(4 + 12);
541 IO5 <= observation_reg(5 + 12);
541 IO5 <= observation_reg(5 + 12);
542 IO6 <= observation_reg(6 + 12);
542 IO6 <= observation_reg(6 + 12);
543 IO7 <= observation_reg(7 + 12);
543 IO7 <= observation_reg(7 + 12);
544 IO8 <= observation_reg(8 + 12);
544 IO8 <= observation_reg(8 + 12);
545 IO9 <= observation_reg(9 + 12);
545 IO9 <= observation_reg(9 + 12);
546 IO10 <= observation_reg(10 + 12);
546 IO10 <= observation_reg(10 + 12);
547 IO11 <= observation_reg(11 + 12);
547 IO11 <= observation_reg(11 + 12);
548 WHEN "10" =>
548 WHEN "10" =>
549 IO0 <= observation_reg(0 + 12 + 12);
549 IO0 <= observation_reg(0 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
557 IO8 <= '0';
557 IO8 <= '0';
558 IO9 <= '0';
558 IO9 <= '0';
559 IO10 <= '0';
559 IO10 <= '0';
560 IO11 <= '0';
560 IO11 <= '0';
561 WHEN "11" =>
561 WHEN "11" =>
562 IO0 <= '0';
562 IO0 <= '0';
563 IO1 <= '0';
563 IO1 <= '0';
564 IO2 <= '0';
564 IO2 <= '0';
565 IO3 <= '0';
565 IO3 <= '0';
566 IO4 <= '0';
566 IO4 <= '0';
567 IO5 <= '0';
567 IO5 <= '0';
568 IO6 <= '0';
568 IO6 <= '0';
569 IO7 <= '0';
569 IO7 <= '0';
570 IO8 <= '0';
570 IO8 <= '0';
571 IO9 <= '0';
571 IO9 <= '0';
572 IO10 <= '0';
572 IO10 <= '0';
573 IO11 <= '0';
573 IO11 <= '0';
574 WHEN OTHERS => NULL;
574 WHEN OTHERS => NULL;
575 END CASE;
575 END CASE;
576
576
577 END IF;
577 END IF;
578 END PROCESS;
578 END PROCESS;
579
579
580 END beh;
580 END beh;
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@@ -1,95 +1,100
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library lpp;
25 library lpp;
26 use lpp.lpp_fft.all;
26 use lpp.lpp_fft.all;
27 use lpp.fft_components.all;
27 use lpp.fft_components.all;
28
28
29 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "crοΏ½neau"
29 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "crοΏ½neau"
30
30
31 entity FFT is
31 entity FFT is
32 generic(
32 generic(
33 Data_sz : integer := 16;
33 Data_sz : integer := 16;
34 NbData : integer := 256);
34 NbData : integer := 256);
35 port(
35 port(
36 clkm : in std_logic;
36 clkm : in std_logic;
37 rstn : in std_logic;
37 rstn : in std_logic;
38 FifoIN_Empty : in std_logic_vector(4 downto 0);
38 FifoIN_Empty : in std_logic_vector(4 downto 0);
39 FifoIN_Data : in std_logic_vector(79 downto 0);
39 FifoIN_Data : in std_logic_vector(79 downto 0);
40 FifoOUT_Full : in std_logic_vector(4 downto 0);
40 FifoOUT_Full : in std_logic_vector(4 downto 0);
41 Load : out std_logic;
41 Load : out std_logic;
42 Read : out std_logic_vector(4 downto 0);
42 Read : out std_logic_vector(4 downto 0);
43 Write : out std_logic_vector(4 downto 0);
43 Write : out std_logic_vector(4 downto 0);
44 ReUse : out std_logic_vector(4 downto 0);
44 ReUse : out std_logic_vector(4 downto 0);
45 Data : out std_logic_vector(79 downto 0)
45 Data : out std_logic_vector(79 downto 0)
46 );
46 );
47 end entity;
47 end entity;
48
48
49
49
50 architecture ar_FFT of FFT is
50 architecture ar_FFT of FFT is
51
51
52 signal Drive_Write : std_logic;
52 signal Drive_Write : std_logic;
53 signal Drive_DataRE : std_logic_vector(15 downto 0);
53 signal Drive_DataRE : std_logic_vector(15 downto 0);
54 signal Drive_DataIM : std_logic_vector(15 downto 0);
54 signal Drive_DataIM : std_logic_vector(15 downto 0);
55
55
56 signal Start : std_logic;
56 signal Start : std_logic;
57 signal FFT_Load : std_logic;
57 signal FFT_Load : std_logic;
58 signal FFT_Ready : std_logic;
58 signal FFT_Ready : std_logic;
59 signal FFT_Valid : std_logic;
59 signal FFT_Valid : std_logic;
60 signal FFT_DataRE : std_logic_vector(15 downto 0);
60 signal FFT_DataRE : std_logic_vector(15 downto 0);
61 signal FFT_DataIM : std_logic_vector(15 downto 0);
61 signal FFT_DataIM : std_logic_vector(15 downto 0);
62
62
63 signal Link_Read : std_logic;
63 signal Link_Read : std_logic;
64
64
65 begin
65 begin
66
66
67 Start <= '0';
67 Start <= '0';
68 Load <= FFT_Load;
68 Load <= FFT_Load;
69
69
70 DRIVE : Driver_FFT
70 DRIVE : Driver_FFT
71 generic map(Data_sz,NbData)
71 generic map(Data_sz,NbData)
72 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
72 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
73
73
74 FFT0 : CoreFFT
74 FFT0 : CoreFFT
75 generic map(
75 generic map(
76 LOGPTS => gLOGPTS,
76 LOGPTS => gLOGPTS,
77 LOGLOGPTS => gLOGLOGPTS,
77 LOGLOGPTS => gLOGLOGPTS,
78 WSIZE => gWSIZE,
78 WSIZE => gWSIZE,
79 TWIDTH => gTWIDTH,
79 TWIDTH => gTWIDTH,
80 DWIDTH => gDWIDTH,
80 DWIDTH => gDWIDTH,
81 TDWIDTH => gTDWIDTH,
81 TDWIDTH => gTDWIDTH,
82 RND_MODE => gRND_MODE,
82 RND_MODE => gRND_MODE,
83 SCALE_MODE => gSCALE_MODE,
83 SCALE_MODE => gSCALE_MODE,
84 PTS => gPTS,
84 PTS => gPTS,
85 HALFPTS => gHALFPTS,
85 HALFPTS => gHALFPTS,
86 inBuf_RWDLY => gInBuf_RWDLY)
86 inBuf_RWDLY => gInBuf_RWDLY)
87 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
87 port map(clkm,start,rstn,
88 Drive_Write,Link_Read,
89 Drive_DataIM,Drive_DataRE,
90 FFT_Load,open,
91 FFT_DataIM,FFT_DataRE,
92 FFT_Valid,FFT_Ready);
88
93
89
94
90 LINK : Linker_FFT
95 LINK : Linker_FFT
91 generic map(Data_sz,NbData)
96 generic map(Data_sz,NbData)
92 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
97 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
93
98
94
99
95 end architecture; No newline at end of file
100 end architecture;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_lfr_apbreg IS
37 ENTITY lpp_lfr_apbreg IS
38 GENERIC (
38 GENERIC (
39 nb_data_by_buffer_size : INTEGER := 11;
39 nb_data_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
41 nb_snapshot_param_size : INTEGER := 11;
41 nb_snapshot_param_size : INTEGER := 11;
42 delta_vector_size : INTEGER := 20;
42 delta_vector_size : INTEGER := 20;
43 delta_vector_size_f0_2 : INTEGER := 3;
43 delta_vector_size_f0_2 : INTEGER := 3;
44
44
45 pindex : INTEGER := 4;
45 pindex : INTEGER := 4;
46 paddr : INTEGER := 4;
46 paddr : INTEGER := 4;
47 pmask : INTEGER := 16#fff#;
47 pmask : INTEGER := 16#fff#;
48 pirq_ms : INTEGER := 0;
48 pirq_ms : INTEGER := 0;
49 pirq_wfp : INTEGER := 1;
49 pirq_wfp : INTEGER := 1;
50 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
50 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
51 PORT (
51 PORT (
52 -- AMBA AHB system signals
52 -- AMBA AHB system signals
53 HCLK : IN STD_ULOGIC;
53 HCLK : IN STD_ULOGIC;
54 HRESETn : IN STD_ULOGIC;
54 HRESETn : IN STD_ULOGIC;
55
55
56 -- AMBA APB Slave Interface
56 -- AMBA APB Slave Interface
57 apbi : IN apb_slv_in_type;
57 apbi : IN apb_slv_in_type;
58 apbo : OUT apb_slv_out_type;
58 apbo : OUT apb_slv_out_type;
59
59
60 ---------------------------------------------------------------------------
60 ---------------------------------------------------------------------------
61 -- Spectral Matrix Reg
61 -- Spectral Matrix Reg
62 run_ms : OUT STD_LOGIC;
62 run_ms : OUT STD_LOGIC;
63 -- IN
63 -- IN
64 ready_matrix_f0_0 : IN STD_LOGIC;
64 ready_matrix_f0_0 : IN STD_LOGIC;
65 ready_matrix_f0_1 : IN STD_LOGIC;
65 ready_matrix_f0_1 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
68 error_anticipating_empty_fifo : IN STD_LOGIC;
68 error_anticipating_empty_fifo : IN STD_LOGIC;
69 error_bad_component_error : IN STD_LOGIC;
69 error_bad_component_error : IN STD_LOGIC;
70 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71
71
72 -- OUT
72 -- OUT
73 status_ready_matrix_f0_0 : OUT STD_LOGIC;
73 status_ready_matrix_f0_0 : OUT STD_LOGIC;
74 status_ready_matrix_f0_1 : OUT STD_LOGIC;
74 status_ready_matrix_f0_1 : OUT STD_LOGIC;
75 status_ready_matrix_f1 : OUT STD_LOGIC;
75 status_ready_matrix_f1 : OUT STD_LOGIC;
76 status_ready_matrix_f2 : OUT STD_LOGIC;
76 status_ready_matrix_f2 : OUT STD_LOGIC;
77 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
77 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
78 status_error_bad_component_error : OUT STD_LOGIC;
78 status_error_bad_component_error : OUT STD_LOGIC;
79
79
80 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 config_active_interruption_onError : OUT STD_LOGIC;
81 config_active_interruption_onError : OUT STD_LOGIC;
82
82
83 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87
87
88 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
90 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
90 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
91 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
91 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92
92
93 ---------------------------------------------------------------------------
93 ---------------------------------------------------------------------------
94 ---------------------------------------------------------------------------
94 ---------------------------------------------------------------------------
95 -- WaveForm picker Reg
95 -- WaveForm picker Reg
96 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
96 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
97 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
97 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
98 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
98 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
99 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
99 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100
100
101 -- OUT
101 -- OUT
102 data_shaping_BW : OUT STD_LOGIC;
102 data_shaping_BW : OUT STD_LOGIC;
103 data_shaping_SP0 : OUT STD_LOGIC;
103 data_shaping_SP0 : OUT STD_LOGIC;
104 data_shaping_SP1 : OUT STD_LOGIC;
104 data_shaping_SP1 : OUT STD_LOGIC;
105 data_shaping_R0 : OUT STD_LOGIC;
105 data_shaping_R0 : OUT STD_LOGIC;
106 data_shaping_R1 : OUT STD_LOGIC;
106 data_shaping_R1 : OUT STD_LOGIC;
107
107
108 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
108 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
109 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
109 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
110 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
110 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
111 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
113 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
114 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
114 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
115 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
115 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
116
116
117 enable_f0 : OUT STD_LOGIC;
117 enable_f0 : OUT STD_LOGIC;
118 enable_f1 : OUT STD_LOGIC;
118 enable_f1 : OUT STD_LOGIC;
119 enable_f2 : OUT STD_LOGIC;
119 enable_f2 : OUT STD_LOGIC;
120 enable_f3 : OUT STD_LOGIC;
120 enable_f3 : OUT STD_LOGIC;
121
121
122 burst_f0 : OUT STD_LOGIC;
122 burst_f0 : OUT STD_LOGIC;
123 burst_f1 : OUT STD_LOGIC;
123 burst_f1 : OUT STD_LOGIC;
124 burst_f2 : OUT STD_LOGIC;
124 burst_f2 : OUT STD_LOGIC;
125
125
126 run : OUT STD_LOGIC;
126 run : OUT STD_LOGIC;
127
127
128 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
131 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
131 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
132 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
133 ---------------------------------------------------------------------------
133 ---------------------------------------------------------------------------
134 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
141 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
141 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
142
142
143 ---------------------------------------------------------------------------
143 ---------------------------------------------------------------------------
144 );
144 );
145
145
146 END lpp_lfr_apbreg;
146 END lpp_lfr_apbreg;
147
147
148 ARCHITECTURE beh OF lpp_lfr_apbreg IS
148 ARCHITECTURE beh OF lpp_lfr_apbreg IS
149
149
150 CONSTANT REVISION : INTEGER := 1;
150 CONSTANT REVISION : INTEGER := 1;
151
151
152 CONSTANT pconfig : apb_config_type := (
152 CONSTANT pconfig : apb_config_type := (
153 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
153 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
154 1 => apb_iobar(paddr, pmask));
154 1 => apb_iobar(paddr, pmask));
155
155
156 TYPE lpp_SpectralMatrix_regs IS RECORD
156 TYPE lpp_SpectralMatrix_regs IS RECORD
157 config_active_interruption_onNewMatrix : STD_LOGIC;
157 config_active_interruption_onNewMatrix : STD_LOGIC;
158 config_active_interruption_onError : STD_LOGIC;
158 config_active_interruption_onError : STD_LOGIC;
159 config_ms_run : STD_LOGIC;
159 config_ms_run : STD_LOGIC;
160 status_ready_matrix_f0_0 : STD_LOGIC;
160 status_ready_matrix_f0_0 : STD_LOGIC;
161 status_ready_matrix_f0_1 : STD_LOGIC;
161 status_ready_matrix_f0_1 : STD_LOGIC;
162 status_ready_matrix_f1 : STD_LOGIC;
162 status_ready_matrix_f1 : STD_LOGIC;
163 status_ready_matrix_f2 : STD_LOGIC;
163 status_ready_matrix_f2 : STD_LOGIC;
164 status_error_anticipating_empty_fifo : STD_LOGIC;
164 status_error_anticipating_empty_fifo : STD_LOGIC;
165 status_error_bad_component_error : STD_LOGIC;
165 status_error_bad_component_error : STD_LOGIC;
166 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170
170
171 coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175
175
176 -- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
176 -- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
177 -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
177 -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
178 -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
178 -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
179 -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
179 -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
180 END RECORD;
180 END RECORD;
181 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
181 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
182
182
183 TYPE lpp_WaveformPicker_regs IS RECORD
183 TYPE lpp_WaveformPicker_regs IS RECORD
184 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
184 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 data_shaping_BW : STD_LOGIC;
187 data_shaping_BW : STD_LOGIC;
188 data_shaping_SP0 : STD_LOGIC;
188 data_shaping_SP0 : STD_LOGIC;
189 data_shaping_SP1 : STD_LOGIC;
189 data_shaping_SP1 : STD_LOGIC;
190 data_shaping_R0 : STD_LOGIC;
190 data_shaping_R0 : STD_LOGIC;
191 data_shaping_R1 : STD_LOGIC;
191 data_shaping_R1 : STD_LOGIC;
192 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
192 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
193 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
193 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
194 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
194 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
195 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
195 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
196 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
196 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
197 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
197 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
198 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
198 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
199 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
199 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
200 enable_f0 : STD_LOGIC;
200 enable_f0 : STD_LOGIC;
201 enable_f1 : STD_LOGIC;
201 enable_f1 : STD_LOGIC;
202 enable_f2 : STD_LOGIC;
202 enable_f2 : STD_LOGIC;
203 enable_f3 : STD_LOGIC;
203 enable_f3 : STD_LOGIC;
204 burst_f0 : STD_LOGIC;
204 burst_f0 : STD_LOGIC;
205 burst_f1 : STD_LOGIC;
205 burst_f1 : STD_LOGIC;
206 burst_f2 : STD_LOGIC;
206 burst_f2 : STD_LOGIC;
207 run : STD_LOGIC;
207 run : STD_LOGIC;
208 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
212 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
213 END RECORD;
213 END RECORD;
214 SIGNAL reg_wp : lpp_WaveformPicker_regs;
214 SIGNAL reg_wp : lpp_WaveformPicker_regs;
215
215
216 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
217
217
218 -----------------------------------------------------------------------------
218 -----------------------------------------------------------------------------
219 -- IRQ
219 -- IRQ
220 -----------------------------------------------------------------------------
220 -----------------------------------------------------------------------------
221 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
221 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
222 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
222 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
223 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
223 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
224 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
224 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
225 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
225 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
226 SIGNAL ored_irq_wfp : STD_LOGIC;
226 SIGNAL ored_irq_wfp : STD_LOGIC;
227
227
228 BEGIN -- beh
228 BEGIN -- beh
229
229
230 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
230 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
231 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
231 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
232 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
232 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
233 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
233 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
234 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
234 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
235 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
235 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
236
236
237 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
237 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
238 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
238 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
239 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
239 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
240 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
240 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
241 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
241 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
242 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
242 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
243
243
244
244
245 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
245 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
246 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
246 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
247 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
247 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
248 data_shaping_R0 <= reg_wp.data_shaping_R0;
248 data_shaping_R0 <= reg_wp.data_shaping_R0;
249 data_shaping_R1 <= reg_wp.data_shaping_R1;
249 data_shaping_R1 <= reg_wp.data_shaping_R1;
250
250
251 delta_snapshot <= reg_wp.delta_snapshot;
251 delta_snapshot <= reg_wp.delta_snapshot;
252 delta_f0 <= reg_wp.delta_f0;
252 delta_f0 <= reg_wp.delta_f0;
253 delta_f0_2 <= reg_wp.delta_f0_2;
253 delta_f0_2 <= reg_wp.delta_f0_2;
254 delta_f1 <= reg_wp.delta_f1;
254 delta_f1 <= reg_wp.delta_f1;
255 delta_f2 <= reg_wp.delta_f2;
255 delta_f2 <= reg_wp.delta_f2;
256 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
256 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
257 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
257 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
258 nb_snapshot_param <= reg_wp.nb_snapshot_param;
258 nb_snapshot_param <= reg_wp.nb_snapshot_param;
259
259
260 enable_f0 <= reg_wp.enable_f0;
260 enable_f0 <= reg_wp.enable_f0;
261 enable_f1 <= reg_wp.enable_f1;
261 enable_f1 <= reg_wp.enable_f1;
262 enable_f2 <= reg_wp.enable_f2;
262 enable_f2 <= reg_wp.enable_f2;
263 enable_f3 <= reg_wp.enable_f3;
263 enable_f3 <= reg_wp.enable_f3;
264
264
265 burst_f0 <= reg_wp.burst_f0;
265 burst_f0 <= reg_wp.burst_f0;
266 burst_f1 <= reg_wp.burst_f1;
266 burst_f1 <= reg_wp.burst_f1;
267 burst_f2 <= reg_wp.burst_f2;
267 burst_f2 <= reg_wp.burst_f2;
268
268
269 run <= reg_wp.run;
269 run <= reg_wp.run;
270
270
271 addr_data_f0 <= reg_wp.addr_data_f0;
271 addr_data_f0 <= reg_wp.addr_data_f0;
272 addr_data_f1 <= reg_wp.addr_data_f1;
272 addr_data_f1 <= reg_wp.addr_data_f1;
273 addr_data_f2 <= reg_wp.addr_data_f2;
273 addr_data_f2 <= reg_wp.addr_data_f2;
274 addr_data_f3 <= reg_wp.addr_data_f3;
274 addr_data_f3 <= reg_wp.addr_data_f3;
275
275
276 start_date <= reg_wp.start_date;
276 start_date <= reg_wp.start_date;
277
277
278 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
278 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
279 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
279 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
280 BEGIN -- PROCESS lpp_dma_top
280 BEGIN -- PROCESS lpp_dma_top
281 IF HRESETn = '0' THEN -- asynchronous reset (active low)
281 IF HRESETn = '0' THEN -- asynchronous reset (active low)
282 reg_sp.config_active_interruption_onNewMatrix <= '0';
282 reg_sp.config_active_interruption_onNewMatrix <= '0';
283 reg_sp.config_active_interruption_onError <= '0';
283 reg_sp.config_active_interruption_onError <= '0';
284 reg_sp.config_ms_run <= '1';
284 reg_sp.config_ms_run <= '1';
285 reg_sp.status_ready_matrix_f0_0 <= '0';
285 reg_sp.status_ready_matrix_f0_0 <= '0';
286 reg_sp.status_ready_matrix_f0_1 <= '0';
286 reg_sp.status_ready_matrix_f0_1 <= '0';
287 reg_sp.status_ready_matrix_f1 <= '0';
287 reg_sp.status_ready_matrix_f1 <= '0';
288 reg_sp.status_ready_matrix_f2 <= '0';
288 reg_sp.status_ready_matrix_f2 <= '0';
289 reg_sp.status_error_anticipating_empty_fifo <= '0';
289 reg_sp.status_error_anticipating_empty_fifo <= '0';
290 reg_sp.status_error_bad_component_error <= '0';
290 reg_sp.status_error_bad_component_error <= '0';
291 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
291 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
292 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
292 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
293 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
293 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
294 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
294 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
295
295
296 reg_sp.coarse_time_f0_0 <= (OTHERS => '0');
296 reg_sp.coarse_time_f0_0 <= (OTHERS => '0');
297 reg_sp.coarse_time_f0_1 <= (OTHERS => '0');
297 reg_sp.coarse_time_f0_1 <= (OTHERS => '0');
298 reg_sp.coarse_time_f1 <= (OTHERS => '0');
298 reg_sp.coarse_time_f1 <= (OTHERS => '0');
299 reg_sp.coarse_time_f2 <= (OTHERS => '0');
299 reg_sp.coarse_time_f2 <= (OTHERS => '0');
300 --reg_sp.fine_time_f0_0 <= (OTHERS => '0');
300 --reg_sp.fine_time_f0_0 <= (OTHERS => '0');
301 --reg_sp.fine_time_f0_1 <= (OTHERS => '0');
301 --reg_sp.fine_time_f0_1 <= (OTHERS => '0');
302 --reg_sp.fine_time_f1 <= (OTHERS => '0');
302 --reg_sp.fine_time_f1 <= (OTHERS => '0');
303 --reg_sp.fine_time_f2 <= (OTHERS => '0');
303 --reg_sp.fine_time_f2 <= (OTHERS => '0');
304
304
305 prdata <= (OTHERS => '0');
305 prdata <= (OTHERS => '0');
306
306
307 apbo.pirq <= (OTHERS => '0');
307 apbo.pirq <= (OTHERS => '0');
308
308
309 status_full_ack <= (OTHERS => '0');
309 status_full_ack <= (OTHERS => '0');
310
310
311 reg_wp.data_shaping_BW <= '0';
311 reg_wp.data_shaping_BW <= '0';
312 reg_wp.data_shaping_SP0 <= '0';
312 reg_wp.data_shaping_SP0 <= '0';
313 reg_wp.data_shaping_SP1 <= '0';
313 reg_wp.data_shaping_SP1 <= '0';
314 reg_wp.data_shaping_R0 <= '0';
314 reg_wp.data_shaping_R0 <= '0';
315 reg_wp.data_shaping_R1 <= '0';
315 reg_wp.data_shaping_R1 <= '0';
316 reg_wp.enable_f0 <= '0';
316 reg_wp.enable_f0 <= '0';
317 reg_wp.enable_f1 <= '0';
317 reg_wp.enable_f1 <= '0';
318 reg_wp.enable_f2 <= '0';
318 reg_wp.enable_f2 <= '0';
319 reg_wp.enable_f3 <= '0';
319 reg_wp.enable_f3 <= '0';
320 reg_wp.burst_f0 <= '0';
320 reg_wp.burst_f0 <= '0';
321 reg_wp.burst_f1 <= '0';
321 reg_wp.burst_f1 <= '0';
322 reg_wp.burst_f2 <= '0';
322 reg_wp.burst_f2 <= '0';
323 reg_wp.run <= '0';
323 reg_wp.run <= '0';
324 reg_wp.addr_data_f0 <= (OTHERS => '0');
324 reg_wp.addr_data_f0 <= (OTHERS => '0');
325 reg_wp.addr_data_f1 <= (OTHERS => '0');
325 reg_wp.addr_data_f1 <= (OTHERS => '0');
326 reg_wp.addr_data_f2 <= (OTHERS => '0');
326 reg_wp.addr_data_f2 <= (OTHERS => '0');
327 reg_wp.addr_data_f3 <= (OTHERS => '0');
327 reg_wp.addr_data_f3 <= (OTHERS => '0');
328 reg_wp.status_full <= (OTHERS => '0');
328 reg_wp.status_full <= (OTHERS => '0');
329 reg_wp.status_full_err <= (OTHERS => '0');
329 reg_wp.status_full_err <= (OTHERS => '0');
330 reg_wp.status_new_err <= (OTHERS => '0');
330 reg_wp.status_new_err <= (OTHERS => '0');
331 reg_wp.delta_snapshot <= (OTHERS => '0');
331 reg_wp.delta_snapshot <= (OTHERS => '0');
332 reg_wp.delta_f0 <= (OTHERS => '0');
332 reg_wp.delta_f0 <= (OTHERS => '0');
333 reg_wp.delta_f0_2 <= (OTHERS => '0');
333 reg_wp.delta_f0_2 <= (OTHERS => '0');
334 reg_wp.delta_f1 <= (OTHERS => '0');
334 reg_wp.delta_f1 <= (OTHERS => '0');
335 reg_wp.delta_f2 <= (OTHERS => '0');
335 reg_wp.delta_f2 <= (OTHERS => '0');
336 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
336 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
337 reg_wp.nb_snapshot_param <= (OTHERS => '0');
337 reg_wp.nb_snapshot_param <= (OTHERS => '0');
338 reg_wp.start_date <= (OTHERS => '0');
338 reg_wp.start_date <= (OTHERS => '0');
339
339
340 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
340 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
341
341
342 reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0);
342 reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0);
343 reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0);
343 reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0);
344 reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0);
344 reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0);
345 reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0);
345 reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0);
346
346
347 --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0);
347 --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0);
348 --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0);
348 --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0);
349 --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0);
349 --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0);
350 --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0);
350 --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0);
351
351
352 status_full_ack <= (OTHERS => '0');
352 status_full_ack <= (OTHERS => '0');
353
353
354 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
354 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
355 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
355 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
356 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
356 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
357 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
357 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
358
358
359 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
359 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
360 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
360 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
361 all_status: FOR I IN 3 DOWNTO 0 LOOP
361 all_status: FOR I IN 3 DOWNTO 0 LOOP
362 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
362 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
363 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
363 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
364 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
364 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
365 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
365 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
366 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
366 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
367 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
367 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
368 END LOOP all_status;
368 END LOOP all_status;
369
369
370 paddr := "000000";
370 paddr := "000000";
371 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
371 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
372 prdata <= (OTHERS => '0');
372 prdata <= (OTHERS => '0');
373 IF apbi.psel(pindex) = '1' THEN
373 IF apbi.psel(pindex) = '1' THEN
374 -- APB DMA READ --
374 -- APB DMA READ --
375 CASE paddr(7 DOWNTO 2) IS
375 CASE paddr(7 DOWNTO 2) IS
376 --
376 --
377 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
377 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
378 prdata(1) <= reg_sp.config_active_interruption_onError;
378 prdata(1) <= reg_sp.config_active_interruption_onError;
379 prdata(2) <= reg_sp.config_ms_run;
379 prdata(2) <= reg_sp.config_ms_run;
380 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
380 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
381 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
381 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
382 prdata(2) <= reg_sp.status_ready_matrix_f1;
382 prdata(2) <= reg_sp.status_ready_matrix_f1;
383 prdata(3) <= reg_sp.status_ready_matrix_f2;
383 prdata(3) <= reg_sp.status_ready_matrix_f2;
384 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
384 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
385 prdata(5) <= reg_sp.status_error_bad_component_error;
385 prdata(5) <= reg_sp.status_error_bad_component_error;
386 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
386 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
387 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
387 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
388 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
388 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
389 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
389 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
390
390
391 WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0;
391 WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0;
392 WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1;
392 WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1;
393 WHEN "001000" => prdata <= reg_sp.coarse_time_f1;
393 WHEN "001000" => prdata <= reg_sp.coarse_time_f1;
394 WHEN "001001" => prdata <= reg_sp.coarse_time_f2;
394 WHEN "001001" => prdata <= reg_sp.coarse_time_f2;
395 WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0;
395 WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0;
396 WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1;
396 WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1;
397 WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1;
397 WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1;
398 WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2;
398 WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2;
399
399
400 WHEN "001111" => prdata <= debug_reg;
400 WHEN "001111" => prdata <= debug_reg;
401 ---------------------------------------------------------------------
401 ---------------------------------------------------------------------
402 WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW;
402 WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW;
403 prdata(1) <= reg_wp.data_shaping_SP0;
403 prdata(1) <= reg_wp.data_shaping_SP0;
404 prdata(2) <= reg_wp.data_shaping_SP1;
404 prdata(2) <= reg_wp.data_shaping_SP1;
405 prdata(3) <= reg_wp.data_shaping_R0;
405 prdata(3) <= reg_wp.data_shaping_R0;
406 prdata(4) <= reg_wp.data_shaping_R1;
406 prdata(4) <= reg_wp.data_shaping_R1;
407 WHEN "010001" => prdata(0) <= reg_wp.enable_f0;
407 WHEN "010001" => prdata(0) <= reg_wp.enable_f0;
408 prdata(1) <= reg_wp.enable_f1;
408 prdata(1) <= reg_wp.enable_f1;
409 prdata(2) <= reg_wp.enable_f2;
409 prdata(2) <= reg_wp.enable_f2;
410 prdata(3) <= reg_wp.enable_f3;
410 prdata(3) <= reg_wp.enable_f3;
411 prdata(4) <= reg_wp.burst_f0;
411 prdata(4) <= reg_wp.burst_f0;
412 prdata(5) <= reg_wp.burst_f1;
412 prdata(5) <= reg_wp.burst_f1;
413 prdata(6) <= reg_wp.burst_f2;
413 prdata(6) <= reg_wp.burst_f2;
414 prdata(7) <= reg_wp.run;
414 prdata(7) <= reg_wp.run;
415 WHEN "010010" => prdata <= reg_wp.addr_data_f0;
415 WHEN "010010" => prdata <= reg_wp.addr_data_f0;
416 WHEN "010011" => prdata <= reg_wp.addr_data_f1;
416 WHEN "010011" => prdata <= reg_wp.addr_data_f1;
417 WHEN "010100" => prdata <= reg_wp.addr_data_f2;
417 WHEN "010100" => prdata <= reg_wp.addr_data_f2;
418 WHEN "010101" => prdata <= reg_wp.addr_data_f3;
418 WHEN "010101" => prdata <= reg_wp.addr_data_f3;
419 WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
419 WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
420 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
420 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
421 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
421 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
422 WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
422 WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
423 WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
423 WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
424 WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
424 WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
425 WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
425 WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
426 WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
426 WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
427 WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
427 WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
428 WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
428 WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
429 WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
429 WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
430 WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
430 WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
431 ----------------------------------------------------
431 ----------------------------------------------------
432 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
432 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
433 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
433 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
434 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
434 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
435 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
435 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
436 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
436 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
437 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
437 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
438 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
438 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
439 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
439 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
440 ----------------------------------------------------
440 ----------------------------------------------------
441 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
441 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
442 WHEN OTHERS => NULL;
442 WHEN OTHERS => NULL;
443
443
444 END CASE;
444 END CASE;
445 IF (apbi.pwrite AND apbi.penable) = '1' THEN
445 IF (apbi.pwrite AND apbi.penable) = '1' THEN
446 -- APB DMA WRITE --
446 -- APB DMA WRITE --
447 CASE paddr(7 DOWNTO 2) IS
447 CASE paddr(7 DOWNTO 2) IS
448 --
448 --
449 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
449 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
450 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
450 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
451 reg_sp.config_ms_run <= apbi.pwdata(2);
451 reg_sp.config_ms_run <= apbi.pwdata(2);
452 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
452 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
453 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
453 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
454 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
454 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
455 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
455 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
456 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
456 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
457 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
457 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
458 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
458 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
459 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
459 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
460 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
460 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
461 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
461 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
462 --
462 --
463 WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
463 WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
464 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
464 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
465 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
465 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
466 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
466 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
467 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
467 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
468 WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0);
468 WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0);
469 reg_wp.enable_f1 <= apbi.pwdata(1);
469 reg_wp.enable_f1 <= apbi.pwdata(1);
470 reg_wp.enable_f2 <= apbi.pwdata(2);
470 reg_wp.enable_f2 <= apbi.pwdata(2);
471 reg_wp.enable_f3 <= apbi.pwdata(3);
471 reg_wp.enable_f3 <= apbi.pwdata(3);
472 reg_wp.burst_f0 <= apbi.pwdata(4);
472 reg_wp.burst_f0 <= apbi.pwdata(4);
473 reg_wp.burst_f1 <= apbi.pwdata(5);
473 reg_wp.burst_f1 <= apbi.pwdata(5);
474 reg_wp.burst_f2 <= apbi.pwdata(6);
474 reg_wp.burst_f2 <= apbi.pwdata(6);
475 reg_wp.run <= apbi.pwdata(7);
475 reg_wp.run <= apbi.pwdata(7);
476 WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata;
476 WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata;
477 WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata;
477 WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata;
478 WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata;
478 WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata;
479 WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata;
479 WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata;
480 WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
480 WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
481 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
481 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
482 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
482 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
483 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
483 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
484 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
484 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
485 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
485 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
486 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
486 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
487 WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
487 WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
488 WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
488 WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
489 WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
489 WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
490 WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
490 WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
491 WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
491 WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
492 WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
492 WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
493 WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
493 WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
494 WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
494 WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
495 WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
495 WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
496 --
496 --
497 WHEN OTHERS => NULL;
497 WHEN OTHERS => NULL;
498 END CASE;
498 END CASE;
499 END IF;
499 END IF;
500 END IF;
500 END IF;
501
501
502 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
502 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
503 ready_matrix_f0_1 OR
503 ready_matrix_f0_1 OR
504 ready_matrix_f1 OR
504 ready_matrix_f1 OR
505 ready_matrix_f2)
505 ready_matrix_f2)
506 )
506 )
507 OR
507 OR
508 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
508 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
509 error_bad_component_error)
509 error_bad_component_error)
510 ));
510 ));
511
511
512 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
512 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
513
513
514 END IF;
514 END IF;
515 END PROCESS lpp_lfr_apbreg;
515 END PROCESS lpp_lfr_apbreg;
516
516
517 apbo.pindex <= pindex;
517 apbo.pindex <= pindex;
518 apbo.pconfig <= pconfig;
518 apbo.pconfig <= pconfig;
519 apbo.prdata <= prdata;
519 apbo.prdata <= prdata;
520
520
521 -----------------------------------------------------------------------------
521 -----------------------------------------------------------------------------
522 -- IRQ
522 -- IRQ
523 -----------------------------------------------------------------------------
523 -----------------------------------------------------------------------------
524 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
524 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
525
525
526 PROCESS (HCLK, HRESETn)
526 PROCESS (HCLK, HRESETn)
527 BEGIN -- PROCESS
527 BEGIN -- PROCESS
528 IF HRESETn = '0' THEN -- asynchronous reset (active low)
528 IF HRESETn = '0' THEN -- asynchronous reset (active low)
529 irq_wfp_reg <= (OTHERS => '0');
529 irq_wfp_reg <= (OTHERS => '0');
530 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
530 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
531 irq_wfp_reg <= irq_wfp_reg_s;
531 irq_wfp_reg <= irq_wfp_reg_s;
532 END IF;
532 END IF;
533 END PROCESS;
533 END PROCESS;
534
534
535 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
535 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
536 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
536 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
537 END GENERATE all_irq_wfp;
537 END GENERATE all_irq_wfp;
538
538
539 irq_wfp_ZERO <= (OTHERS => '0');
539 irq_wfp_ZERO <= (OTHERS => '0');
540 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
540 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
541
541
542 run_ms <= reg_sp.config_ms_run;
542 run_ms <= reg_sp.config_ms_run;
543
543
544 END beh;
544 END beh; No newline at end of file
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@@ -1,374 +1,394
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY lpp;
4 LIBRARY lpp;
5 USE lpp.lpp_amba.ALL;
5 USE lpp.lpp_amba.ALL;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 --USE lpp.lpp_uart.ALL;
7 --USE lpp.lpp_uart.ALL;
8 USE lpp.lpp_matrix.ALL;
8 USE lpp.lpp_matrix.ALL;
9 --USE lpp.lpp_delay.ALL;
9 --USE lpp.lpp_delay.ALL;
10 USE lpp.lpp_fft.ALL;
10 USE lpp.lpp_fft.ALL;
11 USE lpp.fft_components.ALL;
11 USE lpp.fft_components.ALL;
12 USE lpp.lpp_ad_conv.ALL;
12 USE lpp.lpp_ad_conv.ALL;
13 USE lpp.iir_filter.ALL;
13 USE lpp.iir_filter.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15 USE lpp.Filtercfg.ALL;
15 USE lpp.Filtercfg.ALL;
16 USE lpp.lpp_demux.ALL;
16 USE lpp.lpp_demux.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
19 USE lpp.lpp_Header.ALL;
19 USE lpp.lpp_Header.ALL;
20 USE lpp.lpp_lfr_pkg.ALL;
20 USE lpp.lpp_lfr_pkg.ALL;
21
21
22 LIBRARY grlib;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
25 USE grlib.devices.ALL;
26 USE GRLIB.DMA2AHB_Package.ALL;
26 USE GRLIB.DMA2AHB_Package.ALL;
27
27
28
28
29 ENTITY lpp_lfr_ms IS
29 ENTITY lpp_lfr_ms IS
30 GENERIC (
30 GENERIC (
31 Mem_use : INTEGER
31 Mem_use : INTEGER := use_RAM
32 );
32 );
33 PORT (
33 PORT (
34 clk : IN STD_LOGIC;
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36
36
37 ---------------------------------------------------------------------------
37 ---------------------------------------------------------------------------
38 -- DATA INPUT
38 -- DATA INPUT
39 ---------------------------------------------------------------------------
39 ---------------------------------------------------------------------------
40 -- TIME
40 -- TIME
41 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
41 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
42 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
42 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
43 --
43 --
44 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
45 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
45 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
46 --
46 --
47 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49 --
49 --
50 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
50 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
51 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
51 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
52
52
53 ---------------------------------------------------------------------------
53 ---------------------------------------------------------------------------
54 -- DMA
54 -- DMA
55 ---------------------------------------------------------------------------
55 ---------------------------------------------------------------------------
56 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
57 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
57 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
58 dma_valid : OUT STD_LOGIC;
58 dma_valid : OUT STD_LOGIC;
59 dma_valid_burst : OUT STD_LOGIC;
59 dma_valid_burst : OUT STD_LOGIC;
60 dma_ren : IN STD_LOGIC;
60 dma_ren : IN STD_LOGIC;
61 dma_done : IN STD_LOGIC;
61 dma_done : IN STD_LOGIC;
62
62
63 -- Reg out
63 -- Reg out
64 ready_matrix_f0_0 : OUT STD_LOGIC;
64 ready_matrix_f0_0 : OUT STD_LOGIC;
65 ready_matrix_f0_1 : OUT STD_LOGIC;
65 ready_matrix_f0_1 : OUT STD_LOGIC;
66 ready_matrix_f1 : OUT STD_LOGIC;
66 ready_matrix_f1 : OUT STD_LOGIC;
67 ready_matrix_f2 : OUT STD_LOGIC;
67 ready_matrix_f2 : OUT STD_LOGIC;
68 error_anticipating_empty_fifo : OUT STD_LOGIC;
68 error_anticipating_empty_fifo : OUT STD_LOGIC;
69 error_bad_component_error : OUT STD_LOGIC;
69 error_bad_component_error : OUT STD_LOGIC;
70 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
70 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
71
71
72 -- Reg In
72 -- Reg In
73 status_ready_matrix_f0_0 :IN STD_LOGIC;
73 status_ready_matrix_f0_0 :IN STD_LOGIC;
74 status_ready_matrix_f0_1 :IN STD_LOGIC;
74 status_ready_matrix_f0_1 :IN STD_LOGIC;
75 status_ready_matrix_f1 :IN STD_LOGIC;
75 status_ready_matrix_f1 :IN STD_LOGIC;
76 status_ready_matrix_f2 :IN STD_LOGIC;
76 status_ready_matrix_f2 :IN STD_LOGIC;
77 status_error_anticipating_empty_fifo :IN STD_LOGIC;
77 status_error_anticipating_empty_fifo :IN STD_LOGIC;
78 status_error_bad_component_error :IN STD_LOGIC;
78 status_error_bad_component_error :IN STD_LOGIC;
79
79
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
82 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86
86
87 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
87 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
90 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
90 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
91
91
92 );
92 );
93 END;
93 END;
94
94
95 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
95 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
96 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
97 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
100 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
101 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
101 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
102 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
102 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
103
103
104 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
105 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
105 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
106 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
107 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
108 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
108 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
109
109
110 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
111 SIGNAL FFT_Load : STD_LOGIC;
111 SIGNAL FFT_Load : STD_LOGIC;
112 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
112 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
113 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
113 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
115 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
115 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
116
116
117 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
118 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
119 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
120
120
121 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122 SIGNAL SM_FlagError : STD_LOGIC;
122 SIGNAL SM_FlagError : STD_LOGIC;
123 -- SIGNAL SM_Pong : STD_LOGIC;
123 -- SIGNAL SM_Pong : STD_LOGIC;
124 SIGNAL SM_Wen : STD_LOGIC;
124 SIGNAL SM_Wen : STD_LOGIC;
125 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
128 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
129 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
130
130
131 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
132 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
134 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
135
135
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
137 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
138 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL Head_Empty : STD_LOGIC;
139 SIGNAL Head_Empty : STD_LOGIC;
140 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 SIGNAL Head_Valid : STD_LOGIC;
141 SIGNAL Head_Valid : STD_LOGIC;
142 SIGNAL Head_Val : STD_LOGIC;
142 SIGNAL Head_Val : STD_LOGIC;
143
143
144 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
145 SIGNAL DMA_Read : STD_LOGIC;
145 SIGNAL DMA_Read : STD_LOGIC;
146 SIGNAL DMA_ack : STD_LOGIC;
146 SIGNAL DMA_ack : STD_LOGIC;
147
147
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
149 SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
150
150
151 BEGIN
151 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
152
152 SIGNAL dma_valid_s : STD_LOGIC;
153 -----------------------------------------------------------------------------
153 SIGNAL dma_valid_burst_s : STD_LOGIC;
154 Memf0: lppFIFOxN
154
155 GENERIC MAP (
155 BEGIN
156 tech => 0, Mem_use => Mem_use, Data_sz => 16,
156
157 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
157 -----------------------------------------------------------------------------
158 PORT MAP (
158 Memf0: lppFIFOxN
159 rstn => rstn, wclk => clk, rclk => clk,
159 GENERIC MAP (
160 ReUse => (OTHERS => '0'),
160 tech => 0, Mem_use => Mem_use, Data_sz => 16,
161 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
161 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
162 wdata => sample_f0_wdata, rdata => FifoF0_Data,
162 PORT MAP (
163 full => OPEN, empty => FifoF0_Empty);
163 rstn => rstn, wclk => clk, rclk => clk,
164
164 ReUse => (OTHERS => '0'),
165 Memf1: lppFIFOxN
165 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
166 GENERIC MAP (
166 wdata => sample_f0_wdata, rdata => FifoF0_Data,
167 tech => 0, Mem_use => Mem_use, Data_sz => 16,
167 full => OPEN, empty => FifoF0_Empty);
168 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
168
169 PORT MAP (
169 Memf1: lppFIFOxN
170 rstn => rstn, wclk => clk, rclk => clk,
170 GENERIC MAP (
171 ReUse => (OTHERS => '0'),
171 tech => 0, Mem_use => Mem_use, Data_sz => 16,
172 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
172 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
173 wdata => sample_f1_wdata, rdata => FifoF1_Data,
173 PORT MAP (
174 full => OPEN, empty => FifoF1_Empty);
174 rstn => rstn, wclk => clk, rclk => clk,
175
175 ReUse => (OTHERS => '0'),
176
176 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
177 Memf2: lppFIFOxN
177 wdata => sample_f1_wdata, rdata => FifoF1_Data,
178 GENERIC MAP (
178 full => OPEN, empty => FifoF1_Empty);
179 tech => 0, Mem_use => Mem_use, Data_sz => 16,
179
180 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
180
181 PORT MAP (
181 Memf2: lppFIFOxN
182 rstn => rstn, wclk => clk, rclk => clk,
182 GENERIC MAP (
183 ReUse => (OTHERS => '0'),
183 tech => 0, Mem_use => Mem_use, Data_sz => 16,
184 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
184 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
185 wdata => sample_f3_wdata, rdata => FifoF3_Data,
185 PORT MAP (
186 full => OPEN, empty => FifoF3_Empty);
186 rstn => rstn, wclk => clk, rclk => clk,
187 -----------------------------------------------------------------------------
187 ReUse => (OTHERS => '0'),
188
188 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
189
189 wdata => sample_f3_wdata, rdata => FifoF3_Data,
190 -----------------------------------------------------------------------------
190 full => OPEN, empty => FifoF3_Empty);
191 DMUX0 : DEMUX
191 -----------------------------------------------------------------------------
192 GENERIC MAP (
192
193 Data_sz => 16)
193
194 PORT MAP (
194 -----------------------------------------------------------------------------
195 clk => clk,
195 DMUX0 : DEMUX
196 rstn => rstn,
196 GENERIC MAP (
197 Read => FFT_Read,
197 Data_sz => 16)
198 Load => FFT_Load,
198 PORT MAP (
199 EmptyF0 => FifoF0_Empty,
199 clk => clk,
200 EmptyF1 => FifoF1_Empty,
200 rstn => rstn,
201 EmptyF2 => FifoF3_Empty,
201 Read => FFT_Read,
202 DataF0 => FifoF0_Data,
202 Load => FFT_Load,
203 DataF1 => FifoF1_Data,
203 EmptyF0 => FifoF0_Empty,
204 DataF2 => FifoF3_Data,
204 EmptyF1 => FifoF1_Empty,
205 WorkFreq => DMUX_WorkFreq,
205 EmptyF2 => FifoF3_Empty,
206 Read_DEMUX => DMUX_Read,
206 DataF0 => FifoF0_Data,
207 Empty => DMUX_Empty,
207 DataF1 => FifoF1_Data,
208 Data => DMUX_Data);
208 DataF2 => FifoF3_Data,
209 -----------------------------------------------------------------------------
209 WorkFreq => DMUX_WorkFreq,
210
210 Read_DEMUX => DMUX_Read,
211
211 Empty => DMUX_Empty,
212 -----------------------------------------------------------------------------
212 Data => DMUX_Data);
213 FFT0: FFT
213 -----------------------------------------------------------------------------
214 GENERIC MAP (
214
215 Data_sz => 16,
215
216 NbData => 256)
216 -----------------------------------------------------------------------------
217 PORT MAP (
217 FFT0: FFT
218 clkm => clk,
218 GENERIC MAP (
219 rstn => rstn,
219 Data_sz => 16,
220 FifoIN_Empty => DMUX_Empty,
220 NbData => 256)
221 FifoIN_Data => DMUX_Data,
221 PORT MAP (
222 FifoOUT_Full => FifoINT_Full,
222 clkm => clk,
223 Load => FFT_Load,
223 rstn => rstn,
224 Read => FFT_Read,
224 FifoIN_Empty => DMUX_Empty,
225 Write => FFT_Write,
225 FifoIN_Data => DMUX_Data,
226 ReUse => FFT_ReUse,
226 FifoOUT_Full => FifoINT_Full,
227 Data => FFT_Data);
227 Load => FFT_Load,
228 -----------------------------------------------------------------------------
228 Read => FFT_Read,
229
229 Write => FFT_Write,
230
230 ReUse => FFT_ReUse,
231 -----------------------------------------------------------------------------
231 Data => FFT_Data);
232 MemInt : lppFIFOxN
232 -----------------------------------------------------------------------------
233 GENERIC MAP (
233
234 tech => 0,
234
235 Mem_use => Mem_use,
235 -----------------------------------------------------------------------------
236 Data_sz => 16,
236 MemInt : lppFIFOxN
237 Addr_sz => 8,
237 GENERIC MAP (
238 FifoCnt => 5,
238 tech => 0,
239 Enable_ReUse => '1')
239 Mem_use => Mem_use,
240 PORT MAP (
240 Data_sz => 16,
241 rstn => rstn,
241 Addr_sz => 8,
242 wclk => clk,
242 FifoCnt => 5,
243 rclk => clk,
243 Enable_ReUse => '1')
244 ReUse => SM_ReUse,
244 PORT MAP (
245 wen => FFT_Write,
245 rstn => rstn,
246 ren => SM_Read,
246 wclk => clk,
247 wdata => FFT_Data,
247 rclk => clk,
248 rdata => FifoINT_Data,
248 ReUse => SM_ReUse,
249 full => FifoINT_Full,
249 wen => FFT_Write,
250 empty => OPEN);
250 ren => SM_Read,
251 -----------------------------------------------------------------------------
251 wdata => FFT_Data,
252
252 rdata => FifoINT_Data,
253 -----------------------------------------------------------------------------
253 full => FifoINT_Full,
254 SM0 : MatriceSpectrale
254 empty => OPEN);
255 GENERIC MAP (
255 -----------------------------------------------------------------------------
256 Input_SZ => 16,
256
257 Result_SZ => 32)
257 -----------------------------------------------------------------------------
258 PORT MAP (
258 SM0 : MatriceSpectrale
259 clkm => clk,
259 GENERIC MAP (
260 rstn => rstn,
260 Input_SZ => 16,
261 FifoIN_Full => FifoINT_Full,
261 Result_SZ => 32)
262 SetReUse => FFT_ReUse,
262 PORT MAP (
263 Valid => Head_Valid,
263 clkm => clk,
264 Data_IN => FifoINT_Data,
264 rstn => rstn,
265 ACK => DMA_ack,
265 FifoIN_Full => FifoINT_Full,
266 SM_Write => SM_Wen,
266 SetReUse => FFT_ReUse,
267 FlagError => SM_FlagError,
267 Valid => Head_Valid,
268 -- Pong => SM_Pong,
268 Data_IN => FifoINT_Data,
269 Statu => SM_Param,
269 ACK => DMA_ack,
270 Write => SM_Write,
270 SM_Write => SM_Wen,
271 Read => SM_Read,
271 FlagError => SM_FlagError,
272 ReUse => SM_ReUse,
272 -- Pong => SM_Pong,
273 Data_OUT => SM_Data);
273 Statu => SM_Param,
274 -----------------------------------------------------------------------------
274 Write => SM_Write,
275
275 Read => SM_Read,
276 -----------------------------------------------------------------------------
276 ReUse => SM_ReUse,
277 MemOut : lppFIFOxN
277 Data_OUT => SM_Data);
278 GENERIC MAP (
278 -----------------------------------------------------------------------------
279 tech => 0,
279
280 Mem_use => Mem_use,
280 -----------------------------------------------------------------------------
281 Data_sz => 32,
281 MemOut : lppFIFOxN
282 Addr_sz => 8,
282 GENERIC MAP (
283 FifoCnt => 2,
283 tech => 0,
284 Enable_ReUse => '0')
284 Mem_use => Mem_use,
285 PORT MAP (
285 Data_sz => 32,
286 rstn => rstn,
286 Addr_sz => 8,
287 wclk => clk,
287 FifoCnt => 2,
288 rclk => clk,
288 Enable_ReUse => '0')
289 ReUse => (OTHERS => '0'),
289 PORT MAP (
290 wen => SM_Write,
290 rstn => rstn,
291 ren => Head_Read,
291 wclk => clk,
292 wdata => SM_Data,
292 rclk => clk,
293 rdata => FifoOUT_Data,
293 ReUse => (OTHERS => '0'),
294 full => FifoOUT_Full,
294 wen => SM_Write,
295 empty => FifoOUT_Empty);
295 ren => Head_Read,
296 -----------------------------------------------------------------------------
296 wdata => SM_Data,
297
297 rdata => FifoOUT_Data,
298 -----------------------------------------------------------------------------
298 full => FifoOUT_Full,
299 Head0 : HeaderBuilder
299 empty => FifoOUT_Empty);
300 GENERIC MAP (
300 -----------------------------------------------------------------------------
301 Data_sz => 32)
301
302 PORT MAP (
302 -----------------------------------------------------------------------------
303 clkm => clk,
303 Head0 : HeaderBuilder
304 rstn => rstn,
304 GENERIC MAP (
305 -- pong => SM_Pong,
305 Data_sz => 32)
306 Statu => SM_Param,
306 PORT MAP (
307 Matrix_Type => DMUX_WorkFreq,
307 clkm => clk,
308 Matrix_Write => SM_Wen,
308 rstn => rstn,
309 Valid => Head_Valid,
309 -- pong => SM_Pong,
310
310 Statu => SM_Param,
311 dataIN => FifoOUT_Data,
311 Matrix_Type => DMUX_WorkFreq,
312 emptyIN => FifoOUT_Empty,
312 Matrix_Write => SM_Wen,
313 RenOUT => Head_Read,
313 Valid => Head_Valid,
314
314
315 dataOUT => Head_Data,
315 dataIN => FifoOUT_Data,
316 emptyOUT => Head_Empty,
316 emptyIN => FifoOUT_Empty,
317 RenIN => DMA_Read,
317 RenOUT => Head_Read,
318
318
319 header => Head_Header,
319 dataOUT => Head_Data,
320 header_val => Head_Val,
320 emptyOUT => Head_Empty,
321 header_ack => DMA_ack );
321 RenIN => DMA_Read,
322 -----------------------------------------------------------------------------
322
323 data_time(31 DOWNTO 0) <= coarse_time;
323 header => Head_Header,
324 data_time(47 DOWNTO 32) <= fine_time;
324 header_val => Head_Val,
325
325 header_ack => DMA_ack );
326 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
326 -----------------------------------------------------------------------------
327 PORT MAP (
327 data_time(31 DOWNTO 0) <= coarse_time;
328 HCLK => clk,
328 data_time(47 DOWNTO 32) <= fine_time;
329 HRESETn => rstn,
329
330
330 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
331 data_time => data_time,
331 PORT MAP (
332
332 HCLK => clk,
333 fifo_data => Head_Data,
333 HRESETn => rstn,
334 fifo_empty => Head_Empty,
334
335 fifo_ren => DMA_Read,
335 data_time => data_time,
336
336
337 header => Head_Header,
337 fifo_data => Head_Data,
338 header_val => Head_Val,
338 fifo_empty => Head_Empty,
339 header_ack => DMA_ack,
339 fifo_ren => DMA_Read,
340
340
341 dma_addr => dma_addr,
341 header => Head_Header,
342 dma_data => dma_data,
342 header_val => Head_Val,
343 dma_valid => dma_valid,
343 header_ack => DMA_ack,
344 dma_valid_burst => dma_valid_burst,
344
345 dma_ren => dma_ren,
345 dma_addr => dma_addr,
346 dma_done => dma_done,
346 dma_data => dma_data,
347
347 dma_valid => dma_valid_s,
348 ready_matrix_f0_0 => ready_matrix_f0_0,
348 dma_valid_burst => dma_valid_burst_s,
349 ready_matrix_f0_1 => ready_matrix_f0_1,
349 dma_ren => dma_ren,
350 ready_matrix_f1 => ready_matrix_f1,
350 dma_done => dma_done,
351 ready_matrix_f2 => ready_matrix_f2,
351
352 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
352 ready_matrix_f0_0 => ready_matrix_f0_0,
353 error_bad_component_error => error_bad_component_error,
353 ready_matrix_f0_1 => ready_matrix_f0_1,
354 debug_reg => debug_reg,
354 ready_matrix_f1 => ready_matrix_f1,
355 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
355 ready_matrix_f2 => ready_matrix_f2,
356 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
356 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
357 status_ready_matrix_f1 => status_ready_matrix_f1,
357 error_bad_component_error => error_bad_component_error,
358 status_ready_matrix_f2 => status_ready_matrix_f2,
358 debug_reg => debug_reg_s,
359 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
359 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
360 status_error_bad_component_error => status_error_bad_component_error,
360 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
361 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
361 status_ready_matrix_f1 => status_ready_matrix_f1,
362 config_active_interruption_onError => config_active_interruption_onError,
362 status_ready_matrix_f2 => status_ready_matrix_f2,
363 addr_matrix_f0_0 => addr_matrix_f0_0,
363 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
364 addr_matrix_f0_1 => addr_matrix_f0_1,
364 status_error_bad_component_error => status_error_bad_component_error,
365 addr_matrix_f1 => addr_matrix_f1,
365 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
366 addr_matrix_f2 => addr_matrix_f2,
366 config_active_interruption_onError => config_active_interruption_onError,
367
367 addr_matrix_f0_0 => addr_matrix_f0_0,
368 matrix_time_f0_0 => matrix_time_f0_0,
368 addr_matrix_f0_1 => addr_matrix_f0_1,
369 matrix_time_f0_1 => matrix_time_f0_1,
369 addr_matrix_f1 => addr_matrix_f1,
370 matrix_time_f1 => matrix_time_f1,
370 addr_matrix_f2 => addr_matrix_f2,
371 matrix_time_f2 => matrix_time_f2
371
372 );
372 matrix_time_f0_0 => matrix_time_f0_0,
373
373 matrix_time_f0_1 => matrix_time_f0_1,
374 END Behavioral;
374 matrix_time_f1 => matrix_time_f1,
375 matrix_time_f2 => matrix_time_f2
376 );
377
378 dma_valid <= dma_valid_s;
379 dma_valid_burst <= dma_valid_burst_s;
380
381 debug_reg(9 DOWNTO 0) <= debug_reg_s(9 DOWNTO 0);
382 debug_reg(10) <= Head_Empty;
383 debug_reg(11) <= DMA_Read;
384 debug_reg(12) <= Head_Val;
385 debug_reg(13) <= DMA_ack;
386 debug_reg(14) <= dma_ren;
387 debug_reg(15) <= dma_done;
388 debug_reg(16) <= dma_valid_s;
389 debug_reg(17) <= dma_valid_burst_s;
390 debug_reg(31 DOWNTO 18) <= (OTHERS => '0');
391
392
393
394 END Behavioral;
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@@ -1,383 +1,386
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -------------------------------------------------------------------------------
25 -------------------------------------------------------------------------------
26 LIBRARY ieee;
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
28 USE ieee.numeric_std.ALL;
29 LIBRARY grlib;
29 LIBRARY grlib;
30 USE grlib.amba.ALL;
30 USE grlib.amba.ALL;
31 USE grlib.stdlib.ALL;
31 USE grlib.stdlib.ALL;
32 USE grlib.devices.ALL;
32 USE grlib.devices.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
34 LIBRARY lpp;
34 LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
35 USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
36 USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
39 LIBRARY techmap;
39 LIBRARY techmap;
40 USE techmap.gencomp.ALL;
40 USE techmap.gencomp.ALL;
41
41
42
42
43 ENTITY lpp_lfr_ms_fsmdma IS
43 ENTITY lpp_lfr_ms_fsmdma IS
44 PORT (
44 PORT (
45 -- AMBA AHB system signals
45 -- AMBA AHB system signals
46 HCLK : IN STD_ULOGIC;
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48
48
49 --TIME
49 --TIME
50 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
50 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
51
51
52 -- fifo interface
52 -- fifo interface
53 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 fifo_empty : IN STD_LOGIC;
54 fifo_empty : IN STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
56
56
57 -- header
57 -- header
58 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 header_val : IN STD_LOGIC;
59 header_val : IN STD_LOGIC;
60 header_ack : OUT STD_LOGIC;
60 header_ack : OUT STD_LOGIC;
61
61
62 -- DMA
62 -- DMA
63 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 dma_valid : OUT STD_LOGIC;
65 dma_valid : OUT STD_LOGIC;
66 dma_valid_burst : OUT STD_LOGIC;
66 dma_valid_burst : OUT STD_LOGIC;
67 dma_ren : IN STD_LOGIC;
67 dma_ren : IN STD_LOGIC;
68 dma_done : IN STD_LOGIC;
68 dma_done : IN STD_LOGIC;
69
69
70 -- Reg out
70 -- Reg out
71 ready_matrix_f0_0 : OUT STD_LOGIC;
71 ready_matrix_f0_0 : OUT STD_LOGIC;
72 ready_matrix_f0_1 : OUT STD_LOGIC;
72 ready_matrix_f0_1 : OUT STD_LOGIC;
73 ready_matrix_f1 : OUT STD_LOGIC;
73 ready_matrix_f1 : OUT STD_LOGIC;
74 ready_matrix_f2 : OUT STD_LOGIC;
74 ready_matrix_f2 : OUT STD_LOGIC;
75 error_anticipating_empty_fifo : OUT STD_LOGIC;
75 error_anticipating_empty_fifo : OUT STD_LOGIC;
76 error_bad_component_error : OUT STD_LOGIC;
76 error_bad_component_error : OUT STD_LOGIC;
77 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78
78
79 -- Reg In
79 -- Reg In
80 status_ready_matrix_f0_0 : IN STD_LOGIC;
80 status_ready_matrix_f0_0 : IN STD_LOGIC;
81 status_ready_matrix_f0_1 : IN STD_LOGIC;
81 status_ready_matrix_f0_1 : IN STD_LOGIC;
82 status_ready_matrix_f1 : IN STD_LOGIC;
82 status_ready_matrix_f1 : IN STD_LOGIC;
83 status_ready_matrix_f2 : IN STD_LOGIC;
83 status_ready_matrix_f2 : IN STD_LOGIC;
84 status_error_anticipating_empty_fifo : IN STD_LOGIC;
84 status_error_anticipating_empty_fifo : IN STD_LOGIC;
85 status_error_bad_component_error : IN STD_LOGIC;
85 status_error_bad_component_error : IN STD_LOGIC;
86
86
87 config_active_interruption_onNewMatrix : IN STD_LOGIC;
87 config_active_interruption_onNewMatrix : IN STD_LOGIC;
88 config_active_interruption_onError : IN STD_LOGIC;
88 config_active_interruption_onError : IN STD_LOGIC;
89 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93
93
94 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
96 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
96 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
97 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
97 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
98
98
99 );
99 );
100 END;
100 END;
101
101
102 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
102 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
103 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
104 -- SIGNAL DMAIn : DMA_In_Type;
104 -- SIGNAL DMAIn : DMA_In_Type;
105 -- SIGNAL header_dmai : DMA_In_Type;
105 -- SIGNAL header_dmai : DMA_In_Type;
106 -- SIGNAL component_dmai : DMA_In_Type;
106 -- SIGNAL component_dmai : DMA_In_Type;
107 -- SIGNAL DMAOut : DMA_OUt_Type;
107 -- SIGNAL DMAOut : DMA_OUt_Type;
108 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
109
109
110 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 TYPE state_DMAWriteBurst IS (IDLE,
112 TYPE state_DMAWriteBurst IS (IDLE,
113 CHECK_COMPONENT_TYPE,
113 CHECK_COMPONENT_TYPE,
114 WRITE_COARSE_TIME,
114 WRITE_COARSE_TIME,
115 WRITE_FINE_TIME,
115 WRITE_FINE_TIME,
116 TRASH_FIFO,
116 TRASH_FIFO,
117 SEND_DATA,
117 SEND_DATA,
118 WAIT_DATA_ACK,
118 WAIT_DATA_ACK,
119 CHECK_LENGTH
119 CHECK_LENGTH
120 );
120 );
121 SIGNAL state : state_DMAWriteBurst; -- := IDLE;
121 SIGNAL state : state_DMAWriteBurst; -- := IDLE;
122
122
123 -- SIGNAL nbSend : INTEGER;
123 -- SIGNAL nbSend : INTEGER;
124 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
124 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
125 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
125 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL header_check_ok : STD_LOGIC;
127 SIGNAL header_check_ok : STD_LOGIC;
128 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL send_matrix : STD_LOGIC;
129 SIGNAL send_matrix : STD_LOGIC;
130 -- SIGNAL request : STD_LOGIC;
130 -- SIGNAL request : STD_LOGIC;
131 -- SIGNAL remaining_data_request : INTEGER;
131 -- SIGNAL remaining_data_request : INTEGER;
132 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 -----------------------------------------------------------------------------
133 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
135 SIGNAL header_select : STD_LOGIC;
135 SIGNAL header_select : STD_LOGIC;
136
136
137 SIGNAL header_send : STD_LOGIC;
137 SIGNAL header_send : STD_LOGIC;
138 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL header_send_ok : STD_LOGIC;
139 SIGNAL header_send_ok : STD_LOGIC;
140 SIGNAL header_send_ko : STD_LOGIC;
140 SIGNAL header_send_ko : STD_LOGIC;
141
141
142 SIGNAL component_send : STD_LOGIC;
142 SIGNAL component_send : STD_LOGIC;
143 SIGNAL component_send_ok : STD_LOGIC;
143 SIGNAL component_send_ok : STD_LOGIC;
144 SIGNAL component_send_ko : STD_LOGIC;
144 SIGNAL component_send_ko : STD_LOGIC;
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 SIGNAL fifo_ren_trash : STD_LOGIC;
146 SIGNAL fifo_ren_trash : STD_LOGIC;
147 SIGNAL component_fifo_ren : STD_LOGIC;
147 SIGNAL component_fifo_ren : STD_LOGIC;
148
148
149 -----------------------------------------------------------------------------
149 -----------------------------------------------------------------------------
150 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
151 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
152
152
153 BEGIN
153 BEGIN
154
154
155 debug_reg <= debug_reg_s;
155 debug_reg <= debug_reg_s;
156
156
157
157
158 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
158 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
159 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
159 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
160 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
160 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
161 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
161 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
162 '0';
162 '0';
163
163
164 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
164 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
165 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
165 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
166 '1' WHEN component_type = component_type_pre + "0001" ELSE
166 '1' WHEN component_type = component_type_pre + "0001" ELSE
167 '0';
167 '0';
168
168
169 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
169 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
170 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
170 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
171 addr_matrix_f1 WHEN matrix_type = "10" ELSE
171 addr_matrix_f1 WHEN matrix_type = "10" ELSE
172 addr_matrix_f2 WHEN matrix_type = "11" ELSE
172 addr_matrix_f2 WHEN matrix_type = "11" ELSE
173 (OTHERS => '0');
173 (OTHERS => '0');
174
174
175 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
176 -- DMA control
176 -- DMA control
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
178 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
179 BEGIN -- PROCESS DMAWriteBurst_p
179 BEGIN -- PROCESS DMAWriteBurst_p
180 IF HRESETn = '0' THEN -- asynchronous reset (active low)
180 IF HRESETn = '0' THEN -- asynchronous reset (active low)
181 matrix_type <= (OTHERS => '0');
181 matrix_type <= (OTHERS => '0');
182 component_type <= (OTHERS => '0');
182 component_type <= (OTHERS => '0');
183 state <= IDLE;
183 state <= IDLE;
184 header_ack <= '0';
184 header_ack <= '0';
185 ready_matrix_f0_0 <= '0';
185 ready_matrix_f0_0 <= '0';
186 ready_matrix_f0_1 <= '0';
186 ready_matrix_f0_1 <= '0';
187 ready_matrix_f1 <= '0';
187 ready_matrix_f1 <= '0';
188 ready_matrix_f2 <= '0';
188 ready_matrix_f2 <= '0';
189 error_anticipating_empty_fifo <= '0';
189 error_anticipating_empty_fifo <= '0';
190 error_bad_component_error <= '0';
190 error_bad_component_error <= '0';
191 component_type_pre <= "0000";
191 component_type_pre <= "0000";
192 fifo_ren_trash <= '1';
192 fifo_ren_trash <= '1';
193 component_send <= '0';
193 component_send <= '0';
194 address <= (OTHERS => '0');
194 address <= (OTHERS => '0');
195 header_select <= '0';
195 header_select <= '0';
196 header_send <= '0';
196 header_send <= '0';
197 header_data <= (OTHERS => '0');
197 header_data <= (OTHERS => '0');
198 fine_time_reg <= (OTHERS => '0');
198 fine_time_reg <= (OTHERS => '0');
199
199
200 debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0');
200 debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0');
201
201
202 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
202 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
203
203 debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
204
204 CASE state IS
205 CASE state IS
205 WHEN IDLE =>
206 WHEN IDLE =>
206 debug_reg_s(2 DOWNTO 0) <= "000";
207 debug_reg_s(2 DOWNTO 0) <= "000";
207
208
208 matrix_type <= header(1 DOWNTO 0);
209 matrix_type <= header(1 DOWNTO 0);
209 --component_type <= header(5 DOWNTO 2);
210 --component_type <= header(5 DOWNTO 2);
210
211
211 ready_matrix_f0_0 <= '0';
212 ready_matrix_f0_0 <= '0';
212 ready_matrix_f0_1 <= '0';
213 ready_matrix_f0_1 <= '0';
213 ready_matrix_f1 <= '0';
214 ready_matrix_f1 <= '0';
214 ready_matrix_f2 <= '0';
215 ready_matrix_f2 <= '0';
215 error_bad_component_error <= '0';
216 error_bad_component_error <= '0';
216 header_select <= '1';
217 header_select <= '1';
218 IF header_val = '1' THEN
219 header_ack <= '1';
220 END IF;
217 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
221 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
218 debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0);
222 debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0);
219 debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2);
223 debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2);
220
224
221 matrix_type <= header(1 DOWNTO 0);
225 matrix_type <= header(1 DOWNTO 0);
222 component_type <= header(5 DOWNTO 2);
226 component_type <= header(5 DOWNTO 2);
223 component_type_pre <= component_type;
227 component_type_pre <= component_type;
224 state <= CHECK_COMPONENT_TYPE;
228 state <= CHECK_COMPONENT_TYPE;
225 END IF;
229 END IF;
226
230
227 WHEN CHECK_COMPONENT_TYPE =>
231 WHEN CHECK_COMPONENT_TYPE =>
228 debug_reg_s(2 DOWNTO 0) <= "001";
232 debug_reg_s(2 DOWNTO 0) <= "001";
233 header_ack <= '0';
229
234
230 IF header_check_ok = '1' THEN
235 IF header_check_ok = '1' THEN
231 header_ack <= '1';
232 header_send <= '0';
236 header_send <= '0';
233 --
237 --
234 IF component_type = "0000" THEN
238 IF component_type = "0000" THEN
235 address <= address_matrix;
239 address <= address_matrix;
236 CASE matrix_type IS
240 CASE matrix_type IS
237 WHEN "00" => matrix_time_f0_0 <= data_time;
241 WHEN "00" => matrix_time_f0_0 <= data_time;
238 WHEN "01" => matrix_time_f0_1 <= data_time;
242 WHEN "01" => matrix_time_f0_1 <= data_time;
239 WHEN "10" => matrix_time_f1 <= data_time;
243 WHEN "10" => matrix_time_f1 <= data_time;
240 WHEN "11" => matrix_time_f2 <= data_time ;
244 WHEN "11" => matrix_time_f2 <= data_time ;
241 WHEN OTHERS => NULL;
245 WHEN OTHERS => NULL;
242 END CASE;
246 END CASE;
243
247
244 header_data <= data_time(31 DOWNTO 0);
248 header_data <= data_time(31 DOWNTO 0);
245 fine_time_reg <= data_time(47 DOWNTO 32);
249 fine_time_reg <= data_time(47 DOWNTO 32);
246 --state <= WRITE_COARSE_TIME;
250 --state <= WRITE_COARSE_TIME;
247 --header_send <= '1';
251 --header_send <= '1';
248 state <= SEND_DATA;
252 state <= SEND_DATA;
249 header_send <= '0';
253 header_send <= '0';
250 component_send <= '1';
254 component_send <= '1';
251 header_select <= '0';
255 header_select <= '0';
252 ELSE
256 ELSE
253 state <= SEND_DATA;
257 state <= SEND_DATA;
254 END IF;
258 END IF;
255 --
259 --
256 ELSE
260 ELSE
257 error_bad_component_error <= '1';
261 error_bad_component_error <= '1';
258 component_type_pre <= "0000";
262 component_type_pre <= "0000";
259 header_ack <= '1';
260 state <= TRASH_FIFO;
263 state <= TRASH_FIFO;
261 END IF;
264 END IF;
262
265
263 --WHEN WRITE_COARSE_TIME =>
266 --WHEN WRITE_COARSE_TIME =>
264 -- debug_reg_s(2 DOWNTO 0) <= "010";
267 -- debug_reg_s(2 DOWNTO 0) <= "010";
265
268
266 -- header_ack <= '0';
269 -- header_ack <= '0';
267
270
268 -- IF dma_ren = '0' THEN
271 -- IF dma_ren = '0' THEN
269 -- header_send <= '0';
272 -- header_send <= '0';
270 -- ELSE
273 -- ELSE
271 -- header_send <= header_send;
274 -- header_send <= header_send;
272 -- END IF;
275 -- END IF;
273
276
274
277
275 -- IF header_send_ko = '1' THEN
278 -- IF header_send_ko = '1' THEN
276 -- header_send <= '0';
279 -- header_send <= '0';
277 -- state <= TRASH_FIFO;
280 -- state <= TRASH_FIFO;
278 -- error_anticipating_empty_fifo <= '1';
281 -- error_anticipating_empty_fifo <= '1';
279 -- -- TODO : error sending header
282 -- -- TODO : error sending header
280 -- ELSIF header_send_ok = '1' THEN
283 -- ELSIF header_send_ok = '1' THEN
281 -- header_send <= '1';
284 -- header_send <= '1';
282 -- header_select <= '1';
285 -- header_select <= '1';
283 -- header_data(15 DOWNTO 0) <= fine_time_reg;
286 -- header_data(15 DOWNTO 0) <= fine_time_reg;
284 -- header_data(31 DOWNTO 16) <= (OTHERS => '0');
287 -- header_data(31 DOWNTO 16) <= (OTHERS => '0');
285 -- state <= WRITE_FINE_TIME;
288 -- state <= WRITE_FINE_TIME;
286 -- address <= address + 4;
289 -- address <= address + 4;
287 -- END IF;
290 -- END IF;
288
291
289
292
290 --WHEN WRITE_FINE_TIME =>
293 --WHEN WRITE_FINE_TIME =>
291 -- debug_reg_s(2 DOWNTO 0) <= "011";
294 -- debug_reg_s(2 DOWNTO 0) <= "011";
292
295
293 -- header_ack <= '0';
296 -- header_ack <= '0';
294
297
295 -- IF dma_ren = '0' THEN
298 -- IF dma_ren = '0' THEN
296 -- header_send <= '0';
299 -- header_send <= '0';
297 -- ELSE
300 -- ELSE
298 -- header_send <= header_send;
301 -- header_send <= header_send;
299 -- END IF;
302 -- END IF;
300
303
301 -- IF header_send_ko = '1' THEN
304 -- IF header_send_ko = '1' THEN
302 -- header_send <= '0';
305 -- header_send <= '0';
303 -- state <= TRASH_FIFO;
306 -- state <= TRASH_FIFO;
304 -- error_anticipating_empty_fifo <= '1';
307 -- error_anticipating_empty_fifo <= '1';
305 -- -- TODO : error sending header
308 -- -- TODO : error sending header
306 -- ELSIF header_send_ok = '1' THEN
309 -- ELSIF header_send_ok = '1' THEN
307 -- header_send <= '0';
310 -- header_send <= '0';
308 -- header_select <= '0';
311 -- header_select <= '0';
309 -- state <= SEND_DATA;
312 -- state <= SEND_DATA;
310 -- address <= address + 4;
313 -- address <= address + 4;
311 -- END IF;
314 -- END IF;
312
315
313 WHEN TRASH_FIFO =>
316 WHEN TRASH_FIFO =>
314 debug_reg_s(2 DOWNTO 0) <= "100";
317 debug_reg_s(2 DOWNTO 0) <= "100";
315
318
316 header_ack <= '0';
319 header_ack <= '0';
317 error_bad_component_error <= '0';
320 error_bad_component_error <= '0';
318 error_anticipating_empty_fifo <= '0';
321 error_anticipating_empty_fifo <= '0';
319 IF fifo_empty = '1' THEN
322 IF fifo_empty = '1' THEN
320 state <= IDLE;
323 state <= IDLE;
321 fifo_ren_trash <= '1';
324 fifo_ren_trash <= '1';
322 ELSE
325 ELSE
323 fifo_ren_trash <= '0';
326 fifo_ren_trash <= '0';
324 END IF;
327 END IF;
325
328
326 WHEN SEND_DATA =>
329 WHEN SEND_DATA =>
327 header_ack <= '0';
330 header_ack <= '0';
328 debug_reg_s(2 DOWNTO 0) <= "101";
331 debug_reg_s(2 DOWNTO 0) <= "101";
329
332
330 IF fifo_empty = '1' THEN
333 IF fifo_empty = '1' THEN
331 state <= IDLE;
334 state <= IDLE;
332 IF component_type = "1110" THEN --"1110" -- JC
335 IF component_type = "1110" THEN --"1110" -- JC
333 CASE matrix_type IS
336 CASE matrix_type IS
334 WHEN "00" => ready_matrix_f0_0 <= '1';
337 WHEN "00" => ready_matrix_f0_0 <= '1';
335 WHEN "01" => ready_matrix_f0_1 <= '1';
338 WHEN "01" => ready_matrix_f0_1 <= '1';
336 WHEN "10" => ready_matrix_f1 <= '1';
339 WHEN "10" => ready_matrix_f1 <= '1';
337 WHEN "11" => ready_matrix_f2 <= '1';
340 WHEN "11" => ready_matrix_f2 <= '1';
338 WHEN OTHERS => NULL;
341 WHEN OTHERS => NULL;
339 END CASE;
342 END CASE;
340
343
341 END IF;
344 END IF;
342 ELSE
345 ELSE
343 component_send <= '1';
346 component_send <= '1';
344 address <= address;
347 address <= address;
345 state <= WAIT_DATA_ACK;
348 state <= WAIT_DATA_ACK;
346 END IF;
349 END IF;
347
350
348 WHEN WAIT_DATA_ACK =>
351 WHEN WAIT_DATA_ACK =>
349 debug_reg_s(2 DOWNTO 0) <= "110";
352 debug_reg_s(2 DOWNTO 0) <= "110";
350
353
351 component_send <= '0';
354 component_send <= '0';
352 IF component_send_ok = '1' THEN
355 IF component_send_ok = '1' THEN
353 address <= address + 64;
356 address <= address + 64;
354 state <= SEND_DATA;
357 state <= SEND_DATA;
355 ELSIF component_send_ko = '1' THEN
358 ELSIF component_send_ko = '1' THEN
356 error_anticipating_empty_fifo <= '0';
359 error_anticipating_empty_fifo <= '0';
357 state <= TRASH_FIFO;
360 state <= TRASH_FIFO;
358 END IF;
361 END IF;
359
362
360 WHEN CHECK_LENGTH =>
363 WHEN CHECK_LENGTH =>
361 component_send <= '0';
364 component_send <= '0';
362 debug_reg_s(2 DOWNTO 0) <= "111";
365 debug_reg_s(2 DOWNTO 0) <= "111";
363 state <= IDLE;
366 state <= IDLE;
364
367
365 WHEN OTHERS => NULL;
368 WHEN OTHERS => NULL;
366 END CASE;
369 END CASE;
367
370
368 END IF;
371 END IF;
369 END PROCESS DMAWriteFSM_p;
372 END PROCESS DMAWriteFSM_p;
370
373
371 dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
374 dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
372 dma_valid <= header_send WHEN header_select = '1' ELSE '0';
375 dma_valid <= header_send WHEN header_select = '1' ELSE '0';
373 dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
376 dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
374 dma_addr <= address;
377 dma_addr <= address;
375 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
378 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
376
379
377 component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
380 component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
378 component_send_ko <= '0';
381 component_send_ko <= '0';
379
382
380 header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
383 header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
381 header_send_ko <= '0';
384 header_send_ko <= '0';
382
385
383 END Behavioral;
386 END Behavioral;
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