HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r273:8decc2aa17b6

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designs/BeagleSynth/GPMC_SLAVE.vhd created 644 +100 0

@@ -0,0 +1,100
	1	----------------------------------------------------------------------------------
	2	-- Company:
	3	-- Engineer:
	4	--
	5	-- Create Date: 15:20:11 12/08/2013
	6	-- Design Name:
	7	-- Module Name: GPMC_SLAVE - Behavioral
	8	-- Project Name:
	9	-- Target Devices:
	10	-- Tool versions:
	11	-- Description:
	12	--
	13	-- Dependencies:
	14	--
	15	-- Revision:
	16	-- Revision 0.01 - File Created
	17	-- Additional Comments:
	18	--
	19	----------------------------------------------------------------------------------
	20	library IEEE;
	21	use IEEE.STD_LOGIC_1164.ALL;
	22	use IEEE.numeric_std.all;
	23	library grlib, techmap;
	24	use grlib.stdlib.all;
	25	use techmap.gencomp.all;
	26	use techmap.allclkgen.all;
	27	library lpp;
	28	use lpp.general_purpose.all;
	29
	30	entity GPMC_SLAVE is
	31	generic (
	32	memtech : integer := 0;
	33	padtech : integer := 0
	34	);
	35	Port (
	36	clk : in STD_LOGIC;
	37	reset : in STD_LOGIC;
	38	GPMC_AD : inout std_logic_vector(15 downto 0);
	39	GPMC_A : in std_logic_vector(19 downto 0);
	40	GPMC_CLK_MUX0 : in std_ulogic;
	41	GPMC_WEN : in std_ulogic;
	42	GPMC_OEN_REN : in std_ulogic;
	43	GPMC_ADVN_ALE : in std_ulogic;
	44	GPMC_CSN : in std_ulogic_vector(2 downto 0);
	45	GPMC_BE0N_CLE : in std_ulogic;
	46	GPMC_BE1N : in std_ulogic;
	47	GPMC_WAIT0 : in std_ulogic;
	48	GPMC_WPN : in std_ulogic
	49	);
	50	end GPMC_SLAVE;
	51
	52	architecture Behavioral of GPMC_SLAVE is
	53	constant VectInit : std_logic_vector(15 downto 0):=(others => '0');
	54
	55	signal data_out :std_logic_vector(15 downto 0);
	56	signal data_in :std_logic_vector(15 downto 0);
	57
	58	type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0);
	59	signal RAMarray : RAMarrayT:=(others => VectInit);
	60	signal ramindex : integer range 0 to 255;
	61
	62	begin
	63
	64	data_pad : iopadv generic map (tech=> padtech,width => 16)
	65	port map (
	66	pad => GPMC_AD(15 downto 0),
	67	o => data_in(15 downto 0),
	68	en => GPMC_OEN_REN,
	69	i => data_out(15 downto 0)
	70	);
	71
	72	process(reset,GPMC_CLK_MUX0)
	73	begin
	74	if reset = '0' then
	75	data_out <= (others => '0');
	76	ramindex <= 0;
	77	elsif GPMC_CLK_MUX0'event and GPMC_CLK_MUX0 = '1' then
	78	ramindex <= to_integer(unsigned(GPMC_A));
	79	data_out <= RAMarray(ramindex);
	80	if GPMC_WEN = '0' then
	81	RAMarray(ramindex) <= data_in;
	82	end if;
	83	end if;
	84	end process;
	85
	86	end Behavioral;
	87
	88
	89
	90
	91
	92
	93
	94
	95
	96
	97
	98
	99
	100

boards/BeagleSynth/default.ucf +65 -7

@@ -2,10 +2,11
2	NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE;	2	NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE;
3	NET "CLK" LOC = "K20"\| slew=FAST \| IOSTANDARD=LVTTL;	3	NET "CLK" LOC = "K20"\| slew=FAST \| IOSTANDARD=LVTTL;
4	NET "CLKM" TNM_NET = "clkm_net";	4	NET "CLKM" TNM_NET = "clkm_net";
5	TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;	5	TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;
6		6
		7
7	NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;	8	NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
8	NET "RESET" LOC = "AB11" \| slew=FAST \| IOSTANDARD=LVTTL;	9	NET "RESET" LOC = "AB11" \| slew=FAST \| IOSTANDARD=LVTTL;
9		10
10	NET "DAC_nCLR" LOC = "R11" \| IOSTANDARD=LVTTL;	11	NET "DAC_nCLR" LOC = "R11" \| IOSTANDARD=LVTTL;
11	NET "DAC_nCS" LOC = "T12" \| IOSTANDARD=LVTTL;	12	NET "DAC_nCS" LOC = "T12" \| IOSTANDARD=LVTTL;
@@ -17,15 +18,15 NET "DAC_SDI(3)" LOC = "M6" \| IOSTANDA
17	NET "DAC_SDI(4)" LOC = "K22" \| IOSTANDARD=LVTTL;	18	NET "DAC_SDI(4)" LOC = "K22" \| IOSTANDARD=LVTTL;
18	NET "DAC_SDI(5)" LOC = "L22" \| IOSTANDARD=LVTTL;	19	NET "DAC_SDI(5)" LOC = "L22" \| IOSTANDARD=LVTTL;
19	NET "DAC_SDI(6)" LOC = "G19" \| IOSTANDARD=LVTTL;	20	NET "DAC_SDI(6)" LOC = "G19" \| IOSTANDARD=LVTTL;
20	NET "DAC_SDI(7)" LOC = "F20" \| IOSTANDARD=LVTTL;	21	NET "DAC_SDI(7)" LOC = "F20" \| IOSTANDARD=LVTTL;
21		22
22		23
23	NET "TXD" LOC = "V22"\| slew=FAST \| IOSTANDARD=LVTTL;	24	NET "TXD" LOC = "V22"\| slew=FAST \| IOSTANDARD=LVTTL;
24	NET "RXD" LOC = "U22"\| slew=FAST \| IOSTANDARD=LVTTL;	25	NET "RXD" LOC = "U22"\| slew=FAST \| IOSTANDARD=LVTTL;
25	NET "LED(0)" LOC = "AB9"\| slew=FAST \| IOSTANDARD=LVTTL;	26	NET "LED(0)" LOC = "AB9"\| slew=FAST \| IOSTANDARD=LVTTL;
26	NET "LED(1)" LOC = "AB8"\| slew=FAST \| IOSTANDARD=LVTTL;	27	NET "LED(1)" LOC = "AB8"\| slew=FAST \| IOSTANDARD=LVTTL;
27	NET "LED(2)" LOC = "AA8"\| slew=FAST \| IOSTANDARD=LVTTL;	28	NET "LED(2)" LOC = "AA8"\| slew=FAST \| IOSTANDARD=LVTTL;
28		29
29	NET "urxd1" LOC = "D3" \| IOSTANDARD=LVTTL; # Unused PIN	30	NET "urxd1" LOC = "D3" \| IOSTANDARD=LVTTL; # Unused PIN
30	NET "utxd1" LOC = "C4" \| IOSTANDARD=LVTTL; # Unused PIN	31	NET "utxd1" LOC = "C4" \| IOSTANDARD=LVTTL; # Unused PIN
31		32
@@ -91,6 +92,58 NET "Data(2)" LOC = "A20"\| slew=FAS
91	NET "Data(1)" LOC = "B18"\| slew=FAST \| IOSTANDARD=LVTTL; # sdram data	92	NET "Data(1)" LOC = "B18"\| slew=FAST \| IOSTANDARD=LVTTL; # sdram data
92	NET "Data(0)" LOC = "A18"\| slew=FAST \| IOSTANDARD=LVTTL; # sdram data	93	NET "Data(0)" LOC = "A18"\| slew=FAST \| IOSTANDARD=LVTTL; # sdram data
93		94
		95	NET "GPMC_AD(0)" LOC = "M1"\| slew=FAST \| IOSTANDARD=LVTTL;
		96	NET "GPMC_AD(1)" LOC = "M2"\| slew=FAST \| IOSTANDARD=LVTTL;
		97	NET "GPMC_AD(2)" LOC = "AB3"\| slew=FAST \| IOSTANDARD=LVTTL;
		98	NET "GPMC_AD(3)" LOC = "AB2"\| slew=FAST \| IOSTANDARD=LVTTL;
		99	NET "GPMC_AD(4)" LOC = "N1"\| slew=FAST \| IOSTANDARD=LVTTL;
		100	NET "GPMC_AD(5)" LOC = "N3"\| slew=FAST \| IOSTANDARD=LVTTL;
		101	NET "GPMC_AD(6)" LOC = "AB5"\| slew=FAST \| IOSTANDARD=LVTTL;
		102	NET "GPMC_AD(7)" LOC = "AB4"\| slew=FAST \| IOSTANDARD=LVTTL;
		103	NET "GPMC_AD(8)" LOC = "R1"\| slew=FAST \| IOSTANDARD=LVTTL;
		104	NET "GPMC_AD(9)" LOC = "V1"\| slew=FAST \| IOSTANDARD=LVTTL;
		105	NET "GPMC_AD(10)" LOC = "U3"\| slew=FAST \| IOSTANDARD=LVTTL;
		106	NET "GPMC_AD(11)" LOC = "T1"\| slew=FAST \| IOSTANDARD=LVTTL;
		107	NET "GPMC_AD(12)" LOC = "V2"\| slew=FAST \| IOSTANDARD=LVTTL;
		108	NET "GPMC_AD(13)" LOC = "W1"\| slew=FAST \| IOSTANDARD=LVTTL;
		109	NET "GPMC_AD(14)" LOC = "T2"\| slew=FAST \| IOSTANDARD=LVTTL;
		110	NET "GPMC_AD(15)" LOC = "U1"\| slew=FAST \| IOSTANDARD=LVTTL;
		111
		112
		113
		114	NET "GPMC_A(0)" LOC = "N4"\| slew=FAST \| IOSTANDARD=LVTTL;
		115	NET "GPMC_A(1)" LOC = "N6"\| slew=FAST \| IOSTANDARD=LVTTL;
		116	NET "GPMC_A(2)" LOC = "P3"\| slew=FAST \| IOSTANDARD=LVTTL;
		117	NET "GPMC_A(3)" LOC = "P4"\| slew=FAST \| IOSTANDARD=LVTTL;
		118	NET "GPMC_A(4)" LOC = "R4"\| slew=FAST \| IOSTANDARD=LVTTL;
		119	NET "GPMC_A(5)" LOC = "T5"\| slew=FAST \| IOSTANDARD=LVTTL;
		120	NET "GPMC_A(6)" LOC = "T6"\| slew=FAST \| IOSTANDARD=LVTTL;
		121	NET "GPMC_A(7)" LOC = "T3"\| slew=FAST \| IOSTANDARD=LVTTL;
		122	NET "GPMC_A(8)" LOC = "L1"\| slew=FAST \| IOSTANDARD=LVTTL;
		123	NET "GPMC_A(9)" LOC = "K1"\| slew=FAST \| IOSTANDARD=LVTTL;
		124	NET "GPMC_A(10)" LOC = "L3"\| slew=FAST \| IOSTANDARD=LVTTL;
		125	NET "GPMC_A(11)" LOC = "K2"\| slew=FAST \| IOSTANDARD=LVTTL;
		126	NET "GPMC_A(12)" LOC = "F1"\| slew=FAST \| IOSTANDARD=LVTTL;
		127	NET "GPMC_A(13)" LOC = "F2"\| slew=FAST \| IOSTANDARD=LVTTL;
		128	NET "GPMC_A(14)" LOC = "G3"\| slew=FAST \| IOSTANDARD=LVTTL;
		129	NET "GPMC_A(15)" LOC = "H2"\| slew=FAST \| IOSTANDARD=LVTTL;
		130	NET "GPMC_A(16)" LOC = "G1"\| slew=FAST \| IOSTANDARD=LVTTL;
		131	NET "GPMC_A(17)" LOC = "H1"\| slew=FAST \| IOSTANDARD=LVTTL;
		132	NET "GPMC_A(18)" LOC = "J1"\| slew=FAST \| IOSTANDARD=LVTTL;
		133	NET "GPMC_A(19)" LOC = "J3"\| slew=FAST \| IOSTANDARD=LVTTL;
		134
		135	NET "GPMC_CLK_MUX0" CLOCK_DEDICATED_ROUTE = FALSE;
		136	NET "GPMC_CLK_MUX0" LOC = "R3"\| slew=FAST \| IOSTANDARD=LVTTL;
		137	NET "GPMC_WEN" LOC = "W3"\| slew=FAST \| IOSTANDARD=LVTTL;
		138	NET "GPMC_OEN_REN" LOC = "Y2"\| slew=FAST \| IOSTANDARD=LVTTL;
		139	NET "GPMC_ADVN_ALE" LOC = "AA2"\| slew=FAST \| IOSTANDARD=LVTTL;
		140	NET "GPMC_CSN(0)" LOC = "M3"\| slew=FAST \| IOSTANDARD=LVTTL;
		141	NET "GPMC_CSN(1)" LOC = "P1"\| slew=FAST \| IOSTANDARD=LVTTL;
		142	NET "GPMC_CSN(2)" LOC = "P2"\| slew=FAST \| IOSTANDARD=LVTTL;
		143	NET "GPMC_BE0N_CLE" LOC = "Y1"\| slew=FAST \| IOSTANDARD=LVTTL;
		144	NET "GPMC_BE1N" LOC = "AB21"\| slew=FAST \| IOSTANDARD=LVTTL;
		145	NET "GPMC_WAIT0" LOC = "AA21"\| slew=FAST \| IOSTANDARD=LVTTL;
		146	NET "GPMC_WPN" LOC = "W22"\| slew=FAST \| IOSTANDARD=LVTTL;
94		147
95		148
96		149
@@ -107,3 +160,8 NET "Data(0)" LOC = "A18"\| slew=FAS
107		160
108		161
109		162
		163
		164
		165
		166
		167

designs/BeagleSynth/BeagleSynth.vhd +46 -12

@@ -22,7 +22,7 use lpp.apb_devices_list.all;
22	use lpp.general_purpose.all;	22	use lpp.general_purpose.all;
23	use lpp.lpp_cna.all;	23	use lpp.lpp_cna.all;
24		24
25	Library UNISIM;	25	Library UNISIM;
26	use UNISIM.vcomponents.all;	26	use UNISIM.vcomponents.all;
27		27
28		28
@@ -43,17 +43,32 entity BeagleSynth is
43	clktech : integer := CFG_CLKTECH	43	clktech : integer := CFG_CLKTECH
44	);	44	);
45	port (	45	port (
46	reset : in std_ulogic;	46	reset : in std_ulogic;
47	clk : in std_ulogic;	47	clk : in std_ulogic;
48	DAC_nCLR : out std_ulogic;	48	DAC_nCLR : out std_ulogic;
49	DAC_nCS : out std_ulogic;	49	DAC_nCS : out std_ulogic;
50	CAL_IN_SCK : out std_ulogic;	50	CAL_IN_SCK : out std_ulogic;
51	DAC_SDI : out std_logic_vector(7 downto 0);	51	DAC_SDI : out std_logic_vector(7 downto 0);
52	TXD : out std_ulogic;	52	TXD : out std_ulogic;
53	RXD : in std_ulogic;	53	RXD : in std_ulogic;
54	urxd1 : in std_ulogic;	54	urxd1 : in std_ulogic;
55	utxd1 : out std_ulogic;	55	utxd1 : out std_ulogic;
56	LED : out std_ulogic_vector(2 downto 0);	56	LED : out std_ulogic_vector(2 downto 0);
		57	--------------------------------------------------------
		58	---- Beaglebone GPMC
		59	--------------------------------------------------------
		60	GPMC_AD : inout std_logic_vector(15 downto 0);
		61	GPMC_A : in std_logic_vector(19 downto 0);
		62	GPMC_CLK_MUX0 : in std_ulogic;
		63	GPMC_WEN : in std_ulogic;
		64	GPMC_OEN_REN : in std_ulogic;
		65	GPMC_ADVN_ALE : in std_ulogic;
		66	GPMC_CSN : in std_ulogic_vector(2 downto 0);
		67	GPMC_BE0N_CLE : in std_ulogic;
		68	GPMC_BE1N : in std_ulogic;
		69	GPMC_WAIT0 : in std_ulogic;
		70	GPMC_WPN : in std_ulogic;
		71
57	--------------------------------------------------------	72	--------------------------------------------------------
58	---- SDRAM	73	---- SDRAM
59	---- For SDRAM config have a look on leon3-altera-ep1c20	74	---- For SDRAM config have a look on leon3-altera-ep1c20
@@ -127,6 +142,7 signal smpclk : std_logic;
127	signal smpclk_reg : std_logic;	142	signal smpclk_reg : std_logic;
128	signal DAC_SDO : std_logic;	143	signal DAC_SDO : std_logic;
129		144
		145	signal gpmc_clk : std_logic;
130	begin	146	begin
131		147
132	DAC_nCLR <= '1';	148	DAC_nCLR <= '1';
@@ -323,6 +339,24 elsif clkm'event and clkm = '1' then
323	end if;	339	end if;
324	end process;	340	end process;
325		341
		342	gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
		343	GPMCS0: entity work.GPMC_SLAVE
		344	generic map(memtech,padtech)
		345	Port map(
		346	clk => clkm,
		347	reset => rstn,
		348	GPMC_AD => GPMC_AD,
		349	GPMC_A => GPMC_A,
		350	GPMC_CLK_MUX0 => gpmc_clk,
		351	GPMC_WEN => GPMC_WEN,
		352	GPMC_OEN_REN => GPMC_OEN_REN,
		353	GPMC_ADVN_ALE => GPMC_ADVN_ALE,
		354	GPMC_CSN => GPMC_CSN,
		355	GPMC_BE0N_CLE => GPMC_BE0N_CLE,
		356	GPMC_BE1N => GPMC_BE1N,
		357	GPMC_WAIT0 => GPMC_WAIT0,
		358	GPMC_WPN => GPMC_WAIT0
		359	);
326		360
327	end rtl;	361	end rtl;
328		362

designs/BeagleSynth/Makefile +1 -1

             VHDLSYNFILES= \
-            	config.vhd  BeagleSynth.vhd BeagleSynth_MCTRL.vhd
+            	config.vhd  BeagleSynth.vhd BeagleSynth_MCTRL.vhd GPMC_SLAVE.vhd
             #VHDLSIMFILES=testbench.vhd
             #SIMTOP=testbench
             #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc

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