HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r273:8decc2aa17b6

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designs/BeagleSynth/GPMC_SLAVE.vhd created 644 +100 0

@@ -0,0 +1,100
	1	----------------------------------------------------------------------------------
	2	-- Company:
	3	-- Engineer:
	4	--
	5	-- Create Date: 15:20:11 12/08/2013
	6	-- Design Name:
	7	-- Module Name: GPMC_SLAVE - Behavioral
	8	-- Project Name:
	9	-- Target Devices:
	10	-- Tool versions:
	11	-- Description:
	12	--
	13	-- Dependencies:
	14	--
	15	-- Revision:
	16	-- Revision 0.01 - File Created
	17	-- Additional Comments:
	18	--
	19	----------------------------------------------------------------------------------
	20	library IEEE;
	21	use IEEE.STD_LOGIC_1164.ALL;
	22	use IEEE.numeric_std.all;
	23	library grlib, techmap;
	24	use grlib.stdlib.all;
	25	use techmap.gencomp.all;
	26	use techmap.allclkgen.all;
	27	library lpp;
	28	use lpp.general_purpose.all;
	29
	30	entity GPMC_SLAVE is
	31	generic (
	32	memtech : integer := 0;
	33	padtech : integer := 0
	34	);
	35	Port (
	36	clk : in STD_LOGIC;
	37	reset : in STD_LOGIC;
	38	GPMC_AD : inout std_logic_vector(15 downto 0);
	39	GPMC_A : in std_logic_vector(19 downto 0);
	40	GPMC_CLK_MUX0 : in std_ulogic;
	41	GPMC_WEN : in std_ulogic;
	42	GPMC_OEN_REN : in std_ulogic;
	43	GPMC_ADVN_ALE : in std_ulogic;
	44	GPMC_CSN : in std_ulogic_vector(2 downto 0);
	45	GPMC_BE0N_CLE : in std_ulogic;
	46	GPMC_BE1N : in std_ulogic;
	47	GPMC_WAIT0 : in std_ulogic;
	48	GPMC_WPN : in std_ulogic
	49	);
	50	end GPMC_SLAVE;
	51
	52	architecture Behavioral of GPMC_SLAVE is
	53	constant VectInit : std_logic_vector(15 downto 0):=(others => '0');
	54
	55	signal data_out :std_logic_vector(15 downto 0);
	56	signal data_in :std_logic_vector(15 downto 0);
	57
	58	type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0);
	59	signal RAMarray : RAMarrayT:=(others => VectInit);
	60	signal ramindex : integer range 0 to 255;
	61
	62	begin
	63
	64	data_pad : iopadv generic map (tech=> padtech,width => 16)
	65	port map (
	66	pad => GPMC_AD(15 downto 0),
	67	o => data_in(15 downto 0),
	68	en => GPMC_OEN_REN,
	69	i => data_out(15 downto 0)
	70	);
	71
	72	process(reset,GPMC_CLK_MUX0)
	73	begin
	74	if reset = '0' then
	75	data_out <= (others => '0');
	76	ramindex <= 0;
	77	elsif GPMC_CLK_MUX0'event and GPMC_CLK_MUX0 = '1' then
	78	ramindex <= to_integer(unsigned(GPMC_A));
	79	data_out <= RAMarray(ramindex);
	80	if GPMC_WEN = '0' then
	81	RAMarray(ramindex) <= data_in;
	82	end if;
	83	end if;
	84	end process;
	85
	86	end Behavioral;
	87
	88
	89
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	100

boards/BeagleSynth/default.ucf +65 -7

             NET "CLK"      CLOCK_DEDICATED_ROUTE = FALSE;
             NET "CLK"              LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL;
             NET "CLKM" TNM_NET = "clkm_net";
             TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;
             NET "RESET"    CLOCK_DEDICATED_ROUTE = FALSE;
             NET "RESET"            LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL;
             NET "DAC_nCLR"     LOC = "R11" | IOSTANDARD=LVTTL;
             NET "DAC_nCS"      LOC = "T12" | IOSTANDARD=LVTTL;
             NET "CAL_IN_SCK"   LOC = "R13" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(0)"   LOC = "P5" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(1)"   LOC = "M5" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(2)"   LOC = "C8" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(3)"   LOC = "M6" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(4)"   LOC = "K22" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(5)"   LOC = "L22" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(6)"   LOC = "G19" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(7)"   LOC = "F20" | IOSTANDARD=LVTTL;
             NET "TXD"          LOC = "V22"| slew=FAST  | IOSTANDARD=LVTTL;
             NET "RXD"          LOC = "U22"| slew=FAST  | IOSTANDARD=LVTTL;
             NET "LED(0)"       LOC = "AB9"| slew=FAST  | IOSTANDARD=LVTTL;
             NET "LED(1)"       LOC = "AB8"| slew=FAST  | IOSTANDARD=LVTTL;
             NET "LED(2)"       LOC = "AA8"| slew=FAST  | IOSTANDARD=LVTTL;
             NET "urxd1"        LOC = "D3" | IOSTANDARD=LVTTL; # Unused PIN
             NET "utxd1"        LOC = "C4" | IOSTANDARD=LVTTL; # Unused PIN
             NET "sdcke"        LOC = "B6" | slew=FAST | IOSTANDARD=LVTTL; # clk en
             NET "sdcsn"        LOC = "G20"| slew=FAST | IOSTANDARD=LVTTL; # chip sel
             NET "sdwen"        LOC = "D14"| slew=FAST | IOSTANDARD=LVTTL; # write en
             NET "sdrasn"       LOC = "H19"| slew=FAST | IOSTANDARD=LVTTL; # row addr stb
             NET "sdcasn"       LOC = "C14"| slew=FAST | IOSTANDARD=LVTTL; # col addr stb
             NET "sddqm(3)"     LOC = "A5" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
             NET "sddqm(2)"     LOC = "D21"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
             NET "sddqm(1)"     LOC = "C7" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
             NET "sddqm(0)"     LOC = "D15"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
             NET "sdclk"    CLOCK_DEDICATED_ROUTE = FALSE;
             NET "sdclk"        LOC = "A6" | slew=FAST  | IOSTANDARD=LVTTL; # sdram clk output
             NET "sdba(1)"      LOC = "J20"| slew=FAST  | IOSTANDARD=LVTTL; # bank select address
             NET "sdba(0)"      LOC = "G16"| slew=FAST  | IOSTANDARD=LVTTL; # bank select address
             NET "Address(11)"  LOC = "H8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(10)"  LOC = "G7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(9)"   LOC = "K7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(8)"   LOC = "H6"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(7)"   LOC = "H5"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(6)"   LOC = "K8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(5)"   LOC = "G4"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(4)"   LOC = "H3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(3)"   LOC = "D2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(2)"   LOC = "B3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(1)"   LOC = "A2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(0)"   LOC = "C22"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Data(31)"     LOC = "C5" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(30)"     LOC = "A4" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(29)"     LOC = "A3" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(28)"     LOC = "B2" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(27)"     LOC = "B1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(26)"     LOC = "C1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(25)"     LOC = "D1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(24)"     LOC = "E1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(23)"     LOC = "J22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(22)"     LOC = "H22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(21)"     LOC = "H21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(20)"     LOC = "G22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(19)"     LOC = "F22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(18)"     LOC = "F21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(17)"     LOC = "E22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(16)"     LOC = "D22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(15)"     LOC = "A7" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(14)"     LOC = "B8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(13)"     LOC = "A8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(12)"     LOC = "C9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(11)"     LOC = "A9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(10)"     LOC = "B10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(9)"      LOC = "A10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(8)"      LOC = "C11"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(7)"      LOC = "A13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(6)"      LOC = "C13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(5)"      LOC = "B22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(4)"      LOC = "B21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(3)"      LOC = "B20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(2)"      LOC = "A20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(1)"      LOC = "B18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(0)"      LOC = "A18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
+            NET "GPMC_AD(0)"   LOC = "M1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(1)"   LOC = "M2"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(2)"   LOC = "AB3"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(3)"   LOC = "AB2"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(4)"   LOC = "N1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(5)"   LOC = "N3"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(6)"   LOC = "AB5"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(7)"   LOC = "AB4"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(8)"   LOC = "R1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(9)"   LOC = "V1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(10)"  LOC = "U3"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(11)"  LOC = "T1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(12)"  LOC = "V2"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(13)"  LOC = "W1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(14)"  LOC = "T2"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_AD(15)"  LOC = "U1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(0)"    LOC = "N4"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(1)"    LOC = "N6"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(2)"    LOC = "P3"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(3)"    LOC = "P4"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(4)"    LOC = "R4"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(5)"    LOC = "T5"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(6)"    LOC = "T6"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(7)"    LOC = "T3"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(8)"    LOC = "L1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(9)"    LOC = "K1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(10)"   LOC = "L3"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(11)"   LOC = "K2"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(12)"   LOC = "F1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(13)"   LOC = "F2"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(14)"   LOC = "G3"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(15)"   LOC = "H2"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(16)"   LOC = "G1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(17)"   LOC = "H1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(18)"   LOC = "J1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_A(19)"   LOC = "J3"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_CLK_MUX0"    CLOCK_DEDICATED_ROUTE = FALSE;
+            NET "GPMC_CLK_MUX0"   LOC = "R3"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_WEN"        LOC = "W3"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_OEN_REN"    LOC = "Y2"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_ADVN_ALE"   LOC = "AA2"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_CSN(0)"     LOC = "M3"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_CSN(1)"     LOC = "P1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_CSN(2)"     LOC = "P2"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_BE0N_CLE"   LOC = "Y1"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_BE1N"       LOC = "AB21"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_WAIT0"      LOC = "AA21"| slew=FAST | IOSTANDARD=LVTTL;
+            NET "GPMC_WPN"        LOC = "W22"| slew=FAST | IOSTANDARD=LVTTL;

designs/BeagleSynth/BeagleSynth.vhd +46 -12

             library ieee;
             use ieee.std_logic_1164.all;
             use IEEE.numeric_std.all;
             library grlib, techmap;
             use grlib.amba.all;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use techmap.gencomp.all;
             use techmap.allclkgen.all;
             library gaisler;
             use gaisler.memctrl.all;
             use gaisler.leon3.all;
             use gaisler.uart.all;
             use gaisler.misc.all;
             library esa;
             use esa.memoryctrl.all;
             --use gaisler.sim.all;
             library lpp;
             use lpp.lpp_ad_conv.all;
             use lpp.lpp_amba.all;
             use lpp.apb_devices_list.all;
             use lpp.general_purpose.all;
             use lpp.lpp_cna.all;
             Library UNISIM;
             use UNISIM.vcomponents.all;
             use work.config.all;
             --==================================================================
             --
             --
             --			FPGA FREQ = 100MHz
             --
             --
             --==================================================================
             entity BeagleSynth is
               generic (
                 fabtech       : integer := CFG_FABTECH;
                 memtech       : integer := CFG_MEMTECH;
                 padtech       : integer := CFG_PADTECH;
                 clktech       : integer := CFG_CLKTECH
               );
               port (
-                reset         : in  std_ulogic;
+                     reset         : in  std_ulogic;
-                clk           : in  std_ulogic;
+                     clk           : in  std_ulogic;
-            	 DAC_nCLR		: out std_ulogic;
+                     DAC_nCLR      : out std_ulogic;
-            	 DAC_nCS       : out std_ulogic;
+                     DAC_nCS       : out std_ulogic;
-            	 CAL_IN_SCK		: out std_ulogic;
+                     CAL_IN_SCK    : out std_ulogic;
-            	 DAC_SDI			: out std_logic_vector(7 downto 0);
+                     DAC_SDI       : out std_logic_vector(7 downto 0);
-            	 TXD				: out std_ulogic;
+                     TXD           : out std_ulogic;
-            	 RXD				: in  std_ulogic;
+                     RXD           : in  std_ulogic;
-            	 urxd1	      : in  std_ulogic;
+                     urxd1         : in  std_ulogic;
-            	 utxd1         : out std_ulogic;
+                     utxd1         : out std_ulogic;
-            	 LED				: out std_ulogic_vector(2 downto 0);
+                     LED           : out std_ulogic_vector(2 downto 0);
+            --------------------------------------------------------
+            ----       Beaglebone GPMC
+            --------------------------------------------------------
+                    GPMC_AD       : inout std_logic_vector(15 downto 0);
+                    GPMC_A        : in  std_logic_vector(19 downto 0);
+                    GPMC_CLK_MUX0 : in  std_ulogic;
+                    GPMC_WEN      : in  std_ulogic;
+                    GPMC_OEN_REN  : in  std_ulogic;
+                    GPMC_ADVN_ALE : in  std_ulogic;
+                    GPMC_CSN      : in  std_ulogic_vector(2 downto 0);
+                    GPMC_BE0N_CLE : in  std_ulogic;
+                    GPMC_BE1N     : in  std_ulogic;
+                    GPMC_WAIT0    : in  std_ulogic;
+                    GPMC_WPN      : in  std_ulogic;
             --------------------------------------------------------
             ----       SDRAM
             ---- For SDRAM config have a look on leon3-altera-ep1c20
             ---- design from GRLIB, the  IS42S32400E is similar to
             ---- MT48LC4M32B2.
             --------------------------------------------------------
             	 sdcke         : out std_logic; -- clk en
             	 sdcsn         : out std_logic; -- chip sel
             	 sdwen         : out std_logic;                      -- write en
             	 sdrasn        : out std_logic;                      -- row addr stb
             	 sdcasn        : out std_logic;                      -- col addr stb
             	 sddqm         : out std_logic_vector (3 downto 0);  -- data i/o mask
             	 sdclk         : out std_logic;                      -- sdram clk output
             	 sdba          : out std_logic_vector (1 downto 0);  -- bank select address
             	 Address       : out std_logic_vector(11 downto 0);  -- sdram address
             	 Data          : inout std_logic_vector(31 downto 0) -- optional sdram data
             	 );
             end;
             architecture rtl of BeagleSynth is
             constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
             	CFG_GRETH+CFG_AHB_JTAG;
             constant maxahbm : integer := maxahbmsp;
             constant IOAEN  : integer := CFG_CAN;
             constant boardfreq : integer := 100000;
             signal clk2x    : std_ulogic;
             signal lclk     : std_ulogic;
             signal clkm     : std_ulogic;
             signal rstn     : std_ulogic;
             signal rst      : std_ulogic;
             signal rstraw   : std_ulogic;
             signal pciclk   : std_ulogic;
             signal sdclkl   : std_ulogic;
             signal sdclkl_DDR2   : std_ulogic;
             signal cgi      : clkgen_in_type;
             signal cgo      : clkgen_out_type;
             --- AHB / APB
             signal apbi     : apb_slv_in_type;
             signal apbo     : apb_slv_out_vector := (others => apb_none);
             signal ahbsi    : ahb_slv_in_type;
             signal ahbso    : ahb_slv_out_vector := (others => ahbs_none);
             signal ahbmi    : ahb_mst_in_type;
             signal ahbmo    : ahb_mst_out_vector := (others => ahbm_none);
             --- MEM CTRLR
             signal sdi : sdctrl_in_type;
             signal sdo : sdctrl_out_type;
             --UART
             signal ahbuarti : uart_in_type;
             signal ahbuarto : uart_out_type;
             signal apbuarti : uart_in_type;
             signal apbuarto : uart_out_type;
             signal led2int  : std_logic;
             signal DAC0_DATA	 : std_logic_vector(15 downto 0);
             signal DAC1_DATA	 : std_logic_vector(15 downto 0);
             signal DAC2_DATA	 : std_logic_vector(15 downto 0);
             signal DAC3_DATA	 : std_logic_vector(15 downto 0);
             signal DAC4_DATA	 : std_logic_vector(15 downto 0);
             signal DAC5_DATA	 : std_logic_vector(15 downto 0);
             signal DAC6_DATA	 : std_logic_vector(15 downto 0);
             signal DAC7_DATA	 : std_logic_vector(15 downto 0);
             signal DAC_DATA    : CNA_16bit_T(7 downto 0,15 downto 0);
             signal smpclk      : std_logic;
             signal smpclk_reg  : std_logic;
             signal DAC_SDO	    : std_logic;
+            signal gpmc_clk    : std_logic;
             begin
             DAC_nCLR		<= '1';
             --DAC_nCS     <= SYNC;
             --CAL_IN_SCK  <= '1';
             --DAC_SDI		<= (others =>'1');
             resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
               rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
               --rstn	<= reset;
               --lclk <= clk;
               clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
               cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
               clkgen0 : clkgen  		-- clock generator
                 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
                 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
             --  sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
             --sdclk <= sdclkl;
             sdclk <= sdclkl_DDR2;
             LED(1)  <= not cgo.clklock;
             LED(0)  <= cgo.clklock;
             ODDR2_inst : ODDR2
                generic map(
                   DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
                   INIT => '0', -- Sets initial state of the Q output to '0' or '1'
                   SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
                port map (
                   Q => sdclkl_DDR2, -- 1-bit output data
                   C0 => sdclkl, -- 1-bit clock input
                   C1 => not sdclkl, -- 1-bit clock input
                   CE => '1',  -- 1-bit clock enable input
                   D0 => '1',   -- 1-bit data input (associated with C0)
                   D1 => '0',   -- 1-bit data input (associated with C1)
                   R =>  '0',    -- 1-bit reset input
                   S => '0'     -- 1-bit set input
                );
             ----------------------------------------------------------------------
             ---  AHB CONTROLLER  -------------------------------------------------
             ----------------------------------------------------------------------
               ahb0 : ahbctrl 		-- AHB arbiter/multiplexer
               generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
             	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
             	ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
               port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
             ----------------------------------------------------------------------
             ---  AHB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               dcomgen : if CFG_AHB_UART = 1 generate
                 dcom0: ahbuart		-- Debug UART
                 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
                 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
                 ahbuarti.rxd  <= RXD;
                 TXD           <= ahbuarto.txd;
               end generate;
               nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
             ----------------------------------------------------------------------
             ---  APB Bridge  -----------------------------------------------------
             ----------------------------------------------------------------------
               apb0 : apbctrl				-- AHB/APB bridge
               generic map (hindex => 1, haddr => CFG_APBADDR)
               port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
             ----------------------------------------------------------------------
             ---  APB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               ua1 : if CFG_UART1_ENABLE /= 0 generate
                 uart1 : apbuart			-- UART 1
                 generic map (pindex => 1, paddr => 1,  pirq => 2, console => CFG_DUART,
             	fifosize => CFG_UART1_FIFO)
                 port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
                 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
                 apbuarti.ctsn <= '0';
               end generate;
               noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
             --div0: Clk_divider
             --	 generic map( 100000000,1)
             --    Port map( clkm,rstn,LED(2));
             LED(2) <= led2int;
             process(clkm,rstn)
             begin
             	if rstn = '0' then
             		led2int <= '0';
             	elsif clkm'event and clkm='1' then
             		led2int <= not led2int;
             	end if;
             end process;
             sdc : sdctrl
                generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0,
             	invclk => 0,sdbits =>32)
             	port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo);
             --Alternative data pad instantiation with vectored bdrive
             sd_pad : iopadvv generic map (tech=> padtech,width => 32)
             port map (
               data(31 downto 0),
               sdo.data(31 downto 0),
               sdo.vbdrive(31 downto 0),
               sdi.data(31 downto 0));
             -- connect memory controller outputs to entity output signals
             Address <= sdo.address(13 downto 2);
             --sdba	  <= sdo.address(16 downto 15);
             sdba	  <= "00";
             sdcke <= sdo.sdcke(0);
             sdwen <= sdo.sdwen;
             sdcsn <= sdo.sdcsn(0);
             sdrasn <= sdo.rasn;
             sdcasn <= sdo.casn;
             sddqm <= sdo.dqm(3 downto 0);
             DAC0 :  DAC8581
                 generic map(100,8)
                 Port map(
             	        clk =>      clkm,
                        rstn =>     rstn,
                        smpclk =>   smpclk,
                        sclk =>     CAL_IN_SCK,
                        csn =>		  DAC_nCS,
                        sdo =>      DAC_SDI,
                        smp_in =>   DAC_DATA
             			  );
               smpclk0: Clk_divider
                 GENERIC map(OSC_freqHz  => 50000000,
                         TargetFreq_Hz   => 256000)
                 PORT map( clk          =>  clkm,
                        reset        =>  rstn,
                        clk_divided  =>  smpclk
             			  );
             all_bits: FOR I in 15 downto 0 GENERATE
             	DAC_DATA(0,I) <= DAC0_DATA(I);
             	DAC_DATA(1,I) <= DAC1_DATA(I);
             	DAC_DATA(2,I) <= DAC2_DATA(I);
             	DAC_DATA(3,I) <= DAC3_DATA(I);
             	DAC_DATA(4,I) <= DAC4_DATA(I);
             	DAC_DATA(5,I) <= DAC5_DATA(I);
             	DAC_DATA(6,I) <= DAC6_DATA(I);
             	DAC_DATA(7,I) <= DAC7_DATA(I);
             end GENERATE;
             process(clkm,rstn)
             begin
             if rstn ='0' then
             	DAC0_DATA	<= X"0000";
             	DAC1_DATA	<= X"0000";
             	DAC2_DATA	<= X"0000";
             	DAC3_DATA	<= X"0000";
             	DAC4_DATA	<= X"0000";
             	DAC5_DATA	<= X"0000";
             	DAC6_DATA	<= X"0000";
             	DAC7_DATA	<= X"0000";
             	smpclk_reg	<= smpclk;
             elsif clkm'event and clkm = '1' then
             	smpclk_reg <= smpclk;
             	if smpclk_reg = '0' and smpclk = '1' then
             		DAC0_DATA <= std_logic_vector( UNSIGNED(DAC0_DATA) +1);
             		DAC1_DATA <= std_logic_vector( UNSIGNED(DAC1_DATA) +2);
             		DAC2_DATA <= std_logic_vector( UNSIGNED(DAC2_DATA) +3);
             		DAC3_DATA <= std_logic_vector( UNSIGNED(DAC3_DATA) +4);
             		DAC4_DATA <= std_logic_vector( UNSIGNED(DAC4_DATA) +5);
             		DAC5_DATA <= std_logic_vector( UNSIGNED(DAC5_DATA) +6);
             		DAC6_DATA <= std_logic_vector( UNSIGNED(DAC6_DATA) +7);
             		DAC7_DATA <= std_logic_vector( UNSIGNED(DAC7_DATA) +8);
             --		DAC_DATA <= "0100000000000000";
             	end if;
             end if;
             end process;
+            gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
+            GPMCS0: entity work.GPMC_SLAVE
+              generic map(memtech,padtech)
+                Port map(
+            	     clk           => clkm,
+                    reset         => rstn,
+                    GPMC_AD       => GPMC_AD,
+                    GPMC_A        => GPMC_A,
+                    GPMC_CLK_MUX0 => gpmc_clk,
+                    GPMC_WEN      => GPMC_WEN,
+                    GPMC_OEN_REN  => GPMC_OEN_REN,
+                    GPMC_ADVN_ALE => GPMC_ADVN_ALE,
+                    GPMC_CSN      => GPMC_CSN,
+                    GPMC_BE0N_CLE => GPMC_BE0N_CLE,
+                    GPMC_BE1N     => GPMC_BE1N,
+                    GPMC_WAIT0    => GPMC_WAIT0,
+                    GPMC_WPN      => GPMC_WAIT0
+            		  );
             end rtl;

designs/BeagleSynth/Makefile +1 -1

             include .config
             #GRLIB=$(GRLIB)
             TOP=BeagleSynth
             BOARD=BeagleSynth
             #BOARD=SP601
             include ../../boards/$(BOARD)/Makefile.inc
             DEVICE=$(PART)-$(PACKAGE)$(SPEED)
             #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
             UCF=../../boards/$(BOARD)/default.ucf
             QSF=../../boards/$(BOARD)/$(TOP).qsf
             EFFORT=high
             ISEMAPOPT="-timing"
             XSTOPT=""
             SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
             VHDLOPTSYNFILES=
             VHDLSYNFILES= \
-            	config.vhd  BeagleSynth.vhd BeagleSynth_MCTRL.vhd
+            	config.vhd  BeagleSynth.vhd BeagleSynth_MCTRL.vhd GPMC_SLAVE.vhd
             #VHDLSIMFILES=testbench.vhd
             #SIMTOP=testbench
             #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
             SDCFILE=default.sdc
             BITGEN=../../boards/$(BOARD)/default.ut
             CLEAN=soft-clean
             VCOMOPT=-explicit
             TECHLIBS = secureip unisim
             LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
             	tmtc openchip cypress ihp gleichmann gsi fmf spansion
             DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
             	leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
             	ac97 hcan usb
             DIRADD =
             FILEADD =
             FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
             include $(GRLIB)/bin/Makefile
             include $(GRLIB)/software/leon3/Makefile
             ##################  project specific targets ##########################
             flash:
             	xc3sprog -c ftdi -p 1 BeagleSynth.bit
             ram:
             	xc3sprog -c ftdi -p 0 BeagleSynth.bit

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