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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library grlib, techmap;
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use grlib.amba.all;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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library esa;
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use esa.memoryctrl.all;
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--use gaisler.sim.all;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.general_purpose.all;
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use lpp.lpp_cna.all;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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use work.config.all;
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--==================================================================
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--
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--
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-- FPGA FREQ = 100MHz
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--
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--
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--==================================================================
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entity BeagleSynth is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH
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);
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port (
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reset : in std_ulogic;
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clk : in std_ulogic;
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DAC_nCLR : out std_ulogic;
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DAC_nCS : out std_ulogic;
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CAL_IN_SCK : out std_ulogic;
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DAC_SDI : out std_logic_vector(7 downto 0);
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TXD : out std_ulogic;
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RXD : in std_ulogic;
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urxd1 : in std_ulogic;
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utxd1 : out std_ulogic;
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LED : out std_ulogic_vector(2 downto 0);
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--------------------------------------------------------
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---- SDRAM
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---- For SDRAM config have a look on leon3-altera-ep1c20
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---- design from GRLIB, the IS42S32400E is similar to
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---- MT48LC4M32B2.
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--------------------------------------------------------
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sdcke : out std_logic; -- clk en
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sdcsn : out std_logic; -- chip sel
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sdwen : out std_logic; -- write en
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sdrasn : out std_logic; -- row addr stb
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sdcasn : out std_logic; -- col addr stb
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sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
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sdclk : out std_logic; -- sdram clk output
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sdba : out std_logic_vector (1 downto 0); -- bank select address
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Address : out std_logic_vector(11 downto 0); -- sdram address
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Data : inout std_logic_vector(31 downto 0) -- optional sdram data
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);
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end;
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architecture rtl of BeagleSynth is
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constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
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CFG_GRETH+CFG_AHB_JTAG;
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constant maxahbm : integer := maxahbmsp;
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constant IOAEN : integer := CFG_CAN;
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constant boardfreq : integer := 100000;
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signal clk2x : std_ulogic;
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signal lclk : std_ulogic;
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signal clkm : std_ulogic;
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signal rstn : std_ulogic;
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signal rst : std_ulogic;
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signal rstraw : std_ulogic;
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signal pciclk : std_ulogic;
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signal sdclkl : std_ulogic;
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signal sdclkl_DDR2 : std_ulogic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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--- AHB / APB
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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--- MEM CTRLR
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signal sdi : sdctrl_in_type;
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signal sdo : sdctrl_out_type;
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--UART
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signal ahbuarti : uart_in_type;
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signal ahbuarto : uart_out_type;
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signal apbuarti : uart_in_type;
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signal apbuarto : uart_out_type;
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signal led2int : std_logic;
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signal DAC0_DATA : std_logic_vector(15 downto 0);
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signal DAC1_DATA : std_logic_vector(15 downto 0);
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signal DAC2_DATA : std_logic_vector(15 downto 0);
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signal DAC3_DATA : std_logic_vector(15 downto 0);
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signal DAC4_DATA : std_logic_vector(15 downto 0);
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signal DAC5_DATA : std_logic_vector(15 downto 0);
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signal DAC6_DATA : std_logic_vector(15 downto 0);
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signal DAC7_DATA : std_logic_vector(15 downto 0);
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signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
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signal smpclk : std_logic;
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signal smpclk_reg : std_logic;
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signal DAC_SDO : std_logic;
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begin
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DAC_nCLR <= '1';
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--DAC_nCS <= SYNC;
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--CAL_IN_SCK <= '1';
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--DAC_SDI <= (others =>'1');
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resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
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rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
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--rstn <= reset;
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--lclk <= clk;
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clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
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cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
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clkgen0 : clkgen -- clock generator
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generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
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port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
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-- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
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--sdclk <= sdclkl;
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sdclk <= sdclkl_DDR2;
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LED(1) <= not cgo.clklock;
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LED(0) <= cgo.clklock;
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ODDR2_inst : ODDR2
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generic map(
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DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
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INIT => '0', -- Sets initial state of the Q output to '0' or '1'
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SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
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port map (
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Q => sdclkl_DDR2, -- 1-bit output data
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C0 => sdclkl, -- 1-bit clock input
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C1 => not sdclkl, -- 1-bit clock input
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CE => '1', -- 1-bit clock enable input
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D0 => '1', -- 1-bit data input (associated with C0)
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D1 => '0', -- 1-bit data input (associated with C1)
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R => '0', -- 1-bit reset input
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S => '0' -- 1-bit set input
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);
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----------------------------------------------------------------------
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--- AHB CONTROLLER -------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
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ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
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port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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--- AHB UART -------------------------------------------------------
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----------------------------------------------------------------------
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dcomgen : if CFG_AHB_UART = 1 generate
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dcom0: ahbuart -- Debug UART
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generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
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port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
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ahbuarti.rxd <= RXD;
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TXD <= ahbuarto.txd;
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end generate;
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nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
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----------------------------------------------------------------------
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--- APB Bridge -----------------------------------------------------
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----------------------------------------------------------------------
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apb0 : apbctrl -- AHB/APB bridge
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generic map (hindex => 1, haddr => CFG_APBADDR)
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port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
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----------------------------------------------------------------------
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--- APB UART -------------------------------------------------------
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----------------------------------------------------------------------
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ua1 : if CFG_UART1_ENABLE /= 0 generate
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uart1 : apbuart -- UART 1
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generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
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fifosize => CFG_UART1_FIFO)
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port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
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apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
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apbuarti.ctsn <= '0';
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end generate;
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noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
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--div0: Clk_divider
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-- generic map( 100000000,1)
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-- Port map( clkm,rstn,LED(2));
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LED(2) <= led2int;
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process(clkm,rstn)
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begin
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if rstn = '0' then
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led2int <= '0';
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elsif clkm'event and clkm='1' then
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led2int <= not led2int;
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end if;
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end process;
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sdc : sdctrl
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generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0,
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invclk => 0,sdbits =>32)
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port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo);
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--Alternative data pad instantiation with vectored bdrive
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sd_pad : iopadvv generic map (tech=> padtech,width => 32)
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port map (
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data(31 downto 0),
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sdo.data(31 downto 0),
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sdo.vbdrive(31 downto 0),
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sdi.data(31 downto 0));
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-- connect memory controller outputs to entity output signals
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Address <= sdo.address(13 downto 2);
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--sdba <= sdo.address(16 downto 15);
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sdba <= "00";
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sdcke <= sdo.sdcke(0);
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sdwen <= sdo.sdwen;
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sdcsn <= sdo.sdcsn(0);
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sdrasn <= sdo.rasn;
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sdcasn <= sdo.casn;
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sddqm <= sdo.dqm(3 downto 0);
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DAC0 : DAC8581
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generic map(100,8)
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Port map(
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clk => clkm,
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rstn => rstn,
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smpclk => smpclk,
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sclk => CAL_IN_SCK,
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csn => DAC_nCS,
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sdo => DAC_SDI,
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smp_in => DAC_DATA
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);
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smpclk0: Clk_divider
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GENERIC map(OSC_freqHz => 50000000,
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TargetFreq_Hz => 256000)
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PORT map( clk => clkm,
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reset => rstn,
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clk_divided => smpclk
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);
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all_bits: FOR I in 15 downto 0 GENERATE
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DAC_DATA(0,I) <= DAC0_DATA(I);
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DAC_DATA(1,I) <= DAC1_DATA(I);
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DAC_DATA(2,I) <= DAC2_DATA(I);
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DAC_DATA(3,I) <= DAC3_DATA(I);
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DAC_DATA(4,I) <= DAC4_DATA(I);
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DAC_DATA(5,I) <= DAC5_DATA(I);
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DAC_DATA(6,I) <= DAC6_DATA(I);
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DAC_DATA(7,I) <= DAC7_DATA(I);
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end GENERATE;
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process(clkm,rstn)
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begin
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if rstn ='0' then
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DAC0_DATA <= X"0000";
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DAC1_DATA <= X"0000";
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DAC2_DATA <= X"0000";
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DAC3_DATA <= X"0000";
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DAC4_DATA <= X"0000";
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DAC5_DATA <= X"0000";
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DAC6_DATA <= X"0000";
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DAC7_DATA <= X"0000";
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smpclk_reg <= smpclk;
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elsif clkm'event and clkm = '1' then
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smpclk_reg <= smpclk;
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if smpclk_reg = '0' and smpclk = '1' then
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DAC0_DATA <= std_logic_vector( UNSIGNED(DAC0_DATA) +1);
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DAC1_DATA <= std_logic_vector( UNSIGNED(DAC1_DATA) +2);
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DAC2_DATA <= std_logic_vector( UNSIGNED(DAC2_DATA) +3);
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DAC3_DATA <= std_logic_vector( UNSIGNED(DAC3_DATA) +4);
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DAC4_DATA <= std_logic_vector( UNSIGNED(DAC4_DATA) +5);
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DAC5_DATA <= std_logic_vector( UNSIGNED(DAC5_DATA) +6);
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DAC6_DATA <= std_logic_vector( UNSIGNED(DAC6_DATA) +7);
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DAC7_DATA <= std_logic_vector( UNSIGNED(DAC7_DATA) +8);
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-- DAC_DATA <= "0100000000000000";
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end if;
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end if;
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end process;
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end rtl;
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