BeagleSynth.vhd
330 lines
| 9.9 KiB
| text/x-vhdl
|
VhdlLexer
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r255 | library ieee; | ||
use ieee.std_logic_1164.all; | ||||
use IEEE.numeric_std.all; | ||||
library grlib, techmap; | ||||
use grlib.amba.all; | ||||
use grlib.amba.all; | ||||
use grlib.stdlib.all; | ||||
use techmap.gencomp.all; | ||||
use techmap.allclkgen.all; | ||||
library gaisler; | ||||
use gaisler.memctrl.all; | ||||
use gaisler.leon3.all; | ||||
use gaisler.uart.all; | ||||
use gaisler.misc.all; | ||||
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r265 | library esa; | ||
use esa.memoryctrl.all; | ||||
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r255 | --use gaisler.sim.all; | ||
library lpp; | ||||
use lpp.lpp_ad_conv.all; | ||||
use lpp.lpp_amba.all; | ||||
use lpp.apb_devices_list.all; | ||||
use lpp.general_purpose.all; | ||||
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r271 | use lpp.lpp_cna.all; | ||
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r255 | |||
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r265 | Library UNISIM; | ||
use UNISIM.vcomponents.all; | ||||
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r255 | |||
use work.config.all; | ||||
--================================================================== | ||||
-- | ||||
-- | ||||
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r263 | -- FPGA FREQ = 100MHz | ||
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r255 | -- | ||
-- | ||||
--================================================================== | ||||
entity BeagleSynth is | ||||
generic ( | ||||
fabtech : integer := CFG_FABTECH; | ||||
memtech : integer := CFG_MEMTECH; | ||||
padtech : integer := CFG_PADTECH; | ||||
clktech : integer := CFG_CLKTECH | ||||
); | ||||
port ( | ||||
reset : in std_ulogic; | ||||
clk : in std_ulogic; | ||||
DAC_nCLR : out std_ulogic; | ||||
DAC_nCS : out std_ulogic; | ||||
CAL_IN_SCK : out std_ulogic; | ||||
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r271 | DAC_SDI : out std_logic_vector(7 downto 0); | ||
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r263 | TXD : out std_ulogic; | ||
RXD : in std_ulogic; | ||||
urxd1 : in std_ulogic; | ||||
utxd1 : out std_ulogic; | ||||
LED : out std_ulogic_vector(2 downto 0); | ||||
-------------------------------------------------------- | ||||
---- SDRAM | ||||
---- For SDRAM config have a look on leon3-altera-ep1c20 | ||||
---- design from GRLIB, the IS42S32400E is similar to | ||||
---- MT48LC4M32B2. | ||||
-------------------------------------------------------- | ||||
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r265 | sdcke : out std_logic; -- clk en | ||
sdcsn : out std_logic; -- chip sel | ||||
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r263 | sdwen : out std_logic; -- write en | ||
sdrasn : out std_logic; -- row addr stb | ||||
sdcasn : out std_logic; -- col addr stb | ||||
sddqm : out std_logic_vector (3 downto 0); -- data i/o mask | ||||
sdclk : out std_logic; -- sdram clk output | ||||
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r265 | sdba : out std_logic_vector (1 downto 0); -- bank select address | ||
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r263 | Address : out std_logic_vector(11 downto 0); -- sdram address | ||
Data : inout std_logic_vector(31 downto 0) -- optional sdram data | ||||
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r255 | ); | ||
end; | ||||
architecture rtl of BeagleSynth is | ||||
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r263 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ | ||
CFG_GRETH+CFG_AHB_JTAG; | ||||
constant maxahbm : integer := maxahbmsp; | ||||
constant IOAEN : integer := CFG_CAN; | ||||
constant boardfreq : integer := 100000; | ||||
signal clk2x : std_ulogic; | ||||
signal lclk : std_ulogic; | ||||
signal clkm : std_ulogic; | ||||
signal rstn : std_ulogic; | ||||
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r265 | signal rst : std_ulogic; | ||
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r263 | signal rstraw : std_ulogic; | ||
signal pciclk : std_ulogic; | ||||
signal sdclkl : std_ulogic; | ||||
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r265 | signal sdclkl_DDR2 : std_ulogic; | ||
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r263 | signal cgi : clkgen_in_type; | ||
signal cgo : clkgen_out_type; | ||||
--- AHB / APB | ||||
signal apbi : apb_slv_in_type; | ||||
signal apbo : apb_slv_out_vector := (others => apb_none); | ||||
signal ahbsi : ahb_slv_in_type; | ||||
signal ahbso : ahb_slv_out_vector := (others => ahbs_none); | ||||
signal ahbmi : ahb_mst_in_type; | ||||
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); | ||||
--- MEM CTRLR | ||||
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r265 | signal sdi : sdctrl_in_type; | ||
signal sdo : sdctrl_out_type; | ||||
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r263 | |||
--UART | ||||
signal ahbuarti : uart_in_type; | ||||
signal ahbuarto : uart_out_type; | ||||
signal apbuarti : uart_in_type; | ||||
signal apbuarto : uart_out_type; | ||||
signal led2int : std_logic; | ||||
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r255 | |||
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r271 | |||
signal DAC0_DATA : std_logic_vector(15 downto 0); | ||||
signal DAC1_DATA : std_logic_vector(15 downto 0); | ||||
signal DAC2_DATA : std_logic_vector(15 downto 0); | ||||
signal DAC3_DATA : std_logic_vector(15 downto 0); | ||||
signal DAC4_DATA : std_logic_vector(15 downto 0); | ||||
signal DAC5_DATA : std_logic_vector(15 downto 0); | ||||
signal DAC6_DATA : std_logic_vector(15 downto 0); | ||||
signal DAC7_DATA : std_logic_vector(15 downto 0); | ||||
signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0); | ||||
signal smpclk : std_logic; | ||||
signal smpclk_reg : std_logic; | ||||
signal DAC_SDO : std_logic; | ||||
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r255 | begin | ||
DAC_nCLR <= '1'; | ||||
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r271 | --DAC_nCS <= SYNC; | ||
--CAL_IN_SCK <= '1'; | ||||
--DAC_SDI <= (others =>'1'); | ||||
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r255 | |||
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r265 | resetn_pad : inpad generic map (tech => padtech) port map (reset, rst); | ||
rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw); | ||||
--rstn <= reset; | ||||
--lclk <= clk; | ||||
clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk); | ||||
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r263 | |||
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r265 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; | ||
clkgen0 : clkgen -- clock generator | ||||
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq) | ||||
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open); | ||||
-- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2); | ||||
--sdclk <= sdclkl; | ||||
sdclk <= sdclkl_DDR2; | ||||
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r263 | |||
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r269 | LED(1) <= not cgo.clklock; | ||
LED(0) <= cgo.clklock; | ||||
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r265 | ODDR2_inst : ODDR2 | ||
generic map( | ||||
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r269 | DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" | ||
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r265 | INIT => '0', -- Sets initial state of the Q output to '0' or '1' | ||
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r269 | SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset | ||
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r265 | port map ( | ||
Q => sdclkl_DDR2, -- 1-bit output data | ||||
C0 => sdclkl, -- 1-bit clock input | ||||
C1 => not sdclkl, -- 1-bit clock input | ||||
CE => '1', -- 1-bit clock enable input | ||||
D0 => '1', -- 1-bit data input (associated with C0) | ||||
D1 => '0', -- 1-bit data input (associated with C1) | ||||
R => '0', -- 1-bit reset input | ||||
S => '0' -- 1-bit set input | ||||
); | ||||
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r263 | |||
---------------------------------------------------------------------- | ||||
--- AHB CONTROLLER ------------------------------------------------- | ||||
---------------------------------------------------------------------- | ||||
ahb0 : ahbctrl -- AHB arbiter/multiplexer | ||||
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, | ||||
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | ||||
ioen => IOAEN, nahbm => maxahbm, nahbs => 8) | ||||
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | ||||
---------------------------------------------------------------------- | ||||
--- AHB UART ------------------------------------------------------- | ||||
---------------------------------------------------------------------- | ||||
dcomgen : if CFG_AHB_UART = 1 generate | ||||
dcom0: ahbuart -- Debug UART | ||||
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) | ||||
port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); | ||||
ahbuarti.rxd <= RXD; | ||||
TXD <= ahbuarto.txd; | ||||
end generate; | ||||
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; | ||||
---------------------------------------------------------------------- | ||||
--- APB Bridge ----------------------------------------------------- | ||||
---------------------------------------------------------------------- | ||||
apb0 : apbctrl -- AHB/APB bridge | ||||
generic map (hindex => 1, haddr => CFG_APBADDR) | ||||
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); | ||||
---------------------------------------------------------------------- | ||||
--- APB UART ------------------------------------------------------- | ||||
---------------------------------------------------------------------- | ||||
ua1 : if CFG_UART1_ENABLE /= 0 generate | ||||
uart1 : apbuart -- UART 1 | ||||
generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART, | ||||
fifosize => CFG_UART1_FIFO) | ||||
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r265 | port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); | ||
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r263 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; | ||
apbuarti.ctsn <= '0'; | ||||
end generate; | ||||
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; | ||||
--div0: Clk_divider | ||||
-- generic map( 100000000,1) | ||||
-- Port map( clkm,rstn,LED(2)); | ||||
LED(2) <= led2int; | ||||
process(clkm,rstn) | ||||
begin | ||||
if rstn = '0' then | ||||
led2int <= '0'; | ||||
elsif clkm'event and clkm='1' then | ||||
led2int <= not led2int; | ||||
end if; | ||||
end process; | ||||
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r265 | sdc : sdctrl | ||
generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0, | ||||
invclk => 0,sdbits =>32) | ||||
port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo); | ||||
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r263 | |||
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r265 | |||
--Alternative data pad instantiation with vectored bdrive | ||||
sd_pad : iopadvv generic map (tech=> padtech,width => 32) | ||||
port map ( | ||||
data(31 downto 0), | ||||
sdo.data(31 downto 0), | ||||
sdo.vbdrive(31 downto 0), | ||||
sdi.data(31 downto 0)); | ||||
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r263 | |||
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r265 | |||
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r263 | -- connect memory controller outputs to entity output signals | ||
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r265 | Address <= sdo.address(13 downto 2); | ||
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r269 | --sdba <= sdo.address(16 downto 15); | ||
sdba <= "00"; | ||||
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r265 | sdcke <= sdo.sdcke(0); | ||
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r263 | sdwen <= sdo.sdwen; | ||
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r265 | sdcsn <= sdo.sdcsn(0); | ||
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r263 | sdrasn <= sdo.rasn; | ||
sdcasn <= sdo.casn; | ||||
sddqm <= sdo.dqm(3 downto 0); | ||||
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r271 | DAC0 : DAC8581 | ||
generic map(100,8) | ||||
Port map( | ||||
clk => clkm, | ||||
rstn => rstn, | ||||
smpclk => smpclk, | ||||
sclk => CAL_IN_SCK, | ||||
csn => DAC_nCS, | ||||
sdo => DAC_SDI, | ||||
smp_in => DAC_DATA | ||||
); | ||||
smpclk0: Clk_divider | ||||
GENERIC map(OSC_freqHz => 50000000, | ||||
TargetFreq_Hz => 256000) | ||||
PORT map( clk => clkm, | ||||
reset => rstn, | ||||
clk_divided => smpclk | ||||
); | ||||
all_bits: FOR I in 15 downto 0 GENERATE | ||||
DAC_DATA(0,I) <= DAC0_DATA(I); | ||||
DAC_DATA(1,I) <= DAC1_DATA(I); | ||||
DAC_DATA(2,I) <= DAC2_DATA(I); | ||||
DAC_DATA(3,I) <= DAC3_DATA(I); | ||||
DAC_DATA(4,I) <= DAC4_DATA(I); | ||||
DAC_DATA(5,I) <= DAC5_DATA(I); | ||||
DAC_DATA(6,I) <= DAC6_DATA(I); | ||||
DAC_DATA(7,I) <= DAC7_DATA(I); | ||||
end GENERATE; | ||||
process(clkm,rstn) | ||||
begin | ||||
if rstn ='0' then | ||||
DAC0_DATA <= X"0000"; | ||||
DAC1_DATA <= X"0000"; | ||||
DAC2_DATA <= X"0000"; | ||||
DAC3_DATA <= X"0000"; | ||||
DAC4_DATA <= X"0000"; | ||||
DAC5_DATA <= X"0000"; | ||||
DAC6_DATA <= X"0000"; | ||||
DAC7_DATA <= X"0000"; | ||||
smpclk_reg <= smpclk; | ||||
elsif clkm'event and clkm = '1' then | ||||
smpclk_reg <= smpclk; | ||||
if smpclk_reg = '0' and smpclk = '1' then | ||||
DAC0_DATA <= std_logic_vector( UNSIGNED(DAC0_DATA) +1); | ||||
DAC1_DATA <= std_logic_vector( UNSIGNED(DAC1_DATA) +2); | ||||
DAC2_DATA <= std_logic_vector( UNSIGNED(DAC2_DATA) +3); | ||||
DAC3_DATA <= std_logic_vector( UNSIGNED(DAC3_DATA) +4); | ||||
DAC4_DATA <= std_logic_vector( UNSIGNED(DAC4_DATA) +5); | ||||
DAC5_DATA <= std_logic_vector( UNSIGNED(DAC5_DATA) +6); | ||||
DAC6_DATA <= std_logic_vector( UNSIGNED(DAC6_DATA) +7); | ||||
DAC7_DATA <= std_logic_vector( UNSIGNED(DAC7_DATA) +8); | ||||
-- DAC_DATA <= "0100000000000000"; | ||||
end if; | ||||
end if; | ||||
end process; | ||||
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r255 | |||
end rtl; | ||||