library ieee; use ieee.std_logic_1164.all; use IEEE.numeric_std.all; library grlib, techmap; use grlib.amba.all; use grlib.amba.all; use grlib.stdlib.all; use techmap.gencomp.all; use techmap.allclkgen.all; library gaisler; use gaisler.memctrl.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; library esa; use esa.memoryctrl.all; --use gaisler.sim.all; library lpp; use lpp.lpp_ad_conv.all; use lpp.lpp_amba.all; use lpp.apb_devices_list.all; use lpp.general_purpose.all; use lpp.lpp_cna.all; Library UNISIM; use UNISIM.vcomponents.all; use work.config.all; --================================================================== -- -- -- FPGA FREQ = 100MHz -- -- --================================================================== entity BeagleSynth is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH ); port ( reset : in std_ulogic; clk : in std_ulogic; DAC_nCLR : out std_ulogic; DAC_nCS : out std_ulogic; CAL_IN_SCK : out std_ulogic; DAC_SDI : out std_logic_vector(7 downto 0); TXD : out std_ulogic; RXD : in std_ulogic; urxd1 : in std_ulogic; utxd1 : out std_ulogic; LED : out std_ulogic_vector(2 downto 0); -------------------------------------------------------- ---- SDRAM ---- For SDRAM config have a look on leon3-altera-ep1c20 ---- design from GRLIB, the IS42S32400E is similar to ---- MT48LC4M32B2. -------------------------------------------------------- sdcke : out std_logic; -- clk en sdcsn : out std_logic; -- chip sel sdwen : out std_logic; -- write en sdrasn : out std_logic; -- row addr stb sdcasn : out std_logic; -- col addr stb sddqm : out std_logic_vector (3 downto 0); -- data i/o mask sdclk : out std_logic; -- sdram clk output sdba : out std_logic_vector (1 downto 0); -- bank select address Address : out std_logic_vector(11 downto 0); -- sdram address Data : inout std_logic_vector(31 downto 0) -- optional sdram data ); end; architecture rtl of BeagleSynth is constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ CFG_GRETH+CFG_AHB_JTAG; constant maxahbm : integer := maxahbmsp; constant IOAEN : integer := CFG_CAN; constant boardfreq : integer := 100000; signal clk2x : std_ulogic; signal lclk : std_ulogic; signal clkm : std_ulogic; signal rstn : std_ulogic; signal rst : std_ulogic; signal rstraw : std_ulogic; signal pciclk : std_ulogic; signal sdclkl : std_ulogic; signal sdclkl_DDR2 : std_ulogic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; --- AHB / APB signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); --- MEM CTRLR signal sdi : sdctrl_in_type; signal sdo : sdctrl_out_type; --UART signal ahbuarti : uart_in_type; signal ahbuarto : uart_out_type; signal apbuarti : uart_in_type; signal apbuarto : uart_out_type; signal led2int : std_logic; signal DAC0_DATA : std_logic_vector(15 downto 0); signal DAC1_DATA : std_logic_vector(15 downto 0); signal DAC2_DATA : std_logic_vector(15 downto 0); signal DAC3_DATA : std_logic_vector(15 downto 0); signal DAC4_DATA : std_logic_vector(15 downto 0); signal DAC5_DATA : std_logic_vector(15 downto 0); signal DAC6_DATA : std_logic_vector(15 downto 0); signal DAC7_DATA : std_logic_vector(15 downto 0); signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0); signal smpclk : std_logic; signal smpclk_reg : std_logic; signal DAC_SDO : std_logic; begin DAC_nCLR <= '1'; --DAC_nCS <= SYNC; --CAL_IN_SCK <= '1'; --DAC_SDI <= (others =>'1'); resetn_pad : inpad generic map (tech => padtech) port map (reset, rst); rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw); --rstn <= reset; --lclk <= clk; clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk); cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; clkgen0 : clkgen -- clock generator generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq) port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open); -- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2); --sdclk <= sdclkl; sdclk <= sdclkl_DDR2; LED(1) <= not cgo.clklock; LED(0) <= cgo.clklock; ODDR2_inst : ODDR2 generic map( DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" INIT => '0', -- Sets initial state of the Q output to '0' or '1' SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset port map ( Q => sdclkl_DDR2, -- 1-bit output data C0 => sdclkl, -- 1-bit clock input C1 => not sdclkl, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D0 => '1', -- 1-bit data input (associated with C0) D1 => '0', -- 1-bit data input (associated with C1) R => '0', -- 1-bit reset input S => '0' -- 1-bit set input ); ---------------------------------------------------------------------- --- AHB CONTROLLER ------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN, nahbm => maxahbm, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- AHB UART ------------------------------------------------------- ---------------------------------------------------------------------- dcomgen : if CFG_AHB_UART = 1 generate dcom0: ahbuart -- Debug UART generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); ahbuarti.rxd <= RXD; TXD <= ahbuarto.txd; end generate; nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; ---------------------------------------------------------------------- --- APB Bridge ----------------------------------------------------- ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); ---------------------------------------------------------------------- --- APB UART ------------------------------------------------------- ---------------------------------------------------------------------- ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; apbuarti.ctsn <= '0'; end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; --div0: Clk_divider -- generic map( 100000000,1) -- Port map( clkm,rstn,LED(2)); LED(2) <= led2int; process(clkm,rstn) begin if rstn = '0' then led2int <= '0'; elsif clkm'event and clkm='1' then led2int <= not led2int; end if; end process; sdc : sdctrl generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0, invclk => 0,sdbits =>32) port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo); --Alternative data pad instantiation with vectored bdrive sd_pad : iopadvv generic map (tech=> padtech,width => 32) port map ( data(31 downto 0), sdo.data(31 downto 0), sdo.vbdrive(31 downto 0), sdi.data(31 downto 0)); -- connect memory controller outputs to entity output signals Address <= sdo.address(13 downto 2); --sdba <= sdo.address(16 downto 15); sdba <= "00"; sdcke <= sdo.sdcke(0); sdwen <= sdo.sdwen; sdcsn <= sdo.sdcsn(0); sdrasn <= sdo.rasn; sdcasn <= sdo.casn; sddqm <= sdo.dqm(3 downto 0); DAC0 : DAC8581 generic map(100,8) Port map( clk => clkm, rstn => rstn, smpclk => smpclk, sclk => CAL_IN_SCK, csn => DAC_nCS, sdo => DAC_SDI, smp_in => DAC_DATA ); smpclk0: Clk_divider GENERIC map(OSC_freqHz => 50000000, TargetFreq_Hz => 256000) PORT map( clk => clkm, reset => rstn, clk_divided => smpclk ); all_bits: FOR I in 15 downto 0 GENERATE DAC_DATA(0,I) <= DAC0_DATA(I); DAC_DATA(1,I) <= DAC1_DATA(I); DAC_DATA(2,I) <= DAC2_DATA(I); DAC_DATA(3,I) <= DAC3_DATA(I); DAC_DATA(4,I) <= DAC4_DATA(I); DAC_DATA(5,I) <= DAC5_DATA(I); DAC_DATA(6,I) <= DAC6_DATA(I); DAC_DATA(7,I) <= DAC7_DATA(I); end GENERATE; process(clkm,rstn) begin if rstn ='0' then DAC0_DATA <= X"0000"; DAC1_DATA <= X"0000"; DAC2_DATA <= X"0000"; DAC3_DATA <= X"0000"; DAC4_DATA <= X"0000"; DAC5_DATA <= X"0000"; DAC6_DATA <= X"0000"; DAC7_DATA <= X"0000"; smpclk_reg <= smpclk; elsif clkm'event and clkm = '1' then smpclk_reg <= smpclk; if smpclk_reg = '0' and smpclk = '1' then DAC0_DATA <= std_logic_vector( UNSIGNED(DAC0_DATA) +1); DAC1_DATA <= std_logic_vector( UNSIGNED(DAC1_DATA) +2); DAC2_DATA <= std_logic_vector( UNSIGNED(DAC2_DATA) +3); DAC3_DATA <= std_logic_vector( UNSIGNED(DAC3_DATA) +4); DAC4_DATA <= std_logic_vector( UNSIGNED(DAC4_DATA) +5); DAC5_DATA <= std_logic_vector( UNSIGNED(DAC5_DATA) +6); DAC6_DATA <= std_logic_vector( UNSIGNED(DAC6_DATA) +7); DAC7_DATA <= std_logic_vector( UNSIGNED(DAC7_DATA) +8); -- DAC_DATA <= "0100000000000000"; end if; end if; end process; end rtl;