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1 | ---------------------------------------------------------------------------------- | |
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2 | -- Company: | |
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3 | -- Engineer: | |
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4 | -- | |
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5 | -- Create Date: 15:20:11 12/08/2013 | |
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6 | -- Design Name: | |
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7 | -- Module Name: GPMC_SLAVE - Behavioral | |
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8 | -- Project Name: | |
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9 | -- Target Devices: | |
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10 | -- Tool versions: | |
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11 | -- Description: | |
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12 | -- | |
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13 | -- Dependencies: | |
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14 | -- | |
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15 | -- Revision: | |
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16 | -- Revision 0.01 - File Created | |
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17 | -- Additional Comments: | |
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18 | -- | |
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19 | ---------------------------------------------------------------------------------- | |
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20 | library IEEE; | |
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21 | use IEEE.STD_LOGIC_1164.ALL; | |
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22 | use IEEE.numeric_std.all; | |
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23 | library grlib, techmap; | |
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24 | use grlib.stdlib.all; | |
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25 | use techmap.gencomp.all; | |
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26 | use techmap.allclkgen.all; | |
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27 | library lpp; | |
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28 | use lpp.general_purpose.all; | |
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29 | ||
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30 | entity GPMC_SLAVE is | |
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31 | generic ( | |
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32 | memtech : integer := 0; | |
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33 | padtech : integer := 0 | |
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34 | ); | |
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35 | Port ( | |
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36 | clk : in STD_LOGIC; | |
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37 | reset : in STD_LOGIC; | |
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38 | GPMC_AD : inout std_logic_vector(15 downto 0); | |
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39 | GPMC_A : in std_logic_vector(19 downto 0); | |
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40 | GPMC_CLK_MUX0 : in std_ulogic; | |
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41 | GPMC_WEN : in std_ulogic; | |
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42 | GPMC_OEN_REN : in std_ulogic; | |
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43 | GPMC_ADVN_ALE : in std_ulogic; | |
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44 | GPMC_CSN : in std_ulogic_vector(2 downto 0); | |
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45 | GPMC_BE0N_CLE : in std_ulogic; | |
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46 | GPMC_BE1N : in std_ulogic; | |
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47 | GPMC_WAIT0 : in std_ulogic; | |
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48 | GPMC_WPN : in std_ulogic | |
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49 | ); | |
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50 | end GPMC_SLAVE; | |
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51 | ||
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52 | architecture Behavioral of GPMC_SLAVE is | |
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53 | constant VectInit : std_logic_vector(15 downto 0):=(others => '0'); | |
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54 | ||
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55 | signal data_out :std_logic_vector(15 downto 0); | |
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56 | signal data_in :std_logic_vector(15 downto 0); | |
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57 | ||
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58 | type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0); | |
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59 | signal RAMarray : RAMarrayT:=(others => VectInit); | |
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60 | signal ramindex : integer range 0 to 255; | |
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61 | ||
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62 | begin | |
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63 | ||
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64 | data_pad : iopadv generic map (tech=> padtech,width => 16) | |
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65 | port map ( | |
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66 | pad => GPMC_AD(15 downto 0), | |
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67 | o => data_in(15 downto 0), | |
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68 | en => GPMC_OEN_REN, | |
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69 | i => data_out(15 downto 0) | |
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70 | ); | |
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71 | ||
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72 | process(reset,GPMC_CLK_MUX0) | |
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73 | begin | |
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74 | if reset = '0' then | |
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75 | data_out <= (others => '0'); | |
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76 | ramindex <= 0; | |
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77 | elsif GPMC_CLK_MUX0'event and GPMC_CLK_MUX0 = '1' then | |
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78 | ramindex <= to_integer(unsigned(GPMC_A)); | |
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79 | data_out <= RAMarray(ramindex); | |
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80 | if GPMC_WEN = '0' then | |
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81 | RAMarray(ramindex) <= data_in; | |
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82 | end if; | |
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83 | end if; | |
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84 | end process; | |
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85 | ||
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86 | end Behavioral; | |
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87 | ||
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88 | ||
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89 | ||
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90 | ||
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91 | ||
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92 | ||
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93 | ||
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94 | ||
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95 | ||
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96 | ||
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97 | ||
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98 | ||
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99 | ||
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100 |
@@ -2,10 +2,11 | |||
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2 | 2 | NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; |
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3 | 3 | NET "CLK" LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL; |
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4 | 4 | NET "CLKM" TNM_NET = "clkm_net"; |
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5 |
TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%; |
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6 | ||
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5 | TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%; | |
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6 | ||
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7 | ||
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7 | 8 | NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE; |
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8 |
NET "RESET" LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL; |
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9 | NET "RESET" LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL; | |
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9 | 10 | |
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10 | 11 | NET "DAC_nCLR" LOC = "R11" | IOSTANDARD=LVTTL; |
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11 | 12 | NET "DAC_nCS" LOC = "T12" | IOSTANDARD=LVTTL; |
@@ -17,15 +18,15 NET "DAC_SDI(3)" LOC = "M6" | IOSTANDA | |||
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17 | 18 | NET "DAC_SDI(4)" LOC = "K22" | IOSTANDARD=LVTTL; |
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18 | 19 | NET "DAC_SDI(5)" LOC = "L22" | IOSTANDARD=LVTTL; |
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19 | 20 | NET "DAC_SDI(6)" LOC = "G19" | IOSTANDARD=LVTTL; |
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20 |
NET "DAC_SDI(7)" LOC = "F20" | IOSTANDARD=LVTTL; |
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21 | NET "DAC_SDI(7)" LOC = "F20" | IOSTANDARD=LVTTL; | |
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21 | 22 | |
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22 | ||
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23 | ||
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23 | 24 | NET "TXD" LOC = "V22"| slew=FAST | IOSTANDARD=LVTTL; |
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24 | 25 | NET "RXD" LOC = "U22"| slew=FAST | IOSTANDARD=LVTTL; |
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25 | 26 | NET "LED(0)" LOC = "AB9"| slew=FAST | IOSTANDARD=LVTTL; |
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26 | 27 | NET "LED(1)" LOC = "AB8"| slew=FAST | IOSTANDARD=LVTTL; |
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27 |
NET "LED(2)" LOC = "AA8"| slew=FAST | IOSTANDARD=LVTTL; |
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28 | ||
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28 | NET "LED(2)" LOC = "AA8"| slew=FAST | IOSTANDARD=LVTTL; | |
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29 | ||
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29 | 30 | NET "urxd1" LOC = "D3" | IOSTANDARD=LVTTL; # Unused PIN |
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30 | 31 | NET "utxd1" LOC = "C4" | IOSTANDARD=LVTTL; # Unused PIN |
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31 | 32 | |
@@ -91,6 +92,58 NET "Data(2)" LOC = "A20"| slew=FAS | |||
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91 | 92 | NET "Data(1)" LOC = "B18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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92 | 93 | NET "Data(0)" LOC = "A18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data |
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93 | 94 | |
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95 | NET "GPMC_AD(0)" LOC = "M1"| slew=FAST | IOSTANDARD=LVTTL; | |
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96 | NET "GPMC_AD(1)" LOC = "M2"| slew=FAST | IOSTANDARD=LVTTL; | |
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97 | NET "GPMC_AD(2)" LOC = "AB3"| slew=FAST | IOSTANDARD=LVTTL; | |
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98 | NET "GPMC_AD(3)" LOC = "AB2"| slew=FAST | IOSTANDARD=LVTTL; | |
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99 | NET "GPMC_AD(4)" LOC = "N1"| slew=FAST | IOSTANDARD=LVTTL; | |
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100 | NET "GPMC_AD(5)" LOC = "N3"| slew=FAST | IOSTANDARD=LVTTL; | |
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101 | NET "GPMC_AD(6)" LOC = "AB5"| slew=FAST | IOSTANDARD=LVTTL; | |
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102 | NET "GPMC_AD(7)" LOC = "AB4"| slew=FAST | IOSTANDARD=LVTTL; | |
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103 | NET "GPMC_AD(8)" LOC = "R1"| slew=FAST | IOSTANDARD=LVTTL; | |
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104 | NET "GPMC_AD(9)" LOC = "V1"| slew=FAST | IOSTANDARD=LVTTL; | |
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105 | NET "GPMC_AD(10)" LOC = "U3"| slew=FAST | IOSTANDARD=LVTTL; | |
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106 | NET "GPMC_AD(11)" LOC = "T1"| slew=FAST | IOSTANDARD=LVTTL; | |
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107 | NET "GPMC_AD(12)" LOC = "V2"| slew=FAST | IOSTANDARD=LVTTL; | |
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108 | NET "GPMC_AD(13)" LOC = "W1"| slew=FAST | IOSTANDARD=LVTTL; | |
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109 | NET "GPMC_AD(14)" LOC = "T2"| slew=FAST | IOSTANDARD=LVTTL; | |
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110 | NET "GPMC_AD(15)" LOC = "U1"| slew=FAST | IOSTANDARD=LVTTL; | |
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111 | ||
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112 | ||
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113 | ||
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114 | NET "GPMC_A(0)" LOC = "N4"| slew=FAST | IOSTANDARD=LVTTL; | |
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115 | NET "GPMC_A(1)" LOC = "N6"| slew=FAST | IOSTANDARD=LVTTL; | |
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116 | NET "GPMC_A(2)" LOC = "P3"| slew=FAST | IOSTANDARD=LVTTL; | |
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117 | NET "GPMC_A(3)" LOC = "P4"| slew=FAST | IOSTANDARD=LVTTL; | |
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118 | NET "GPMC_A(4)" LOC = "R4"| slew=FAST | IOSTANDARD=LVTTL; | |
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119 | NET "GPMC_A(5)" LOC = "T5"| slew=FAST | IOSTANDARD=LVTTL; | |
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120 | NET "GPMC_A(6)" LOC = "T6"| slew=FAST | IOSTANDARD=LVTTL; | |
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121 | NET "GPMC_A(7)" LOC = "T3"| slew=FAST | IOSTANDARD=LVTTL; | |
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122 | NET "GPMC_A(8)" LOC = "L1"| slew=FAST | IOSTANDARD=LVTTL; | |
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123 | NET "GPMC_A(9)" LOC = "K1"| slew=FAST | IOSTANDARD=LVTTL; | |
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124 | NET "GPMC_A(10)" LOC = "L3"| slew=FAST | IOSTANDARD=LVTTL; | |
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125 | NET "GPMC_A(11)" LOC = "K2"| slew=FAST | IOSTANDARD=LVTTL; | |
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126 | NET "GPMC_A(12)" LOC = "F1"| slew=FAST | IOSTANDARD=LVTTL; | |
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127 | NET "GPMC_A(13)" LOC = "F2"| slew=FAST | IOSTANDARD=LVTTL; | |
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128 | NET "GPMC_A(14)" LOC = "G3"| slew=FAST | IOSTANDARD=LVTTL; | |
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129 | NET "GPMC_A(15)" LOC = "H2"| slew=FAST | IOSTANDARD=LVTTL; | |
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130 | NET "GPMC_A(16)" LOC = "G1"| slew=FAST | IOSTANDARD=LVTTL; | |
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131 | NET "GPMC_A(17)" LOC = "H1"| slew=FAST | IOSTANDARD=LVTTL; | |
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132 | NET "GPMC_A(18)" LOC = "J1"| slew=FAST | IOSTANDARD=LVTTL; | |
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133 | NET "GPMC_A(19)" LOC = "J3"| slew=FAST | IOSTANDARD=LVTTL; | |
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134 | ||
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135 | NET "GPMC_CLK_MUX0" CLOCK_DEDICATED_ROUTE = FALSE; | |
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136 | NET "GPMC_CLK_MUX0" LOC = "R3"| slew=FAST | IOSTANDARD=LVTTL; | |
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137 | NET "GPMC_WEN" LOC = "W3"| slew=FAST | IOSTANDARD=LVTTL; | |
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138 | NET "GPMC_OEN_REN" LOC = "Y2"| slew=FAST | IOSTANDARD=LVTTL; | |
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139 | NET "GPMC_ADVN_ALE" LOC = "AA2"| slew=FAST | IOSTANDARD=LVTTL; | |
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140 | NET "GPMC_CSN(0)" LOC = "M3"| slew=FAST | IOSTANDARD=LVTTL; | |
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141 | NET "GPMC_CSN(1)" LOC = "P1"| slew=FAST | IOSTANDARD=LVTTL; | |
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142 | NET "GPMC_CSN(2)" LOC = "P2"| slew=FAST | IOSTANDARD=LVTTL; | |
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143 | NET "GPMC_BE0N_CLE" LOC = "Y1"| slew=FAST | IOSTANDARD=LVTTL; | |
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144 | NET "GPMC_BE1N" LOC = "AB21"| slew=FAST | IOSTANDARD=LVTTL; | |
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145 | NET "GPMC_WAIT0" LOC = "AA21"| slew=FAST | IOSTANDARD=LVTTL; | |
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146 | NET "GPMC_WPN" LOC = "W22"| slew=FAST | IOSTANDARD=LVTTL; | |
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94 | 147 | |
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95 | 148 | |
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96 | 149 | |
@@ -107,3 +160,8 NET "Data(0)" LOC = "A18"| slew=FAS | |||
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107 | 160 | |
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108 | 161 | |
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109 | 162 | |
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163 | ||
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164 | ||
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165 | ||
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166 | ||
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167 |
@@ -22,7 +22,7 use lpp.apb_devices_list.all; | |||
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22 | 22 | use lpp.general_purpose.all; |
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23 | 23 | use lpp.lpp_cna.all; |
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24 | 24 | |
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25 | Library UNISIM; | |
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25 | Library UNISIM; | |
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26 | 26 | use UNISIM.vcomponents.all; |
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27 | 27 | |
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28 | 28 | |
@@ -43,17 +43,32 entity BeagleSynth is | |||
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43 | 43 | clktech : integer := CFG_CLKTECH |
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44 | 44 | ); |
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45 | 45 | port ( |
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46 | reset : in std_ulogic; | |
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47 | clk : in std_ulogic; | |
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48 |
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49 |
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50 |
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51 |
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52 |
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53 |
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54 |
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55 |
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56 |
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46 | reset : in std_ulogic; | |
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47 | clk : in std_ulogic; | |
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48 | DAC_nCLR : out std_ulogic; | |
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49 | DAC_nCS : out std_ulogic; | |
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50 | CAL_IN_SCK : out std_ulogic; | |
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51 | DAC_SDI : out std_logic_vector(7 downto 0); | |
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52 | TXD : out std_ulogic; | |
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53 | RXD : in std_ulogic; | |
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54 | urxd1 : in std_ulogic; | |
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55 | utxd1 : out std_ulogic; | |
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56 | LED : out std_ulogic_vector(2 downto 0); | |
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57 | -------------------------------------------------------- | |
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58 | ---- Beaglebone GPMC | |
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59 | -------------------------------------------------------- | |
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60 | GPMC_AD : inout std_logic_vector(15 downto 0); | |
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61 | GPMC_A : in std_logic_vector(19 downto 0); | |
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62 | GPMC_CLK_MUX0 : in std_ulogic; | |
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63 | GPMC_WEN : in std_ulogic; | |
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64 | GPMC_OEN_REN : in std_ulogic; | |
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65 | GPMC_ADVN_ALE : in std_ulogic; | |
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66 | GPMC_CSN : in std_ulogic_vector(2 downto 0); | |
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67 | GPMC_BE0N_CLE : in std_ulogic; | |
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68 | GPMC_BE1N : in std_ulogic; | |
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69 | GPMC_WAIT0 : in std_ulogic; | |
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70 | GPMC_WPN : in std_ulogic; | |
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71 | ||
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57 | 72 | -------------------------------------------------------- |
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58 | 73 | ---- SDRAM |
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59 | 74 | ---- For SDRAM config have a look on leon3-altera-ep1c20 |
@@ -127,6 +142,7 signal smpclk : std_logic; | |||
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127 | 142 | signal smpclk_reg : std_logic; |
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128 | 143 | signal DAC_SDO : std_logic; |
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129 | 144 | |
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145 | signal gpmc_clk : std_logic; | |
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130 | 146 | begin |
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131 | 147 | |
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132 | 148 | DAC_nCLR <= '1'; |
@@ -323,6 +339,24 elsif clkm'event and clkm = '1' then | |||
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323 | 339 | end if; |
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324 | 340 | end process; |
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325 | 341 | |
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342 | gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk); | |
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343 | GPMCS0: entity work.GPMC_SLAVE | |
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344 | generic map(memtech,padtech) | |
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345 | Port map( | |
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346 | clk => clkm, | |
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347 | reset => rstn, | |
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348 | GPMC_AD => GPMC_AD, | |
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349 | GPMC_A => GPMC_A, | |
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350 | GPMC_CLK_MUX0 => gpmc_clk, | |
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351 | GPMC_WEN => GPMC_WEN, | |
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352 | GPMC_OEN_REN => GPMC_OEN_REN, | |
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353 | GPMC_ADVN_ALE => GPMC_ADVN_ALE, | |
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354 | GPMC_CSN => GPMC_CSN, | |
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355 | GPMC_BE0N_CLE => GPMC_BE0N_CLE, | |
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356 | GPMC_BE1N => GPMC_BE1N, | |
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357 | GPMC_WAIT0 => GPMC_WAIT0, | |
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358 | GPMC_WPN => GPMC_WAIT0 | |
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359 | ); | |
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326 | 360 | |
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327 | 361 | end rtl; |
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328 | 362 |
@@ -17,7 +17,7 VHDLOPTSYNFILES= | |||
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17 | 17 | |
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18 | 18 | |
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19 | 19 | VHDLSYNFILES= \ |
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20 | config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd | |
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20 | config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd GPMC_SLAVE.vhd | |
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21 | 21 | #VHDLSIMFILES=testbench.vhd |
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22 | 22 | #SIMTOP=testbench |
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23 | 23 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc |
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