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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Added missing files (sdc/pdc/makefile) for LFR-EQM boards...
pellion -
r639:5ffe6bd0368c default draft
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1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname N18 -fixed yes -DIRECTION Inout
4
5 set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout
24 set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout
25
26 set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout
27 set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout
28 set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout
29 set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout
30 set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout
31 set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout
32 set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout
33 set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout
34 set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout
35 set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout
37 set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout
38 set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout
39 set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout
40 set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout
41 set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout
42 set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout
43 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
44 set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout
45 set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout
46 set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout
47 set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout
48 set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout
49 set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout
50 set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout
51 set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout
52 set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout
53 set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout
54 set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout
55 set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout
56 set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout
57 set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout
58
59 set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout
60 set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout
61 set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout
62 set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout
63 set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout
64 set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout
65 set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout
66
67 set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76
77 set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
78 set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
79 set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
80
81 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
82 set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout
83 set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout
84 set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
85 #set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout
86 #set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout
87 #set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
88 set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
89 #set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
90
91 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
92
93 set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
98 set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout
99 set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout
100 set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout
101
102 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
103
104 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
105 set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout
106 set_io {HK_SEL[0]} -pinname A2 -fixed yes -DIRECTION Inout
107 set_io {HK_SEL[1]} -pinname C3 -fixed yes -DIRECTION Inout
108
109 set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout
119 set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout
120 set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout
121 set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout
122 set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout
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@@ -0,0 +1,124
1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On
4
5 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
24
25 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
26 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
27 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
28 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
29 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
30 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
31 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
32 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
33 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
34 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
35 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
37 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
38 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
39 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
40 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
41 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
42 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
43 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
44 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
45 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
46 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
47 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
48 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
49 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
50 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
51 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
52 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
53 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
54 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
55 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
56 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
57
58 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
61 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
65
66 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
72 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
73 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
74 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
77
78 set_io {TAG[1]} -pinname J12 -fixed yes -DIRECTION Inout
79 set_io {TAG[2]} -pinname K12 -fixed yes -DIRECTION Inout
80 set_io {TAG[3]} -pinname K13 -fixed yes -DIRECTION Inout
81 set_io {TAG[4]} -pinname L16 -fixed yes -DIRECTION Inout
82 set_io {TAG[5]} -pinname L15 -fixed yes -DIRECTION Inout
83 set_io {TAG[6]} -pinname M16 -fixed yes -DIRECTION Inout
84 set_io {TAG[7]} -pinname J14 -fixed yes -DIRECTION Inout
85 set_io {TAG[8]} -pinname K15 -fixed yes -DIRECTION Inout
86 set_io {TAG[9]} -pinname J17 -fixed yes -DIRECTION Inout
87
88 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
89
90 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
98
99 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
100
101 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
102 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
104 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
105
106 #set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
107 #set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
108 #set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
109 #set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
110 #set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
111 #set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
112 #set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
113 #set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
114 #set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
115 #set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
116 #set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
117 #set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
118 #set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
119 #set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
120
121 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
122 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
123 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
124 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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@@ -0,0 +1,123
1 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
2 set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On
3
4 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
5 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
6 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
7 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
8 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
9 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
10 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
11 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
12 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
13 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
14 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
15 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
16 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
17 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
18 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
19 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
20 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
21 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
22 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
23
24 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
25 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
26 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
27 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
28 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
29 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
30 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
31 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
32 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
33 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
34 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
35 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
36 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
37 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
38 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
39 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
40 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
41 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
42 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
43 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
44 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
45 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
46 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
47 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
48 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
49 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
50 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
51 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
52 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
53 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
54 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
55 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
56
57 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
58 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
60 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
61 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
62 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
63 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
64
65 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
66 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
67 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
68 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
69 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
70
71 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76
77 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
78 set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout
79 set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout
80 set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout
81 #set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout
82 #set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
83 #set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
84 set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout
85 #set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout
86
87 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
88
89 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
90 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
97
98 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
99
100 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
101 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
102 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
104
105 set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
106 set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
107 set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
108 set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
119
120 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
121 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
122 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
123 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Jul 24 14:50:40 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_pad_25/U0:Y }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41
42
43 ######## Output Delay Constraints ########
44 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address }]
45
46 set_min_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 }]
47
48
49
50 ######## Delay Constraints ########
51
52
53
54 ######## Delay Constraints ########
55
56
57
58 ######## Multicycle Constraints ########
59
60
61
62 ######## False Path Constraints ########
63
64
65
66 ######## Output load Constraints ########
67
68
69
70 ######## Disable Timing Constraints #########
71
72
73
74 ######## Clock Uncertainty Constraints #########
75
76
77
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Tue May 19 15:46:14 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42
43 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
44
45 set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
46 set_input_delay -min 15.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
47
48
49
50 ######## Output Delay Constraints ########
51
52 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
53
54 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
55
56 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
57
58 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
59
60 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
61
62 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
63 set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
64 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
65 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
66 set_min_delay 8.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
67 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
68 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
69
70
71
72 ######## Delay Constraints ########
73
74 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
75 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
76 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
77 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
78
79 set_max_delay 12.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
80
81 set_max_delay 12.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
82 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
83 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
84 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
85
86 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
87 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
88 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
89 address[7] address[8] address[9] }]
90
91 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
92
93 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
94
95 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
96
97 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
98 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
99
100 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
101 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
102
103
104
105 ######## Delay Constraints ########
106
107 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
108 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
109 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
110 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
111
112 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
113
114 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
115 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
116 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
117 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
118
119 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
120 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
121 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
122 address[7] address[8] address[9] }]
123
124 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
125
126 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
127
128 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
129
130
131
132 ######## Multicycle Constraints ########
133
134
135
136 ######## False Path Constraints ########
137
138
139
140 ######## Output load Constraints ########
141
142
143
144 ######## Disable Timing Constraints #########
145
146
147
148 ######## Clock Uncertainty Constraints #########
149
150
151
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Tue May 05 13:46:34 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42
43 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
44
45 set_input_delay -max 20.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
46
47
48
49 ######## Output Delay Constraints ########
50
51 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
52
53 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
54
55 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
56
57 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
60
61 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
62 set_max_delay 35.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
63 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
64 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
65 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
66 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
67 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
68
69
70
71 ######## Delay Constraints ########
72
73 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
74 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
75 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
76 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
77
78 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
79
80 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
81 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
82 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
83 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
84
85 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
86 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
87 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
88 address[7] address[8] address[9] }]
89
90 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
91
92 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
93
94 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
95
96 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
97 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
98
99 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
100 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
101
102
103
104 ######## Delay Constraints ########
105
106 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
107 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
108 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
109 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
110
111 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
112
113 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
114 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
115 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
116 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
117
118 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
119 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
120 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
121 address[7] address[8] address[9] }]
122
123 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
124
125 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
126
127 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
128
129
130
131 ######## Multicycle Constraints ########
132
133
134
135 ######## False Path Constraints ########
136
137 set_false_path -from [get_pins { \
138 USE_ADCDRIVER_true.top_ad_conv_RHF1401_withFilter_1/cnv_s_reg:CLK }] -to [get_pins { \
139 USE_ADCDRIVER_true.top_ad_conv_RHF1401_withFilter_1/SYNC_FF_cnv/sync_loop.1.A_temp[1]:D \
140 }]
141 # SYNC PATH of ADC_CNV signal from CLK_domain_24 to CLK_domain_25
142
143
144
145 ######## Output load Constraints ########
146
147
148
149 ######## Disable Timing Constraints #########
150
151
152
153 ######## Clock Uncertainty Constraints #########
154
155
156
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50
51 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
73 address[7] address[8] address[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
77 address[7] address[8] address[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82
83 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
84 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
85 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
86
87 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
88 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
89 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
90
91
92
93 ######## Delay Constraints ########
94
95 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
96 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
97 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
98
99 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
100 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
101 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
102
103
104
105 ######## Delay Constraints ########
106
107
108
109 ######## Multicycle Constraints ########
110
111
112
113 ######## False Path Constraints ########
114
115
116
117 ######## Output load Constraints ########
118
119
120
121 ######## Disable Timing Constraints #########
122
123
124
125 ######## Clock Uncertainty Constraints #########
126
127
128
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25
26 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1_0:Y }
27
28 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1_0:Y }
29
30
31
32 ######## Generated Clock Constraints ########
33
34
35
36 ######## Clock Source Latency Constraints #########
37
38
39
40 ######## Input Delay Constraints ########
41
42 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
43 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
44 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
45 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
46 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
47 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
48 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
49 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
50 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
51
52 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
53 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
55
56
57
58 ######## Output Delay Constraints ########
59
60 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
61 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
62 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
63 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
64 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
65 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
66 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
67 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
68 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
69
70 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
71 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
72 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
73 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
74 address[7] address[8] address[9] }]
75 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
76 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
77 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
78 address[7] address[8] address[9] }]
79
80 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
81 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
83
84 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
85 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
86 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
87
88 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
89 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
90 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
91
92
93
94 ######## Delay Constraints ########
95
96 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
97 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
98 {spw_inputloop.0.spw_phy0/rxclki_1_0:Y}]
99
100 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
101 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
102 {spw_inputloop.1.spw_phy0/rxclki_1_0:YY}]
103
104
105
106 ######## Delay Constraints ########
107
108
109
110 ######## Multicycle Constraints ########
111
112
113
114 ######## False Path Constraints ########
115
116
117
118 ######## Output load Constraints ########
119
120
121
122 ######## Disable Timing Constraints #########
123
124
125
126 ######## Clock Uncertainty Constraints #########
127
128
129
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 ##create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 ##create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50
51 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
73 address[7] address[8] address[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
77 address[7] address[8] address[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82
83 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
84 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
85 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
86
87 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
88 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
89 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
90
91
92
93 ######## Delay Constraints ########
94
95 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
96
97 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
98
99
100
101 ######## Delay Constraints ########
102
103
104
105 ######## Multicycle Constraints ########
106
107
108
109 ######## False Path Constraints ########
110
111
112
113 ######## Output load Constraints ########
114
115
116
117 ######## Disable Timing Constraints #########
118
119
120
121 ######## Clock Uncertainty Constraints #########
122
123
124
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Wed May 13 13:09:37 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
20
21 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
22
23 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
24
25
26
27 ######## Generated Clock Constraints ########
28
29
30
31 ######## Clock Source Latency Constraints #########
32
33
34
35 ######## Input Delay Constraints ########
36
37 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
38
39 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
40
41 set_input_delay -max 0.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
42 set_input_delay -min 0.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }]
43
44
45
46 ######## Output Delay Constraints ########
47
48 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
49
50 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
51
52 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
53
54 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
55
56 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
57
58 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
59
60
61
62 ######## Delay Constraints ########
63
64 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
65 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
66 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
67 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
68
69 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
70
71 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
72 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
73 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
74 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
75
76 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
77 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
78 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
79 address[7] address[8] address[9] }]
80
81 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82
83 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
84
85 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
86
87 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
88 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
89
90 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
91 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
92
93 set_max_delay 30.000 -from [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] \
94 ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] \
95 ADC_data[7] ADC_data[8] ADC_data[9] }] -to [get_clocks {clk_25:Q}]
96
97 set_max_delay 15.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
98 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
99 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
100
101
102
103 ######## Delay Constraints ########
104
105 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
106 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
107 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
108 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
109
110 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
111
112 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
113 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
114 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
115 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
116
117 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
118 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
119 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
120 address[7] address[8] address[9] }]
121
122 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
123
124 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
125
126 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
127
128 set_min_delay 0.000 -from [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] \
129 ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] \
130 ADC_data[7] ADC_data[8] ADC_data[9] }] -to [get_clocks {clk_25:Q}]
131
132 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \
133 ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \
134 ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }]
135
136
137
138 ######## Multicycle Constraints ########
139
140
141
142 ######## False Path Constraints ########
143
144
145
146 ######## Output load Constraints ########
147
148
149
150 ######## Disable Timing Constraints #########
151
152
153
154 ######## Clock Uncertainty Constraints #########
155
156
157
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1 # Synplicity, Inc. constraint file
2 # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
3 # Written on Wed Aug 1 19:29:24 2007
4 # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
5
6 #
7 # Collections
8 #
9
10 #
11 # Clocks
12 #
13
14 define_clock -name {clk50MHz} -freq 50 -clockgroup default_clkgroup_50 -route 5
15 define_clock -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_49 -route 5
16
17 #
18 # Clock to Clock
19 #
20
21 #
22 # Inputs/Outputs
23 #
24
25
26 #
27 # Registers
28 #
29
30 #
31 # Multicycle Path
32 #
33
34 #
35 # False Path
36 #
37
38 set_false_path -from reset
39
40 #
41 # Path Delay
42 #
43
44 #
45 # Attributes
46 #
47
48 define_global_attribute syn_useioff {1}
49 define_global_attribute -disable syn_netlist_hierarchy {0}
50
51 #
52 # I/O standards
53 #
54
55 #
56 # Compile Points
57 #
58
59 #
60 # Other Constraints
61 #
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1 PACKAGE=CQFP352
2 SPEED=Std
3 SYNFREQ=50
4
5 TECHNOLOGY=Axcelerator
6
7 DESIGNER_PACKAGE=CQFP
8 DESIGNER_PINS=352
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11
12 #ifeq ("$(FPGA_RTAX4000)","S")
13 # LIBERO_DIE=70800rts
14 # PART=RTAX4000S
15 # LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r
16 #endif
17
18 #ifeq ("$(FPGA_RTAX4000)","D")
19 LIBERO_DIE=70800d
20 PART=RTAX4000D
21 LIBERO_PACKAGE=cq$(DESIGNER_PINS)
22 #endif
23
24 MANUFACTURER=Actel
25 MGCPART=$(PART)
26 MGCTECHNOLOGY=Axcelerator
27 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
28
29 ## RTAX4000S OPTIONS
30 #LIBERO_DIE=70800rts
31 #PART=RTAX4000S
32
33 ## RTAX4000D OPTIONS
34 #LIBERO_DIE=70800d
35 #PART=RTAX4000D
36
37 # RTAX4000D
38 #LIBERO_PACKAGE=cq$(DESIGNER_PINS)
39
40 # RTAX4000S
41 #LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r
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1 {
2 "cells": [
3 {
4 "cell_type": "code",
5 "execution_count": null,
6 "metadata": {
7 "collapsed": false
8 },
9 "outputs": [],
10 "source": [
11 "#%matplotlib qt\n",
12 "%matplotlib inline\n",
13 "import matplotlib.pyplot as plt\n",
14 "plt.rcParams[\"figure.figsize\"] = [12,12]\n",
15 "import numpy as np\n",
16 "import pandas as pds"
17 ]
18 },
19 {
20 "cell_type": "code",
21 "execution_count": null,
22 "metadata": {
23 "collapsed": false
24 },
25 "outputs": [],
26 "source": [
27 "def try_plot(df,ax,left,right):\n",
28 " try:\n",
29 " df[(df.index >= left) & (df.index <= right)].plot(ax=ax,subplots=True,legend=False)\n",
30 " except:\n",
31 " pass\n",
32 " \n",
33 "def make_plots(path=\"./simulation\",left=50e-3,right=100e-3):\n",
34 " inputSig = pds.read_csv(path+\"/log_input.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS2\",\"BIAS3\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
35 " fXSig=[]\n",
36 " G=[0.89,0.87,0.89]\n",
37 " [fXSig.append(pds.read_csv(\n",
38 " path+\"./log_output_f{0}.txt\".format(F),index_col=0,delim_whitespace=True,header=None,\n",
39 " names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])) for F in range(3) ]\n",
40 " inputSig.index*=5e-9\n",
41 " for F in range(3):\n",
42 " if len(fXSig[F].index):\n",
43 " fXSig[F].index*=5e-9\n",
44 " fXSig[F]/=G[F]\n",
45 " axes=inputSig[(inputSig.index >= left) & (inputSig.index <= right)].filter([\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"]).plot(subplots=True,layout=(3,2)) \n",
46 " [ try_plot(df,axes,left,right) for df in fXSig ]\n",
47 " "
48 ]
49 },
50 {
51 "cell_type": "code",
52 "execution_count": null,
53 "metadata": {
54 "collapsed": false
55 },
56 "outputs": [],
57 "source": [
58 "make_plots()"
59 ]
60 }
61 ],
62 "metadata": {
63 "kernelspec": {
64 "display_name": "Python 3",
65 "language": "python",
66 "name": "python3"
67 },
68 "language_info": {
69 "codemirror_mode": {
70 "name": "ipython",
71 "version": 3
72 },
73 "file_extension": ".py",
74 "mimetype": "text/x-python",
75 "name": "python",
76 "nbconvert_exporter": "python",
77 "pygments_lexer": "ipython3",
78 "version": "3.5.2"
79 }
80 },
81 "nbformat": 4,
82 "nbformat_minor": 1
83 }
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1 {
2 "cells": [
3 {
4 "cell_type": "code",
5 "execution_count": null,
6 "metadata": {
7 "collapsed": false
8 },
9 "outputs": [],
10 "source": [
11 "import random\n",
12 "import time\n",
13 "#%matplotlib inline\n",
14 "import matplotlib.pyplot as plt\n",
15 "import numpy as np\n",
16 "import pandas as pds\n",
17 "import datetime as dt"
18 ]
19 },
20 {
21 "cell_type": "code",
22 "execution_count": null,
23 "metadata": {
24 "collapsed": true
25 },
26 "outputs": [],
27 "source": [
28 "DOFILE=\"run.do.in\"\n",
29 "RAM1={\n",
30 "\"instance\":\"testbench/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
31 "\"abits\":8,\n",
32 "\"dbits\":12,\n",
33 "\"name\":\"RAM1.txt\"\n",
34 "}\n",
35 "RAM2={\n",
36 "\"instance\":\"testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
37 "\"abits\":8,\n",
38 "\"dbits\":12,\n",
39 "\"name\":\"RAM2.txt\"\n",
40 "}\n",
41 "RAM3={\n",
42 "\"instance\":\"testbench/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
43 "\"abits\":9,\n",
44 "\"dbits\":10,\n",
45 "\"name\":\"RAM3.txt\"\n",
46 "}\n",
47 "RAM4={\n",
48 "\"instance\":\"testbench/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/axc/x0/a8to12/agen(1)/u0/u0/MEMORYFILE\",\n",
49 "\"abits\":9,\n",
50 "\"dbits\":10,\n",
51 "\"name\":\"RAM4.txt\"\n",
52 "}\n",
53 "RAM5={\n",
54 "\"instance\":\"testbench/lpp_lfr_filter_1/YES_IIR_FILTER_f2_f3/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
55 "\"abits\":8,\n",
56 "\"dbits\":12,\n",
57 "\"name\":\"RAM5.txt\"\n",
58 "}\n",
59 "RAM6={\n",
60 "\"instance\":\"testbench/lpp_lfr_filter_1/YES_IIR_FILTER_f2_f3/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n",
61 "\"abits\":8,\n",
62 "\"dbits\":12,\n",
63 "\"name\":\"RAM6.txt\"\n",
64 "}\n",
65 "\n",
66 "RAMS=[RAM1,RAM2,RAM3,RAM4,RAM5,RAM6]"
67 ]
68 },
69 {
70 "cell_type": "code",
71 "execution_count": null,
72 "metadata": {
73 "collapsed": false
74 },
75 "outputs": [],
76 "source": [
77 "def mkram(length,width,gentype='rand',**kwargs):\n",
78 " return toBinStr(gen(length,width,gentype,**kwargs),width)\n",
79 "\n",
80 "def toBinStr(data,width):\n",
81 " return [format(val, 'b').zfill(width) for val in data]\n",
82 "\n",
83 "def gen(length,width,gentype='rand',**kwargs):\n",
84 " LUT={\n",
85 " \"rand\":gen_rand,\n",
86 " \"const\":gen_const\n",
87 " }\n",
88 " return LUT[gentype](length,width,**kwargs)\n",
89 "\n",
90 "def gen_rand(length,width,**kwargs):\n",
91 " random.seed(time.time())\n",
92 " mask=(2**width)-1\n",
93 " data=[]\n",
94 " for line in range(length):\n",
95 " data.append(int(2**32*random.random())&mask)\n",
96 " return data\n",
97 "\n",
98 "def gen_const(length,width, value):\n",
99 " mask=(2**width)-1\n",
100 " return [value&mask for i in range(length)]\n",
101 "\n",
102 "def save(data,file):\n",
103 " f = open(file,\"w\")\n",
104 " [f.write(line+'\\n') for line in data]\n",
105 " f.close()\n",
106 " \n",
107 "def start_Vsim(gentype='rand',**kwargs):\n",
108 " args=\"\"\n",
109 " for RAM in RAMS:\n",
110 " save(mkram(2**RAM[\"abits\"],RAM[\"dbits\"],gentype=gentype,**kwargs),\"simulation/\"+RAM[\"name\"])\n",
111 " args = args + \" -g\" + RAM[\"instance\"] + \"=\\\"\" + RAM[\"name\"] + \"\\\"\"\n",
112 " with open(\"run.do.in\",\"r\") as inFile, open(\"simulation/run.do\",\"w\") as outFile:\n",
113 " input = inFile.read()\n",
114 " outFile.write(input.replace(\"#VSIM_ARGS#\",args))\n",
115 " $(cd simulation)\n",
116 " vsim -do run.do > sim.log\n",
117 " folder=dt.datetime.today().strftime(\"%Y-%m-%d_%H-%M\")\n",
118 " mkdir @(folder)\n",
119 " for RAM in RAMS:\n",
120 " cp @(RAM[\"name\"]) @(folder+\"/\"+RAM[\"name\"])\n",
121 " cp log*.txt run.do sim.log @(folder) \n",
122 " $(cd ..)\n",
123 " \n"
124 ]
125 },
126 {
127 "cell_type": "code",
128 "execution_count": null,
129 "metadata": {
130 "collapsed": false
131 },
132 "outputs": [],
133 "source": []
134 },
135 {
136 "cell_type": "code",
137 "execution_count": null,
138 "metadata": {
139 "collapsed": false
140 },
141 "outputs": [],
142 "source": [
143 "df = pds.read_csv(\"./simulation/log_input.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS2\",\"BIAS3\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
144 "df2 = pds.read_csv(\"./simulation/log_output_f0.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
145 "df3 = pds.read_csv(\"./simulation/log_output_f1.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
146 "df4 = pds.read_csv(\"./simulation/log_output_f2.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n",
147 "\n",
148 "df.index*=5e-9\n",
149 "if len(df2.index):\n",
150 " df2.index*=5e-9\n",
151 " df2/=0.89\n",
152 "if len(df3.index):\n",
153 " df3.index*=5e-9\n",
154 " df3/=0.87\n",
155 "if len(df4.index):\n",
156 " df4.index*=5e-9\n",
157 " df4/=0.89\n",
158 "\n",
159 "print(len(df))\n",
160 "df.filter([\"B1\"]).plot()\n",
161 "#plt.plot(df2)\n",
162 "plt.plot(df3.filter([\"B1\"]))\n",
163 "#plt.plot(df4)\n",
164 "plt.show()"
165 ]
166 },
167 {
168 "cell_type": "code",
169 "execution_count": null,
170 "metadata": {
171 "collapsed": false
172 },
173 "outputs": [],
174 "source": [
175 "cd .."
176 ]
177 },
178 {
179 "cell_type": "code",
180 "execution_count": null,
181 "metadata": {
182 "collapsed": false
183 },
184 "outputs": [],
185 "source": [
186 "mkram(2,32)\n",
187 "\n",
188 "mkram(20,32,gentype='const',value=55)\n",
189 "\n",
190 "save(mkram(10,32),\"RAM_FILE.txt\")"
191 ]
192 },
193 {
194 "cell_type": "code",
195 "execution_count": null,
196 "metadata": {
197 "collapsed": false,
198 "scrolled": false
199 },
200 "outputs": [],
201 "source": [
202 "for i in range(2):\n",
203 " start_Vsim(gentype='rand',value=0)"
204 ]
205 }
206 ],
207 "metadata": {
208 "kernelspec": {
209 "display_name": "Xonsh",
210 "language": "xonsh",
211 "name": "xonsh"
212 },
213 "language_info": {
214 "codemirror_mode": "shell",
215 "file_extension": ".xsh",
216 "mimetype": "text/x-sh",
217 "name": "xonsh",
218 "pygments_lexer": "xonsh"
219 }
220 },
221 "nbformat": 4,
222 "nbformat_minor": 1
223 }
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@@ -0,0 +1,74
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 use ieee.numeric_std.all;
27 USE IEEE.std_logic_signed.ALL;
28 USE IEEE.MATH_real.ALL;
29
30 ENTITY generator IS
31
32 GENERIC (
33 AMPLITUDE : INTEGER := 100;
34 NB_BITS : INTEGER := 16);
35
36 PORT (
37 clk : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
39 run : IN STD_LOGIC;
40
41 data_ack : IN STD_LOGIC;
42 offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
43 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
44 );
45
46 END generator;
47
48 ARCHITECTURE beh OF generator IS
49
50 SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
51 BEGIN -- beh
52
53
54 PROCESS (clk, rstn)
55 variable seed1, seed2: positive; -- seed values for random generator
56 variable rand: real; -- random real-number value in range 0 to 1.0
57 BEGIN -- PROCESS
58 uniform(seed1, seed2, rand);--more entropy by skipping values
59 IF rstn = '0' THEN -- asynchronous reset (active low)
60 reg <= (OTHERS => '0');
61 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
62 IF run = '0' THEN
63 reg <= (OTHERS => '0');
64 ELSE
65 IF data_ack = '1' THEN
66 reg <= std_logic_vector(to_signed(INTEGER( (REAL(AMPLITUDE) * rand) + REAL(to_integer(SIGNED(offset))) ),NB_BITS));
67 END IF;
68 END IF;
69 END IF;
70 END PROCESS;
71
72 data <= reg;
73
74 END beh;
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This diff has been collapsed as it changes many lines, (516 lines changed) Show them Hide them
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1 quietly set ACTELLIBNAME Axcelerator
2 quietly set PROJECT_DIR "C:/opt/VHDLIB/designs/Validation_IIR_LFR"
3
4 if {[file exists presynth/_info]} {
5 echo "INFO: Simulation library presynth already exists"
6 } else {
7 vlib presynth
8 }
9 vmap presynth presynth
10 vmap Axcelerator "C:/Microsemi/Libero_v9.2/Designer/lib/modelsim/precompiled/vhdl/Axcelerator"
11 if {[file exists grlib/_info]} {
12 echo "INFO: Simulation library grlib already exists"
13 } else {
14 vlib grlib
15 }
16 vmap grlib "grlib"
17 if {[file exists synplify/_info]} {
18 echo "INFO: Simulation library synplify already exists"
19 } else {
20 vlib synplify
21 }
22 vmap synplify "synplify"
23 if {[file exists techmap/_info]} {
24 echo "INFO: Simulation library techmap already exists"
25 } else {
26 vlib techmap
27 }
28 vmap techmap "techmap"
29 if {[file exists spw/_info]} {
30 echo "INFO: Simulation library spw already exists"
31 } else {
32 vlib spw
33 }
34 vmap spw "spw"
35 if {[file exists eth/_info]} {
36 echo "INFO: Simulation library eth already exists"
37 } else {
38 vlib eth
39 }
40 vmap eth "eth"
41 if {[file exists gaisler/_info]} {
42 echo "INFO: Simulation library gaisler already exists"
43 } else {
44 vlib gaisler
45 }
46 vmap gaisler "gaisler"
47 if {[file exists esa/_info]} {
48 echo "INFO: Simulation library esa already exists"
49 } else {
50 vlib esa
51 }
52 vmap esa "esa"
53 if {[file exists fmf/_info]} {
54 echo "INFO: Simulation library fmf already exists"
55 } else {
56 vlib fmf
57 }
58 vmap fmf "fmf"
59 if {[file exists spansion/_info]} {
60 echo "INFO: Simulation library spansion already exists"
61 } else {
62 vlib spansion
63 }
64 vmap spansion "spansion"
65 if {[file exists gsi/_info]} {
66 echo "INFO: Simulation library gsi already exists"
67 } else {
68 vlib gsi
69 }
70 vmap gsi "gsi"
71 if {[file exists iap/_info]} {
72 echo "INFO: Simulation library iap already exists"
73 } else {
74 vlib iap
75 }
76 vmap iap "iap"
77 if {[file exists lpp/_info]} {
78 echo "INFO: Simulation library lpp already exists"
79 } else {
80 vlib lpp
81 }
82 vmap lpp "lpp"
83 if {[file exists cypress/_info]} {
84 echo "INFO: Simulation library cypress already exists"
85 } else {
86 vlib cypress
87 }
88 vmap cypress "cypress"
89
90 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/version.vhd"
91 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/config_types.vhd"
92 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/config.vhd"
93 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/stdlib.vhd"
94 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/stdio.vhd"
95 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/testlib.vhd"
96 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/ftlib/mtie_ftlib.vhd"
97 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/util/util.vhd"
98 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/sparc/sparc.vhd"
99 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/sparc/sparc_disas.vhd"
100 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/sparc/cpu_disas.vhd"
101 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/modgen/multlib.vhd"
102 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/modgen/leaves.vhd"
103 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/amba.vhd"
104 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/devices.vhd"
105 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/defmst.vhd"
106 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/apbctrl.vhd"
107 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ahbctrl.vhd"
108 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/dma2ahb_pkg.vhd"
109 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/dma2ahb.vhd"
110 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ahbmst.vhd"
111 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ahbmon.vhd"
112 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/apbmon.vhd"
113 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ambamon.vhd"
114 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/dma2ahb_tp.vhd"
115 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/amba_tp.vhd"
116 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_pkg.vhd"
117 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_mst_pkg.vhd"
118 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_slv_pkg.vhd"
119 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_util.vhd"
120 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_mst.vhd"
121 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_slv.vhd"
122 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahbs.vhd"
123 vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_ctrl.vhd"
124 vcom -93 -explicit -work synplify "${PROJECT_DIR}/../../../GRLIB/lib/synplify/sim/synplify.vhd"
125 vcom -93 -explicit -work synplify "${PROJECT_DIR}/../../../GRLIB/lib/synplify/sim/synattr.vhd"
126 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/gencomp/gencomp.vhd"
127 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/gencomp/netcomp.vhd"
128 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/memory_inferred.vhd"
129 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/tap_inferred.vhd"
130 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/ddr_inferred.vhd"
131 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/mul_inferred.vhd"
132 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/ddr_phy_inferred.vhd"
133 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/ddrphy_datapath.vhd"
134 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/sim_pll.vhd"
135 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/lpddr2_phy_inferred.vhd"
136 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/axcomp.vhd"
137 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/memory_axcelerator.vhd"
138 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/buffer_axcelerator.vhd"
139 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/pads_axcelerator.vhd"
140 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/clkgen_axcelerator.vhd"
141 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/ddr_axcelerator.vhd"
142 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/mul_axcelerator.vhd"
143 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/grpci2_phy_rtax_bypass.vhd"
144 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allclkgen.vhd"
145 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allddr.vhd"
146 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allmem.vhd"
147 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allmul.vhd"
148 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allpads.vhd"
149 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/alltap.vhd"
150 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkgen.vhd"
151 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkmux.vhd"
152 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkinv.vhd"
153 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkand.vhd"
154 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ddr_ireg.vhd"
155 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ddr_oreg.vhd"
156 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ddrphy.vhd"
157 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram.vhd"
158 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram64.vhd"
159 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram_2p.vhd"
160 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram_dp.vhd"
161 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncfifo_2p.vhd"
162 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/regfile_3p.vhd"
163 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/tap.vhd"
164 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/techbuf.vhd"
165 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/nandtree.vhd"
166 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkpad.vhd"
167 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkpad_ds.vhd"
168 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/inpad.vhd"
169 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/inpad_ds.vhd"
170 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iodpad.vhd"
171 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iopad.vhd"
172 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iopad_ds.vhd"
173 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/lvds_combo.vhd"
174 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/odpad.vhd"
175 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/outpad.vhd"
176 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/outpad_ds.vhd"
177 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/toutpad.vhd"
178 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/skew_outpad.vhd"
179 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/mul_61x61.vhd"
180 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/cpu_disas_net.vhd"
181 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ringosc.vhd"
182 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/grpci2_phy_net.vhd"
183 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/system_monitor.vhd"
184 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/grgates.vhd"
185 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/inpad_ddr.vhd"
186 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/outpad_ddr.vhd"
187 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iopad_ddr.vhd"
188 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram128bw.vhd"
189 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram256bw.vhd"
190 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram128.vhd"
191 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram156bw.vhd"
192 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/techmult.vhd"
193 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/spictrl_net.vhd"
194 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncrambw.vhd"
195 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram_2pbw.vhd"
196 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/sdram_phy.vhd"
197 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/from.vhd"
198 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncreg.vhd"
199 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/serdes.vhd"
200 vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/mtie_maps.vhd"
201 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/comp/spwcomp.vhd"
202 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/core/mtie_core.vhd"
203 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/wrapper/grspw_gen.vhd"
204 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/wrapper/grspw2_gen.vhd"
205 vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/wrapper/grspw_codec_gen.vhd"
206 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/comp/ethcomp.vhd"
207 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_pkg.vhd"
208 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_rstgen.vhd"
209 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_edcl_ahb_mst.vhd"
210 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_ahb_mst_gbit.vhd"
211 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_ahb_mst.vhd"
212 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbit_rx.vhd"
213 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbit_tx.vhd"
214 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbit_gtx.vhd"
215 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_tx.vhd"
216 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_rx.vhd"
217 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbitc.vhd"
218 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/grethc.vhd"
219 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/wrapper/greth_gen.vhd"
220 vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/wrapper/greth_gbit_gen.vhd"
221 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/arith/arith.vhd"
222 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/arith/mul32.vhd"
223 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/arith/div32.vhd"
224 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/memctrl.vhd"
225 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/sdctrl.vhd"
226 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/sdctrl64.vhd"
227 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/sdmctrl.vhd"
228 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/srctrl.vhd"
229 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ssrctrl.vhd"
230 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsrctrlc.vhd"
231 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsrctrl.vhd"
232 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsdctrl.vhd"
233 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsrctrl8.vhd"
234 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsdmctrl.vhd"
235 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftmctrl.vhd"
236 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsdctrl64.vhd"
237 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/grlfpu/mtie_grlfpu.vhd"
238 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/grlfpc/mtie_grlfpc.vhd"
239 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmuconfig.vhd"
240 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmuiface.vhd"
241 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/libmmu.vhd"
242 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmutlbcam.vhd"
243 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmulrue.vhd"
244 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmulru.vhd"
245 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmutlb.vhd"
246 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmutw.vhd"
247 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmu.vhd"
248 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/leon3/leon3.vhd"
249 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/leon3/grfpushwx.vhd"
250 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/leon3v3/mtie_leon3v3.vhd"
251 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqmp.vhd"
252 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqmp2x.vhd"
253 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqamp.vhd"
254 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqamp2x.vhd"
255 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/l2cache/v2-pkg/l2cache.vhd"
256 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/misc.vhd"
257 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/rstgen.vhd"
258 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/gptimer.vhd"
259 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbram.vhd"
260 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbdpram.vhd"
261 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbtrace_mmb.vhd"
262 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbtrace_mb.vhd"
263 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbtrace.vhd"
264 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grgpio.vhd"
265 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ftahbram.vhd"
266 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ftahbram2.vhd"
267 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbstat.vhd"
268 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/logan.vhd"
269 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/apbps2.vhd"
270 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/charrom_package.vhd"
271 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/charrom.vhd"
272 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/apbvga.vhd"
273 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahb2ahb.vhd"
274 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbbridge.vhd"
275 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/svgactrl.vhd"
276 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grfifo.vhd"
277 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/gradcdac.vhd"
278 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grsysmon.vhd"
279 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/gracectrl.vhd"
280 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grgpreg.vhd"
281 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/memscrub.vhd"
282 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahb_mst_iface.vhd"
283 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grgprbank.vhd"
284 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grclkgate.vhd"
285 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grclkgate2x.vhd"
286 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grtimer.vhd"
287 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grpulse.vhd"
288 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grversion.vhd"
289 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbfrom.vhd"
290 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/ambatest/ahbtbp.vhd"
291 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/ambatest/ahbtbm.vhd"
292 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/net/net.vhd"
293 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/uart.vhd"
294 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/libdcom.vhd"
295 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/apbuart.vhd"
296 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/dcom.vhd"
297 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/dcom_uart.vhd"
298 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/ahbuart.vhd"
299 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sim.vhd"
300 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sram.vhd"
301 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sramft.vhd"
302 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sram16.vhd"
303 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/phy.vhd"
304 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ahbrep.vhd"
305 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/delay_wire.vhd"
306 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/pwm_check.vhd"
307 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ramback.vhd"
308 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/zbtssram.vhd"
309 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/slavecheck.vhd"
310 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/spwtrace.vhd"
311 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/spwtracev.vhd"
312 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ddrram.vhd"
313 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ddr2ram.vhd"
314 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ddr3ram.vhd"
315 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtag.vhd"
316 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/libjtagcom.vhd"
317 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtagcom.vhd"
318 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/ahbjtag.vhd"
319 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/ahbjtag_bsd.vhd"
320 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/bscanctrl.vhd"
321 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/bscanregs.vhd"
322 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/bscanregsbd.vhd"
323 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtagcom2.vhd"
324 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtagtst.vhd"
325 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/spacewire.vhd"
326 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw.vhd"
327 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw2.vhd"
328 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspwm.vhd"
329 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw2_phy.vhd"
330 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw_codec_clockgate.vhd"
331 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw_phy.vhd"
332 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/gr1553b/gr1553b_pkg.vhd"
333 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/gr1553b/gr1553b_pads.vhd"
334 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/gr1553b/simtrans1553.vhd"
335 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/nand/nandpkg.vhd"
336 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/nand/nandfctrlx.vhd"
337 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/nand/nandfctrl.vhd"
338 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/clk2x/clk2x.vhd"
339 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/clk2x/qmod.vhd"
340 vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/clk2x/qmod_prect.vhd"
341 vcom -93 -explicit -work esa "${PROJECT_DIR}/../../../GRLIB/lib/esa/memoryctrl/memoryctrl.vhd"
342 vcom -93 -explicit -work esa "${PROJECT_DIR}/../../../GRLIB/lib/esa/memoryctrl/mctrl.vhd"
343 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/utilities/conversions.vhd"
344 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/utilities/gen_utils.vhd"
345 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/flash/flash.vhd"
346 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/flash/s25fl064a.vhd"
347 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/flash/m25p80.vhd"
348 vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/fifo/idt7202.vhd"
349 vcom -93 -explicit -work gsi "${PROJECT_DIR}/../../../GRLIB/lib/gsi/ssram/functions.vhd"
350 vcom -93 -explicit -work gsi "${PROJECT_DIR}/../../../GRLIB/lib/gsi/ssram/core_burst.vhd"
351 vcom -93 -explicit -work gsi "${PROJECT_DIR}/../../../GRLIB/lib/gsi/ssram/g880e18bt.vhd"
352 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./apb_devices/apb_devices_list.vhd"
353 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./apb_devices/apb_devices.vhd"
354 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./memctrlr/memctrlr.vhd"
355 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./memctrlr/srctrle-0ws.vhd"
356 vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./memctrlr/srctrle-1ws.vhd"
357 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/data_type_pkg.vhd"
358 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/general_purpose.vhd"
359 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/ADDRcntr.vhd"
360 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/ALU.vhd"
361 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Adder.vhd"
362 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Clk_Divider2.vhd"
363 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Clk_divider.vhd"
364 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC.vhd"
365 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_CONTROLER.vhd"
366 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_MUX.vhd"
367 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_MUX2.vhd"
368 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_REG.vhd"
369 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MUX2.vhd"
370 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MUXN.vhd"
371 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Multiplier.vhd"
372 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/REG.vhd"
373 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/SYNC_FF.vhd"
374 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Shifter.vhd"
375 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/TwoComplementer.vhd"
376 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Clock_Divider.vhd"
377 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/lpp_front_to_level.vhd"
378 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/lpp_front_detection.vhd"
379 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd"
380 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/RR_Arbiter_4.vhd"
381 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/general_counter.vhd"
382 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/ramp_generator.vhd"
383 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_amba/apb_devices_list.vhd"
384 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_amba/lpp_amba.vhd"
385 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/chirp/chirp_pkg.vhd"
386 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/chirp/chirp.vhd"
387 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/iir_filter.vhd"
388 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd"
389 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/RAM.vhd"
390 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd"
391 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd"
392 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd"
393 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd"
394 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd"
395 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd"
396 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd"
397 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_pkg.vhd"
398 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic.vhd"
399 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_integrator.vhd"
400 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_downsampler.vhd"
401 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_comb.vhd"
402 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr.vhd"
403 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_control.vhd"
404 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_add_sub.vhd"
405 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_address_gen.vhd"
406 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_r2.vhd"
407 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_control_r2.vhd"
408 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd"
409 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/fft_components.vhd"
410 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/lpp_fft.vhd"
411 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/actar.vhd"
412 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/actram.vhd"
413 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/fftDp.vhd"
414 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/fftSm.vhd"
415 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/primitives.vhd"
416 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/twiddle.vhd"
417 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/Driver_FFT.vhd"
418 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/FFT.vhd"
419 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/Linker_FFT.vhd"
420 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/window_function_pkg.vhd"
421 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/window_function.vhd"
422 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/WF_processing.vhd"
423 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/WF_rom.vhd"
424 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_memory.vhd"
425 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO.vhd"
426 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared.vhd"
427 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_control.vhd"
428 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd"
429 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd"
430 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lppFIFOxN.vhd"
431 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd"
432 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/RHF1401.vhd"
433 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd"
434 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd"
435 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd"
436 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd"
437 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd"
438 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/lpp_lfr_hk.vhd"
439 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd"
440 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd"
441 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/MS_control.vhd"
442 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd"
443 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd"
444 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_demux/DEMUX.vhd"
445 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_demux/lpp_demux.vhd"
446 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_Header/lpp_Header.vhd"
447 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_Header/HeaderBuilder.vhd"
448 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/lpp_matrix.vhd"
449 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/ALU_Driver.vhd"
450 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd"
451 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/Dispatch.vhd"
452 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/DriveInputs.vhd"
453 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/GetResult.vhd"
454 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd"
455 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/Matrix.vhd"
456 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/SpectralMatrix.vhd"
457 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd"
458 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd"
459 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/fifo_latency_correction.vhd"
460 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma.vhd"
461 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_ip.vhd"
462 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd"
463 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd"
464 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd"
465 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem.vhd"
466 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd"
467 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd"
468 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd"
469 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd"
470 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd"
471 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform.vhd"
472 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd"
473 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd"
474 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd"
475 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd"
476 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd"
477 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd"
478 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd"
479 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd"
480 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd"
481 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd"
482 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd"
483 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd"
484 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd"
485 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd"
486 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd"
487 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd"
488 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd"
489 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd"
490 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd"
491 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd"
492 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd"
493 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd"
494 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_reg_head.vhd"
495 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd"
496 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd"
497 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd"
498 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd"
499 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd"
500 vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_file/reader_pkg.vhd"
501 vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/components.vhd"
502 vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/package_utility.vhd"
503 vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/cy7c1354b.vhd"
504 vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/cy7c1380d.vhd"
505 vcom -93 -explicit -work presynth "${PROJECT_DIR}/../../../GRLIB/lib/work/debug/debug.vhd"
506 vcom -93 -explicit -work presynth "${PROJECT_DIR}/../../../GRLIB/lib/work/debug/grtestmod.vhd"
507 vcom -93 -explicit -work presynth "${PROJECT_DIR}/../../../GRLIB/lib/work/debug/cpu_disas.vhd"
508 vcom -93 -explicit -work presynth "${PROJECT_DIR}/IIR_CEL_TEST.vhd"
509 vcom -93 -explicit -work presynth "${PROJECT_DIR}/tb.vhd"
510 vcom -93 -explicit -work presynth "${PROJECT_DIR}/IIR_CEL_TEST_v3.vhd"
511 vcom -93 -explicit -work presynth "${PROJECT_DIR}/generator.vhd"
512
513 vsim #VSIM_ARGS# -L Axcelerator -L presynth -L grlib -L synplify -L techmap -L spw -L eth -L gaisler -L esa -L fmf -L spansion -L gsi -L iap -L lpp -L cypress -t 1ps presynth.testbench
514 # The following lines are commented because no testbench is associated with the project
515 # do "wave.do"
516 run 2000ms
Show file before | Show file after | Hide comments
@@ -39,3 +39,4 actar.vhd
39 39 *.bak
40 40 *.pdc.ce
41 41 *.zip
42 */.ipynb_checkpoints/*
Show file before | Show file after | Hide comments
@@ -1,208 +1,208
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
14 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
15 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
16
17 -- LEON3 processor core
18 constant CFG_LEON3 : integer := CONFIG_LEON3;
19 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
20 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
21 constant CFG_V8 : integer := CFG_IU_V8;
22 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
23 constant CFG_SVT : integer := CONFIG_IU_SVT;
24 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
25 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
26 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
27 constant CFG_PWD : integer := CONFIG_PWD*2;
28 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
29 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
30 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
31 constant CFG_ISETS : integer := CFG_IU_ISETS;
32 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
33 constant CFG_ILINE : integer := CFG_ILINE_SZ;
34 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
35 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
36 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
37 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
38 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
39 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
40 constant CFG_DSETS : integer := CFG_IU_DSETS;
41 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
42 constant CFG_DLINE : integer := CFG_DLINE_SZ;
43 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
44 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
45 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
46 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
47 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
48 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
49 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
50 constant CFG_MMUEN : integer := CONFIG_MMUEN;
51 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
52 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
53 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
54 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
55 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
56 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
57 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
58 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
59 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
60 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
61 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
62 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
63 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
64 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
65 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
66 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
67 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
68
69 -- AMBA settings
70 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
71 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
72 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
73 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
74 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
75 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
76 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
77 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
78
79 -- DSU UART
80 constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
81
82 -- JTAG based DSU interface
83 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
84
85 -- Ethernet DSU
86 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
87 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
88 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
89 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
90 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
91 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
92
93 -- PROM/SRAM controller
94 constant CFG_SRCTRL : integer := CONFIG_SRCTRL;
95 constant CFG_SRCTRL_PROMWS : integer := CONFIG_SRCTRL_PROMWS;
96 constant CFG_SRCTRL_RAMWS : integer := CONFIG_SRCTRL_RAMWS;
97 constant CFG_SRCTRL_IOWS : integer := CONFIG_SRCTRL_IOWS;
98 constant CFG_SRCTRL_RMW : integer := CONFIG_SRCTRL_RMW;
99 constant CFG_SRCTRL_8BIT : integer := CONFIG_SRCTRL_8BIT;
100
101 constant CFG_SRCTRL_SRBANKS : integer := CFG_SR_CTRL_SRBANKS;
102 constant CFG_SRCTRL_BANKSZ : integer := CFG_SR_CTRL_BANKSZ;
103 constant CFG_SRCTRL_ROMASEL : integer := CONFIG_SRCTRL_ROMASEL;
104 -- LEON2 memory controller
105 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
106 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
107 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
108 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
109 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
110 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
111 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
112 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
113 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
114
115 -- SDRAM controller
116 constant CFG_SDCTRL : integer := CONFIG_SDCTRL;
117 constant CFG_SDCTRL_INVCLK : integer := CONFIG_SDCTRL_INVCLK;
118 constant CFG_SDCTRL_SD64 : integer := CONFIG_SDCTRL_BUS64;
119 constant CFG_SDCTRL_PAGE : integer := CONFIG_SDCTRL_PAGE + CONFIG_SDCTRL_PROGPAGE;
120
121 -- AHB ROM
122 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
123 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
124 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
125 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
126 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
127
128 -- AHB RAM
129 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
130 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
131 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
132
133 -- Gaisler Ethernet core
134 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
135 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
136 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
137
138 -- CAN 2.0 interface
139 constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
140 constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
141 constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
142 constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
143 constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
144 constant CFG_CANFT : integer := CONFIG_CAN_FT;
145
146 -- PCI interface
147 constant CFG_PCI : integer := CFG_PCITYPE;
148 constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#;
149 constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#;
150 constant CFG_PCIDEPTH : integer := CFG_PCIFIFO;
151 constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO;
152
153 -- PCI arbiter
154 constant CFG_PCI_ARB : integer := CONFIG_PCI_ARBITER;
155 constant CFG_PCI_ARBAPB : integer := CONFIG_PCI_ARBITER_APB;
156 constant CFG_PCI_ARB_NGNT : integer := CONFIG_PCI_ARBITER_NREQ;
157
158 -- PCI trace buffer
159 constant CFG_PCITBUFEN: integer := CONFIG_PCI_TRACE;
160 constant CFG_PCITBUF : integer := CFG_PCI_TRACEBUF;
161
162 -- Spacewire interface
163 constant CFG_SPW_EN : integer := CONFIG_SPW_ENABLE;
164 constant CFG_SPW_NUM : integer := CONFIG_SPW_NUM;
165 constant CFG_SPW_AHBFIFO : integer := CONFIG_SPW_AHBFIFO;
166 constant CFG_SPW_RXFIFO : integer := CONFIG_SPW_RXFIFO;
167 constant CFG_SPW_RMAP : integer := CONFIG_SPW_RMAP;
168 constant CFG_SPW_RMAPBUF : integer := CONFIG_SPW_RMAPBUF;
169 constant CFG_SPW_RMAPCRC : integer := CONFIG_SPW_RMAPCRC;
170 constant CFG_SPW_NETLIST : integer := CONFIG_SPW_NETLIST;
171 constant CFG_SPW_FT : integer := CONFIG_SPW_FT;
172 constant CFG_SPW_GRSPW : integer := CONFIG_SPW_GRSPW;
173 constant CFG_SPW_RXUNAL : integer := CONFIG_SPW_RXUNAL;
174 constant CFG_SPW_DMACHAN : integer := CONFIG_SPW_DMACHAN;
175 constant CFG_SPW_PORTS : integer := CONFIG_SPW_PORTS;
176 constant CFG_SPW_INPUT : integer := CONFIG_SPW_INPUT;
177 constant CFG_SPW_OUTPUT : integer := CONFIG_SPW_OUTPUT;
178 constant CFG_SPW_RTSAME : integer := CONFIG_SPW_RTSAME;
179 -- UART 1
180 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
181 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
182
183 -- UART 2
184 constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE;
185 constant CFG_UART2_FIFO : integer := CFG_UA2_FIFO;
186
187 -- LEON3 interrupt controller
188 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
189 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
190
191 -- Modular timer
192 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
193 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
194 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
195 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
196 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
197 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
198 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
199 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
200
201 -- GPIO port
202 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
203 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
204 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
205
206 -- GRLIB debugging
207 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
208
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
14 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
15 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
16
17 -- LEON3 processor core
18 constant CFG_LEON3 : integer := CONFIG_LEON3;
19 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
20 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
21 constant CFG_V8 : integer := CFG_IU_V8;
22 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
23 constant CFG_SVT : integer := CONFIG_IU_SVT;
24 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
25 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
26 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
27 constant CFG_PWD : integer := CONFIG_PWD*2;
28 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
29 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
30 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
31 constant CFG_ISETS : integer := CFG_IU_ISETS;
32 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
33 constant CFG_ILINE : integer := CFG_ILINE_SZ;
34 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
35 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
36 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
37 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
38 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
39 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
40 constant CFG_DSETS : integer := CFG_IU_DSETS;
41 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
42 constant CFG_DLINE : integer := CFG_DLINE_SZ;
43 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
44 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
45 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
46 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
47 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
48 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
49 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
50 constant CFG_MMUEN : integer := CONFIG_MMUEN;
51 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
52 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
53 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
54 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
55 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
56 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
57 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
58 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
59 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
60 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
61 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
62 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
63 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
64 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
65 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
66 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
67 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
68
69 -- AMBA settings
70 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
71 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
72 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
73 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
74 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
75 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
76 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
77 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
78
79 -- DSU UART
80 constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
81
82 -- JTAG based DSU interface
83 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
84
85 -- Ethernet DSU
86 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
87 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
88 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
89 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
90 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
91 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
92
93 -- PROM/SRAM controller
94 constant CFG_SRCTRL : integer := CONFIG_SRCTRL;
95 constant CFG_SRCTRL_PROMWS : integer := CONFIG_SRCTRL_PROMWS;
96 constant CFG_SRCTRL_RAMWS : integer := CONFIG_SRCTRL_RAMWS;
97 constant CFG_SRCTRL_IOWS : integer := CONFIG_SRCTRL_IOWS;
98 constant CFG_SRCTRL_RMW : integer := CONFIG_SRCTRL_RMW;
99 constant CFG_SRCTRL_8BIT : integer := CONFIG_SRCTRL_8BIT;
100
101 constant CFG_SRCTRL_SRBANKS : integer := CFG_SR_CTRL_SRBANKS;
102 constant CFG_SRCTRL_BANKSZ : integer := CFG_SR_CTRL_BANKSZ;
103 constant CFG_SRCTRL_ROMASEL : integer := CONFIG_SRCTRL_ROMASEL;
104 -- LEON2 memory controller
105 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
106 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
107 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
108 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
109 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
110 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
111 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
112 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
113 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
114
115 -- SDRAM controller
116 constant CFG_SDCTRL : integer := CONFIG_SDCTRL;
117 constant CFG_SDCTRL_INVCLK : integer := CONFIG_SDCTRL_INVCLK;
118 constant CFG_SDCTRL_SD64 : integer := CONFIG_SDCTRL_BUS64;
119 constant CFG_SDCTRL_PAGE : integer := CONFIG_SDCTRL_PAGE + CONFIG_SDCTRL_PROGPAGE;
120
121 -- AHB ROM
122 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
123 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
124 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
125 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
126 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
127
128 -- AHB RAM
129 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
130 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
131 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
132
133 -- Gaisler Ethernet core
134 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
135 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
136 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
137
138 -- CAN 2.0 interface
139 constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
140 constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
141 constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
142 constant CFG_CANLOOP : integer := CONFIG_CANLOOP;
143 constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
144 constant CFG_CANFT : integer := CONFIG_CAN_FT;
145
146 -- PCI interface
147 constant CFG_PCI : integer := CFG_PCITYPE;
148 constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#;
149 constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#;
150 constant CFG_PCIDEPTH : integer := CFG_PCIFIFO;
151 constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO;
152
153 -- PCI arbiter
154 constant CFG_PCI_ARB : integer := CONFIG_PCI_ARBITER;
155 constant CFG_PCI_ARBAPB : integer := CONFIG_PCI_ARBITER_APB;
156 constant CFG_PCI_ARB_NGNT : integer := CONFIG_PCI_ARBITER_NREQ;
157
158 -- PCI trace buffer
159 constant CFG_PCITBUFEN: integer := CONFIG_PCI_TRACE;
160 constant CFG_PCITBUF : integer := CFG_PCI_TRACEBUF;
161
162 -- Spacewire interface
163 constant CFG_SPW_EN : integer := CONFIG_SPW_ENABLE;
164 constant CFG_SPW_NUM : integer := CONFIG_SPW_NUM;
165 constant CFG_SPW_AHBFIFO : integer := CONFIG_SPW_AHBFIFO;
166 constant CFG_SPW_RXFIFO : integer := CONFIG_SPW_RXFIFO;
167 constant CFG_SPW_RMAP : integer := CONFIG_SPW_RMAP;
168 constant CFG_SPW_RMAPBUF : integer := CONFIG_SPW_RMAPBUF;
169 constant CFG_SPW_RMAPCRC : integer := CONFIG_SPW_RMAPCRC;
170 constant CFG_SPW_NETLIST : integer := CONFIG_SPW_NETLIST;
171 constant CFG_SPW_FT : integer := CONFIG_SPW_FT;
172 constant CFG_SPW_GRSPW : integer := CONFIG_SPW_GRSPW;
173 constant CFG_SPW_RXUNAL : integer := CONFIG_SPW_RXUNAL;
174 constant CFG_SPW_DMACHAN : integer := CONFIG_SPW_DMACHAN;
175 constant CFG_SPW_PORTS : integer := CONFIG_SPW_PORTS;
176 constant CFG_SPW_INPUT : integer := CONFIG_SPW_INPUT;
177 constant CFG_SPW_OUTPUT : integer := CONFIG_SPW_OUTPUT;
178 constant CFG_SPW_RTSAME : integer := CONFIG_SPW_RTSAME;
179 -- UART 1
180 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
181 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
182
183 -- UART 2
184 constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE;
185 constant CFG_UART2_FIFO : integer := CFG_UA2_FIFO;
186
187 -- LEON3 interrupt controller
188 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
189 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
190
191 -- Modular timer
192 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
193 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
194 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
195 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
196 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
197 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
198 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
199 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
200
201 -- GPIO port
202 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
203 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
204 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
205
206 -- GRLIB debugging
207 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
208
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@@ -1,1189 +1,1189
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_PROASICPLUS
14 #define CONFIG_SYN_TECH proasic
15 #elif defined CONFIG_SYN_ALTERA
16 #define CONFIG_SYN_TECH altera
17 #elif defined CONFIG_SYN_STRATIX
18 #define CONFIG_SYN_TECH stratix1
19 #elif defined CONFIG_SYN_STRATIXII
20 #define CONFIG_SYN_TECH stratix2
21 #elif defined CONFIG_SYN_STRATIXIII
22 #define CONFIG_SYN_TECH stratix3
23 #elif defined CONFIG_SYN_CYCLONEIII
24 #define CONFIG_SYN_TECH cyclone3
25 #elif defined CONFIG_SYN_EASIC90
26 #define CONFIG_SYN_TECH easic90
27 #elif defined CONFIG_SYN_IHP25
28 #define CONFIG_SYN_TECH ihp25
29 #elif defined CONFIG_SYN_IHP25RH
30 #define CONFIG_SYN_TECH ihp25rh
31 #elif defined CONFIG_SYN_LATTICE
32 #define CONFIG_SYN_TECH lattice
33 #elif defined CONFIG_SYN_ECLIPSE
34 #define CONFIG_SYN_TECH eclipse
35 #elif defined CONFIG_SYN_PEREGRINE
36 #define CONFIG_SYN_TECH peregrine
37 #elif defined CONFIG_SYN_PROASIC
38 #define CONFIG_SYN_TECH proasic
39 #elif defined CONFIG_SYN_PROASIC3
40 #define CONFIG_SYN_TECH apa3
41 #elif defined CONFIG_SYN_SPARTAN2
42 #define CONFIG_SYN_TECH virtex
43 #elif defined CONFIG_SYN_VIRTEX
44 #define CONFIG_SYN_TECH virtex
45 #elif defined CONFIG_SYN_VIRTEXE
46 #define CONFIG_SYN_TECH virtex
47 #elif defined CONFIG_SYN_SPARTAN3
48 #define CONFIG_SYN_TECH spartan3
49 #elif defined CONFIG_SYN_SPARTAN3E
50 #define CONFIG_SYN_TECH spartan3e
51 #elif defined CONFIG_SYN_VIRTEX2
52 #define CONFIG_SYN_TECH virtex2
53 #elif defined CONFIG_SYN_VIRTEX4
54 #define CONFIG_SYN_TECH virtex4
55 #elif defined CONFIG_SYN_VIRTEX5
56 #define CONFIG_SYN_TECH virtex5
57 #elif defined CONFIG_SYN_RH_LIB18T
58 #define CONFIG_SYN_TECH rhlib18t
59 #elif defined CONFIG_SYN_SMIC13
60 #define CONFIG_SYN_TECH smic013
61 #elif defined CONFIG_SYN_UT025CRH
62 #define CONFIG_SYN_TECH ut25
63 #elif defined CONFIG_SYN_TSMC90
64 #define CONFIG_SYN_TECH tsmc90
65 #elif defined CONFIG_SYN_CUSTOM1
66 #define CONFIG_SYN_TECH custom1
67 #else
68 #error "unknown target technology"
69 #endif
70
71 #if defined CONFIG_SYN_INFER_RAM
72 #define CFG_RAM_TECH inferred
73 #elif defined CONFIG_MEM_UMC
74 #define CFG_RAM_TECH umc
75 #elif defined CONFIG_MEM_RHUMC
76 #define CFG_RAM_TECH rhumc
77 #elif defined CONFIG_MEM_VIRAGE
78 #define CFG_RAM_TECH memvirage
79 #elif defined CONFIG_MEM_ARTISAN
80 #define CFG_RAM_TECH memartisan
81 #elif defined CONFIG_MEM_CUSTOM1
82 #define CFG_RAM_TECH custom1
83 #elif defined CONFIG_MEM_VIRAGE90
84 #define CFG_RAM_TECH memvirage90
85 #elif defined CONFIG_MEM_INFERRED
86 #define CFG_RAM_TECH inferred
87 #else
88 #define CFG_RAM_TECH CONFIG_SYN_TECH
89 #endif
90
91 #if defined CONFIG_SYN_INFER_PADS
92 #define CFG_PAD_TECH inferred
93 #else
94 #define CFG_PAD_TECH CONFIG_SYN_TECH
95 #endif
96
97 #ifndef CONFIG_SYN_NO_ASYNC
98 #define CONFIG_SYN_NO_ASYNC 0
99 #endif
100
101 #ifndef CONFIG_SYN_SCAN
102 #define CONFIG_SYN_SCAN 0
103 #endif
104
105
106 #if defined CONFIG_CLK_ALTDLL
107 #define CFG_CLK_TECH CONFIG_SYN_TECH
108 #elif defined CONFIG_CLK_HCLKBUF
109 #define CFG_CLK_TECH axcel
110 #elif defined CONFIG_CLK_LATDLL
111 #define CFG_CLK_TECH lattice
112 #elif defined CONFIG_CLK_PRO3PLL
113 #define CFG_CLK_TECH apa3
114 #elif defined CONFIG_CLK_CLKDLL
115 #define CFG_CLK_TECH virtex
116 #elif defined CONFIG_CLK_DCM
117 #define CFG_CLK_TECH CONFIG_SYN_TECH
118 #elif defined CONFIG_CLK_LIB18T
119 #define CFG_CLK_TECH rhlib18t
120 #elif defined CONFIG_CLK_RHUMC
121 #define CFG_CLK_TECH rhumc
122 #else
123 #define CFG_CLK_TECH inferred
124 #endif
125
126 #ifndef CONFIG_CLK_MUL
127 #define CONFIG_CLK_MUL 2
128 #endif
129
130 #ifndef CONFIG_CLK_DIV
131 #define CONFIG_CLK_DIV 2
132 #endif
133
134 #ifndef CONFIG_OCLK_DIV
135 #define CONFIG_OCLK_DIV 2
136 #endif
137
138 #ifndef CONFIG_PCI_CLKDLL
139 #define CONFIG_PCI_CLKDLL 0
140 #endif
141
142 #ifndef CONFIG_PCI_SYSCLK
143 #define CONFIG_PCI_SYSCLK 0
144 #endif
145
146 #ifndef CONFIG_CLK_NOFB
147 #define CONFIG_CLK_NOFB 0
148 #endif
149 #ifndef CONFIG_LEON3
150 #define CONFIG_LEON3 0
151 #endif
152
153 #ifndef CONFIG_PROC_NUM
154 #define CONFIG_PROC_NUM 1
155 #endif
156
157 #ifndef CONFIG_IU_NWINDOWS
158 #define CONFIG_IU_NWINDOWS 8
159 #endif
160
161 #ifndef CONFIG_IU_RSTADDR
162 #define CONFIG_IU_RSTADDR 8
163 #endif
164
165 #ifndef CONFIG_IU_LDELAY
166 #define CONFIG_IU_LDELAY 1
167 #endif
168
169 #ifndef CONFIG_IU_WATCHPOINTS
170 #define CONFIG_IU_WATCHPOINTS 0
171 #endif
172
173 #ifdef CONFIG_IU_V8MULDIV
174 #ifdef CONFIG_IU_MUL_LATENCY_4
175 #define CFG_IU_V8 1
176 #elif defined CONFIG_IU_MUL_LATENCY_5
177 #define CFG_IU_V8 2
178 #elif defined CONFIG_IU_MUL_LATENCY_2
179 #define CFG_IU_V8 16#32#
180 #endif
181 #else
182 #define CFG_IU_V8 0
183 #endif
184
185 #ifndef CONFIG_PWD
186 #define CONFIG_PWD 0
187 #endif
188
189 #ifndef CONFIG_IU_MUL_MAC
190 #define CONFIG_IU_MUL_MAC 0
191 #endif
192
193 #ifndef CONFIG_IU_SVT
194 #define CONFIG_IU_SVT 0
195 #endif
196
197 #if defined CONFIG_FPU_GRFPC1
198 #define CONFIG_FPU_GRFPC 1
199 #elif defined CONFIG_FPU_GRFPC2
200 #define CONFIG_FPU_GRFPC 2
201 #else
202 #define CONFIG_FPU_GRFPC 0
203 #endif
204
205 #if defined CONFIG_FPU_GRFPU_INFMUL
206 #define CONFIG_FPU_GRFPU_MUL 0
207 #elif defined CONFIG_FPU_GRFPU_DWMUL
208 #define CONFIG_FPU_GRFPU_MUL 1
209 #elif defined CONFIG_FPU_GRFPU_MODGEN
210 #define CONFIG_FPU_GRFPU_MUL 2
211 #else
212 #define CONFIG_FPU_GRFPU_MUL 0
213 #endif
214
215 #if defined CONFIG_FPU_GRFPU_SH
216 #define CONFIG_FPU_GRFPU_SHARED 1
217 #else
218 #define CONFIG_FPU_GRFPU_SHARED 0
219 #endif
220
221 #if defined CONFIG_FPU_GRFPU
222 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
223 #elif defined CONFIG_FPU_MEIKO
224 #define CONFIG_FPU 15
225 #elif defined CONFIG_FPU_GRFPULITE
226 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
227 #else
228 #define CONFIG_FPU 0
229 #endif
230
231 #ifndef CONFIG_FPU_NETLIST
232 #define CONFIG_FPU_NETLIST 0
233 #endif
234
235 #ifndef CONFIG_ICACHE_ENABLE
236 #define CONFIG_ICACHE_ENABLE 0
237 #endif
238
239 #if defined CONFIG_ICACHE_ASSO1
240 #define CFG_IU_ISETS 1
241 #elif defined CONFIG_ICACHE_ASSO2
242 #define CFG_IU_ISETS 2
243 #elif defined CONFIG_ICACHE_ASSO3
244 #define CFG_IU_ISETS 3
245 #elif defined CONFIG_ICACHE_ASSO4
246 #define CFG_IU_ISETS 4
247 #else
248 #define CFG_IU_ISETS 1
249 #endif
250
251 #if defined CONFIG_ICACHE_SZ1
252 #define CFG_ICACHE_SZ 1
253 #elif defined CONFIG_ICACHE_SZ2
254 #define CFG_ICACHE_SZ 2
255 #elif defined CONFIG_ICACHE_SZ4
256 #define CFG_ICACHE_SZ 4
257 #elif defined CONFIG_ICACHE_SZ8
258 #define CFG_ICACHE_SZ 8
259 #elif defined CONFIG_ICACHE_SZ16
260 #define CFG_ICACHE_SZ 16
261 #elif defined CONFIG_ICACHE_SZ32
262 #define CFG_ICACHE_SZ 32
263 #elif defined CONFIG_ICACHE_SZ64
264 #define CFG_ICACHE_SZ 64
265 #elif defined CONFIG_ICACHE_SZ128
266 #define CFG_ICACHE_SZ 128
267 #elif defined CONFIG_ICACHE_SZ256
268 #define CFG_ICACHE_SZ 256
269 #else
270 #define CFG_ICACHE_SZ 1
271 #endif
272
273 #ifdef CONFIG_ICACHE_LZ16
274 #define CFG_ILINE_SZ 4
275 #else
276 #define CFG_ILINE_SZ 8
277 #endif
278
279 #if defined CONFIG_ICACHE_ALGORND
280 #define CFG_ICACHE_ALGORND 2
281 #elif defined CONFIG_ICACHE_ALGOLRR
282 #define CFG_ICACHE_ALGORND 1
283 #else
284 #define CFG_ICACHE_ALGORND 0
285 #endif
286
287 #ifndef CONFIG_ICACHE_LOCK
288 #define CONFIG_ICACHE_LOCK 0
289 #endif
290
291 #ifndef CONFIG_ICACHE_LRAM
292 #define CONFIG_ICACHE_LRAM 0
293 #endif
294
295 #ifndef CONFIG_ICACHE_LRSTART
296 #define CONFIG_ICACHE_LRSTART 8E
297 #endif
298
299 #if defined CONFIG_ICACHE_LRAM_SZ2
300 #define CFG_ILRAM_SIZE 2
301 #elif defined CONFIG_ICACHE_LRAM_SZ4
302 #define CFG_ILRAM_SIZE 4
303 #elif defined CONFIG_ICACHE_LRAM_SZ8
304 #define CFG_ILRAM_SIZE 8
305 #elif defined CONFIG_ICACHE_LRAM_SZ16
306 #define CFG_ILRAM_SIZE 16
307 #elif defined CONFIG_ICACHE_LRAM_SZ32
308 #define CFG_ILRAM_SIZE 32
309 #elif defined CONFIG_ICACHE_LRAM_SZ64
310 #define CFG_ILRAM_SIZE 64
311 #elif defined CONFIG_ICACHE_LRAM_SZ128
312 #define CFG_ILRAM_SIZE 128
313 #elif defined CONFIG_ICACHE_LRAM_SZ256
314 #define CFG_ILRAM_SIZE 256
315 #else
316 #define CFG_ILRAM_SIZE 1
317 #endif
318
319
320 #ifndef CONFIG_DCACHE_ENABLE
321 #define CONFIG_DCACHE_ENABLE 0
322 #endif
323
324 #if defined CONFIG_DCACHE_ASSO1
325 #define CFG_IU_DSETS 1
326 #elif defined CONFIG_DCACHE_ASSO2
327 #define CFG_IU_DSETS 2
328 #elif defined CONFIG_DCACHE_ASSO3
329 #define CFG_IU_DSETS 3
330 #elif defined CONFIG_DCACHE_ASSO4
331 #define CFG_IU_DSETS 4
332 #else
333 #define CFG_IU_DSETS 1
334 #endif
335
336 #if defined CONFIG_DCACHE_SZ1
337 #define CFG_DCACHE_SZ 1
338 #elif defined CONFIG_DCACHE_SZ2
339 #define CFG_DCACHE_SZ 2
340 #elif defined CONFIG_DCACHE_SZ4
341 #define CFG_DCACHE_SZ 4
342 #elif defined CONFIG_DCACHE_SZ8
343 #define CFG_DCACHE_SZ 8
344 #elif defined CONFIG_DCACHE_SZ16
345 #define CFG_DCACHE_SZ 16
346 #elif defined CONFIG_DCACHE_SZ32
347 #define CFG_DCACHE_SZ 32
348 #elif defined CONFIG_DCACHE_SZ64
349 #define CFG_DCACHE_SZ 64
350 #elif defined CONFIG_DCACHE_SZ128
351 #define CFG_DCACHE_SZ 128
352 #elif defined CONFIG_DCACHE_SZ256
353 #define CFG_DCACHE_SZ 256
354 #else
355 #define CFG_DCACHE_SZ 1
356 #endif
357
358 #ifdef CONFIG_DCACHE_LZ16
359 #define CFG_DLINE_SZ 4
360 #else
361 #define CFG_DLINE_SZ 8
362 #endif
363
364 #if defined CONFIG_DCACHE_ALGORND
365 #define CFG_DCACHE_ALGORND 2
366 #elif defined CONFIG_DCACHE_ALGOLRR
367 #define CFG_DCACHE_ALGORND 1
368 #else
369 #define CFG_DCACHE_ALGORND 0
370 #endif
371
372 #ifndef CONFIG_DCACHE_LOCK
373 #define CONFIG_DCACHE_LOCK 0
374 #endif
375
376 #ifndef CONFIG_DCACHE_SNOOP
377 #define CONFIG_DCACHE_SNOOP 0
378 #endif
379
380 #ifndef CONFIG_DCACHE_SNOOP_FAST
381 #define CONFIG_DCACHE_SNOOP_FAST 0
382 #endif
383
384 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
385 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
386 #endif
387
388 #ifndef CONFIG_CACHE_FIXED
389 #define CONFIG_CACHE_FIXED 0
390 #endif
391
392 #ifndef CONFIG_DCACHE_LRAM
393 #define CONFIG_DCACHE_LRAM 0
394 #endif
395
396 #ifndef CONFIG_DCACHE_LRSTART
397 #define CONFIG_DCACHE_LRSTART 8F
398 #endif
399
400 #if defined CONFIG_DCACHE_LRAM_SZ2
401 #define CFG_DLRAM_SIZE 2
402 #elif defined CONFIG_DCACHE_LRAM_SZ4
403 #define CFG_DLRAM_SIZE 4
404 #elif defined CONFIG_DCACHE_LRAM_SZ8
405 #define CFG_DLRAM_SIZE 8
406 #elif defined CONFIG_DCACHE_LRAM_SZ16
407 #define CFG_DLRAM_SIZE 16
408 #elif defined CONFIG_DCACHE_LRAM_SZ32
409 #define CFG_DLRAM_SIZE 32
410 #elif defined CONFIG_DCACHE_LRAM_SZ64
411 #define CFG_DLRAM_SIZE 64
412 #elif defined CONFIG_DCACHE_LRAM_SZ128
413 #define CFG_DLRAM_SIZE 128
414 #elif defined CONFIG_DCACHE_LRAM_SZ256
415 #define CFG_DLRAM_SIZE 256
416 #else
417 #define CFG_DLRAM_SIZE 1
418 #endif
419
420 #if defined CONFIG_MMU_PAGE_4K
421 #define CONFIG_MMU_PAGE 0
422 #elif defined CONFIG_MMU_PAGE_8K
423 #define CONFIG_MMU_PAGE 1
424 #elif defined CONFIG_MMU_PAGE_16K
425 #define CONFIG_MMU_PAGE 2
426 #elif defined CONFIG_MMU_PAGE_32K
427 #define CONFIG_MMU_PAGE 3
428 #elif defined CONFIG_MMU_PAGE_PROG
429 #define CONFIG_MMU_PAGE 4
430 #else
431 #define CONFIG_MMU_PAGE 0
432 #endif
433
434 #ifdef CONFIG_MMU_ENABLE
435 #define CONFIG_MMUEN 1
436
437 #ifdef CONFIG_MMU_SPLIT
438 #define CONFIG_TLB_TYPE 0
439 #endif
440 #ifdef CONFIG_MMU_COMBINED
441 #define CONFIG_TLB_TYPE 1
442 #endif
443
444 #ifdef CONFIG_MMU_REPARRAY
445 #define CONFIG_TLB_REP 0
446 #endif
447 #ifdef CONFIG_MMU_REPINCREMENT
448 #define CONFIG_TLB_REP 1
449 #endif
450
451 #ifdef CONFIG_MMU_I2
452 #define CONFIG_ITLBNUM 2
453 #endif
454 #ifdef CONFIG_MMU_I4
455 #define CONFIG_ITLBNUM 4
456 #endif
457 #ifdef CONFIG_MMU_I8
458 #define CONFIG_ITLBNUM 8
459 #endif
460 #ifdef CONFIG_MMU_I16
461 #define CONFIG_ITLBNUM 16
462 #endif
463 #ifdef CONFIG_MMU_I32
464 #define CONFIG_ITLBNUM 32
465 #endif
466
467 #define CONFIG_DTLBNUM 2
468 #ifdef CONFIG_MMU_D2
469 #undef CONFIG_DTLBNUM
470 #define CONFIG_DTLBNUM 2
471 #endif
472 #ifdef CONFIG_MMU_D4
473 #undef CONFIG_DTLBNUM
474 #define CONFIG_DTLBNUM 4
475 #endif
476 #ifdef CONFIG_MMU_D8
477 #undef CONFIG_DTLBNUM
478 #define CONFIG_DTLBNUM 8
479 #endif
480 #ifdef CONFIG_MMU_D16
481 #undef CONFIG_DTLBNUM
482 #define CONFIG_DTLBNUM 16
483 #endif
484 #ifdef CONFIG_MMU_D32
485 #undef CONFIG_DTLBNUM
486 #define CONFIG_DTLBNUM 32
487 #endif
488 #ifdef CONFIG_MMU_FASTWB
489 #define CFG_MMU_FASTWB 1
490 #else
491 #define CFG_MMU_FASTWB 0
492 #endif
493
494 #else
495 #define CONFIG_MMUEN 0
496 #define CONFIG_ITLBNUM 2
497 #define CONFIG_DTLBNUM 2
498 #define CONFIG_TLB_TYPE 1
499 #define CONFIG_TLB_REP 1
500 #define CFG_MMU_FASTWB 0
501 #endif
502
503 #ifndef CONFIG_DSU_ENABLE
504 #define CONFIG_DSU_ENABLE 0
505 #endif
506
507 #if defined CONFIG_DSU_ITRACESZ1
508 #define CFG_DSU_ITB 1
509 #elif CONFIG_DSU_ITRACESZ2
510 #define CFG_DSU_ITB 2
511 #elif CONFIG_DSU_ITRACESZ4
512 #define CFG_DSU_ITB 4
513 #elif CONFIG_DSU_ITRACESZ8
514 #define CFG_DSU_ITB 8
515 #elif CONFIG_DSU_ITRACESZ16
516 #define CFG_DSU_ITB 16
517 #else
518 #define CFG_DSU_ITB 0
519 #endif
520
521 #if defined CONFIG_DSU_ATRACESZ1
522 #define CFG_DSU_ATB 1
523 #elif CONFIG_DSU_ATRACESZ2
524 #define CFG_DSU_ATB 2
525 #elif CONFIG_DSU_ATRACESZ4
526 #define CFG_DSU_ATB 4
527 #elif CONFIG_DSU_ATRACESZ8
528 #define CFG_DSU_ATB 8
529 #elif CONFIG_DSU_ATRACESZ16
530 #define CFG_DSU_ATB 16
531 #else
532 #define CFG_DSU_ATB 0
533 #endif
534
535 #ifndef CONFIG_LEON3FT_EN
536 #define CONFIG_LEON3FT_EN 0
537 #endif
538
539 #if defined CONFIG_IUFT_PAR
540 #define CONFIG_IUFT_EN 1
541 #elif defined CONFIG_IUFT_DMR
542 #define CONFIG_IUFT_EN 2
543 #elif defined CONFIG_IUFT_BCH
544 #define CONFIG_IUFT_EN 3
545 #elif defined CONFIG_IUFT_TMR
546 #define CONFIG_IUFT_EN 4
547 #else
548 #define CONFIG_IUFT_EN 0
549 #endif
550 #ifndef CONFIG_RF_ERRINJ
551 #define CONFIG_RF_ERRINJ 0
552 #endif
553
554 #ifndef CONFIG_FPUFT_EN
555 #define CONFIG_FPUFT 0
556 #else
557 #ifdef CONFIG_FPU_GRFPU
558 #define CONFIG_FPUFT 2
559 #else
560 #define CONFIG_FPUFT 1
561 #endif
562 #endif
563
564 #ifndef CONFIG_CACHE_FT_EN
565 #define CONFIG_CACHE_FT_EN 0
566 #endif
567 #ifndef CONFIG_CACHE_ERRINJ
568 #define CONFIG_CACHE_ERRINJ 0
569 #endif
570
571 #ifndef CONFIG_LEON3_NETLIST
572 #define CONFIG_LEON3_NETLIST 0
573 #endif
574
575 #ifdef CONFIG_DEBUG_PC32
576 #define CFG_DEBUG_PC32 0
577 #else
578 #define CFG_DEBUG_PC32 2
579 #endif
580 #ifndef CONFIG_IU_DISAS
581 #define CONFIG_IU_DISAS 0
582 #endif
583 #ifndef CONFIG_IU_DISAS_NET
584 #define CONFIG_IU_DISAS_NET 0
585 #endif
586
587
588 #ifndef CONFIG_AHB_SPLIT
589 #define CONFIG_AHB_SPLIT 0
590 #endif
591
592 #ifndef CONFIG_AHB_RROBIN
593 #define CONFIG_AHB_RROBIN 0
594 #endif
595
596 #ifndef CONFIG_AHB_IOADDR
597 #define CONFIG_AHB_IOADDR FFF
598 #endif
599
600 #ifndef CONFIG_APB_HADDR
601 #define CONFIG_APB_HADDR 800
602 #endif
603
604 #ifndef CONFIG_AHB_MON
605 #define CONFIG_AHB_MON 0
606 #endif
607
608 #ifndef CONFIG_AHB_MONERR
609 #define CONFIG_AHB_MONERR 0
610 #endif
611
612 #ifndef CONFIG_AHB_MONWAR
613 #define CONFIG_AHB_MONWAR 0
614 #endif
615
616 #ifndef CONFIG_DSU_UART
617 #define CONFIG_DSU_UART 0
618 #endif
619
620
621 #ifndef CONFIG_DSU_JTAG
622 #define CONFIG_DSU_JTAG 0
623 #endif
624
625 #ifndef CONFIG_DSU_ETH
626 #define CONFIG_DSU_ETH 0
627 #endif
628
629 #ifndef CONFIG_DSU_IPMSB
630 #define CONFIG_DSU_IPMSB C0A8
631 #endif
632
633 #ifndef CONFIG_DSU_IPLSB
634 #define CONFIG_DSU_IPLSB 0033
635 #endif
636
637 #ifndef CONFIG_DSU_ETHMSB
638 #define CONFIG_DSU_ETHMSB 020000
639 #endif
640
641 #ifndef CONFIG_DSU_ETHLSB
642 #define CONFIG_DSU_ETHLSB 000009
643 #endif
644
645 #if defined CONFIG_DSU_ETHSZ1
646 #define CFG_DSU_ETHB 1
647 #elif CONFIG_DSU_ETHSZ2
648 #define CFG_DSU_ETHB 2
649 #elif CONFIG_DSU_ETHSZ4
650 #define CFG_DSU_ETHB 4
651 #elif CONFIG_DSU_ETHSZ8
652 #define CFG_DSU_ETHB 8
653 #elif CONFIG_DSU_ETHSZ16
654 #define CFG_DSU_ETHB 16
655 #elif CONFIG_DSU_ETHSZ32
656 #define CFG_DSU_ETHB 32
657 #else
658 #define CFG_DSU_ETHB 1
659 #endif
660
661 #ifndef CONFIG_DSU_ETH_PROG
662 #define CONFIG_DSU_ETH_PROG 0
663 #endif
664
665
666 #ifndef CONFIG_SRCTRL
667 #define CONFIG_SRCTRL 0
668 #endif
669
670 #ifndef CONFIG_SRCTRL_PROMWS
671 #define CONFIG_SRCTRL_PROMWS 0
672 #endif
673
674 #ifndef CONFIG_SRCTRL_RAMWS
675 #define CONFIG_SRCTRL_RAMWS 0
676 #endif
677
678 #ifndef CONFIG_SRCTRL_IOWS
679 #define CONFIG_SRCTRL_IOWS 0
680 #endif
681
682 #ifndef CONFIG_SRCTRL_RMW
683 #define CONFIG_SRCTRL_RMW 0
684 #endif
685
686 #ifndef CONFIG_SRCTRL_8BIT
687 #define CONFIG_SRCTRL_8BIT 0
688 #endif
689
690
691 #ifndef CONFIG_SRCTRL_ROMASEL
692 #define CONFIG_SRCTRL_ROMASEL 0
693 #endif
694
695 #if defined CONFIG_SRCTRL_SRBANKS1
696 #define CFG_SR_CTRL_SRBANKS 1
697 #elif defined CONFIG_SRCTRL_SRBANKS2
698 #define CFG_SR_CTRL_SRBANKS 2
699 #elif defined CONFIG_SRCTRL_SRBANKS3
700 #define CFG_SR_CTRL_SRBANKS 3
701 #elif defined CONFIG_SRCTRL_SRBANKS4
702 #define CFG_SR_CTRL_SRBANKS 4
703 #elif defined CONFIG_SRCTRL_SRBANKS5
704 #define CFG_SR_CTRL_SRBANKS 5
705 #else
706 #define CFG_SR_CTRL_SRBANKS 1
707 #endif
708
709 #if defined CONFIG_SRCTRL_BANKSZ0
710 #define CFG_SR_CTRL_BANKSZ 0
711 #elif defined CONFIG_SRCTRL_BANKSZ1
712 #define CFG_SR_CTRL_BANKSZ 1
713 #elif defined CONFIG_SRCTRL_BANKSZ2
714 #define CFG_SR_CTRL_BANKSZ 2
715 #elif defined CONFIG_SRCTRL_BANKSZ3
716 #define CFG_SR_CTRL_BANKSZ 3
717 #elif defined CONFIG_SRCTRL_BANKSZ4
718 #define CFG_SR_CTRL_BANKSZ 4
719 #elif defined CONFIG_SRCTRL_BANKSZ5
720 #define CFG_SR_CTRL_BANKSZ 5
721 #elif defined CONFIG_SRCTRL_BANKSZ6
722 #define CFG_SR_CTRL_BANKSZ 6
723 #elif defined CONFIG_SRCTRL_BANKSZ7
724 #define CFG_SR_CTRL_BANKSZ 7
725 #elif defined CONFIG_SRCTRL_BANKSZ8
726 #define CFG_SR_CTRL_BANKSZ 8
727 #elif defined CONFIG_SRCTRL_BANKSZ9
728 #define CFG_SR_CTRL_BANKSZ 9
729 #elif defined CONFIG_SRCTRL_BANKSZ10
730 #define CFG_SR_CTRL_BANKSZ 10
731 #elif defined CONFIG_SRCTRL_BANKSZ11
732 #define CFG_SR_CTRL_BANKSZ 11
733 #elif defined CONFIG_SRCTRL_BANKSZ12
734 #define CFG_SR_CTRL_BANKSZ 12
735 #elif defined CONFIG_SRCTRL_BANKSZ13
736 #define CFG_SR_CTRL_BANKSZ 13
737 #else
738 #define CFG_SR_CTRL_BANKSZ 0
739 #endif
740 #ifndef CONFIG_MCTRL_LEON2
741 #define CONFIG_MCTRL_LEON2 0
742 #endif
743
744 #ifndef CONFIG_MCTRL_SDRAM
745 #define CONFIG_MCTRL_SDRAM 0
746 #endif
747
748 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
749 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
750 #endif
751
752 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
753 #define CONFIG_MCTRL_SDRAM_INVCLK 0
754 #endif
755
756 #ifndef CONFIG_MCTRL_SDRAM_BUS64
757 #define CONFIG_MCTRL_SDRAM_BUS64 0
758 #endif
759
760 #ifndef CONFIG_MCTRL_8BIT
761 #define CONFIG_MCTRL_8BIT 0
762 #endif
763
764 #ifndef CONFIG_MCTRL_16BIT
765 #define CONFIG_MCTRL_16BIT 0
766 #endif
767
768 #ifndef CONFIG_MCTRL_5CS
769 #define CONFIG_MCTRL_5CS 0
770 #endif
771
772 #ifndef CONFIG_MCTRL_EDAC
773 #define CONFIG_MCTRL_EDAC 0
774 #endif
775
776 #ifndef CONFIG_MCTRL_PAGE
777 #define CONFIG_MCTRL_PAGE 0
778 #endif
779
780 #ifndef CONFIG_MCTRL_PROGPAGE
781 #define CONFIG_MCTRL_PROGPAGE 0
782 #endif
783
784 #ifndef CONFIG_SDCTRL
785 #define CONFIG_SDCTRL 0
786 #endif
787
788 #ifndef CONFIG_SDCTRL_SEPBUS
789 #define CONFIG_SDCTRL_SEPBUS 0
790 #endif
791
792 #ifndef CONFIG_SDCTRL_INVCLK
793 #define CONFIG_SDCTRL_INVCLK 0
794 #endif
795
796 #ifndef CONFIG_SDCTRL_BUS64
797 #define CONFIG_SDCTRL_BUS64 0
798 #endif
799
800 #ifndef CONFIG_SDCTRL_PAGE
801 #define CONFIG_SDCTRL_PAGE 0
802 #endif
803
804 #ifndef CONFIG_SDCTRL_PROGPAGE
805 #define CONFIG_SDCTRL_PROGPAGE 0
806 #endif
807
808 #ifndef CONFIG_AHBROM_ENABLE
809 #define CONFIG_AHBROM_ENABLE 0
810 #endif
811
812 #ifndef CONFIG_AHBROM_START
813 #define CONFIG_AHBROM_START 000
814 #endif
815
816 #ifndef CONFIG_AHBROM_PIPE
817 #define CONFIG_AHBROM_PIPE 0
818 #endif
819
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
821 #define CONFIG_ROM_START 100
822 #else
823 #define CONFIG_ROM_START 000
824 #endif
825
826
827 #ifndef CONFIG_AHBRAM_ENABLE
828 #define CONFIG_AHBRAM_ENABLE 0
829 #endif
830
831 #ifndef CONFIG_AHBRAM_START
832 #define CONFIG_AHBRAM_START A00
833 #endif
834
835 #if defined CONFIG_AHBRAM_SZ1
836 #define CFG_AHBRAMSZ 1
837 #elif CONFIG_AHBRAM_SZ2
838 #define CFG_AHBRAMSZ 2
839 #elif CONFIG_AHBRAM_SZ4
840 #define CFG_AHBRAMSZ 4
841 #elif CONFIG_AHBRAM_SZ8
842 #define CFG_AHBRAMSZ 8
843 #elif CONFIG_AHBRAM_SZ16
844 #define CFG_AHBRAMSZ 16
845 #elif CONFIG_AHBRAM_SZ32
846 #define CFG_AHBRAMSZ 32
847 #elif CONFIG_AHBRAM_SZ64
848 #define CFG_AHBRAMSZ 64
849 #else
850 #define CFG_AHBRAMSZ 1
851 #endif
852
853 #ifndef CONFIG_GRETH_ENABLE
854 #define CONFIG_GRETH_ENABLE 0
855 #endif
856
857 #ifndef CONFIG_GRETH_GIGA
858 #define CONFIG_GRETH_GIGA 0
859 #endif
860
861 #if defined CONFIG_GRETH_FIFO4
862 #define CFG_GRETH_FIFO 4
863 #elif defined CONFIG_GRETH_FIFO8
864 #define CFG_GRETH_FIFO 8
865 #elif defined CONFIG_GRETH_FIFO16
866 #define CFG_GRETH_FIFO 16
867 #elif defined CONFIG_GRETH_FIFO32
868 #define CFG_GRETH_FIFO 32
869 #elif defined CONFIG_GRETH_FIFO64
870 #define CFG_GRETH_FIFO 64
871 #else
872 #define CFG_GRETH_FIFO 8
873 #endif
874
875 #ifndef CONFIG_CAN_ENABLE
876 #define CONFIG_CAN_ENABLE 0
877 #endif
878
879 #ifndef CONFIG_CANIO
880 #define CONFIG_CANIO 0
881 #endif
882
883 #ifndef CONFIG_CANIRQ
884 #define CONFIG_CANIRQ 0
885 #endif
886
887 #ifndef CONFIG_CANLOOP
888 #define CONFIG_CANLOOP 0
889 #endif
890
891 #ifndef CONFIG_CAN_SYNCRST
892 #define CONFIG_CAN_SYNCRST 0
893 #endif
894
895
896 #ifndef CONFIG_CAN_FT
897 #define CONFIG_CAN_FT 0
898 #endif
899 #if defined CONFIG_PCI_SIMPLE_TARGET
900 #define CFG_PCITYPE 1
901 #elif defined CONFIG_PCI_MASTER_TARGET_DMA
902 #define CFG_PCITYPE 3
903 #elif defined CONFIG_PCI_MASTER_TARGET
904 #define CFG_PCITYPE 2
905 #else
906 #define CFG_PCITYPE 0
907 #endif
908
909 #ifndef CONFIG_PCI_VENDORID
910 #define CONFIG_PCI_VENDORID 0
911 #endif
912
913 #ifndef CONFIG_PCI_DEVICEID
914 #define CONFIG_PCI_DEVICEID 0
915 #endif
916
917 #ifndef CONFIG_PCI_REVID
918 #define CONFIG_PCI_REVID 0
919 #endif
920
921 #if defined CONFIG_PCI_FIFO0
922 #define CFG_PCIFIFO 8
923 #define CFG_PCI_ENFIFO 0
924 #elif defined CONFIG_PCI_FIFO16
925 #define CFG_PCIFIFO 16
926 #elif defined CONFIG_PCI_FIFO32
927 #define CFG_PCIFIFO 32
928 #elif defined CONFIG_PCI_FIFO64
929 #define CFG_PCIFIFO 64
930 #elif defined CONFIG_PCI_FIFO128
931 #define CFG_PCIFIFO 128
932 #elif defined CONFIG_PCI_FIFO256
933 #define CFG_PCIFIFO 256
934 #else
935 #define CFG_PCIFIFO 8
936 #endif
937
938 #ifndef CFG_PCI_ENFIFO
939 #define CFG_PCI_ENFIFO 1
940 #endif
941
942
943 #ifndef CONFIG_PCI_ARBITER_APB
944 #define CONFIG_PCI_ARBITER_APB 0
945 #endif
946
947 #ifndef CONFIG_PCI_ARBITER
948 #define CONFIG_PCI_ARBITER 0
949 #endif
950
951 #ifndef CONFIG_PCI_ARBITER_NREQ
952 #define CONFIG_PCI_ARBITER_NREQ 4
953 #endif
954
955 #ifndef CONFIG_PCI_TRACE
956 #define CONFIG_PCI_TRACE 0
957 #endif
958
959 #if defined CONFIG_PCI_TRACE512
960 #define CFG_PCI_TRACEBUF 512
961 #elif defined CONFIG_PCI_TRACE1024
962 #define CFG_PCI_TRACEBUF 1024
963 #elif defined CONFIG_PCI_TRACE2048
964 #define CFG_PCI_TRACEBUF 2048
965 #elif defined CONFIG_PCI_TRACE4096
966 #define CFG_PCI_TRACEBUF 4096
967 #else
968 #define CFG_PCI_TRACEBUF 256
969 #endif
970
971
972 #ifndef CONFIG_SPW_ENABLE
973 #define CONFIG_SPW_ENABLE 0
974 #endif
975
976 #ifndef CONFIG_SPW_NUM
977 #define CONFIG_SPW_NUM 1
978 #endif
979
980 #if defined CONFIG_SPW_AHBFIFO4
981 #define CONFIG_SPW_AHBFIFO 4
982 #elif defined CONFIG_SPW_AHBFIFO8
983 #define CONFIG_SPW_AHBFIFO 8
984 #elif defined CONFIG_SPW_AHBFIFO16
985 #define CONFIG_SPW_AHBFIFO 16
986 #elif defined CONFIG_SPW_AHBFIFO32
987 #define CONFIG_SPW_AHBFIFO 32
988 #elif defined CONFIG_SPW_AHBFIFO64
989 #define CONFIG_SPW_AHBFIFO 64
990 #else
991 #define CONFIG_SPW_AHBFIFO 4
992 #endif
993
994 #if defined CONFIG_SPW_RXFIFO16
995 #define CONFIG_SPW_RXFIFO 16
996 #elif defined CONFIG_SPW_RXFIFO32
997 #define CONFIG_SPW_RXFIFO 32
998 #elif defined CONFIG_SPW_RXFIFO64
999 #define CONFIG_SPW_RXFIFO 64
1000 #else
1001 #define CONFIG_SPW_RXFIFO 16
1002 #endif
1003
1004 #ifndef CONFIG_SPW_RMAP
1005 #define CONFIG_SPW_RMAP 0
1006 #endif
1007
1008 #if defined CONFIG_SPW_RMAPBUF2
1009 #define CONFIG_SPW_RMAPBUF 2
1010 #elif defined CONFIG_SPW_RMAPBUF4
1011 #define CONFIG_SPW_RMAPBUF 4
1012 #elif defined CONFIG_SPW_RMAPBUF6
1013 #define CONFIG_SPW_RMAPBUF 6
1014 #elif defined CONFIG_SPW_RMAPBUF8
1015 #define CONFIG_SPW_RMAPBUF 8
1016 #else
1017 #define CONFIG_SPW_RMAPBUF 4
1018 #endif
1019
1020 #ifndef CONFIG_SPW_RMAPCRC
1021 #define CONFIG_SPW_RMAPCRC 0
1022 #endif
1023
1024 #ifndef CONFIG_SPW_RXUNAL
1025 #define CONFIG_SPW_RXUNAL 0
1026 #endif
1027
1028 #ifndef CONFIG_SPW_NETLIST
1029 #define CONFIG_SPW_NETLIST 0
1030 #endif
1031
1032 #ifndef CONFIG_SPW_FT
1033 #define CONFIG_SPW_FT 0
1034 #endif
1035
1036 #if defined CONFIG_SPW_GRSPW1
1037 #define CONFIG_SPW_GRSPW 1
1038 #else
1039 #define CONFIG_SPW_GRSPW 2
1040 #endif
1041
1042 #ifndef CONFIG_SPW_DMACHAN
1043 #define CONFIG_SPW_DMACHAN 1
1044 #endif
1045
1046 #ifndef CONFIG_SPW_PORTS
1047 #define CONFIG_SPW_PORTS 1
1048 #endif
1049
1050 #if defined CONFIG_SPW_RX_SDR
1051 #define CONFIG_SPW_INPUT 2
1052 #elif defined CONFIG_SPW_RX_DDR
1053 #define CONFIG_SPW_INPUT 3
1054 #elif defined CONFIG_SPW_RX_XOR
1055 #define CONFIG_SPW_INPUT 0
1056 #elif defined CONFIG_SPW_RX_AFLEX
1057 #define CONFIG_SPW_INPUT 1
1058 #else
1059 #define CONFIG_SPW_INPUT 2
1060 #endif
1061
1062 #if defined CONFIG_SPW_TX_SDR
1063 #define CONFIG_SPW_OUTPUT 0
1064 #elif defined CONFIG_SPW_TX_DDR
1065 #define CONFIG_SPW_OUTPUT 1
1066 #elif defined CONFIG_SPW_TX_AFLEX
1067 #define CONFIG_SPW_OUTPUT 2
1068 #else
1069 #define CONFIG_SPW_OUTPUT 0
1070 #endif
1071
1072 #ifndef CONFIG_SPW_RTSAME
1073 #define CONFIG_SPW_RTSAME 0
1074 #endif
1075 #ifndef CONFIG_UART1_ENABLE
1076 #define CONFIG_UART1_ENABLE 0
1077 #endif
1078
1079 #if defined CONFIG_UA1_FIFO1
1080 #define CFG_UA1_FIFO 1
1081 #elif defined CONFIG_UA1_FIFO2
1082 #define CFG_UA1_FIFO 2
1083 #elif defined CONFIG_UA1_FIFO4
1084 #define CFG_UA1_FIFO 4
1085 #elif defined CONFIG_UA1_FIFO8
1086 #define CFG_UA1_FIFO 8
1087 #elif defined CONFIG_UA1_FIFO16
1088 #define CFG_UA1_FIFO 16
1089 #elif defined CONFIG_UA1_FIFO32
1090 #define CFG_UA1_FIFO 32
1091 #else
1092 #define CFG_UA1_FIFO 1
1093 #endif
1094
1095 #ifndef CONFIG_UART2_ENABLE
1096 #define CONFIG_UART2_ENABLE 0
1097 #endif
1098
1099 #if defined CONFIG_UA2_FIFO1
1100 #define CFG_UA2_FIFO 1
1101 #elif defined CONFIG_UA2_FIFO2
1102 #define CFG_UA2_FIFO 2
1103 #elif defined CONFIG_UA2_FIFO4
1104 #define CFG_UA2_FIFO 4
1105 #elif defined CONFIG_UA2_FIFO8
1106 #define CFG_UA2_FIFO 8
1107 #elif defined CONFIG_UA2_FIFO16
1108 #define CFG_UA2_FIFO 16
1109 #elif defined CONFIG_UA2_FIFO32
1110 #define CFG_UA2_FIFO 32
1111 #else
1112 #define CFG_UA2_FIFO 1
1113 #endif
1114
1115 #ifndef CONFIG_IRQ3_ENABLE
1116 #define CONFIG_IRQ3_ENABLE 0
1117 #endif
1118 #ifndef CONFIG_IRQ3_NSEC
1119 #define CONFIG_IRQ3_NSEC 0
1120 #endif
1121 #ifndef CONFIG_GPT_ENABLE
1122 #define CONFIG_GPT_ENABLE 0
1123 #endif
1124
1125 #ifndef CONFIG_GPT_NTIM
1126 #define CONFIG_GPT_NTIM 1
1127 #endif
1128
1129 #ifndef CONFIG_GPT_SW
1130 #define CONFIG_GPT_SW 8
1131 #endif
1132
1133 #ifndef CONFIG_GPT_TW
1134 #define CONFIG_GPT_TW 8
1135 #endif
1136
1137 #ifndef CONFIG_GPT_IRQ
1138 #define CONFIG_GPT_IRQ 8
1139 #endif
1140
1141 #ifndef CONFIG_GPT_SEPIRQ
1142 #define CONFIG_GPT_SEPIRQ 0
1143 #endif
1144 #ifndef CONFIG_GPT_ENABLE
1145 #define CONFIG_GPT_ENABLE 0
1146 #endif
1147
1148 #ifndef CONFIG_GPT_NTIM
1149 #define CONFIG_GPT_NTIM 1
1150 #endif
1151
1152 #ifndef CONFIG_GPT_SW
1153 #define CONFIG_GPT_SW 8
1154 #endif
1155
1156 #ifndef CONFIG_GPT_TW
1157 #define CONFIG_GPT_TW 8
1158 #endif
1159
1160 #ifndef CONFIG_GPT_IRQ
1161 #define CONFIG_GPT_IRQ 8
1162 #endif
1163
1164 #ifndef CONFIG_GPT_SEPIRQ
1165 #define CONFIG_GPT_SEPIRQ 0
1166 #endif
1167
1168 #ifndef CONFIG_GPT_WDOGEN
1169 #define CONFIG_GPT_WDOGEN 0
1170 #endif
1171
1172 #ifndef CONFIG_GPT_WDOG
1173 #define CONFIG_GPT_WDOG 0
1174 #endif
1175
1176 #ifndef CONFIG_GRGPIO_ENABLE
1177 #define CONFIG_GRGPIO_ENABLE 0
1178 #endif
1179 #ifndef CONFIG_GRGPIO_IMASK
1180 #define CONFIG_GRGPIO_IMASK 0000
1181 #endif
1182 #ifndef CONFIG_GRGPIO_WIDTH
1183 #define CONFIG_GRGPIO_WIDTH 1
1184 #endif
1185
1186
1187 #ifndef CONFIG_DEBUG_UART
1188 #define CONFIG_DEBUG_UART 0
1189 #endif
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_PROASICPLUS
14 #define CONFIG_SYN_TECH proasic
15 #elif defined CONFIG_SYN_ALTERA
16 #define CONFIG_SYN_TECH altera
17 #elif defined CONFIG_SYN_STRATIX
18 #define CONFIG_SYN_TECH stratix1
19 #elif defined CONFIG_SYN_STRATIXII
20 #define CONFIG_SYN_TECH stratix2
21 #elif defined CONFIG_SYN_STRATIXIII
22 #define CONFIG_SYN_TECH stratix3
23 #elif defined CONFIG_SYN_CYCLONEIII
24 #define CONFIG_SYN_TECH cyclone3
25 #elif defined CONFIG_SYN_EASIC90
26 #define CONFIG_SYN_TECH easic90
27 #elif defined CONFIG_SYN_IHP25
28 #define CONFIG_SYN_TECH ihp25
29 #elif defined CONFIG_SYN_IHP25RH
30 #define CONFIG_SYN_TECH ihp25rh
31 #elif defined CONFIG_SYN_LATTICE
32 #define CONFIG_SYN_TECH lattice
33 #elif defined CONFIG_SYN_ECLIPSE
34 #define CONFIG_SYN_TECH eclipse
35 #elif defined CONFIG_SYN_PEREGRINE
36 #define CONFIG_SYN_TECH peregrine
37 #elif defined CONFIG_SYN_PROASIC
38 #define CONFIG_SYN_TECH proasic
39 #elif defined CONFIG_SYN_PROASIC3
40 #define CONFIG_SYN_TECH apa3
41 #elif defined CONFIG_SYN_SPARTAN2
42 #define CONFIG_SYN_TECH virtex
43 #elif defined CONFIG_SYN_VIRTEX
44 #define CONFIG_SYN_TECH virtex
45 #elif defined CONFIG_SYN_VIRTEXE
46 #define CONFIG_SYN_TECH virtex
47 #elif defined CONFIG_SYN_SPARTAN3
48 #define CONFIG_SYN_TECH spartan3
49 #elif defined CONFIG_SYN_SPARTAN3E
50 #define CONFIG_SYN_TECH spartan3e
51 #elif defined CONFIG_SYN_VIRTEX2
52 #define CONFIG_SYN_TECH virtex2
53 #elif defined CONFIG_SYN_VIRTEX4
54 #define CONFIG_SYN_TECH virtex4
55 #elif defined CONFIG_SYN_VIRTEX5
56 #define CONFIG_SYN_TECH virtex5
57 #elif defined CONFIG_SYN_RH_LIB18T
58 #define CONFIG_SYN_TECH rhlib18t
59 #elif defined CONFIG_SYN_SMIC13
60 #define CONFIG_SYN_TECH smic013
61 #elif defined CONFIG_SYN_UT025CRH
62 #define CONFIG_SYN_TECH ut25
63 #elif defined CONFIG_SYN_TSMC90
64 #define CONFIG_SYN_TECH tsmc90
65 #elif defined CONFIG_SYN_CUSTOM1
66 #define CONFIG_SYN_TECH custom1
67 #else
68 #error "unknown target technology"
69 #endif
70
71 #if defined CONFIG_SYN_INFER_RAM
72 #define CFG_RAM_TECH inferred
73 #elif defined CONFIG_MEM_UMC
74 #define CFG_RAM_TECH umc
75 #elif defined CONFIG_MEM_RHUMC
76 #define CFG_RAM_TECH rhumc
77 #elif defined CONFIG_MEM_VIRAGE
78 #define CFG_RAM_TECH memvirage
79 #elif defined CONFIG_MEM_ARTISAN
80 #define CFG_RAM_TECH memartisan
81 #elif defined CONFIG_MEM_CUSTOM1
82 #define CFG_RAM_TECH custom1
83 #elif defined CONFIG_MEM_VIRAGE90
84 #define CFG_RAM_TECH memvirage90
85 #elif defined CONFIG_MEM_INFERRED
86 #define CFG_RAM_TECH inferred
87 #else
88 #define CFG_RAM_TECH CONFIG_SYN_TECH
89 #endif
90
91 #if defined CONFIG_SYN_INFER_PADS
92 #define CFG_PAD_TECH inferred
93 #else
94 #define CFG_PAD_TECH CONFIG_SYN_TECH
95 #endif
96
97 #ifndef CONFIG_SYN_NO_ASYNC
98 #define CONFIG_SYN_NO_ASYNC 0
99 #endif
100
101 #ifndef CONFIG_SYN_SCAN
102 #define CONFIG_SYN_SCAN 0
103 #endif
104
105
106 #if defined CONFIG_CLK_ALTDLL
107 #define CFG_CLK_TECH CONFIG_SYN_TECH
108 #elif defined CONFIG_CLK_HCLKBUF
109 #define CFG_CLK_TECH axcel
110 #elif defined CONFIG_CLK_LATDLL
111 #define CFG_CLK_TECH lattice
112 #elif defined CONFIG_CLK_PRO3PLL
113 #define CFG_CLK_TECH apa3
114 #elif defined CONFIG_CLK_CLKDLL
115 #define CFG_CLK_TECH virtex
116 #elif defined CONFIG_CLK_DCM
117 #define CFG_CLK_TECH CONFIG_SYN_TECH
118 #elif defined CONFIG_CLK_LIB18T
119 #define CFG_CLK_TECH rhlib18t
120 #elif defined CONFIG_CLK_RHUMC
121 #define CFG_CLK_TECH rhumc
122 #else
123 #define CFG_CLK_TECH inferred
124 #endif
125
126 #ifndef CONFIG_CLK_MUL
127 #define CONFIG_CLK_MUL 2
128 #endif
129
130 #ifndef CONFIG_CLK_DIV
131 #define CONFIG_CLK_DIV 2
132 #endif
133
134 #ifndef CONFIG_OCLK_DIV
135 #define CONFIG_OCLK_DIV 2
136 #endif
137
138 #ifndef CONFIG_PCI_CLKDLL
139 #define CONFIG_PCI_CLKDLL 0
140 #endif
141
142 #ifndef CONFIG_PCI_SYSCLK
143 #define CONFIG_PCI_SYSCLK 0
144 #endif
145
146 #ifndef CONFIG_CLK_NOFB
147 #define CONFIG_CLK_NOFB 0
148 #endif
149 #ifndef CONFIG_LEON3
150 #define CONFIG_LEON3 0
151 #endif
152
153 #ifndef CONFIG_PROC_NUM
154 #define CONFIG_PROC_NUM 1
155 #endif
156
157 #ifndef CONFIG_IU_NWINDOWS
158 #define CONFIG_IU_NWINDOWS 8
159 #endif
160
161 #ifndef CONFIG_IU_RSTADDR
162 #define CONFIG_IU_RSTADDR 8
163 #endif
164
165 #ifndef CONFIG_IU_LDELAY
166 #define CONFIG_IU_LDELAY 1
167 #endif
168
169 #ifndef CONFIG_IU_WATCHPOINTS
170 #define CONFIG_IU_WATCHPOINTS 0
171 #endif
172
173 #ifdef CONFIG_IU_V8MULDIV
174 #ifdef CONFIG_IU_MUL_LATENCY_4
175 #define CFG_IU_V8 1
176 #elif defined CONFIG_IU_MUL_LATENCY_5
177 #define CFG_IU_V8 2
178 #elif defined CONFIG_IU_MUL_LATENCY_2
179 #define CFG_IU_V8 16#32#
180 #endif
181 #else
182 #define CFG_IU_V8 0
183 #endif
184
185 #ifndef CONFIG_PWD
186 #define CONFIG_PWD 0
187 #endif
188
189 #ifndef CONFIG_IU_MUL_MAC
190 #define CONFIG_IU_MUL_MAC 0
191 #endif
192
193 #ifndef CONFIG_IU_SVT
194 #define CONFIG_IU_SVT 0
195 #endif
196
197 #if defined CONFIG_FPU_GRFPC1
198 #define CONFIG_FPU_GRFPC 1
199 #elif defined CONFIG_FPU_GRFPC2
200 #define CONFIG_FPU_GRFPC 2
201 #else
202 #define CONFIG_FPU_GRFPC 0
203 #endif
204
205 #if defined CONFIG_FPU_GRFPU_INFMUL
206 #define CONFIG_FPU_GRFPU_MUL 0
207 #elif defined CONFIG_FPU_GRFPU_DWMUL
208 #define CONFIG_FPU_GRFPU_MUL 1
209 #elif defined CONFIG_FPU_GRFPU_MODGEN
210 #define CONFIG_FPU_GRFPU_MUL 2
211 #else
212 #define CONFIG_FPU_GRFPU_MUL 0
213 #endif
214
215 #if defined CONFIG_FPU_GRFPU_SH
216 #define CONFIG_FPU_GRFPU_SHARED 1
217 #else
218 #define CONFIG_FPU_GRFPU_SHARED 0
219 #endif
220
221 #if defined CONFIG_FPU_GRFPU
222 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
223 #elif defined CONFIG_FPU_MEIKO
224 #define CONFIG_FPU 15
225 #elif defined CONFIG_FPU_GRFPULITE
226 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
227 #else
228 #define CONFIG_FPU 0
229 #endif
230
231 #ifndef CONFIG_FPU_NETLIST
232 #define CONFIG_FPU_NETLIST 0
233 #endif
234
235 #ifndef CONFIG_ICACHE_ENABLE
236 #define CONFIG_ICACHE_ENABLE 0
237 #endif
238
239 #if defined CONFIG_ICACHE_ASSO1
240 #define CFG_IU_ISETS 1
241 #elif defined CONFIG_ICACHE_ASSO2
242 #define CFG_IU_ISETS 2
243 #elif defined CONFIG_ICACHE_ASSO3
244 #define CFG_IU_ISETS 3
245 #elif defined CONFIG_ICACHE_ASSO4
246 #define CFG_IU_ISETS 4
247 #else
248 #define CFG_IU_ISETS 1
249 #endif
250
251 #if defined CONFIG_ICACHE_SZ1
252 #define CFG_ICACHE_SZ 1
253 #elif defined CONFIG_ICACHE_SZ2
254 #define CFG_ICACHE_SZ 2
255 #elif defined CONFIG_ICACHE_SZ4
256 #define CFG_ICACHE_SZ 4
257 #elif defined CONFIG_ICACHE_SZ8
258 #define CFG_ICACHE_SZ 8
259 #elif defined CONFIG_ICACHE_SZ16
260 #define CFG_ICACHE_SZ 16
261 #elif defined CONFIG_ICACHE_SZ32
262 #define CFG_ICACHE_SZ 32
263 #elif defined CONFIG_ICACHE_SZ64
264 #define CFG_ICACHE_SZ 64
265 #elif defined CONFIG_ICACHE_SZ128
266 #define CFG_ICACHE_SZ 128
267 #elif defined CONFIG_ICACHE_SZ256
268 #define CFG_ICACHE_SZ 256
269 #else
270 #define CFG_ICACHE_SZ 1
271 #endif
272
273 #ifdef CONFIG_ICACHE_LZ16
274 #define CFG_ILINE_SZ 4
275 #else
276 #define CFG_ILINE_SZ 8
277 #endif
278
279 #if defined CONFIG_ICACHE_ALGORND
280 #define CFG_ICACHE_ALGORND 2
281 #elif defined CONFIG_ICACHE_ALGOLRR
282 #define CFG_ICACHE_ALGORND 1
283 #else
284 #define CFG_ICACHE_ALGORND 0
285 #endif
286
287 #ifndef CONFIG_ICACHE_LOCK
288 #define CONFIG_ICACHE_LOCK 0
289 #endif
290
291 #ifndef CONFIG_ICACHE_LRAM
292 #define CONFIG_ICACHE_LRAM 0
293 #endif
294
295 #ifndef CONFIG_ICACHE_LRSTART
296 #define CONFIG_ICACHE_LRSTART 8E
297 #endif
298
299 #if defined CONFIG_ICACHE_LRAM_SZ2
300 #define CFG_ILRAM_SIZE 2
301 #elif defined CONFIG_ICACHE_LRAM_SZ4
302 #define CFG_ILRAM_SIZE 4
303 #elif defined CONFIG_ICACHE_LRAM_SZ8
304 #define CFG_ILRAM_SIZE 8
305 #elif defined CONFIG_ICACHE_LRAM_SZ16
306 #define CFG_ILRAM_SIZE 16
307 #elif defined CONFIG_ICACHE_LRAM_SZ32
308 #define CFG_ILRAM_SIZE 32
309 #elif defined CONFIG_ICACHE_LRAM_SZ64
310 #define CFG_ILRAM_SIZE 64
311 #elif defined CONFIG_ICACHE_LRAM_SZ128
312 #define CFG_ILRAM_SIZE 128
313 #elif defined CONFIG_ICACHE_LRAM_SZ256
314 #define CFG_ILRAM_SIZE 256
315 #else
316 #define CFG_ILRAM_SIZE 1
317 #endif
318
319
320 #ifndef CONFIG_DCACHE_ENABLE
321 #define CONFIG_DCACHE_ENABLE 0
322 #endif
323
324 #if defined CONFIG_DCACHE_ASSO1
325 #define CFG_IU_DSETS 1
326 #elif defined CONFIG_DCACHE_ASSO2
327 #define CFG_IU_DSETS 2
328 #elif defined CONFIG_DCACHE_ASSO3
329 #define CFG_IU_DSETS 3
330 #elif defined CONFIG_DCACHE_ASSO4
331 #define CFG_IU_DSETS 4
332 #else
333 #define CFG_IU_DSETS 1
334 #endif
335
336 #if defined CONFIG_DCACHE_SZ1
337 #define CFG_DCACHE_SZ 1
338 #elif defined CONFIG_DCACHE_SZ2
339 #define CFG_DCACHE_SZ 2
340 #elif defined CONFIG_DCACHE_SZ4
341 #define CFG_DCACHE_SZ 4
342 #elif defined CONFIG_DCACHE_SZ8
343 #define CFG_DCACHE_SZ 8
344 #elif defined CONFIG_DCACHE_SZ16
345 #define CFG_DCACHE_SZ 16
346 #elif defined CONFIG_DCACHE_SZ32
347 #define CFG_DCACHE_SZ 32
348 #elif defined CONFIG_DCACHE_SZ64
349 #define CFG_DCACHE_SZ 64
350 #elif defined CONFIG_DCACHE_SZ128
351 #define CFG_DCACHE_SZ 128
352 #elif defined CONFIG_DCACHE_SZ256
353 #define CFG_DCACHE_SZ 256
354 #else
355 #define CFG_DCACHE_SZ 1
356 #endif
357
358 #ifdef CONFIG_DCACHE_LZ16
359 #define CFG_DLINE_SZ 4
360 #else
361 #define CFG_DLINE_SZ 8
362 #endif
363
364 #if defined CONFIG_DCACHE_ALGORND
365 #define CFG_DCACHE_ALGORND 2
366 #elif defined CONFIG_DCACHE_ALGOLRR
367 #define CFG_DCACHE_ALGORND 1
368 #else
369 #define CFG_DCACHE_ALGORND 0
370 #endif
371
372 #ifndef CONFIG_DCACHE_LOCK
373 #define CONFIG_DCACHE_LOCK 0
374 #endif
375
376 #ifndef CONFIG_DCACHE_SNOOP
377 #define CONFIG_DCACHE_SNOOP 0
378 #endif
379
380 #ifndef CONFIG_DCACHE_SNOOP_FAST
381 #define CONFIG_DCACHE_SNOOP_FAST 0
382 #endif
383
384 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
385 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
386 #endif
387
388 #ifndef CONFIG_CACHE_FIXED
389 #define CONFIG_CACHE_FIXED 0
390 #endif
391
392 #ifndef CONFIG_DCACHE_LRAM
393 #define CONFIG_DCACHE_LRAM 0
394 #endif
395
396 #ifndef CONFIG_DCACHE_LRSTART
397 #define CONFIG_DCACHE_LRSTART 8F
398 #endif
399
400 #if defined CONFIG_DCACHE_LRAM_SZ2
401 #define CFG_DLRAM_SIZE 2
402 #elif defined CONFIG_DCACHE_LRAM_SZ4
403 #define CFG_DLRAM_SIZE 4
404 #elif defined CONFIG_DCACHE_LRAM_SZ8
405 #define CFG_DLRAM_SIZE 8
406 #elif defined CONFIG_DCACHE_LRAM_SZ16
407 #define CFG_DLRAM_SIZE 16
408 #elif defined CONFIG_DCACHE_LRAM_SZ32
409 #define CFG_DLRAM_SIZE 32
410 #elif defined CONFIG_DCACHE_LRAM_SZ64
411 #define CFG_DLRAM_SIZE 64
412 #elif defined CONFIG_DCACHE_LRAM_SZ128
413 #define CFG_DLRAM_SIZE 128
414 #elif defined CONFIG_DCACHE_LRAM_SZ256
415 #define CFG_DLRAM_SIZE 256
416 #else
417 #define CFG_DLRAM_SIZE 1
418 #endif
419
420 #if defined CONFIG_MMU_PAGE_4K
421 #define CONFIG_MMU_PAGE 0
422 #elif defined CONFIG_MMU_PAGE_8K
423 #define CONFIG_MMU_PAGE 1
424 #elif defined CONFIG_MMU_PAGE_16K
425 #define CONFIG_MMU_PAGE 2
426 #elif defined CONFIG_MMU_PAGE_32K
427 #define CONFIG_MMU_PAGE 3
428 #elif defined CONFIG_MMU_PAGE_PROG
429 #define CONFIG_MMU_PAGE 4
430 #else
431 #define CONFIG_MMU_PAGE 0
432 #endif
433
434 #ifdef CONFIG_MMU_ENABLE
435 #define CONFIG_MMUEN 1
436
437 #ifdef CONFIG_MMU_SPLIT
438 #define CONFIG_TLB_TYPE 0
439 #endif
440 #ifdef CONFIG_MMU_COMBINED
441 #define CONFIG_TLB_TYPE 1
442 #endif
443
444 #ifdef CONFIG_MMU_REPARRAY
445 #define CONFIG_TLB_REP 0
446 #endif
447 #ifdef CONFIG_MMU_REPINCREMENT
448 #define CONFIG_TLB_REP 1
449 #endif
450
451 #ifdef CONFIG_MMU_I2
452 #define CONFIG_ITLBNUM 2
453 #endif
454 #ifdef CONFIG_MMU_I4
455 #define CONFIG_ITLBNUM 4
456 #endif
457 #ifdef CONFIG_MMU_I8
458 #define CONFIG_ITLBNUM 8
459 #endif
460 #ifdef CONFIG_MMU_I16
461 #define CONFIG_ITLBNUM 16
462 #endif
463 #ifdef CONFIG_MMU_I32
464 #define CONFIG_ITLBNUM 32
465 #endif
466
467 #define CONFIG_DTLBNUM 2
468 #ifdef CONFIG_MMU_D2
469 #undef CONFIG_DTLBNUM
470 #define CONFIG_DTLBNUM 2
471 #endif
472 #ifdef CONFIG_MMU_D4
473 #undef CONFIG_DTLBNUM
474 #define CONFIG_DTLBNUM 4
475 #endif
476 #ifdef CONFIG_MMU_D8
477 #undef CONFIG_DTLBNUM
478 #define CONFIG_DTLBNUM 8
479 #endif
480 #ifdef CONFIG_MMU_D16
481 #undef CONFIG_DTLBNUM
482 #define CONFIG_DTLBNUM 16
483 #endif
484 #ifdef CONFIG_MMU_D32
485 #undef CONFIG_DTLBNUM
486 #define CONFIG_DTLBNUM 32
487 #endif
488 #ifdef CONFIG_MMU_FASTWB
489 #define CFG_MMU_FASTWB 1
490 #else
491 #define CFG_MMU_FASTWB 0
492 #endif
493
494 #else
495 #define CONFIG_MMUEN 0
496 #define CONFIG_ITLBNUM 2
497 #define CONFIG_DTLBNUM 2
498 #define CONFIG_TLB_TYPE 1
499 #define CONFIG_TLB_REP 1
500 #define CFG_MMU_FASTWB 0
501 #endif
502
503 #ifndef CONFIG_DSU_ENABLE
504 #define CONFIG_DSU_ENABLE 0
505 #endif
506
507 #if defined CONFIG_DSU_ITRACESZ1
508 #define CFG_DSU_ITB 1
509 #elif CONFIG_DSU_ITRACESZ2
510 #define CFG_DSU_ITB 2
511 #elif CONFIG_DSU_ITRACESZ4
512 #define CFG_DSU_ITB 4
513 #elif CONFIG_DSU_ITRACESZ8
514 #define CFG_DSU_ITB 8
515 #elif CONFIG_DSU_ITRACESZ16
516 #define CFG_DSU_ITB 16
517 #else
518 #define CFG_DSU_ITB 0
519 #endif
520
521 #if defined CONFIG_DSU_ATRACESZ1
522 #define CFG_DSU_ATB 1
523 #elif CONFIG_DSU_ATRACESZ2
524 #define CFG_DSU_ATB 2
525 #elif CONFIG_DSU_ATRACESZ4
526 #define CFG_DSU_ATB 4
527 #elif CONFIG_DSU_ATRACESZ8
528 #define CFG_DSU_ATB 8
529 #elif CONFIG_DSU_ATRACESZ16
530 #define CFG_DSU_ATB 16
531 #else
532 #define CFG_DSU_ATB 0
533 #endif
534
535 #ifndef CONFIG_LEON3FT_EN
536 #define CONFIG_LEON3FT_EN 0
537 #endif
538
539 #if defined CONFIG_IUFT_PAR
540 #define CONFIG_IUFT_EN 1
541 #elif defined CONFIG_IUFT_DMR
542 #define CONFIG_IUFT_EN 2
543 #elif defined CONFIG_IUFT_BCH
544 #define CONFIG_IUFT_EN 3
545 #elif defined CONFIG_IUFT_TMR
546 #define CONFIG_IUFT_EN 4
547 #else
548 #define CONFIG_IUFT_EN 0
549 #endif
550 #ifndef CONFIG_RF_ERRINJ
551 #define CONFIG_RF_ERRINJ 0
552 #endif
553
554 #ifndef CONFIG_FPUFT_EN
555 #define CONFIG_FPUFT 0
556 #else
557 #ifdef CONFIG_FPU_GRFPU
558 #define CONFIG_FPUFT 2
559 #else
560 #define CONFIG_FPUFT 1
561 #endif
562 #endif
563
564 #ifndef CONFIG_CACHE_FT_EN
565 #define CONFIG_CACHE_FT_EN 0
566 #endif
567 #ifndef CONFIG_CACHE_ERRINJ
568 #define CONFIG_CACHE_ERRINJ 0
569 #endif
570
571 #ifndef CONFIG_LEON3_NETLIST
572 #define CONFIG_LEON3_NETLIST 0
573 #endif
574
575 #ifdef CONFIG_DEBUG_PC32
576 #define CFG_DEBUG_PC32 0
577 #else
578 #define CFG_DEBUG_PC32 2
579 #endif
580 #ifndef CONFIG_IU_DISAS
581 #define CONFIG_IU_DISAS 0
582 #endif
583 #ifndef CONFIG_IU_DISAS_NET
584 #define CONFIG_IU_DISAS_NET 0
585 #endif
586
587
588 #ifndef CONFIG_AHB_SPLIT
589 #define CONFIG_AHB_SPLIT 0
590 #endif
591
592 #ifndef CONFIG_AHB_RROBIN
593 #define CONFIG_AHB_RROBIN 0
594 #endif
595
596 #ifndef CONFIG_AHB_IOADDR
597 #define CONFIG_AHB_IOADDR FFF
598 #endif
599
600 #ifndef CONFIG_APB_HADDR
601 #define CONFIG_APB_HADDR 800
602 #endif
603
604 #ifndef CONFIG_AHB_MON
605 #define CONFIG_AHB_MON 0
606 #endif
607
608 #ifndef CONFIG_AHB_MONERR
609 #define CONFIG_AHB_MONERR 0
610 #endif
611
612 #ifndef CONFIG_AHB_MONWAR
613 #define CONFIG_AHB_MONWAR 0
614 #endif
615
616 #ifndef CONFIG_DSU_UART
617 #define CONFIG_DSU_UART 0
618 #endif
619
620
621 #ifndef CONFIG_DSU_JTAG
622 #define CONFIG_DSU_JTAG 0
623 #endif
624
625 #ifndef CONFIG_DSU_ETH
626 #define CONFIG_DSU_ETH 0
627 #endif
628
629 #ifndef CONFIG_DSU_IPMSB
630 #define CONFIG_DSU_IPMSB C0A8
631 #endif
632
633 #ifndef CONFIG_DSU_IPLSB
634 #define CONFIG_DSU_IPLSB 0033
635 #endif
636
637 #ifndef CONFIG_DSU_ETHMSB
638 #define CONFIG_DSU_ETHMSB 020000
639 #endif
640
641 #ifndef CONFIG_DSU_ETHLSB
642 #define CONFIG_DSU_ETHLSB 000009
643 #endif
644
645 #if defined CONFIG_DSU_ETHSZ1
646 #define CFG_DSU_ETHB 1
647 #elif CONFIG_DSU_ETHSZ2
648 #define CFG_DSU_ETHB 2
649 #elif CONFIG_DSU_ETHSZ4
650 #define CFG_DSU_ETHB 4
651 #elif CONFIG_DSU_ETHSZ8
652 #define CFG_DSU_ETHB 8
653 #elif CONFIG_DSU_ETHSZ16
654 #define CFG_DSU_ETHB 16
655 #elif CONFIG_DSU_ETHSZ32
656 #define CFG_DSU_ETHB 32
657 #else
658 #define CFG_DSU_ETHB 1
659 #endif
660
661 #ifndef CONFIG_DSU_ETH_PROG
662 #define CONFIG_DSU_ETH_PROG 0
663 #endif
664
665
666 #ifndef CONFIG_SRCTRL
667 #define CONFIG_SRCTRL 0
668 #endif
669
670 #ifndef CONFIG_SRCTRL_PROMWS
671 #define CONFIG_SRCTRL_PROMWS 0
672 #endif
673
674 #ifndef CONFIG_SRCTRL_RAMWS
675 #define CONFIG_SRCTRL_RAMWS 0
676 #endif
677
678 #ifndef CONFIG_SRCTRL_IOWS
679 #define CONFIG_SRCTRL_IOWS 0
680 #endif
681
682 #ifndef CONFIG_SRCTRL_RMW
683 #define CONFIG_SRCTRL_RMW 0
684 #endif
685
686 #ifndef CONFIG_SRCTRL_8BIT
687 #define CONFIG_SRCTRL_8BIT 0
688 #endif
689
690
691 #ifndef CONFIG_SRCTRL_ROMASEL
692 #define CONFIG_SRCTRL_ROMASEL 0
693 #endif
694
695 #if defined CONFIG_SRCTRL_SRBANKS1
696 #define CFG_SR_CTRL_SRBANKS 1
697 #elif defined CONFIG_SRCTRL_SRBANKS2
698 #define CFG_SR_CTRL_SRBANKS 2
699 #elif defined CONFIG_SRCTRL_SRBANKS3
700 #define CFG_SR_CTRL_SRBANKS 3
701 #elif defined CONFIG_SRCTRL_SRBANKS4
702 #define CFG_SR_CTRL_SRBANKS 4
703 #elif defined CONFIG_SRCTRL_SRBANKS5
704 #define CFG_SR_CTRL_SRBANKS 5
705 #else
706 #define CFG_SR_CTRL_SRBANKS 1
707 #endif
708
709 #if defined CONFIG_SRCTRL_BANKSZ0
710 #define CFG_SR_CTRL_BANKSZ 0
711 #elif defined CONFIG_SRCTRL_BANKSZ1
712 #define CFG_SR_CTRL_BANKSZ 1
713 #elif defined CONFIG_SRCTRL_BANKSZ2
714 #define CFG_SR_CTRL_BANKSZ 2
715 #elif defined CONFIG_SRCTRL_BANKSZ3
716 #define CFG_SR_CTRL_BANKSZ 3
717 #elif defined CONFIG_SRCTRL_BANKSZ4
718 #define CFG_SR_CTRL_BANKSZ 4
719 #elif defined CONFIG_SRCTRL_BANKSZ5
720 #define CFG_SR_CTRL_BANKSZ 5
721 #elif defined CONFIG_SRCTRL_BANKSZ6
722 #define CFG_SR_CTRL_BANKSZ 6
723 #elif defined CONFIG_SRCTRL_BANKSZ7
724 #define CFG_SR_CTRL_BANKSZ 7
725 #elif defined CONFIG_SRCTRL_BANKSZ8
726 #define CFG_SR_CTRL_BANKSZ 8
727 #elif defined CONFIG_SRCTRL_BANKSZ9
728 #define CFG_SR_CTRL_BANKSZ 9
729 #elif defined CONFIG_SRCTRL_BANKSZ10
730 #define CFG_SR_CTRL_BANKSZ 10
731 #elif defined CONFIG_SRCTRL_BANKSZ11
732 #define CFG_SR_CTRL_BANKSZ 11
733 #elif defined CONFIG_SRCTRL_BANKSZ12
734 #define CFG_SR_CTRL_BANKSZ 12
735 #elif defined CONFIG_SRCTRL_BANKSZ13
736 #define CFG_SR_CTRL_BANKSZ 13
737 #else
738 #define CFG_SR_CTRL_BANKSZ 0
739 #endif
740 #ifndef CONFIG_MCTRL_LEON2
741 #define CONFIG_MCTRL_LEON2 0
742 #endif
743
744 #ifndef CONFIG_MCTRL_SDRAM
745 #define CONFIG_MCTRL_SDRAM 0
746 #endif
747
748 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
749 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
750 #endif
751
752 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
753 #define CONFIG_MCTRL_SDRAM_INVCLK 0
754 #endif
755
756 #ifndef CONFIG_MCTRL_SDRAM_BUS64
757 #define CONFIG_MCTRL_SDRAM_BUS64 0
758 #endif
759
760 #ifndef CONFIG_MCTRL_8BIT
761 #define CONFIG_MCTRL_8BIT 0
762 #endif
763
764 #ifndef CONFIG_MCTRL_16BIT
765 #define CONFIG_MCTRL_16BIT 0
766 #endif
767
768 #ifndef CONFIG_MCTRL_5CS
769 #define CONFIG_MCTRL_5CS 0
770 #endif
771
772 #ifndef CONFIG_MCTRL_EDAC
773 #define CONFIG_MCTRL_EDAC 0
774 #endif
775
776 #ifndef CONFIG_MCTRL_PAGE
777 #define CONFIG_MCTRL_PAGE 0
778 #endif
779
780 #ifndef CONFIG_MCTRL_PROGPAGE
781 #define CONFIG_MCTRL_PROGPAGE 0
782 #endif
783
784 #ifndef CONFIG_SDCTRL
785 #define CONFIG_SDCTRL 0
786 #endif
787
788 #ifndef CONFIG_SDCTRL_SEPBUS
789 #define CONFIG_SDCTRL_SEPBUS 0
790 #endif
791
792 #ifndef CONFIG_SDCTRL_INVCLK
793 #define CONFIG_SDCTRL_INVCLK 0
794 #endif
795
796 #ifndef CONFIG_SDCTRL_BUS64
797 #define CONFIG_SDCTRL_BUS64 0
798 #endif
799
800 #ifndef CONFIG_SDCTRL_PAGE
801 #define CONFIG_SDCTRL_PAGE 0
802 #endif
803
804 #ifndef CONFIG_SDCTRL_PROGPAGE
805 #define CONFIG_SDCTRL_PROGPAGE 0
806 #endif
807
808 #ifndef CONFIG_AHBROM_ENABLE
809 #define CONFIG_AHBROM_ENABLE 0
810 #endif
811
812 #ifndef CONFIG_AHBROM_START
813 #define CONFIG_AHBROM_START 000
814 #endif
815
816 #ifndef CONFIG_AHBROM_PIPE
817 #define CONFIG_AHBROM_PIPE 0
818 #endif
819
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
821 #define CONFIG_ROM_START 100
822 #else
823 #define CONFIG_ROM_START 000
824 #endif
825
826
827 #ifndef CONFIG_AHBRAM_ENABLE
828 #define CONFIG_AHBRAM_ENABLE 0
829 #endif
830
831 #ifndef CONFIG_AHBRAM_START
832 #define CONFIG_AHBRAM_START A00
833 #endif
834
835 #if defined CONFIG_AHBRAM_SZ1
836 #define CFG_AHBRAMSZ 1
837 #elif CONFIG_AHBRAM_SZ2
838 #define CFG_AHBRAMSZ 2
839 #elif CONFIG_AHBRAM_SZ4
840 #define CFG_AHBRAMSZ 4
841 #elif CONFIG_AHBRAM_SZ8
842 #define CFG_AHBRAMSZ 8
843 #elif CONFIG_AHBRAM_SZ16
844 #define CFG_AHBRAMSZ 16
845 #elif CONFIG_AHBRAM_SZ32
846 #define CFG_AHBRAMSZ 32
847 #elif CONFIG_AHBRAM_SZ64
848 #define CFG_AHBRAMSZ 64
849 #else
850 #define CFG_AHBRAMSZ 1
851 #endif
852
853 #ifndef CONFIG_GRETH_ENABLE
854 #define CONFIG_GRETH_ENABLE 0
855 #endif
856
857 #ifndef CONFIG_GRETH_GIGA
858 #define CONFIG_GRETH_GIGA 0
859 #endif
860
861 #if defined CONFIG_GRETH_FIFO4
862 #define CFG_GRETH_FIFO 4
863 #elif defined CONFIG_GRETH_FIFO8
864 #define CFG_GRETH_FIFO 8
865 #elif defined CONFIG_GRETH_FIFO16
866 #define CFG_GRETH_FIFO 16
867 #elif defined CONFIG_GRETH_FIFO32
868 #define CFG_GRETH_FIFO 32
869 #elif defined CONFIG_GRETH_FIFO64
870 #define CFG_GRETH_FIFO 64
871 #else
872 #define CFG_GRETH_FIFO 8
873 #endif
874
875 #ifndef CONFIG_CAN_ENABLE
876 #define CONFIG_CAN_ENABLE 0
877 #endif
878
879 #ifndef CONFIG_CANIO
880 #define CONFIG_CANIO 0
881 #endif
882
883 #ifndef CONFIG_CANIRQ
884 #define CONFIG_CANIRQ 0
885 #endif
886
887 #ifndef CONFIG_CANLOOP
888 #define CONFIG_CANLOOP 0
889 #endif
890
891 #ifndef CONFIG_CAN_SYNCRST
892 #define CONFIG_CAN_SYNCRST 0
893 #endif
894
895
896 #ifndef CONFIG_CAN_FT
897 #define CONFIG_CAN_FT 0
898 #endif
899 #if defined CONFIG_PCI_SIMPLE_TARGET
900 #define CFG_PCITYPE 1
901 #elif defined CONFIG_PCI_MASTER_TARGET_DMA
902 #define CFG_PCITYPE 3
903 #elif defined CONFIG_PCI_MASTER_TARGET
904 #define CFG_PCITYPE 2
905 #else
906 #define CFG_PCITYPE 0
907 #endif
908
909 #ifndef CONFIG_PCI_VENDORID
910 #define CONFIG_PCI_VENDORID 0
911 #endif
912
913 #ifndef CONFIG_PCI_DEVICEID
914 #define CONFIG_PCI_DEVICEID 0
915 #endif
916
917 #ifndef CONFIG_PCI_REVID
918 #define CONFIG_PCI_REVID 0
919 #endif
920
921 #if defined CONFIG_PCI_FIFO0
922 #define CFG_PCIFIFO 8
923 #define CFG_PCI_ENFIFO 0
924 #elif defined CONFIG_PCI_FIFO16
925 #define CFG_PCIFIFO 16
926 #elif defined CONFIG_PCI_FIFO32
927 #define CFG_PCIFIFO 32
928 #elif defined CONFIG_PCI_FIFO64
929 #define CFG_PCIFIFO 64
930 #elif defined CONFIG_PCI_FIFO128
931 #define CFG_PCIFIFO 128
932 #elif defined CONFIG_PCI_FIFO256
933 #define CFG_PCIFIFO 256
934 #else
935 #define CFG_PCIFIFO 8
936 #endif
937
938 #ifndef CFG_PCI_ENFIFO
939 #define CFG_PCI_ENFIFO 1
940 #endif
941
942
943 #ifndef CONFIG_PCI_ARBITER_APB
944 #define CONFIG_PCI_ARBITER_APB 0
945 #endif
946
947 #ifndef CONFIG_PCI_ARBITER
948 #define CONFIG_PCI_ARBITER 0
949 #endif
950
951 #ifndef CONFIG_PCI_ARBITER_NREQ
952 #define CONFIG_PCI_ARBITER_NREQ 4
953 #endif
954
955 #ifndef CONFIG_PCI_TRACE
956 #define CONFIG_PCI_TRACE 0
957 #endif
958
959 #if defined CONFIG_PCI_TRACE512
960 #define CFG_PCI_TRACEBUF 512
961 #elif defined CONFIG_PCI_TRACE1024
962 #define CFG_PCI_TRACEBUF 1024
963 #elif defined CONFIG_PCI_TRACE2048
964 #define CFG_PCI_TRACEBUF 2048
965 #elif defined CONFIG_PCI_TRACE4096
966 #define CFG_PCI_TRACEBUF 4096
967 #else
968 #define CFG_PCI_TRACEBUF 256
969 #endif
970
971
972 #ifndef CONFIG_SPW_ENABLE
973 #define CONFIG_SPW_ENABLE 0
974 #endif
975
976 #ifndef CONFIG_SPW_NUM
977 #define CONFIG_SPW_NUM 1
978 #endif
979
980 #if defined CONFIG_SPW_AHBFIFO4
981 #define CONFIG_SPW_AHBFIFO 4
982 #elif defined CONFIG_SPW_AHBFIFO8
983 #define CONFIG_SPW_AHBFIFO 8
984 #elif defined CONFIG_SPW_AHBFIFO16
985 #define CONFIG_SPW_AHBFIFO 16
986 #elif defined CONFIG_SPW_AHBFIFO32
987 #define CONFIG_SPW_AHBFIFO 32
988 #elif defined CONFIG_SPW_AHBFIFO64
989 #define CONFIG_SPW_AHBFIFO 64
990 #else
991 #define CONFIG_SPW_AHBFIFO 4
992 #endif
993
994 #if defined CONFIG_SPW_RXFIFO16
995 #define CONFIG_SPW_RXFIFO 16
996 #elif defined CONFIG_SPW_RXFIFO32
997 #define CONFIG_SPW_RXFIFO 32
998 #elif defined CONFIG_SPW_RXFIFO64
999 #define CONFIG_SPW_RXFIFO 64
1000 #else
1001 #define CONFIG_SPW_RXFIFO 16
1002 #endif
1003
1004 #ifndef CONFIG_SPW_RMAP
1005 #define CONFIG_SPW_RMAP 0
1006 #endif
1007
1008 #if defined CONFIG_SPW_RMAPBUF2
1009 #define CONFIG_SPW_RMAPBUF 2
1010 #elif defined CONFIG_SPW_RMAPBUF4
1011 #define CONFIG_SPW_RMAPBUF 4
1012 #elif defined CONFIG_SPW_RMAPBUF6
1013 #define CONFIG_SPW_RMAPBUF 6
1014 #elif defined CONFIG_SPW_RMAPBUF8
1015 #define CONFIG_SPW_RMAPBUF 8
1016 #else
1017 #define CONFIG_SPW_RMAPBUF 4
1018 #endif
1019
1020 #ifndef CONFIG_SPW_RMAPCRC
1021 #define CONFIG_SPW_RMAPCRC 0
1022 #endif
1023
1024 #ifndef CONFIG_SPW_RXUNAL
1025 #define CONFIG_SPW_RXUNAL 0
1026 #endif
1027
1028 #ifndef CONFIG_SPW_NETLIST
1029 #define CONFIG_SPW_NETLIST 0
1030 #endif
1031
1032 #ifndef CONFIG_SPW_FT
1033 #define CONFIG_SPW_FT 0
1034 #endif
1035
1036 #if defined CONFIG_SPW_GRSPW1
1037 #define CONFIG_SPW_GRSPW 1
1038 #else
1039 #define CONFIG_SPW_GRSPW 2
1040 #endif
1041
1042 #ifndef CONFIG_SPW_DMACHAN
1043 #define CONFIG_SPW_DMACHAN 1
1044 #endif
1045
1046 #ifndef CONFIG_SPW_PORTS
1047 #define CONFIG_SPW_PORTS 1
1048 #endif
1049
1050 #if defined CONFIG_SPW_RX_SDR
1051 #define CONFIG_SPW_INPUT 2
1052 #elif defined CONFIG_SPW_RX_DDR
1053 #define CONFIG_SPW_INPUT 3
1054 #elif defined CONFIG_SPW_RX_XOR
1055 #define CONFIG_SPW_INPUT 0
1056 #elif defined CONFIG_SPW_RX_AFLEX
1057 #define CONFIG_SPW_INPUT 1
1058 #else
1059 #define CONFIG_SPW_INPUT 2
1060 #endif
1061
1062 #if defined CONFIG_SPW_TX_SDR
1063 #define CONFIG_SPW_OUTPUT 0
1064 #elif defined CONFIG_SPW_TX_DDR
1065 #define CONFIG_SPW_OUTPUT 1
1066 #elif defined CONFIG_SPW_TX_AFLEX
1067 #define CONFIG_SPW_OUTPUT 2
1068 #else
1069 #define CONFIG_SPW_OUTPUT 0
1070 #endif
1071
1072 #ifndef CONFIG_SPW_RTSAME
1073 #define CONFIG_SPW_RTSAME 0
1074 #endif
1075 #ifndef CONFIG_UART1_ENABLE
1076 #define CONFIG_UART1_ENABLE 0
1077 #endif
1078
1079 #if defined CONFIG_UA1_FIFO1
1080 #define CFG_UA1_FIFO 1
1081 #elif defined CONFIG_UA1_FIFO2
1082 #define CFG_UA1_FIFO 2
1083 #elif defined CONFIG_UA1_FIFO4
1084 #define CFG_UA1_FIFO 4
1085 #elif defined CONFIG_UA1_FIFO8
1086 #define CFG_UA1_FIFO 8
1087 #elif defined CONFIG_UA1_FIFO16
1088 #define CFG_UA1_FIFO 16
1089 #elif defined CONFIG_UA1_FIFO32
1090 #define CFG_UA1_FIFO 32
1091 #else
1092 #define CFG_UA1_FIFO 1
1093 #endif
1094
1095 #ifndef CONFIG_UART2_ENABLE
1096 #define CONFIG_UART2_ENABLE 0
1097 #endif
1098
1099 #if defined CONFIG_UA2_FIFO1
1100 #define CFG_UA2_FIFO 1
1101 #elif defined CONFIG_UA2_FIFO2
1102 #define CFG_UA2_FIFO 2
1103 #elif defined CONFIG_UA2_FIFO4
1104 #define CFG_UA2_FIFO 4
1105 #elif defined CONFIG_UA2_FIFO8
1106 #define CFG_UA2_FIFO 8
1107 #elif defined CONFIG_UA2_FIFO16
1108 #define CFG_UA2_FIFO 16
1109 #elif defined CONFIG_UA2_FIFO32
1110 #define CFG_UA2_FIFO 32
1111 #else
1112 #define CFG_UA2_FIFO 1
1113 #endif
1114
1115 #ifndef CONFIG_IRQ3_ENABLE
1116 #define CONFIG_IRQ3_ENABLE 0
1117 #endif
1118 #ifndef CONFIG_IRQ3_NSEC
1119 #define CONFIG_IRQ3_NSEC 0
1120 #endif
1121 #ifndef CONFIG_GPT_ENABLE
1122 #define CONFIG_GPT_ENABLE 0
1123 #endif
1124
1125 #ifndef CONFIG_GPT_NTIM
1126 #define CONFIG_GPT_NTIM 1
1127 #endif
1128
1129 #ifndef CONFIG_GPT_SW
1130 #define CONFIG_GPT_SW 8
1131 #endif
1132
1133 #ifndef CONFIG_GPT_TW
1134 #define CONFIG_GPT_TW 8
1135 #endif
1136
1137 #ifndef CONFIG_GPT_IRQ
1138 #define CONFIG_GPT_IRQ 8
1139 #endif
1140
1141 #ifndef CONFIG_GPT_SEPIRQ
1142 #define CONFIG_GPT_SEPIRQ 0
1143 #endif
1144 #ifndef CONFIG_GPT_ENABLE
1145 #define CONFIG_GPT_ENABLE 0
1146 #endif
1147
1148 #ifndef CONFIG_GPT_NTIM
1149 #define CONFIG_GPT_NTIM 1
1150 #endif
1151
1152 #ifndef CONFIG_GPT_SW
1153 #define CONFIG_GPT_SW 8
1154 #endif
1155
1156 #ifndef CONFIG_GPT_TW
1157 #define CONFIG_GPT_TW 8
1158 #endif
1159
1160 #ifndef CONFIG_GPT_IRQ
1161 #define CONFIG_GPT_IRQ 8
1162 #endif
1163
1164 #ifndef CONFIG_GPT_SEPIRQ
1165 #define CONFIG_GPT_SEPIRQ 0
1166 #endif
1167
1168 #ifndef CONFIG_GPT_WDOGEN
1169 #define CONFIG_GPT_WDOGEN 0
1170 #endif
1171
1172 #ifndef CONFIG_GPT_WDOG
1173 #define CONFIG_GPT_WDOG 0
1174 #endif
1175
1176 #ifndef CONFIG_GRGPIO_ENABLE
1177 #define CONFIG_GRGPIO_ENABLE 0
1178 #endif
1179 #ifndef CONFIG_GRGPIO_IMASK
1180 #define CONFIG_GRGPIO_IMASK 0000
1181 #endif
1182 #ifndef CONFIG_GRGPIO_WIDTH
1183 #define CONFIG_GRGPIO_WIDTH 1
1184 #endif
1185
1186
1187 #ifndef CONFIG_DEBUG_UART
1188 #define CONFIG_DEBUG_UART 0
1189 #endif
Show file before | Show file after | Hide comments
@@ -1,209 +1,209
1 This leon3 design is tailored to the Xilinx SP605 Spartan6 board
2
3 Simulation and synthesis
4 ------------------------
5
6 The design uses the Xilinx MIG memory interface with an AHB-2.0
7 interface. The MIG source code cannot be distributed due to the
8 prohibitive Xilinx license, so the MIG must be re-generated with
9 coregen before simulation and synthesis can be done.
10
11 To generate the MIG and install tne Xilinx unisim simulation
12 library, do as follows:
13
14 make mig
15 make install-secureip
16
17 This will ONLY work with ISE-13.2 installed, and the XILINX variable
18 properly set in the shell. To synthesize the design, do
19
20 make ise
21
22 and then
23
24 make ise-prog-fpga
25
26 to program the FPGA.
27
28 Design specifics
29 ----------------
30
31 * System reset is mapped to the CPU RESET button
32
33 * The AHB and processor is clocked by a 60 MHz clock, generated
34 from the 33 MHz SYSACE clock using a DCM. You can change the frequency
35 generation in the clocks menu of xconfig. The DDR3 (MIG) controller
36 runs at 667 MHz.
37
38 * The GRETH core is enabled and runs without problems at 100 Mbit.
39 Ethernet debug link is enabled and has IP 192.168.0.51.
40 1 Gbit operation is also possible (requires grlib com release),
41 uncomment related timing constraints in the leon3mp.ucf first.
42
43 * 16-bit flash prom can be read at address 0. It can be programmed
44 with GRMON version 1.1.16 or later.
45
46 * DDR3 is working with the provided Xilinx MIG DDR3 controller.
47 If you want to simulate this design, first install the secure
48 IP models with:
49
50 make install-secureip
51
52 Then rebuild the scripts and simulation model:
53
54 make distclean vsim
55
56 Modelsim v6.6e or newer is required to build the secure IP models.
57 Note that the regular leon3 test bench cannot be run in simulation
58 as the DDR3 model lacks data pre-load.
59
60 * The application UART1 is connected to the USB/UART connector
61
62 * The SVGA frame buffer uses a separate port on the DDR3 controller,
63 and therefore does not noticeably affect the performance of the processor.
64 Default output is analog VGA, to switch to DVI mode execute this
65 command in grmon:
66
67 i2c dvi init_l4itx_vga
68
69 * The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
70 Start grmon with -xilusb to connect.
71
72 * Output from GRMON is:
73
74 $ grmon -xilusb -u
75
76 GRMON LEON debug monitor v1.1.51 professional version (debug)
77
78 Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
79 For latest updates, go to http://www.gaisler.com/
80 Comments or bug-reports to support@gaisler.com
81
82 Xilinx cable: Cable type/rev : 0x3
83 JTAG chain: xc6slx45t xccace
84
85 GRLIB build version: 4111
86
87 initialising ...............
88 detected frequency: 50 MHz
89 SRAM waitstates: 1
90
91 Component Vendor
92 LEON3 SPARC V8 Processor Gaisler Research
93 AHB Debug JTAG TAP Gaisler Research
94 GR Ethernet MAC Gaisler Research
95 LEON2 Memory Controller European Space Agency
96 AHB/APB Bridge Gaisler Research
97 LEON3 Debug Support Unit Gaisler Research
98 Xilinx MIG DDR2 controller Gaisler Research
99 AHB/APB Bridge Gaisler Research
100 Generic APB UART Gaisler Research
101 Multi-processor Interrupt Ctrl Gaisler Research
102 Modular Timer Unit Gaisler Research
103 SVGA Controller Gaisler Research
104 AMBA Wrapper for OC I2C-master Gaisler Research
105 General purpose I/O port Gaisler Research
106 AHB status register Gaisler Research
107
108 Use command 'info sys' to print a detailed report of attached cores
109
110 grlib> inf sys
111 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
112 ahb master 0
113 01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
114 ahb master 1
115 02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
116 ahb master 2, irq 12
117 apb: 80000e00 - 80000f00
118 Device index: dev0
119 edcl ip 192.168.1.51, buffer 2 kbyte
120 00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
121 ahb: 00000000 - 20000000
122 apb: 80000000 - 80000100
123 16-bit prom @ 0x00000000
124 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
125 ahb: 80000000 - 80100000
126 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
127 ahb: 90000000 - a0000000
128 AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
129 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
130 icache 2 * 8 kbyte, 32 byte/line rnd
131 dcache 2 * 4 kbyte, 16 byte/line rnd
132 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
133 ahb: 40000000 - 48000000
134 apb: 80100000 - 80100100
135 DDR2: 128 Mbyte
136 0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
137 ahb: 80100000 - 80200000
138 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
139 irq 2
140 apb: 80000100 - 80000200
141 baud rate 38343, DSU mode (FIFO debug)
142 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
143 apb: 80000200 - 80000300
144 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
145 irq 8
146 apb: 80000300 - 80000400
147 8-bit scaler, 2 * 32-bit timers, divisor 50
148 06.01:063 Gaisler Research SVGA Controller (ver 0x0)
149 apb: 80000600 - 80000700
150 clk0: 50.00 MHz
151 09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
152 irq 14
153 apb: 80000900 - 80000a00
154 0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
155 apb: 80000a00 - 80000b00
156 0f.01:052 Gaisler Research AHB status register (ver 0x0)
157 irq 7
158 apb: 80000f00 - 80001000
159 grlib> fla
160
161 Intel-style 16-bit flash on D[31:16]
162
163 Manuf. Intel
164 Device Strataflash P30
165
166 Device ID 02e44603e127ffff
167 User ID ffffffffffffffff
168
169
170 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
171
172
173 CFI info
174 flash family : 1
175 flash size : 256 Mbit
176 erase regions : 2
177 erase blocks : 259
178 write buffer : 1024 bytes
179 lock-down : yes
180 region 0 : 255 blocks of 128 Kbytes
181 region 1 : 4 blocks of 32 Kbytes
182
183 grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
184 section: .text at 0x40000000, size 102544 bytes
185 section: .data at 0x40019090, size 2788 bytes
186 total size: 105332 bytes (1.2 Mbit/s)
187 read 272 symbols
188 entry point: 0x40000000
189 grlib> run
190 2K performance run parameters for coremark.
191 CoreMark Size : 666
192 Total ticks : 19945918
193 Total time (secs): 19.945918
194 Iterations/Sec : 100.271143
195 Iterations : 2000
196 Compiler version : GCC4.4.2
197 Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
198 Memory location : STACK
199 seedcrc : 0xe9f5
200 [0]crclist : 0xe714
201 [0]crcmatrix : 0x1fd7
202 [0]crcstate : 0x8e3a
203 [0]crcfinal : 0x4983
204 Correct operation validated. See readme.txt for run and reporting rules.
205 CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
206
207 Program exited normally.
208 grlib>
209
1 This leon3 design is tailored to the Xilinx SP605 Spartan6 board
2
3 Simulation and synthesis
4 ------------------------
5
6 The design uses the Xilinx MIG memory interface with an AHB-2.0
7 interface. The MIG source code cannot be distributed due to the
8 prohibitive Xilinx license, so the MIG must be re-generated with
9 coregen before simulation and synthesis can be done.
10
11 To generate the MIG and install tne Xilinx unisim simulation
12 library, do as follows:
13
14 make mig
15 make install-secureip
16
17 This will ONLY work with ISE-13.2 installed, and the XILINX variable
18 properly set in the shell. To synthesize the design, do
19
20 make ise
21
22 and then
23
24 make ise-prog-fpga
25
26 to program the FPGA.
27
28 Design specifics
29 ----------------
30
31 * System reset is mapped to the CPU RESET button
32
33 * The AHB and processor is clocked by a 60 MHz clock, generated
34 from the 33 MHz SYSACE clock using a DCM. You can change the frequency
35 generation in the clocks menu of xconfig. The DDR3 (MIG) controller
36 runs at 667 MHz.
37
38 * The GRETH core is enabled and runs without problems at 100 Mbit.
39 Ethernet debug link is enabled and has IP 192.168.0.51.
40 1 Gbit operation is also possible (requires grlib com release),
41 uncomment related timing constraints in the leon3mp.ucf first.
42
43 * 16-bit flash prom can be read at address 0. It can be programmed
44 with GRMON version 1.1.16 or later.
45
46 * DDR3 is working with the provided Xilinx MIG DDR3 controller.
47 If you want to simulate this design, first install the secure
48 IP models with:
49
50 make install-secureip
51
52 Then rebuild the scripts and simulation model:
53
54 make distclean vsim
55
56 Modelsim v6.6e or newer is required to build the secure IP models.
57 Note that the regular leon3 test bench cannot be run in simulation
58 as the DDR3 model lacks data pre-load.
59
60 * The application UART1 is connected to the USB/UART connector
61
62 * The SVGA frame buffer uses a separate port on the DDR3 controller,
63 and therefore does not noticeably affect the performance of the processor.
64 Default output is analog VGA, to switch to DVI mode execute this
65 command in grmon:
66
67 i2c dvi init_l4itx_vga
68
69 * The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
70 Start grmon with -xilusb to connect.
71
72 * Output from GRMON is:
73
74 $ grmon -xilusb -u
75
76 GRMON LEON debug monitor v1.1.51 professional version (debug)
77
78 Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
79 For latest updates, go to http://www.gaisler.com/
80 Comments or bug-reports to support@gaisler.com
81
82 Xilinx cable: Cable type/rev : 0x3
83 JTAG chain: xc6slx45t xccace
84
85 GRLIB build version: 4111
86
87 initialising ...............
88 detected frequency: 50 MHz
89 SRAM waitstates: 1
90
91 Component Vendor
92 LEON3 SPARC V8 Processor Gaisler Research
93 AHB Debug JTAG TAP Gaisler Research
94 GR Ethernet MAC Gaisler Research
95 LEON2 Memory Controller European Space Agency
96 AHB/APB Bridge Gaisler Research
97 LEON3 Debug Support Unit Gaisler Research
98 Xilinx MIG DDR2 controller Gaisler Research
99 AHB/APB Bridge Gaisler Research
100 Generic APB UART Gaisler Research
101 Multi-processor Interrupt Ctrl Gaisler Research
102 Modular Timer Unit Gaisler Research
103 SVGA Controller Gaisler Research
104 AMBA Wrapper for OC I2C-master Gaisler Research
105 General purpose I/O port Gaisler Research
106 AHB status register Gaisler Research
107
108 Use command 'info sys' to print a detailed report of attached cores
109
110 grlib> inf sys
111 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
112 ahb master 0
113 01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
114 ahb master 1
115 02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
116 ahb master 2, irq 12
117 apb: 80000e00 - 80000f00
118 Device index: dev0
119 edcl ip 192.168.1.51, buffer 2 kbyte
120 00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
121 ahb: 00000000 - 20000000
122 apb: 80000000 - 80000100
123 16-bit prom @ 0x00000000
124 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
125 ahb: 80000000 - 80100000
126 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
127 ahb: 90000000 - a0000000
128 AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
129 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
130 icache 2 * 8 kbyte, 32 byte/line rnd
131 dcache 2 * 4 kbyte, 16 byte/line rnd
132 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
133 ahb: 40000000 - 48000000
134 apb: 80100000 - 80100100
135 DDR2: 128 Mbyte
136 0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
137 ahb: 80100000 - 80200000
138 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
139 irq 2
140 apb: 80000100 - 80000200
141 baud rate 38343, DSU mode (FIFO debug)
142 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
143 apb: 80000200 - 80000300
144 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
145 irq 8
146 apb: 80000300 - 80000400
147 8-bit scaler, 2 * 32-bit timers, divisor 50
148 06.01:063 Gaisler Research SVGA Controller (ver 0x0)
149 apb: 80000600 - 80000700
150 clk0: 50.00 MHz
151 09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
152 irq 14
153 apb: 80000900 - 80000a00
154 0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
155 apb: 80000a00 - 80000b00
156 0f.01:052 Gaisler Research AHB status register (ver 0x0)
157 irq 7
158 apb: 80000f00 - 80001000
159 grlib> fla
160
161 Intel-style 16-bit flash on D[31:16]
162
163 Manuf. Intel
164 Device Strataflash P30
165
166 Device ID 02e44603e127ffff
167 User ID ffffffffffffffff
168
169
170 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
171
172
173 CFI info
174 flash family : 1
175 flash size : 256 Mbit
176 erase regions : 2
177 erase blocks : 259
178 write buffer : 1024 bytes
179 lock-down : yes
180 region 0 : 255 blocks of 128 Kbytes
181 region 1 : 4 blocks of 32 Kbytes
182
183 grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
184 section: .text at 0x40000000, size 102544 bytes
185 section: .data at 0x40019090, size 2788 bytes
186 total size: 105332 bytes (1.2 Mbit/s)
187 read 272 symbols
188 entry point: 0x40000000
189 grlib> run
190 2K performance run parameters for coremark.
191 CoreMark Size : 666
192 Total ticks : 19945918
193 Total time (secs): 19.945918
194 Iterations/Sec : 100.271143
195 Iterations : 2000
196 Compiler version : GCC4.4.2
197 Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
198 Memory location : STACK
199 seedcrc : 0xe9f5
200 [0]crclist : 0xe714
201 [0]crcmatrix : 0x1fd7
202 [0]crcstate : 0x8e3a
203 [0]crcfinal : 0x4983
204 Correct operation validated. See readme.txt for run and reporting rules.
205 CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
206
207 Program exited normally.
208 grlib>
209
Show file before | Show file after | Hide comments
@@ -1,190 +1,190
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
18
19 -- LEON3 processor core
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
23 constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
25 constant CFG_BP : integer := CONFIG_IU_BP;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
72
73 -- AMBA settings
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
83
84 -- JTAG based DSU interface
85 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
86
87 -- Ethernet DSU
88 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
89 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
90 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
91 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
92 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
93 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
94
95 -- LEON2 memory controller
96 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
97 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
98 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
99 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
100 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
101 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
102 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
103 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
104 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
105
106 -- Xilinx MIG
107 constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
108 constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
109 constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
110 constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
111 constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
112 constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
113
114
115 -- AHB status register
116 constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
117 constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
118
119 -- AHB ROM
120 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
121 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
122 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
123 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
124 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
125
126 -- AHB RAM
127 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
128 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
129 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
130
131 -- Gaisler Ethernet core
132 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
133 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
134 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
135
136 -- UART 1
137 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
138 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
139
140 -- LEON3 interrupt controller
141 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
142 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
143
144 -- Modular timer
145 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
146 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
147 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
148 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
149 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
150 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
151 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
152 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
153
154 -- GPIO port
155 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
156 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
157 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
158
159 -- VGA and PS2/ interface
160 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
161 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
162 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
163
164 -- SPI memory controller
165 constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
166 constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
167 constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
168 constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
169 constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
170 constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
171 constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
172 constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
173
174 -- SPI controller
175 constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
176 constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
177 constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
178 constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
179 constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
180 constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
181 constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
182 constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
183 constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
184 constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
185 constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
186 constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
187
188 -- GRLIB debugging
189 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
190
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
18
19 -- LEON3 processor core
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
23 constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
25 constant CFG_BP : integer := CONFIG_IU_BP;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
72
73 -- AMBA settings
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
83
84 -- JTAG based DSU interface
85 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
86
87 -- Ethernet DSU
88 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
89 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
90 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
91 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
92 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
93 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
94
95 -- LEON2 memory controller
96 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
97 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
98 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
99 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
100 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
101 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
102 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
103 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
104 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
105
106 -- Xilinx MIG
107 constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
108 constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
109 constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
110 constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
111 constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
112 constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
113
114
115 -- AHB status register
116 constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
117 constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
118
119 -- AHB ROM
120 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
121 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
122 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
123 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
124 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
125
126 -- AHB RAM
127 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
128 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
129 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
130
131 -- Gaisler Ethernet core
132 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
133 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
134 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
135
136 -- UART 1
137 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
138 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
139
140 -- LEON3 interrupt controller
141 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
142 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
143
144 -- Modular timer
145 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
146 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
147 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
148 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
149 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
150 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
151 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
152 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
153
154 -- GPIO port
155 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
156 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
157 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
158
159 -- VGA and PS2/ interface
160 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
161 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
162 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
163
164 -- SPI memory controller
165 constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
166 constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
167 constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
168 constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
169 constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
170 constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
171 constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
172 constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
173
174 -- SPI controller
175 constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
176 constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
177 constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
178 constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
179 constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
180 constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
181 constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
182 constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
183 constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
184 constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
185 constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
186 constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
187
188 -- GRLIB debugging
189 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
190
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@@ -1,18 +1,18
1
2 main()
3
4 {
5 report_start();
6
7
8 // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
9 base_test();
10 /*
11 greth_test(0x80000e00);
12 spw_test(0x80100A00);
13 spw_test(0x80100B00);
14 spw_test(0x80100C00);
15 svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
16 */
17 report_end();
18 }
1
2 main()
3
4 {
5 report_start();
6
7
8 // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
9 base_test();
10 /*
11 greth_test(0x80000e00);
12 spw_test(0x80100A00);
13 spw_test(0x80100B00);
14 spw_test(0x80100C00);
15 svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
16 */
17 report_end();
18 }
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This diff has been collapsed as it changes many lines, (2102 lines changed) Show them Hide them
@@ -1,1051 +1,1051
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_AXDSP
14 #define CONFIG_SYN_TECH axdsp
15 #elif defined CONFIG_SYN_PROASICPLUS
16 #define CONFIG_SYN_TECH proasic
17 #elif defined CONFIG_SYN_ALTERA
18 #define CONFIG_SYN_TECH altera
19 #elif defined CONFIG_SYN_STRATIX
20 #define CONFIG_SYN_TECH stratix1
21 #elif defined CONFIG_SYN_STRATIXII
22 #define CONFIG_SYN_TECH stratix2
23 #elif defined CONFIG_SYN_STRATIXIII
24 #define CONFIG_SYN_TECH stratix3
25 #elif defined CONFIG_SYN_CYCLONEIII
26 #define CONFIG_SYN_TECH cyclone3
27 #elif defined CONFIG_SYN_EASIC45
28 #define CONFIG_SYN_TECH easic45
29 #elif defined CONFIG_SYN_EASIC90
30 #define CONFIG_SYN_TECH easic90
31 #elif defined CONFIG_SYN_IHP25
32 #define CONFIG_SYN_TECH ihp25
33 #elif defined CONFIG_SYN_IHP25RH
34 #define CONFIG_SYN_TECH ihp25rh
35 #elif defined CONFIG_SYN_CMOS9SF
36 #define CONFIG_SYN_TECH cmos9sf
37 #elif defined CONFIG_SYN_LATTICE
38 #define CONFIG_SYN_TECH lattice
39 #elif defined CONFIG_SYN_ECLIPSE
40 #define CONFIG_SYN_TECH eclipse
41 #elif defined CONFIG_SYN_PEREGRINE
42 #define CONFIG_SYN_TECH peregrine
43 #elif defined CONFIG_SYN_PROASIC
44 #define CONFIG_SYN_TECH proasic
45 #elif defined CONFIG_SYN_PROASIC3
46 #define CONFIG_SYN_TECH apa3
47 #elif defined CONFIG_SYN_PROASIC3E
48 #define CONFIG_SYN_TECH apa3e
49 #elif defined CONFIG_SYN_PROASIC3L
50 #define CONFIG_SYN_TECH apa3l
51 #elif defined CONFIG_SYN_IGLOO
52 #define CONFIG_SYN_TECH apa3
53 #elif defined CONFIG_SYN_FUSION
54 #define CONFIG_SYN_TECH actfus
55 #elif defined CONFIG_SYN_SPARTAN2
56 #define CONFIG_SYN_TECH virtex
57 #elif defined CONFIG_SYN_VIRTEX
58 #define CONFIG_SYN_TECH virtex
59 #elif defined CONFIG_SYN_VIRTEXE
60 #define CONFIG_SYN_TECH virtex
61 #elif defined CONFIG_SYN_SPARTAN3
62 #define CONFIG_SYN_TECH spartan3
63 #elif defined CONFIG_SYN_SPARTAN3E
64 #define CONFIG_SYN_TECH spartan3e
65 #elif defined CONFIG_SYN_SPARTAN6
66 #define CONFIG_SYN_TECH spartan6
67 #elif defined CONFIG_SYN_VIRTEX2
68 #define CONFIG_SYN_TECH virtex2
69 #elif defined CONFIG_SYN_VIRTEX4
70 #define CONFIG_SYN_TECH virtex4
71 #elif defined CONFIG_SYN_VIRTEX5
72 #define CONFIG_SYN_TECH virtex5
73 #elif defined CONFIG_SYN_VIRTEX6
74 #define CONFIG_SYN_TECH virtex6
75 #elif defined CONFIG_SYN_RH_LIB18T
76 #define CONFIG_SYN_TECH rhlib18t
77 #elif defined CONFIG_SYN_SMIC13
78 #define CONFIG_SYN_TECH smic013
79 #elif defined CONFIG_SYN_UT025CRH
80 #define CONFIG_SYN_TECH ut25
81 #elif defined CONFIG_SYN_UT130HBD
82 #define CONFIG_SYN_TECH ut130
83 #elif defined CONFIG_SYN_UT90NHBD
84 #define CONFIG_SYN_TECH ut90
85 #elif defined CONFIG_SYN_TSMC90
86 #define CONFIG_SYN_TECH tsmc90
87 #elif defined CONFIG_SYN_TM65GPLUS
88 #define CONFIG_SYN_TECH tm65gpl
89 #elif defined CONFIG_SYN_CUSTOM1
90 #define CONFIG_SYN_TECH custom1
91 #else
92 #error "unknown target technology"
93 #endif
94
95 #if defined CONFIG_SYN_INFER_RAM
96 #define CFG_RAM_TECH inferred
97 #elif defined CONFIG_MEM_UMC
98 #define CFG_RAM_TECH umc
99 #elif defined CONFIG_MEM_RHUMC
100 #define CFG_RAM_TECH rhumc
101 #elif defined CONFIG_MEM_VIRAGE
102 #define CFG_RAM_TECH memvirage
103 #elif defined CONFIG_MEM_ARTISAN
104 #define CFG_RAM_TECH memartisan
105 #elif defined CONFIG_MEM_CUSTOM1
106 #define CFG_RAM_TECH custom1
107 #elif defined CONFIG_MEM_VIRAGE90
108 #define CFG_RAM_TECH memvirage90
109 #elif defined CONFIG_MEM_INFERRED
110 #define CFG_RAM_TECH inferred
111 #else
112 #define CFG_RAM_TECH CONFIG_SYN_TECH
113 #endif
114
115 #if defined CONFIG_SYN_INFER_PADS
116 #define CFG_PAD_TECH inferred
117 #else
118 #define CFG_PAD_TECH CONFIG_SYN_TECH
119 #endif
120
121 #ifndef CONFIG_SYN_NO_ASYNC
122 #define CONFIG_SYN_NO_ASYNC 0
123 #endif
124
125 #ifndef CONFIG_SYN_SCAN
126 #define CONFIG_SYN_SCAN 0
127 #endif
128
129
130 #if defined CONFIG_CLK_ALTDLL
131 #define CFG_CLK_TECH CONFIG_SYN_TECH
132 #elif defined CONFIG_CLK_HCLKBUF
133 #define CFG_CLK_TECH axcel
134 #elif defined CONFIG_CLK_LATDLL
135 #define CFG_CLK_TECH lattice
136 #elif defined CONFIG_CLK_PRO3PLL
137 #define CFG_CLK_TECH apa3
138 #elif defined CONFIG_CLK_PRO3EPLL
139 #define CFG_CLK_TECH apa3e
140 #elif defined CONFIG_CLK_PRO3LPLL
141 #define CFG_CLK_TECH apa3l
142 #elif defined CONFIG_CLK_FUSPLL
143 #define CFG_CLK_TECH actfus
144 #elif defined CONFIG_CLK_CLKDLL
145 #define CFG_CLK_TECH virtex
146 #elif defined CONFIG_CLK_DCM
147 #define CFG_CLK_TECH CONFIG_SYN_TECH
148 #elif defined CONFIG_CLK_LIB18T
149 #define CFG_CLK_TECH rhlib18t
150 #elif defined CONFIG_CLK_RHUMC
151 #define CFG_CLK_TECH rhumc
152 #elif defined CONFIG_CLK_UT130HBD
153 #define CFG_CLK_TECH ut130
154 #else
155 #define CFG_CLK_TECH inferred
156 #endif
157
158 #ifndef CONFIG_CLK_MUL
159 #define CONFIG_CLK_MUL 2
160 #endif
161
162 #ifndef CONFIG_CLK_DIV
163 #define CONFIG_CLK_DIV 2
164 #endif
165
166 #ifndef CONFIG_OCLK_DIV
167 #define CONFIG_OCLK_DIV 1
168 #endif
169
170 #ifndef CONFIG_OCLKB_DIV
171 #define CONFIG_OCLKB_DIV 0
172 #endif
173
174 #ifndef CONFIG_OCLKC_DIV
175 #define CONFIG_OCLKC_DIV 0
176 #endif
177
178 #ifndef CONFIG_PCI_CLKDLL
179 #define CONFIG_PCI_CLKDLL 0
180 #endif
181
182 #ifndef CONFIG_PCI_SYSCLK
183 #define CONFIG_PCI_SYSCLK 0
184 #endif
185
186 #ifndef CONFIG_CLK_NOFB
187 #define CONFIG_CLK_NOFB 0
188 #endif
189 #ifndef CONFIG_LEON3
190 #define CONFIG_LEON3 0
191 #endif
192
193 #ifndef CONFIG_PROC_NUM
194 #define CONFIG_PROC_NUM 1
195 #endif
196
197 #ifndef CONFIG_IU_NWINDOWS
198 #define CONFIG_IU_NWINDOWS 8
199 #endif
200
201 #ifndef CONFIG_IU_RSTADDR
202 #define CONFIG_IU_RSTADDR 8
203 #endif
204
205 #ifndef CONFIG_IU_LDELAY
206 #define CONFIG_IU_LDELAY 1
207 #endif
208
209 #ifndef CONFIG_IU_WATCHPOINTS
210 #define CONFIG_IU_WATCHPOINTS 0
211 #endif
212
213 #ifdef CONFIG_IU_V8MULDIV
214 #ifdef CONFIG_IU_MUL_LATENCY_4
215 #define CFG_IU_V8 1
216 #elif defined CONFIG_IU_MUL_LATENCY_5
217 #define CFG_IU_V8 2
218 #elif defined CONFIG_IU_MUL_LATENCY_2
219 #define CFG_IU_V8 16#32#
220 #endif
221 #else
222 #define CFG_IU_V8 0
223 #endif
224
225 #ifdef CONFIG_IU_MUL_MODGEN
226 #define CFG_IU_MUL_STRUCT 1
227 #elif defined CONFIG_IU_MUL_TECHSPEC
228 #define CFG_IU_MUL_STRUCT 2
229 #elif defined CONFIG_IU_MUL_DW
230 #define CFG_IU_MUL_STRUCT 3
231 #else
232 #define CFG_IU_MUL_STRUCT 0
233 #endif
234
235 #ifndef CONFIG_PWD
236 #define CONFIG_PWD 0
237 #endif
238
239 #ifndef CONFIG_IU_MUL_MAC
240 #define CONFIG_IU_MUL_MAC 0
241 #endif
242
243 #ifndef CONFIG_IU_BP
244 #define CONFIG_IU_BP 0
245 #endif
246
247 #ifndef CONFIG_NOTAG
248 #define CONFIG_NOTAG 0
249 #endif
250
251 #ifndef CONFIG_IU_SVT
252 #define CONFIG_IU_SVT 0
253 #endif
254
255 #if defined CONFIG_FPU_GRFPC1
256 #define CONFIG_FPU_GRFPC 1
257 #elif defined CONFIG_FPU_GRFPC2
258 #define CONFIG_FPU_GRFPC 2
259 #else
260 #define CONFIG_FPU_GRFPC 0
261 #endif
262
263 #if defined CONFIG_FPU_GRFPU_INFMUL
264 #define CONFIG_FPU_GRFPU_MUL 0
265 #elif defined CONFIG_FPU_GRFPU_DWMUL
266 #define CONFIG_FPU_GRFPU_MUL 1
267 #elif defined CONFIG_FPU_GRFPU_MODGEN
268 #define CONFIG_FPU_GRFPU_MUL 2
269 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
270 #define CONFIG_FPU_GRFPU_MUL 3
271 #else
272 #define CONFIG_FPU_GRFPU_MUL 0
273 #endif
274
275 #if defined CONFIG_FPU_GRFPU_SH
276 #define CONFIG_FPU_GRFPU_SHARED 1
277 #else
278 #define CONFIG_FPU_GRFPU_SHARED 0
279 #endif
280
281 #if defined CONFIG_FPU_GRFPU
282 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
283 #elif defined CONFIG_FPU_MEIKO
284 #define CONFIG_FPU 15
285 #elif defined CONFIG_FPU_GRFPULITE
286 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
287 #else
288 #define CONFIG_FPU 0
289 #endif
290
291 #ifndef CONFIG_FPU_NETLIST
292 #define CONFIG_FPU_NETLIST 0
293 #endif
294
295 #ifndef CONFIG_ICACHE_ENABLE
296 #define CONFIG_ICACHE_ENABLE 0
297 #endif
298
299 #if defined CONFIG_ICACHE_ASSO1
300 #define CFG_IU_ISETS 1
301 #elif defined CONFIG_ICACHE_ASSO2
302 #define CFG_IU_ISETS 2
303 #elif defined CONFIG_ICACHE_ASSO3
304 #define CFG_IU_ISETS 3
305 #elif defined CONFIG_ICACHE_ASSO4
306 #define CFG_IU_ISETS 4
307 #else
308 #define CFG_IU_ISETS 1
309 #endif
310
311 #if defined CONFIG_ICACHE_SZ1
312 #define CFG_ICACHE_SZ 1
313 #elif defined CONFIG_ICACHE_SZ2
314 #define CFG_ICACHE_SZ 2
315 #elif defined CONFIG_ICACHE_SZ4
316 #define CFG_ICACHE_SZ 4
317 #elif defined CONFIG_ICACHE_SZ8
318 #define CFG_ICACHE_SZ 8
319 #elif defined CONFIG_ICACHE_SZ16
320 #define CFG_ICACHE_SZ 16
321 #elif defined CONFIG_ICACHE_SZ32
322 #define CFG_ICACHE_SZ 32
323 #elif defined CONFIG_ICACHE_SZ64
324 #define CFG_ICACHE_SZ 64
325 #elif defined CONFIG_ICACHE_SZ128
326 #define CFG_ICACHE_SZ 128
327 #elif defined CONFIG_ICACHE_SZ256
328 #define CFG_ICACHE_SZ 256
329 #else
330 #define CFG_ICACHE_SZ 1
331 #endif
332
333 #ifdef CONFIG_ICACHE_LZ16
334 #define CFG_ILINE_SZ 4
335 #else
336 #define CFG_ILINE_SZ 8
337 #endif
338
339 #if defined CONFIG_ICACHE_ALGODIR
340 #define CFG_ICACHE_ALGORND 3
341 #elif defined CONFIG_ICACHE_ALGORND
342 #define CFG_ICACHE_ALGORND 2
343 #elif defined CONFIG_ICACHE_ALGOLRR
344 #define CFG_ICACHE_ALGORND 1
345 #else
346 #define CFG_ICACHE_ALGORND 0
347 #endif
348
349 #ifndef CONFIG_ICACHE_LOCK
350 #define CONFIG_ICACHE_LOCK 0
351 #endif
352
353 #ifndef CONFIG_ICACHE_LRAM
354 #define CONFIG_ICACHE_LRAM 0
355 #endif
356
357 #ifndef CONFIG_ICACHE_LRSTART
358 #define CONFIG_ICACHE_LRSTART 8E
359 #endif
360
361 #if defined CONFIG_ICACHE_LRAM_SZ2
362 #define CFG_ILRAM_SIZE 2
363 #elif defined CONFIG_ICACHE_LRAM_SZ4
364 #define CFG_ILRAM_SIZE 4
365 #elif defined CONFIG_ICACHE_LRAM_SZ8
366 #define CFG_ILRAM_SIZE 8
367 #elif defined CONFIG_ICACHE_LRAM_SZ16
368 #define CFG_ILRAM_SIZE 16
369 #elif defined CONFIG_ICACHE_LRAM_SZ32
370 #define CFG_ILRAM_SIZE 32
371 #elif defined CONFIG_ICACHE_LRAM_SZ64
372 #define CFG_ILRAM_SIZE 64
373 #elif defined CONFIG_ICACHE_LRAM_SZ128
374 #define CFG_ILRAM_SIZE 128
375 #elif defined CONFIG_ICACHE_LRAM_SZ256
376 #define CFG_ILRAM_SIZE 256
377 #else
378 #define CFG_ILRAM_SIZE 1
379 #endif
380
381
382 #ifndef CONFIG_DCACHE_ENABLE
383 #define CONFIG_DCACHE_ENABLE 0
384 #endif
385
386 #if defined CONFIG_DCACHE_ASSO1
387 #define CFG_IU_DSETS 1
388 #elif defined CONFIG_DCACHE_ASSO2
389 #define CFG_IU_DSETS 2
390 #elif defined CONFIG_DCACHE_ASSO3
391 #define CFG_IU_DSETS 3
392 #elif defined CONFIG_DCACHE_ASSO4
393 #define CFG_IU_DSETS 4
394 #else
395 #define CFG_IU_DSETS 1
396 #endif
397
398 #if defined CONFIG_DCACHE_SZ1
399 #define CFG_DCACHE_SZ 1
400 #elif defined CONFIG_DCACHE_SZ2
401 #define CFG_DCACHE_SZ 2
402 #elif defined CONFIG_DCACHE_SZ4
403 #define CFG_DCACHE_SZ 4
404 #elif defined CONFIG_DCACHE_SZ8
405 #define CFG_DCACHE_SZ 8
406 #elif defined CONFIG_DCACHE_SZ16
407 #define CFG_DCACHE_SZ 16
408 #elif defined CONFIG_DCACHE_SZ32
409 #define CFG_DCACHE_SZ 32
410 #elif defined CONFIG_DCACHE_SZ64
411 #define CFG_DCACHE_SZ 64
412 #elif defined CONFIG_DCACHE_SZ128
413 #define CFG_DCACHE_SZ 128
414 #elif defined CONFIG_DCACHE_SZ256
415 #define CFG_DCACHE_SZ 256
416 #else
417 #define CFG_DCACHE_SZ 1
418 #endif
419
420 #ifdef CONFIG_DCACHE_LZ16
421 #define CFG_DLINE_SZ 4
422 #else
423 #define CFG_DLINE_SZ 8
424 #endif
425
426 #if defined CONFIG_DCACHE_ALGODIR
427 #define CFG_DCACHE_ALGORND 3
428 #elif defined CONFIG_DCACHE_ALGORND
429 #define CFG_DCACHE_ALGORND 2
430 #elif defined CONFIG_DCACHE_ALGOLRR
431 #define CFG_DCACHE_ALGORND 1
432 #else
433 #define CFG_DCACHE_ALGORND 0
434 #endif
435
436 #ifndef CONFIG_DCACHE_LOCK
437 #define CONFIG_DCACHE_LOCK 0
438 #endif
439
440 #ifndef CONFIG_DCACHE_SNOOP
441 #define CONFIG_DCACHE_SNOOP 0
442 #endif
443
444 #ifndef CONFIG_DCACHE_SNOOP_FAST
445 #define CONFIG_DCACHE_SNOOP_FAST 0
446 #endif
447
448 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
449 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
450 #endif
451
452 #ifndef CONFIG_CACHE_FIXED
453 #define CONFIG_CACHE_FIXED 0
454 #endif
455
456 #ifndef CONFIG_DCACHE_LRAM
457 #define CONFIG_DCACHE_LRAM 0
458 #endif
459
460 #ifndef CONFIG_DCACHE_LRSTART
461 #define CONFIG_DCACHE_LRSTART 8F
462 #endif
463
464 #if defined CONFIG_DCACHE_LRAM_SZ2
465 #define CFG_DLRAM_SIZE 2
466 #elif defined CONFIG_DCACHE_LRAM_SZ4
467 #define CFG_DLRAM_SIZE 4
468 #elif defined CONFIG_DCACHE_LRAM_SZ8
469 #define CFG_DLRAM_SIZE 8
470 #elif defined CONFIG_DCACHE_LRAM_SZ16
471 #define CFG_DLRAM_SIZE 16
472 #elif defined CONFIG_DCACHE_LRAM_SZ32
473 #define CFG_DLRAM_SIZE 32
474 #elif defined CONFIG_DCACHE_LRAM_SZ64
475 #define CFG_DLRAM_SIZE 64
476 #elif defined CONFIG_DCACHE_LRAM_SZ128
477 #define CFG_DLRAM_SIZE 128
478 #elif defined CONFIG_DCACHE_LRAM_SZ256
479 #define CFG_DLRAM_SIZE 256
480 #else
481 #define CFG_DLRAM_SIZE 1
482 #endif
483
484 #if defined CONFIG_MMU_PAGE_4K
485 #define CONFIG_MMU_PAGE 0
486 #elif defined CONFIG_MMU_PAGE_8K
487 #define CONFIG_MMU_PAGE 1
488 #elif defined CONFIG_MMU_PAGE_16K
489 #define CONFIG_MMU_PAGE 2
490 #elif defined CONFIG_MMU_PAGE_32K
491 #define CONFIG_MMU_PAGE 3
492 #elif defined CONFIG_MMU_PAGE_PROG
493 #define CONFIG_MMU_PAGE 4
494 #else
495 #define CONFIG_MMU_PAGE 0
496 #endif
497
498 #ifdef CONFIG_MMU_ENABLE
499 #define CONFIG_MMUEN 1
500
501 #ifdef CONFIG_MMU_SPLIT
502 #define CONFIG_TLB_TYPE 0
503 #endif
504 #ifdef CONFIG_MMU_COMBINED
505 #define CONFIG_TLB_TYPE 1
506 #endif
507
508 #ifdef CONFIG_MMU_REPARRAY
509 #define CONFIG_TLB_REP 0
510 #endif
511 #ifdef CONFIG_MMU_REPINCREMENT
512 #define CONFIG_TLB_REP 1
513 #endif
514
515 #ifdef CONFIG_MMU_I2
516 #define CONFIG_ITLBNUM 2
517 #endif
518 #ifdef CONFIG_MMU_I4
519 #define CONFIG_ITLBNUM 4
520 #endif
521 #ifdef CONFIG_MMU_I8
522 #define CONFIG_ITLBNUM 8
523 #endif
524 #ifdef CONFIG_MMU_I16
525 #define CONFIG_ITLBNUM 16
526 #endif
527 #ifdef CONFIG_MMU_I32
528 #define CONFIG_ITLBNUM 32
529 #endif
530
531 #define CONFIG_DTLBNUM 2
532 #ifdef CONFIG_MMU_D2
533 #undef CONFIG_DTLBNUM
534 #define CONFIG_DTLBNUM 2
535 #endif
536 #ifdef CONFIG_MMU_D4
537 #undef CONFIG_DTLBNUM
538 #define CONFIG_DTLBNUM 4
539 #endif
540 #ifdef CONFIG_MMU_D8
541 #undef CONFIG_DTLBNUM
542 #define CONFIG_DTLBNUM 8
543 #endif
544 #ifdef CONFIG_MMU_D16
545 #undef CONFIG_DTLBNUM
546 #define CONFIG_DTLBNUM 16
547 #endif
548 #ifdef CONFIG_MMU_D32
549 #undef CONFIG_DTLBNUM
550 #define CONFIG_DTLBNUM 32
551 #endif
552 #ifdef CONFIG_MMU_FASTWB
553 #define CFG_MMU_FASTWB 1
554 #else
555 #define CFG_MMU_FASTWB 0
556 #endif
557
558 #else
559 #define CONFIG_MMUEN 0
560 #define CONFIG_ITLBNUM 2
561 #define CONFIG_DTLBNUM 2
562 #define CONFIG_TLB_TYPE 1
563 #define CONFIG_TLB_REP 1
564 #define CFG_MMU_FASTWB 0
565 #endif
566
567 #ifndef CONFIG_DSU_ENABLE
568 #define CONFIG_DSU_ENABLE 0
569 #endif
570
571 #if defined CONFIG_DSU_ITRACESZ1
572 #define CFG_DSU_ITB 1
573 #elif CONFIG_DSU_ITRACESZ2
574 #define CFG_DSU_ITB 2
575 #elif CONFIG_DSU_ITRACESZ4
576 #define CFG_DSU_ITB 4
577 #elif CONFIG_DSU_ITRACESZ8
578 #define CFG_DSU_ITB 8
579 #elif CONFIG_DSU_ITRACESZ16
580 #define CFG_DSU_ITB 16
581 #else
582 #define CFG_DSU_ITB 0
583 #endif
584
585 #if defined CONFIG_DSU_ATRACESZ1
586 #define CFG_DSU_ATB 1
587 #elif CONFIG_DSU_ATRACESZ2
588 #define CFG_DSU_ATB 2
589 #elif CONFIG_DSU_ATRACESZ4
590 #define CFG_DSU_ATB 4
591 #elif CONFIG_DSU_ATRACESZ8
592 #define CFG_DSU_ATB 8
593 #elif CONFIG_DSU_ATRACESZ16
594 #define CFG_DSU_ATB 16
595 #else
596 #define CFG_DSU_ATB 0
597 #endif
598
599 #ifndef CONFIG_LEON3FT_EN
600 #define CONFIG_LEON3FT_EN 0
601 #endif
602
603 #if defined CONFIG_IUFT_PAR
604 #define CONFIG_IUFT_EN 1
605 #elif defined CONFIG_IUFT_DMR
606 #define CONFIG_IUFT_EN 2
607 #elif defined CONFIG_IUFT_BCH
608 #define CONFIG_IUFT_EN 3
609 #elif defined CONFIG_IUFT_TMR
610 #define CONFIG_IUFT_EN 4
611 #else
612 #define CONFIG_IUFT_EN 0
613 #endif
614 #ifndef CONFIG_RF_ERRINJ
615 #define CONFIG_RF_ERRINJ 0
616 #endif
617
618 #ifndef CONFIG_FPUFT_EN
619 #define CONFIG_FPUFT 0
620 #else
621 #ifdef CONFIG_FPU_GRFPU
622 #define CONFIG_FPUFT 2
623 #else
624 #define CONFIG_FPUFT 1
625 #endif
626 #endif
627
628 #ifndef CONFIG_CACHE_FT_EN
629 #define CONFIG_CACHE_FT_EN 0
630 #endif
631 #ifndef CONFIG_CACHE_ERRINJ
632 #define CONFIG_CACHE_ERRINJ 0
633 #endif
634
635 #ifndef CONFIG_LEON3_NETLIST
636 #define CONFIG_LEON3_NETLIST 0
637 #endif
638
639 #ifdef CONFIG_DEBUG_PC32
640 #define CFG_DEBUG_PC32 0
641 #else
642 #define CFG_DEBUG_PC32 2
643 #endif
644 #ifndef CONFIG_IU_DISAS
645 #define CONFIG_IU_DISAS 0
646 #endif
647 #ifndef CONFIG_IU_DISAS_NET
648 #define CONFIG_IU_DISAS_NET 0
649 #endif
650
651
652 #ifndef CONFIG_AHB_SPLIT
653 #define CONFIG_AHB_SPLIT 0
654 #endif
655
656 #ifndef CONFIG_AHB_RROBIN
657 #define CONFIG_AHB_RROBIN 0
658 #endif
659
660 #ifndef CONFIG_AHB_IOADDR
661 #define CONFIG_AHB_IOADDR FFF
662 #endif
663
664 #ifndef CONFIG_APB_HADDR
665 #define CONFIG_APB_HADDR 800
666 #endif
667
668 #ifndef CONFIG_AHB_MON
669 #define CONFIG_AHB_MON 0
670 #endif
671
672 #ifndef CONFIG_AHB_MONERR
673 #define CONFIG_AHB_MONERR 0
674 #endif
675
676 #ifndef CONFIG_AHB_MONWAR
677 #define CONFIG_AHB_MONWAR 0
678 #endif
679
680 #ifndef CONFIG_AHB_DTRACE
681 #define CONFIG_AHB_DTRACE 0
682 #endif
683
684 #ifndef CONFIG_DSU_JTAG
685 #define CONFIG_DSU_JTAG 0
686 #endif
687
688 #ifndef CONFIG_DSU_ETH
689 #define CONFIG_DSU_ETH 0
690 #endif
691
692 #ifndef CONFIG_DSU_IPMSB
693 #define CONFIG_DSU_IPMSB C0A8
694 #endif
695
696 #ifndef CONFIG_DSU_IPLSB
697 #define CONFIG_DSU_IPLSB 0033
698 #endif
699
700 #ifndef CONFIG_DSU_ETHMSB
701 #define CONFIG_DSU_ETHMSB 020000
702 #endif
703
704 #ifndef CONFIG_DSU_ETHLSB
705 #define CONFIG_DSU_ETHLSB 000009
706 #endif
707
708 #if defined CONFIG_DSU_ETHSZ1
709 #define CFG_DSU_ETHB 1
710 #elif CONFIG_DSU_ETHSZ2
711 #define CFG_DSU_ETHB 2
712 #elif CONFIG_DSU_ETHSZ4
713 #define CFG_DSU_ETHB 4
714 #elif CONFIG_DSU_ETHSZ8
715 #define CFG_DSU_ETHB 8
716 #elif CONFIG_DSU_ETHSZ16
717 #define CFG_DSU_ETHB 16
718 #elif CONFIG_DSU_ETHSZ32
719 #define CFG_DSU_ETHB 32
720 #else
721 #define CFG_DSU_ETHB 1
722 #endif
723
724 #ifndef CONFIG_DSU_ETH_PROG
725 #define CONFIG_DSU_ETH_PROG 0
726 #endif
727
728 #ifndef CONFIG_DSU_ETH_DIS
729 #define CONFIG_DSU_ETH_DIS 0
730 #endif
731
732 #ifndef CONFIG_MCTRL_LEON2
733 #define CONFIG_MCTRL_LEON2 0
734 #endif
735
736 #ifndef CONFIG_MCTRL_SDRAM
737 #define CONFIG_MCTRL_SDRAM 0
738 #endif
739
740 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
741 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
742 #endif
743
744 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
745 #define CONFIG_MCTRL_SDRAM_INVCLK 0
746 #endif
747
748 #ifndef CONFIG_MCTRL_SDRAM_BUS64
749 #define CONFIG_MCTRL_SDRAM_BUS64 0
750 #endif
751
752 #ifndef CONFIG_MCTRL_8BIT
753 #define CONFIG_MCTRL_8BIT 0
754 #endif
755
756 #ifndef CONFIG_MCTRL_16BIT
757 #define CONFIG_MCTRL_16BIT 0
758 #endif
759
760 #ifndef CONFIG_MCTRL_5CS
761 #define CONFIG_MCTRL_5CS 0
762 #endif
763
764 #ifndef CONFIG_MCTRL_EDAC
765 #define CONFIG_MCTRL_EDAC 0
766 #endif
767
768 #ifndef CONFIG_MCTRL_PAGE
769 #define CONFIG_MCTRL_PAGE 0
770 #endif
771
772 #ifndef CONFIG_MCTRL_PROGPAGE
773 #define CONFIG_MCTRL_PROGPAGE 0
774 #endif
775
776
777 #ifndef CONFIG_MIG_DDR2
778 #define CONFIG_MIG_DDR2 0
779 #endif
780
781 #ifndef CONFIG_MIG_RANKS
782 #define CONFIG_MIG_RANKS 1
783 #endif
784
785 #ifndef CONFIG_MIG_COLBITS
786 #define CONFIG_MIG_COLBITS 10
787 #endif
788
789 #ifndef CONFIG_MIG_ROWBITS
790 #define CONFIG_MIG_ROWBITS 13
791 #endif
792
793 #ifndef CONFIG_MIG_BANKBITS
794 #define CONFIG_MIG_BANKBITS 2
795 #endif
796
797 #ifndef CONFIG_MIG_HMASK
798 #define CONFIG_MIG_HMASK F00
799 #endif
800 #ifndef CONFIG_AHBSTAT_ENABLE
801 #define CONFIG_AHBSTAT_ENABLE 0
802 #endif
803
804 #ifndef CONFIG_AHBSTAT_NFTSLV
805 #define CONFIG_AHBSTAT_NFTSLV 1
806 #endif
807
808 #ifndef CONFIG_AHBROM_ENABLE
809 #define CONFIG_AHBROM_ENABLE 0
810 #endif
811
812 #ifndef CONFIG_AHBROM_START
813 #define CONFIG_AHBROM_START 000
814 #endif
815
816 #ifndef CONFIG_AHBROM_PIPE
817 #define CONFIG_AHBROM_PIPE 0
818 #endif
819
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
821 #define CONFIG_ROM_START 100
822 #else
823 #define CONFIG_ROM_START 000
824 #endif
825
826
827 #ifndef CONFIG_AHBRAM_ENABLE
828 #define CONFIG_AHBRAM_ENABLE 0
829 #endif
830
831 #ifndef CONFIG_AHBRAM_START
832 #define CONFIG_AHBRAM_START A00
833 #endif
834
835 #if defined CONFIG_AHBRAM_SZ1
836 #define CFG_AHBRAMSZ 1
837 #elif CONFIG_AHBRAM_SZ2
838 #define CFG_AHBRAMSZ 2
839 #elif CONFIG_AHBRAM_SZ4
840 #define CFG_AHBRAMSZ 4
841 #elif CONFIG_AHBRAM_SZ8
842 #define CFG_AHBRAMSZ 8
843 #elif CONFIG_AHBRAM_SZ16
844 #define CFG_AHBRAMSZ 16
845 #elif CONFIG_AHBRAM_SZ32
846 #define CFG_AHBRAMSZ 32
847 #elif CONFIG_AHBRAM_SZ64
848 #define CFG_AHBRAMSZ 64
849 #else
850 #define CFG_AHBRAMSZ 1
851 #endif
852
853 #ifndef CONFIG_GRETH_ENABLE
854 #define CONFIG_GRETH_ENABLE 0
855 #endif
856
857 #ifndef CONFIG_GRETH_GIGA
858 #define CONFIG_GRETH_GIGA 0
859 #endif
860
861 #if defined CONFIG_GRETH_FIFO4
862 #define CFG_GRETH_FIFO 4
863 #elif defined CONFIG_GRETH_FIFO8
864 #define CFG_GRETH_FIFO 8
865 #elif defined CONFIG_GRETH_FIFO16
866 #define CFG_GRETH_FIFO 16
867 #elif defined CONFIG_GRETH_FIFO32
868 #define CFG_GRETH_FIFO 32
869 #elif defined CONFIG_GRETH_FIFO64
870 #define CFG_GRETH_FIFO 64
871 #else
872 #define CFG_GRETH_FIFO 8
873 #endif
874
875 #ifndef CONFIG_UART1_ENABLE
876 #define CONFIG_UART1_ENABLE 0
877 #endif
878
879 #if defined CONFIG_UA1_FIFO1
880 #define CFG_UA1_FIFO 1
881 #elif defined CONFIG_UA1_FIFO2
882 #define CFG_UA1_FIFO 2
883 #elif defined CONFIG_UA1_FIFO4
884 #define CFG_UA1_FIFO 4
885 #elif defined CONFIG_UA1_FIFO8
886 #define CFG_UA1_FIFO 8
887 #elif defined CONFIG_UA1_FIFO16
888 #define CFG_UA1_FIFO 16
889 #elif defined CONFIG_UA1_FIFO32
890 #define CFG_UA1_FIFO 32
891 #else
892 #define CFG_UA1_FIFO 1
893 #endif
894
895 #ifndef CONFIG_IRQ3_ENABLE
896 #define CONFIG_IRQ3_ENABLE 0
897 #endif
898 #ifndef CONFIG_IRQ3_NSEC
899 #define CONFIG_IRQ3_NSEC 0
900 #endif
901 #ifndef CONFIG_GPT_ENABLE
902 #define CONFIG_GPT_ENABLE 0
903 #endif
904
905 #ifndef CONFIG_GPT_NTIM
906 #define CONFIG_GPT_NTIM 1
907 #endif
908
909 #ifndef CONFIG_GPT_SW
910 #define CONFIG_GPT_SW 8
911 #endif
912
913 #ifndef CONFIG_GPT_TW
914 #define CONFIG_GPT_TW 8
915 #endif
916
917 #ifndef CONFIG_GPT_IRQ
918 #define CONFIG_GPT_IRQ 8
919 #endif
920
921 #ifndef CONFIG_GPT_SEPIRQ
922 #define CONFIG_GPT_SEPIRQ 0
923 #endif
924 #ifndef CONFIG_GPT_ENABLE
925 #define CONFIG_GPT_ENABLE 0
926 #endif
927
928 #ifndef CONFIG_GPT_NTIM
929 #define CONFIG_GPT_NTIM 1
930 #endif
931
932 #ifndef CONFIG_GPT_SW
933 #define CONFIG_GPT_SW 8
934 #endif
935
936 #ifndef CONFIG_GPT_TW
937 #define CONFIG_GPT_TW 8
938 #endif
939
940 #ifndef CONFIG_GPT_IRQ
941 #define CONFIG_GPT_IRQ 8
942 #endif
943
944 #ifndef CONFIG_GPT_SEPIRQ
945 #define CONFIG_GPT_SEPIRQ 0
946 #endif
947
948 #ifndef CONFIG_GPT_WDOGEN
949 #define CONFIG_GPT_WDOGEN 0
950 #endif
951
952 #ifndef CONFIG_GPT_WDOG
953 #define CONFIG_GPT_WDOG 0
954 #endif
955
956 #ifndef CONFIG_GRGPIO_ENABLE
957 #define CONFIG_GRGPIO_ENABLE 0
958 #endif
959 #ifndef CONFIG_GRGPIO_IMASK
960 #define CONFIG_GRGPIO_IMASK 0000
961 #endif
962 #ifndef CONFIG_GRGPIO_WIDTH
963 #define CONFIG_GRGPIO_WIDTH 1
964 #endif
965
966 #ifndef CONFIG_VGA_ENABLE
967 #define CONFIG_VGA_ENABLE 0
968 #endif
969 #ifndef CONFIG_SVGA_ENABLE
970 #define CONFIG_SVGA_ENABLE 0
971 #endif
972 #ifndef CONFIG_KBD_ENABLE
973 #define CONFIG_KBD_ENABLE 0
974 #endif
975
976
977 #ifndef CONFIG_SPIMCTRL
978 #define CONFIG_SPIMCTRL 0
979 #endif
980
981 #ifndef CONFIG_SPIMCTRL_SDCARD
982 #define CONFIG_SPIMCTRL_SDCARD 0
983 #endif
984
985 #ifndef CONFIG_SPIMCTRL_READCMD
986 #define CONFIG_SPIMCTRL_READCMD 0
987 #endif
988
989 #ifndef CONFIG_SPIMCTRL_DUMMYBYTE
990 #define CONFIG_SPIMCTRL_DUMMYBYTE 0
991 #endif
992
993 #ifndef CONFIG_SPIMCTRL_DUALOUTPUT
994 #define CONFIG_SPIMCTRL_DUALOUTPUT 0
995 #endif
996
997 #ifndef CONFIG_SPIMCTRL_SCALER
998 #define CONFIG_SPIMCTRL_SCALER 1
999 #endif
1000
1001 #ifndef CONFIG_SPIMCTRL_ASCALER
1002 #define CONFIG_SPIMCTRL_ASCALER 1
1003 #endif
1004
1005 #ifndef CONFIG_SPIMCTRL_PWRUPCNT
1006 #define CONFIG_SPIMCTRL_PWRUPCNT 0
1007 #endif
1008 #ifndef CONFIG_SPICTRL_ENABLE
1009 #define CONFIG_SPICTRL_ENABLE 0
1010 #endif
1011 #ifndef CONFIG_SPICTRL_NUM
1012 #define CONFIG_SPICTRL_NUM 1
1013 #endif
1014 #ifndef CONFIG_SPICTRL_SLVS
1015 #define CONFIG_SPICTRL_SLVS 1
1016 #endif
1017 #ifndef CONFIG_SPICTRL_FIFO
1018 #define CONFIG_SPICTRL_FIFO 1
1019 #endif
1020 #ifndef CONFIG_SPICTRL_SLVREG
1021 #define CONFIG_SPICTRL_SLVREG 0
1022 #endif
1023 #ifndef CONFIG_SPICTRL_ODMODE
1024 #define CONFIG_SPICTRL_ODMODE 0
1025 #endif
1026 #ifndef CONFIG_SPICTRL_AM
1027 #define CONFIG_SPICTRL_AM 0
1028 #endif
1029 #ifndef CONFIG_SPICTRL_ASEL
1030 #define CONFIG_SPICTRL_ASEL 0
1031 #endif
1032 #ifndef CONFIG_SPICTRL_TWEN
1033 #define CONFIG_SPICTRL_TWEN 0
1034 #endif
1035 #ifndef CONFIG_SPICTRL_MAXWLEN
1036 #define CONFIG_SPICTRL_MAXWLEN 0
1037 #endif
1038 #ifndef CONFIG_SPICTRL_SYNCRAM
1039 #define CONFIG_SPICTRL_SYNCRAM 0
1040 #endif
1041 #if defined(CONFIG_SPICTRL_DMRFT)
1042 #define CONFIG_SPICTRL_FT 1
1043 #elif defined(CONFIG_SPICTRL_TMRFT)
1044 #define CONFIG_SPICTRL_FT 2
1045 #else
1046 #define CONFIG_SPICTRL_FT 0
1047 #endif
1048
1049 #ifndef CONFIG_DEBUG_UART
1050 #define CONFIG_DEBUG_UART 0
1051 #endif
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_AXDSP
14 #define CONFIG_SYN_TECH axdsp
15 #elif defined CONFIG_SYN_PROASICPLUS
16 #define CONFIG_SYN_TECH proasic
17 #elif defined CONFIG_SYN_ALTERA
18 #define CONFIG_SYN_TECH altera
19 #elif defined CONFIG_SYN_STRATIX
20 #define CONFIG_SYN_TECH stratix1
21 #elif defined CONFIG_SYN_STRATIXII
22 #define CONFIG_SYN_TECH stratix2
23 #elif defined CONFIG_SYN_STRATIXIII
24 #define CONFIG_SYN_TECH stratix3
25 #elif defined CONFIG_SYN_CYCLONEIII
26 #define CONFIG_SYN_TECH cyclone3
27 #elif defined CONFIG_SYN_EASIC45
28 #define CONFIG_SYN_TECH easic45
29 #elif defined CONFIG_SYN_EASIC90
30 #define CONFIG_SYN_TECH easic90
31 #elif defined CONFIG_SYN_IHP25
32 #define CONFIG_SYN_TECH ihp25
33 #elif defined CONFIG_SYN_IHP25RH
34 #define CONFIG_SYN_TECH ihp25rh
35 #elif defined CONFIG_SYN_CMOS9SF
36 #define CONFIG_SYN_TECH cmos9sf
37 #elif defined CONFIG_SYN_LATTICE
38 #define CONFIG_SYN_TECH lattice
39 #elif defined CONFIG_SYN_ECLIPSE
40 #define CONFIG_SYN_TECH eclipse
41 #elif defined CONFIG_SYN_PEREGRINE
42 #define CONFIG_SYN_TECH peregrine
43 #elif defined CONFIG_SYN_PROASIC
44 #define CONFIG_SYN_TECH proasic
45 #elif defined CONFIG_SYN_PROASIC3
46 #define CONFIG_SYN_TECH apa3
47 #elif defined CONFIG_SYN_PROASIC3E
48 #define CONFIG_SYN_TECH apa3e
49 #elif defined CONFIG_SYN_PROASIC3L
50 #define CONFIG_SYN_TECH apa3l
51 #elif defined CONFIG_SYN_IGLOO
52 #define CONFIG_SYN_TECH apa3
53 #elif defined CONFIG_SYN_FUSION
54 #define CONFIG_SYN_TECH actfus
55 #elif defined CONFIG_SYN_SPARTAN2
56 #define CONFIG_SYN_TECH virtex
57 #elif defined CONFIG_SYN_VIRTEX
58 #define CONFIG_SYN_TECH virtex
59 #elif defined CONFIG_SYN_VIRTEXE
60 #define CONFIG_SYN_TECH virtex
61 #elif defined CONFIG_SYN_SPARTAN3
62 #define CONFIG_SYN_TECH spartan3
63 #elif defined CONFIG_SYN_SPARTAN3E
64 #define CONFIG_SYN_TECH spartan3e
65 #elif defined CONFIG_SYN_SPARTAN6
66 #define CONFIG_SYN_TECH spartan6
67 #elif defined CONFIG_SYN_VIRTEX2
68 #define CONFIG_SYN_TECH virtex2
69 #elif defined CONFIG_SYN_VIRTEX4
70 #define CONFIG_SYN_TECH virtex4
71 #elif defined CONFIG_SYN_VIRTEX5
72 #define CONFIG_SYN_TECH virtex5
73 #elif defined CONFIG_SYN_VIRTEX6
74 #define CONFIG_SYN_TECH virtex6
75 #elif defined CONFIG_SYN_RH_LIB18T
76 #define CONFIG_SYN_TECH rhlib18t
77 #elif defined CONFIG_SYN_SMIC13
78 #define CONFIG_SYN_TECH smic013
79 #elif defined CONFIG_SYN_UT025CRH
80 #define CONFIG_SYN_TECH ut25
81 #elif defined CONFIG_SYN_UT130HBD
82 #define CONFIG_SYN_TECH ut130
83 #elif defined CONFIG_SYN_UT90NHBD
84 #define CONFIG_SYN_TECH ut90
85 #elif defined CONFIG_SYN_TSMC90
86 #define CONFIG_SYN_TECH tsmc90
87 #elif defined CONFIG_SYN_TM65GPLUS
88 #define CONFIG_SYN_TECH tm65gpl
89 #elif defined CONFIG_SYN_CUSTOM1
90 #define CONFIG_SYN_TECH custom1
91 #else
92 #error "unknown target technology"
93 #endif
94
95 #if defined CONFIG_SYN_INFER_RAM
96 #define CFG_RAM_TECH inferred
97 #elif defined CONFIG_MEM_UMC
98 #define CFG_RAM_TECH umc
99 #elif defined CONFIG_MEM_RHUMC
100 #define CFG_RAM_TECH rhumc
101 #elif defined CONFIG_MEM_VIRAGE
102 #define CFG_RAM_TECH memvirage
103 #elif defined CONFIG_MEM_ARTISAN
104 #define CFG_RAM_TECH memartisan
105 #elif defined CONFIG_MEM_CUSTOM1
106 #define CFG_RAM_TECH custom1
107 #elif defined CONFIG_MEM_VIRAGE90
108 #define CFG_RAM_TECH memvirage90
109 #elif defined CONFIG_MEM_INFERRED
110 #define CFG_RAM_TECH inferred
111 #else
112 #define CFG_RAM_TECH CONFIG_SYN_TECH
113 #endif
114
115 #if defined CONFIG_SYN_INFER_PADS
116 #define CFG_PAD_TECH inferred
117 #else
118 #define CFG_PAD_TECH CONFIG_SYN_TECH
119 #endif
120
121 #ifndef CONFIG_SYN_NO_ASYNC
122 #define CONFIG_SYN_NO_ASYNC 0
123 #endif
124
125 #ifndef CONFIG_SYN_SCAN
126 #define CONFIG_SYN_SCAN 0
127 #endif
128
129
130 #if defined CONFIG_CLK_ALTDLL
131 #define CFG_CLK_TECH CONFIG_SYN_TECH
132 #elif defined CONFIG_CLK_HCLKBUF
133 #define CFG_CLK_TECH axcel
134 #elif defined CONFIG_CLK_LATDLL
135 #define CFG_CLK_TECH lattice
136 #elif defined CONFIG_CLK_PRO3PLL
137 #define CFG_CLK_TECH apa3
138 #elif defined CONFIG_CLK_PRO3EPLL
139 #define CFG_CLK_TECH apa3e
140 #elif defined CONFIG_CLK_PRO3LPLL
141 #define CFG_CLK_TECH apa3l
142 #elif defined CONFIG_CLK_FUSPLL
143 #define CFG_CLK_TECH actfus
144 #elif defined CONFIG_CLK_CLKDLL
145 #define CFG_CLK_TECH virtex
146 #elif defined CONFIG_CLK_DCM
147 #define CFG_CLK_TECH CONFIG_SYN_TECH
148 #elif defined CONFIG_CLK_LIB18T
149 #define CFG_CLK_TECH rhlib18t
150 #elif defined CONFIG_CLK_RHUMC
151 #define CFG_CLK_TECH rhumc
152 #elif defined CONFIG_CLK_UT130HBD
153 #define CFG_CLK_TECH ut130
154 #else
155 #define CFG_CLK_TECH inferred
156 #endif
157
158 #ifndef CONFIG_CLK_MUL
159 #define CONFIG_CLK_MUL 2
160 #endif
161
162 #ifndef CONFIG_CLK_DIV
163 #define CONFIG_CLK_DIV 2
164 #endif
165
166 #ifndef CONFIG_OCLK_DIV
167 #define CONFIG_OCLK_DIV 1
168 #endif
169
170 #ifndef CONFIG_OCLKB_DIV
171 #define CONFIG_OCLKB_DIV 0
172 #endif
173
174 #ifndef CONFIG_OCLKC_DIV
175 #define CONFIG_OCLKC_DIV 0
176 #endif
177
178 #ifndef CONFIG_PCI_CLKDLL
179 #define CONFIG_PCI_CLKDLL 0
180 #endif
181
182 #ifndef CONFIG_PCI_SYSCLK
183 #define CONFIG_PCI_SYSCLK 0
184 #endif
185
186 #ifndef CONFIG_CLK_NOFB
187 #define CONFIG_CLK_NOFB 0
188 #endif
189 #ifndef CONFIG_LEON3
190 #define CONFIG_LEON3 0
191 #endif
192
193 #ifndef CONFIG_PROC_NUM
194 #define CONFIG_PROC_NUM 1
195 #endif
196
197 #ifndef CONFIG_IU_NWINDOWS
198 #define CONFIG_IU_NWINDOWS 8
199 #endif
200
201 #ifndef CONFIG_IU_RSTADDR
202 #define CONFIG_IU_RSTADDR 8
203 #endif
204
205 #ifndef CONFIG_IU_LDELAY
206 #define CONFIG_IU_LDELAY 1
207 #endif
208
209 #ifndef CONFIG_IU_WATCHPOINTS
210 #define CONFIG_IU_WATCHPOINTS 0
211 #endif
212
213 #ifdef CONFIG_IU_V8MULDIV
214 #ifdef CONFIG_IU_MUL_LATENCY_4
215 #define CFG_IU_V8 1
216 #elif defined CONFIG_IU_MUL_LATENCY_5
217 #define CFG_IU_V8 2
218 #elif defined CONFIG_IU_MUL_LATENCY_2
219 #define CFG_IU_V8 16#32#
220 #endif
221 #else
222 #define CFG_IU_V8 0
223 #endif
224
225 #ifdef CONFIG_IU_MUL_MODGEN
226 #define CFG_IU_MUL_STRUCT 1
227 #elif defined CONFIG_IU_MUL_TECHSPEC
228 #define CFG_IU_MUL_STRUCT 2
229 #elif defined CONFIG_IU_MUL_DW
230 #define CFG_IU_MUL_STRUCT 3
231 #else
232 #define CFG_IU_MUL_STRUCT 0
233 #endif
234
235 #ifndef CONFIG_PWD
236 #define CONFIG_PWD 0
237 #endif
238
239 #ifndef CONFIG_IU_MUL_MAC
240 #define CONFIG_IU_MUL_MAC 0
241 #endif
242
243 #ifndef CONFIG_IU_BP
244 #define CONFIG_IU_BP 0
245 #endif
246
247 #ifndef CONFIG_NOTAG
248 #define CONFIG_NOTAG 0
249 #endif
250
251 #ifndef CONFIG_IU_SVT
252 #define CONFIG_IU_SVT 0
253 #endif
254
255 #if defined CONFIG_FPU_GRFPC1
256 #define CONFIG_FPU_GRFPC 1
257 #elif defined CONFIG_FPU_GRFPC2
258 #define CONFIG_FPU_GRFPC 2
259 #else
260 #define CONFIG_FPU_GRFPC 0
261 #endif
262
263 #if defined CONFIG_FPU_GRFPU_INFMUL
264 #define CONFIG_FPU_GRFPU_MUL 0
265 #elif defined CONFIG_FPU_GRFPU_DWMUL
266 #define CONFIG_FPU_GRFPU_MUL 1
267 #elif defined CONFIG_FPU_GRFPU_MODGEN
268 #define CONFIG_FPU_GRFPU_MUL 2
269 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
270 #define CONFIG_FPU_GRFPU_MUL 3
271 #else
272 #define CONFIG_FPU_GRFPU_MUL 0
273 #endif
274
275 #if defined CONFIG_FPU_GRFPU_SH
276 #define CONFIG_FPU_GRFPU_SHARED 1
277 #else
278 #define CONFIG_FPU_GRFPU_SHARED 0
279 #endif
280
281 #if defined CONFIG_FPU_GRFPU
282 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
283 #elif defined CONFIG_FPU_MEIKO
284 #define CONFIG_FPU 15
285 #elif defined CONFIG_FPU_GRFPULITE
286 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
287 #else
288 #define CONFIG_FPU 0
289 #endif
290
291 #ifndef CONFIG_FPU_NETLIST
292 #define CONFIG_FPU_NETLIST 0
293 #endif
294
295 #ifndef CONFIG_ICACHE_ENABLE
296 #define CONFIG_ICACHE_ENABLE 0
297 #endif
298
299 #if defined CONFIG_ICACHE_ASSO1
300 #define CFG_IU_ISETS 1
301 #elif defined CONFIG_ICACHE_ASSO2
302 #define CFG_IU_ISETS 2
303 #elif defined CONFIG_ICACHE_ASSO3
304 #define CFG_IU_ISETS 3
305 #elif defined CONFIG_ICACHE_ASSO4
306 #define CFG_IU_ISETS 4
307 #else
308 #define CFG_IU_ISETS 1
309 #endif
310
311 #if defined CONFIG_ICACHE_SZ1
312 #define CFG_ICACHE_SZ 1
313 #elif defined CONFIG_ICACHE_SZ2
314 #define CFG_ICACHE_SZ 2
315 #elif defined CONFIG_ICACHE_SZ4
316 #define CFG_ICACHE_SZ 4
317 #elif defined CONFIG_ICACHE_SZ8
318 #define CFG_ICACHE_SZ 8
319 #elif defined CONFIG_ICACHE_SZ16
320 #define CFG_ICACHE_SZ 16
321 #elif defined CONFIG_ICACHE_SZ32
322 #define CFG_ICACHE_SZ 32
323 #elif defined CONFIG_ICACHE_SZ64
324 #define CFG_ICACHE_SZ 64
325 #elif defined CONFIG_ICACHE_SZ128
326 #define CFG_ICACHE_SZ 128
327 #elif defined CONFIG_ICACHE_SZ256
328 #define CFG_ICACHE_SZ 256
329 #else
330 #define CFG_ICACHE_SZ 1
331 #endif
332
333 #ifdef CONFIG_ICACHE_LZ16
334 #define CFG_ILINE_SZ 4
335 #else
336 #define CFG_ILINE_SZ 8
337 #endif
338
339 #if defined CONFIG_ICACHE_ALGODIR
340 #define CFG_ICACHE_ALGORND 3
341 #elif defined CONFIG_ICACHE_ALGORND
342 #define CFG_ICACHE_ALGORND 2
343 #elif defined CONFIG_ICACHE_ALGOLRR
344 #define CFG_ICACHE_ALGORND 1
345 #else
346 #define CFG_ICACHE_ALGORND 0
347 #endif
348
349 #ifndef CONFIG_ICACHE_LOCK
350 #define CONFIG_ICACHE_LOCK 0
351 #endif
352
353 #ifndef CONFIG_ICACHE_LRAM
354 #define CONFIG_ICACHE_LRAM 0
355 #endif
356
357 #ifndef CONFIG_ICACHE_LRSTART
358 #define CONFIG_ICACHE_LRSTART 8E
359 #endif
360
361 #if defined CONFIG_ICACHE_LRAM_SZ2
362 #define CFG_ILRAM_SIZE 2
363 #elif defined CONFIG_ICACHE_LRAM_SZ4
364 #define CFG_ILRAM_SIZE 4
365 #elif defined CONFIG_ICACHE_LRAM_SZ8
366 #define CFG_ILRAM_SIZE 8
367 #elif defined CONFIG_ICACHE_LRAM_SZ16
368 #define CFG_ILRAM_SIZE 16
369 #elif defined CONFIG_ICACHE_LRAM_SZ32
370 #define CFG_ILRAM_SIZE 32
371 #elif defined CONFIG_ICACHE_LRAM_SZ64
372 #define CFG_ILRAM_SIZE 64
373 #elif defined CONFIG_ICACHE_LRAM_SZ128
374 #define CFG_ILRAM_SIZE 128
375 #elif defined CONFIG_ICACHE_LRAM_SZ256
376 #define CFG_ILRAM_SIZE 256
377 #else
378 #define CFG_ILRAM_SIZE 1
379 #endif
380
381
382 #ifndef CONFIG_DCACHE_ENABLE
383 #define CONFIG_DCACHE_ENABLE 0
384 #endif
385
386 #if defined CONFIG_DCACHE_ASSO1
387 #define CFG_IU_DSETS 1
388 #elif defined CONFIG_DCACHE_ASSO2
389 #define CFG_IU_DSETS 2
390 #elif defined CONFIG_DCACHE_ASSO3
391 #define CFG_IU_DSETS 3
392 #elif defined CONFIG_DCACHE_ASSO4
393 #define CFG_IU_DSETS 4
394 #else
395 #define CFG_IU_DSETS 1
396 #endif
397
398 #if defined CONFIG_DCACHE_SZ1
399 #define CFG_DCACHE_SZ 1
400 #elif defined CONFIG_DCACHE_SZ2
401 #define CFG_DCACHE_SZ 2
402 #elif defined CONFIG_DCACHE_SZ4
403 #define CFG_DCACHE_SZ 4
404 #elif defined CONFIG_DCACHE_SZ8
405 #define CFG_DCACHE_SZ 8
406 #elif defined CONFIG_DCACHE_SZ16
407 #define CFG_DCACHE_SZ 16
408 #elif defined CONFIG_DCACHE_SZ32
409 #define CFG_DCACHE_SZ 32
410 #elif defined CONFIG_DCACHE_SZ64
411 #define CFG_DCACHE_SZ 64
412 #elif defined CONFIG_DCACHE_SZ128
413 #define CFG_DCACHE_SZ 128
414 #elif defined CONFIG_DCACHE_SZ256
415 #define CFG_DCACHE_SZ 256
416 #else
417 #define CFG_DCACHE_SZ 1
418 #endif
419
420 #ifdef CONFIG_DCACHE_LZ16
421 #define CFG_DLINE_SZ 4
422 #else
423 #define CFG_DLINE_SZ 8
424 #endif
425
426 #if defined CONFIG_DCACHE_ALGODIR
427 #define CFG_DCACHE_ALGORND 3
428 #elif defined CONFIG_DCACHE_ALGORND
429 #define CFG_DCACHE_ALGORND 2
430 #elif defined CONFIG_DCACHE_ALGOLRR
431 #define CFG_DCACHE_ALGORND 1
432 #else
433 #define CFG_DCACHE_ALGORND 0
434 #endif
435
436 #ifndef CONFIG_DCACHE_LOCK
437 #define CONFIG_DCACHE_LOCK 0
438 #endif
439
440 #ifndef CONFIG_DCACHE_SNOOP
441 #define CONFIG_DCACHE_SNOOP 0
442 #endif
443
444 #ifndef CONFIG_DCACHE_SNOOP_FAST
445 #define CONFIG_DCACHE_SNOOP_FAST 0
446 #endif
447
448 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
449 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
450 #endif
451
452 #ifndef CONFIG_CACHE_FIXED
453 #define CONFIG_CACHE_FIXED 0
454 #endif
455
456 #ifndef CONFIG_DCACHE_LRAM
457 #define CONFIG_DCACHE_LRAM 0
458 #endif
459
460 #ifndef CONFIG_DCACHE_LRSTART
461 #define CONFIG_DCACHE_LRSTART 8F
462 #endif
463
464 #if defined CONFIG_DCACHE_LRAM_SZ2
465 #define CFG_DLRAM_SIZE 2
466 #elif defined CONFIG_DCACHE_LRAM_SZ4
467 #define CFG_DLRAM_SIZE 4
468 #elif defined CONFIG_DCACHE_LRAM_SZ8
469 #define CFG_DLRAM_SIZE 8
470 #elif defined CONFIG_DCACHE_LRAM_SZ16
471 #define CFG_DLRAM_SIZE 16
472 #elif defined CONFIG_DCACHE_LRAM_SZ32
473 #define CFG_DLRAM_SIZE 32
474 #elif defined CONFIG_DCACHE_LRAM_SZ64
475 #define CFG_DLRAM_SIZE 64
476 #elif defined CONFIG_DCACHE_LRAM_SZ128
477 #define CFG_DLRAM_SIZE 128
478 #elif defined CONFIG_DCACHE_LRAM_SZ256
479 #define CFG_DLRAM_SIZE 256
480 #else
481 #define CFG_DLRAM_SIZE 1
482 #endif
483
484 #if defined CONFIG_MMU_PAGE_4K
485 #define CONFIG_MMU_PAGE 0
486 #elif defined CONFIG_MMU_PAGE_8K
487 #define CONFIG_MMU_PAGE 1
488 #elif defined CONFIG_MMU_PAGE_16K
489 #define CONFIG_MMU_PAGE 2
490 #elif defined CONFIG_MMU_PAGE_32K
491 #define CONFIG_MMU_PAGE 3
492 #elif defined CONFIG_MMU_PAGE_PROG
493 #define CONFIG_MMU_PAGE 4
494 #else
495 #define CONFIG_MMU_PAGE 0
496 #endif
497
498 #ifdef CONFIG_MMU_ENABLE
499 #define CONFIG_MMUEN 1
500
501 #ifdef CONFIG_MMU_SPLIT
502 #define CONFIG_TLB_TYPE 0
503 #endif
504 #ifdef CONFIG_MMU_COMBINED
505 #define CONFIG_TLB_TYPE 1
506 #endif
507
508 #ifdef CONFIG_MMU_REPARRAY
509 #define CONFIG_TLB_REP 0
510 #endif
511 #ifdef CONFIG_MMU_REPINCREMENT
512 #define CONFIG_TLB_REP 1
513 #endif
514
515 #ifdef CONFIG_MMU_I2
516 #define CONFIG_ITLBNUM 2
517 #endif
518 #ifdef CONFIG_MMU_I4
519 #define CONFIG_ITLBNUM 4
520 #endif
521 #ifdef CONFIG_MMU_I8
522 #define CONFIG_ITLBNUM 8
523 #endif
524 #ifdef CONFIG_MMU_I16
525 #define CONFIG_ITLBNUM 16
526 #endif
527 #ifdef CONFIG_MMU_I32
528 #define CONFIG_ITLBNUM 32
529 #endif
530
531 #define CONFIG_DTLBNUM 2
532 #ifdef CONFIG_MMU_D2
533 #undef CONFIG_DTLBNUM
534 #define CONFIG_DTLBNUM 2
535 #endif
536 #ifdef CONFIG_MMU_D4
537 #undef CONFIG_DTLBNUM
538 #define CONFIG_DTLBNUM 4
539 #endif
540 #ifdef CONFIG_MMU_D8
541 #undef CONFIG_DTLBNUM
542 #define CONFIG_DTLBNUM 8
543 #endif
544 #ifdef CONFIG_MMU_D16
545 #undef CONFIG_DTLBNUM
546 #define CONFIG_DTLBNUM 16
547 #endif
548 #ifdef CONFIG_MMU_D32
549 #undef CONFIG_DTLBNUM
550 #define CONFIG_DTLBNUM 32
551 #endif
552 #ifdef CONFIG_MMU_FASTWB
553 #define CFG_MMU_FASTWB 1
554 #else
555 #define CFG_MMU_FASTWB 0
556 #endif
557
558 #else
559 #define CONFIG_MMUEN 0
560 #define CONFIG_ITLBNUM 2
561 #define CONFIG_DTLBNUM 2
562 #define CONFIG_TLB_TYPE 1
563 #define CONFIG_TLB_REP 1
564 #define CFG_MMU_FASTWB 0
565 #endif
566
567 #ifndef CONFIG_DSU_ENABLE
568 #define CONFIG_DSU_ENABLE 0
569 #endif
570
571 #if defined CONFIG_DSU_ITRACESZ1
572 #define CFG_DSU_ITB 1
573 #elif CONFIG_DSU_ITRACESZ2
574 #define CFG_DSU_ITB 2
575 #elif CONFIG_DSU_ITRACESZ4
576 #define CFG_DSU_ITB 4
577 #elif CONFIG_DSU_ITRACESZ8
578 #define CFG_DSU_ITB 8
579 #elif CONFIG_DSU_ITRACESZ16
580 #define CFG_DSU_ITB 16
581 #else
582 #define CFG_DSU_ITB 0
583 #endif
584
585 #if defined CONFIG_DSU_ATRACESZ1
586 #define CFG_DSU_ATB 1
587 #elif CONFIG_DSU_ATRACESZ2
588 #define CFG_DSU_ATB 2
589 #elif CONFIG_DSU_ATRACESZ4
590 #define CFG_DSU_ATB 4
591 #elif CONFIG_DSU_ATRACESZ8
592 #define CFG_DSU_ATB 8
593 #elif CONFIG_DSU_ATRACESZ16
594 #define CFG_DSU_ATB 16
595 #else
596 #define CFG_DSU_ATB 0
597 #endif
598
599 #ifndef CONFIG_LEON3FT_EN
600 #define CONFIG_LEON3FT_EN 0
601 #endif
602
603 #if defined CONFIG_IUFT_PAR
604 #define CONFIG_IUFT_EN 1
605 #elif defined CONFIG_IUFT_DMR
606 #define CONFIG_IUFT_EN 2
607 #elif defined CONFIG_IUFT_BCH
608 #define CONFIG_IUFT_EN 3
609 #elif defined CONFIG_IUFT_TMR
610 #define CONFIG_IUFT_EN 4
611 #else
612 #define CONFIG_IUFT_EN 0
613 #endif
614 #ifndef CONFIG_RF_ERRINJ
615 #define CONFIG_RF_ERRINJ 0
616 #endif
617
618 #ifndef CONFIG_FPUFT_EN
619 #define CONFIG_FPUFT 0
620 #else
621 #ifdef CONFIG_FPU_GRFPU
622 #define CONFIG_FPUFT 2
623 #else
624 #define CONFIG_FPUFT 1
625 #endif
626 #endif
627
628 #ifndef CONFIG_CACHE_FT_EN
629 #define CONFIG_CACHE_FT_EN 0
630 #endif
631 #ifndef CONFIG_CACHE_ERRINJ
632 #define CONFIG_CACHE_ERRINJ 0
633 #endif
634
635 #ifndef CONFIG_LEON3_NETLIST
636 #define CONFIG_LEON3_NETLIST 0
637 #endif
638
639 #ifdef CONFIG_DEBUG_PC32
640 #define CFG_DEBUG_PC32 0
641 #else
642 #define CFG_DEBUG_PC32 2
643 #endif
644 #ifndef CONFIG_IU_DISAS
645 #define CONFIG_IU_DISAS 0
646 #endif
647 #ifndef CONFIG_IU_DISAS_NET
648 #define CONFIG_IU_DISAS_NET 0
649 #endif
650
651
652 #ifndef CONFIG_AHB_SPLIT
653 #define CONFIG_AHB_SPLIT 0
654 #endif
655
656 #ifndef CONFIG_AHB_RROBIN
657 #define CONFIG_AHB_RROBIN 0
658 #endif
659
660 #ifndef CONFIG_AHB_IOADDR
661 #define CONFIG_AHB_IOADDR FFF
662 #endif
663
664 #ifndef CONFIG_APB_HADDR
665 #define CONFIG_APB_HADDR 800
666 #endif
667
668 #ifndef CONFIG_AHB_MON
669 #define CONFIG_AHB_MON 0
670 #endif
671
672 #ifndef CONFIG_AHB_MONERR
673 #define CONFIG_AHB_MONERR 0
674 #endif
675
676 #ifndef CONFIG_AHB_MONWAR
677 #define CONFIG_AHB_MONWAR 0
678 #endif
679
680 #ifndef CONFIG_AHB_DTRACE
681 #define CONFIG_AHB_DTRACE 0
682 #endif
683
684 #ifndef CONFIG_DSU_JTAG
685 #define CONFIG_DSU_JTAG 0
686 #endif
687
688 #ifndef CONFIG_DSU_ETH
689 #define CONFIG_DSU_ETH 0
690 #endif
691
692 #ifndef CONFIG_DSU_IPMSB
693 #define CONFIG_DSU_IPMSB C0A8
694 #endif
695
696 #ifndef CONFIG_DSU_IPLSB
697 #define CONFIG_DSU_IPLSB 0033
698 #endif
699
700 #ifndef CONFIG_DSU_ETHMSB
701 #define CONFIG_DSU_ETHMSB 020000
702 #endif
703
704 #ifndef CONFIG_DSU_ETHLSB
705 #define CONFIG_DSU_ETHLSB 000009
706 #endif
707
708 #if defined CONFIG_DSU_ETHSZ1
709 #define CFG_DSU_ETHB 1
710 #elif CONFIG_DSU_ETHSZ2
711 #define CFG_DSU_ETHB 2
712 #elif CONFIG_DSU_ETHSZ4
713 #define CFG_DSU_ETHB 4
714 #elif CONFIG_DSU_ETHSZ8
715 #define CFG_DSU_ETHB 8
716 #elif CONFIG_DSU_ETHSZ16
717 #define CFG_DSU_ETHB 16
718 #elif CONFIG_DSU_ETHSZ32
719 #define CFG_DSU_ETHB 32
720 #else
721 #define CFG_DSU_ETHB 1
722 #endif
723
724 #ifndef CONFIG_DSU_ETH_PROG
725 #define CONFIG_DSU_ETH_PROG 0
726 #endif
727
728 #ifndef CONFIG_DSU_ETH_DIS
729 #define CONFIG_DSU_ETH_DIS 0
730 #endif
731
732 #ifndef CONFIG_MCTRL_LEON2
733 #define CONFIG_MCTRL_LEON2 0
734 #endif
735
736 #ifndef CONFIG_MCTRL_SDRAM
737 #define CONFIG_MCTRL_SDRAM 0
738 #endif
739
740 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
741 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
742 #endif
743
744 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
745 #define CONFIG_MCTRL_SDRAM_INVCLK 0
746 #endif
747
748 #ifndef CONFIG_MCTRL_SDRAM_BUS64
749 #define CONFIG_MCTRL_SDRAM_BUS64 0
750 #endif
751
752 #ifndef CONFIG_MCTRL_8BIT
753 #define CONFIG_MCTRL_8BIT 0
754 #endif
755
756 #ifndef CONFIG_MCTRL_16BIT
757 #define CONFIG_MCTRL_16BIT 0
758 #endif
759
760 #ifndef CONFIG_MCTRL_5CS
761 #define CONFIG_MCTRL_5CS 0
762 #endif
763
764 #ifndef CONFIG_MCTRL_EDAC
765 #define CONFIG_MCTRL_EDAC 0
766 #endif
767
768 #ifndef CONFIG_MCTRL_PAGE
769 #define CONFIG_MCTRL_PAGE 0
770 #endif
771
772 #ifndef CONFIG_MCTRL_PROGPAGE
773 #define CONFIG_MCTRL_PROGPAGE 0
774 #endif
775
776
777 #ifndef CONFIG_MIG_DDR2
778 #define CONFIG_MIG_DDR2 0
779 #endif
780
781 #ifndef CONFIG_MIG_RANKS
782 #define CONFIG_MIG_RANKS 1
783 #endif
784
785 #ifndef CONFIG_MIG_COLBITS
786 #define CONFIG_MIG_COLBITS 10
787 #endif
788
789 #ifndef CONFIG_MIG_ROWBITS
790 #define CONFIG_MIG_ROWBITS 13
791 #endif
792
793 #ifndef CONFIG_MIG_BANKBITS
794 #define CONFIG_MIG_BANKBITS 2
795 #endif
796
797 #ifndef CONFIG_MIG_HMASK
798 #define CONFIG_MIG_HMASK F00
799 #endif
800 #ifndef CONFIG_AHBSTAT_ENABLE
801 #define CONFIG_AHBSTAT_ENABLE 0
802 #endif
803
804 #ifndef CONFIG_AHBSTAT_NFTSLV
805 #define CONFIG_AHBSTAT_NFTSLV 1
806 #endif
807
808 #ifndef CONFIG_AHBROM_ENABLE
809 #define CONFIG_AHBROM_ENABLE 0
810 #endif
811
812 #ifndef CONFIG_AHBROM_START
813 #define CONFIG_AHBROM_START 000
814 #endif
815
816 #ifndef CONFIG_AHBROM_PIPE
817 #define CONFIG_AHBROM_PIPE 0
818 #endif
819
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
821 #define CONFIG_ROM_START 100
822 #else
823 #define CONFIG_ROM_START 000
824 #endif
825
826
827 #ifndef CONFIG_AHBRAM_ENABLE
828 #define CONFIG_AHBRAM_ENABLE 0
829 #endif
830
831 #ifndef CONFIG_AHBRAM_START
832 #define CONFIG_AHBRAM_START A00
833 #endif
834
835 #if defined CONFIG_AHBRAM_SZ1
836 #define CFG_AHBRAMSZ 1
837 #elif CONFIG_AHBRAM_SZ2
838 #define CFG_AHBRAMSZ 2
839 #elif CONFIG_AHBRAM_SZ4
840 #define CFG_AHBRAMSZ 4
841 #elif CONFIG_AHBRAM_SZ8
842 #define CFG_AHBRAMSZ 8
843 #elif CONFIG_AHBRAM_SZ16
844 #define CFG_AHBRAMSZ 16
845 #elif CONFIG_AHBRAM_SZ32
846 #define CFG_AHBRAMSZ 32
847 #elif CONFIG_AHBRAM_SZ64
848 #define CFG_AHBRAMSZ 64
849 #else
850 #define CFG_AHBRAMSZ 1
851 #endif
852
853 #ifndef CONFIG_GRETH_ENABLE
854 #define CONFIG_GRETH_ENABLE 0
855 #endif
856
857 #ifndef CONFIG_GRETH_GIGA
858 #define CONFIG_GRETH_GIGA 0
859 #endif
860
861 #if defined CONFIG_GRETH_FIFO4
862 #define CFG_GRETH_FIFO 4
863 #elif defined CONFIG_GRETH_FIFO8
864 #define CFG_GRETH_FIFO 8
865 #elif defined CONFIG_GRETH_FIFO16
866 #define CFG_GRETH_FIFO 16
867 #elif defined CONFIG_GRETH_FIFO32
868 #define CFG_GRETH_FIFO 32
869 #elif defined CONFIG_GRETH_FIFO64
870 #define CFG_GRETH_FIFO 64
871 #else
872 #define CFG_GRETH_FIFO 8
873 #endif
874
875 #ifndef CONFIG_UART1_ENABLE
876 #define CONFIG_UART1_ENABLE 0
877 #endif
878
879 #if defined CONFIG_UA1_FIFO1
880 #define CFG_UA1_FIFO 1
881 #elif defined CONFIG_UA1_FIFO2
882 #define CFG_UA1_FIFO 2
883 #elif defined CONFIG_UA1_FIFO4
884 #define CFG_UA1_FIFO 4
885 #elif defined CONFIG_UA1_FIFO8
886 #define CFG_UA1_FIFO 8
887 #elif defined CONFIG_UA1_FIFO16
888 #define CFG_UA1_FIFO 16
889 #elif defined CONFIG_UA1_FIFO32
890 #define CFG_UA1_FIFO 32
891 #else
892 #define CFG_UA1_FIFO 1
893 #endif
894
895 #ifndef CONFIG_IRQ3_ENABLE
896 #define CONFIG_IRQ3_ENABLE 0
897 #endif
898 #ifndef CONFIG_IRQ3_NSEC
899 #define CONFIG_IRQ3_NSEC 0
900 #endif
901 #ifndef CONFIG_GPT_ENABLE
902 #define CONFIG_GPT_ENABLE 0
903 #endif
904
905 #ifndef CONFIG_GPT_NTIM
906 #define CONFIG_GPT_NTIM 1
907 #endif
908
909 #ifndef CONFIG_GPT_SW
910 #define CONFIG_GPT_SW 8
911 #endif
912
913 #ifndef CONFIG_GPT_TW
914 #define CONFIG_GPT_TW 8
915 #endif
916
917 #ifndef CONFIG_GPT_IRQ
918 #define CONFIG_GPT_IRQ 8
919 #endif
920
921 #ifndef CONFIG_GPT_SEPIRQ
922 #define CONFIG_GPT_SEPIRQ 0
923 #endif
924 #ifndef CONFIG_GPT_ENABLE
925 #define CONFIG_GPT_ENABLE 0
926 #endif
927
928 #ifndef CONFIG_GPT_NTIM
929 #define CONFIG_GPT_NTIM 1
930 #endif
931
932 #ifndef CONFIG_GPT_SW
933 #define CONFIG_GPT_SW 8
934 #endif
935
936 #ifndef CONFIG_GPT_TW
937 #define CONFIG_GPT_TW 8
938 #endif
939
940 #ifndef CONFIG_GPT_IRQ
941 #define CONFIG_GPT_IRQ 8
942 #endif
943
944 #ifndef CONFIG_GPT_SEPIRQ
945 #define CONFIG_GPT_SEPIRQ 0
946 #endif
947
948 #ifndef CONFIG_GPT_WDOGEN
949 #define CONFIG_GPT_WDOGEN 0
950 #endif
951
952 #ifndef CONFIG_GPT_WDOG
953 #define CONFIG_GPT_WDOG 0
954 #endif
955
956 #ifndef CONFIG_GRGPIO_ENABLE
957 #define CONFIG_GRGPIO_ENABLE 0
958 #endif
959 #ifndef CONFIG_GRGPIO_IMASK
960 #define CONFIG_GRGPIO_IMASK 0000
961 #endif
962 #ifndef CONFIG_GRGPIO_WIDTH
963 #define CONFIG_GRGPIO_WIDTH 1
964 #endif
965
966 #ifndef CONFIG_VGA_ENABLE
967 #define CONFIG_VGA_ENABLE 0
968 #endif
969 #ifndef CONFIG_SVGA_ENABLE
970 #define CONFIG_SVGA_ENABLE 0
971 #endif
972 #ifndef CONFIG_KBD_ENABLE
973 #define CONFIG_KBD_ENABLE 0
974 #endif
975
976
977 #ifndef CONFIG_SPIMCTRL
978 #define CONFIG_SPIMCTRL 0
979 #endif
980
981 #ifndef CONFIG_SPIMCTRL_SDCARD
982 #define CONFIG_SPIMCTRL_SDCARD 0
983 #endif
984
985 #ifndef CONFIG_SPIMCTRL_READCMD
986 #define CONFIG_SPIMCTRL_READCMD 0
987 #endif
988
989 #ifndef CONFIG_SPIMCTRL_DUMMYBYTE
990 #define CONFIG_SPIMCTRL_DUMMYBYTE 0
991 #endif
992
993 #ifndef CONFIG_SPIMCTRL_DUALOUTPUT
994 #define CONFIG_SPIMCTRL_DUALOUTPUT 0
995 #endif
996
997 #ifndef CONFIG_SPIMCTRL_SCALER
998 #define CONFIG_SPIMCTRL_SCALER 1
999 #endif
1000
1001 #ifndef CONFIG_SPIMCTRL_ASCALER
1002 #define CONFIG_SPIMCTRL_ASCALER 1
1003 #endif
1004
1005 #ifndef CONFIG_SPIMCTRL_PWRUPCNT
1006 #define CONFIG_SPIMCTRL_PWRUPCNT 0
1007 #endif
1008 #ifndef CONFIG_SPICTRL_ENABLE
1009 #define CONFIG_SPICTRL_ENABLE 0
1010 #endif
1011 #ifndef CONFIG_SPICTRL_NUM
1012 #define CONFIG_SPICTRL_NUM 1
1013 #endif
1014 #ifndef CONFIG_SPICTRL_SLVS
1015 #define CONFIG_SPICTRL_SLVS 1
1016 #endif
1017 #ifndef CONFIG_SPICTRL_FIFO
1018 #define CONFIG_SPICTRL_FIFO 1
1019 #endif
1020 #ifndef CONFIG_SPICTRL_SLVREG
1021 #define CONFIG_SPICTRL_SLVREG 0
1022 #endif
1023 #ifndef CONFIG_SPICTRL_ODMODE
1024 #define CONFIG_SPICTRL_ODMODE 0
1025 #endif
1026 #ifndef CONFIG_SPICTRL_AM
1027 #define CONFIG_SPICTRL_AM 0
1028 #endif
1029 #ifndef CONFIG_SPICTRL_ASEL
1030 #define CONFIG_SPICTRL_ASEL 0
1031 #endif
1032 #ifndef CONFIG_SPICTRL_TWEN
1033 #define CONFIG_SPICTRL_TWEN 0
1034 #endif
1035 #ifndef CONFIG_SPICTRL_MAXWLEN
1036 #define CONFIG_SPICTRL_MAXWLEN 0
1037 #endif
1038 #ifndef CONFIG_SPICTRL_SYNCRAM
1039 #define CONFIG_SPICTRL_SYNCRAM 0
1040 #endif
1041 #if defined(CONFIG_SPICTRL_DMRFT)
1042 #define CONFIG_SPICTRL_FT 1
1043 #elif defined(CONFIG_SPICTRL_TMRFT)
1044 #define CONFIG_SPICTRL_FT 2
1045 #else
1046 #define CONFIG_SPICTRL_FT 0
1047 #endif
1048
1049 #ifndef CONFIG_DEBUG_UART
1050 #define CONFIG_DEBUG_UART 0
1051 #endif
Show file before | Show file after | Hide comments
@@ -1,209 +1,209
1 This leon3 design is tailored to the Xilinx SP605 Spartan6 board
2
3 Simulation and synthesis
4 ------------------------
5
6 The design uses the Xilinx MIG memory interface with an AHB-2.0
7 interface. The MIG source code cannot be distributed due to the
8 prohibitive Xilinx license, so the MIG must be re-generated with
9 coregen before simulation and synthesis can be done.
10
11 To generate the MIG and install tne Xilinx unisim simulation
12 library, do as follows:
13
14 make mig
15 make install-secureip
16
17 This will ONLY work with ISE-13.2 installed, and the XILINX variable
18 properly set in the shell. To synthesize the design, do
19
20 make ise
21
22 and then
23
24 make ise-prog-fpga
25
26 to program the FPGA.
27
28 Design specifics
29 ----------------
30
31 * System reset is mapped to the CPU RESET button
32
33 * The AHB and processor is clocked by a 60 MHz clock, generated
34 from the 33 MHz SYSACE clock using a DCM. You can change the frequency
35 generation in the clocks menu of xconfig. The DDR3 (MIG) controller
36 runs at 667 MHz.
37
38 * The GRETH core is enabled and runs without problems at 100 Mbit.
39 Ethernet debug link is enabled and has IP 192.168.0.51.
40 1 Gbit operation is also possible (requires grlib com release),
41 uncomment related timing constraints in the leon3mp.ucf first.
42
43 * 16-bit flash prom can be read at address 0. It can be programmed
44 with GRMON version 1.1.16 or later.
45
46 * DDR3 is working with the provided Xilinx MIG DDR3 controller.
47 If you want to simulate this design, first install the secure
48 IP models with:
49
50 make install-secureip
51
52 Then rebuild the scripts and simulation model:
53
54 make distclean vsim
55
56 Modelsim v6.6e or newer is required to build the secure IP models.
57 Note that the regular leon3 test bench cannot be run in simulation
58 as the DDR3 model lacks data pre-load.
59
60 * The application UART1 is connected to the USB/UART connector
61
62 * The SVGA frame buffer uses a separate port on the DDR3 controller,
63 and therefore does not noticeably affect the performance of the processor.
64 Default output is analog VGA, to switch to DVI mode execute this
65 command in grmon:
66
67 i2c dvi init_l4itx_vga
68
69 * The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
70 Start grmon with -xilusb to connect.
71
72 * Output from GRMON is:
73
74 $ grmon -xilusb -u
75
76 GRMON LEON debug monitor v1.1.51 professional version (debug)
77
78 Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
79 For latest updates, go to http://www.gaisler.com/
80 Comments or bug-reports to support@gaisler.com
81
82 Xilinx cable: Cable type/rev : 0x3
83 JTAG chain: xc6slx45t xccace
84
85 GRLIB build version: 4111
86
87 initialising ...............
88 detected frequency: 50 MHz
89 SRAM waitstates: 1
90
91 Component Vendor
92 LEON3 SPARC V8 Processor Gaisler Research
93 AHB Debug JTAG TAP Gaisler Research
94 GR Ethernet MAC Gaisler Research
95 LEON2 Memory Controller European Space Agency
96 AHB/APB Bridge Gaisler Research
97 LEON3 Debug Support Unit Gaisler Research
98 Xilinx MIG DDR2 controller Gaisler Research
99 AHB/APB Bridge Gaisler Research
100 Generic APB UART Gaisler Research
101 Multi-processor Interrupt Ctrl Gaisler Research
102 Modular Timer Unit Gaisler Research
103 SVGA Controller Gaisler Research
104 AMBA Wrapper for OC I2C-master Gaisler Research
105 General purpose I/O port Gaisler Research
106 AHB status register Gaisler Research
107
108 Use command 'info sys' to print a detailed report of attached cores
109
110 grlib> inf sys
111 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
112 ahb master 0
113 01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
114 ahb master 1
115 02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
116 ahb master 2, irq 12
117 apb: 80000e00 - 80000f00
118 Device index: dev0
119 edcl ip 192.168.1.51, buffer 2 kbyte
120 00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
121 ahb: 00000000 - 20000000
122 apb: 80000000 - 80000100
123 16-bit prom @ 0x00000000
124 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
125 ahb: 80000000 - 80100000
126 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
127 ahb: 90000000 - a0000000
128 AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
129 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
130 icache 2 * 8 kbyte, 32 byte/line rnd
131 dcache 2 * 4 kbyte, 16 byte/line rnd
132 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
133 ahb: 40000000 - 48000000
134 apb: 80100000 - 80100100
135 DDR2: 128 Mbyte
136 0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
137 ahb: 80100000 - 80200000
138 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
139 irq 2
140 apb: 80000100 - 80000200
141 baud rate 38343, DSU mode (FIFO debug)
142 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
143 apb: 80000200 - 80000300
144 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
145 irq 8
146 apb: 80000300 - 80000400
147 8-bit scaler, 2 * 32-bit timers, divisor 50
148 06.01:063 Gaisler Research SVGA Controller (ver 0x0)
149 apb: 80000600 - 80000700
150 clk0: 50.00 MHz
151 09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
152 irq 14
153 apb: 80000900 - 80000a00
154 0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
155 apb: 80000a00 - 80000b00
156 0f.01:052 Gaisler Research AHB status register (ver 0x0)
157 irq 7
158 apb: 80000f00 - 80001000
159 grlib> fla
160
161 Intel-style 16-bit flash on D[31:16]
162
163 Manuf. Intel
164 Device Strataflash P30
165
166 Device ID 02e44603e127ffff
167 User ID ffffffffffffffff
168
169
170 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
171
172
173 CFI info
174 flash family : 1
175 flash size : 256 Mbit
176 erase regions : 2
177 erase blocks : 259
178 write buffer : 1024 bytes
179 lock-down : yes
180 region 0 : 255 blocks of 128 Kbytes
181 region 1 : 4 blocks of 32 Kbytes
182
183 grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
184 section: .text at 0x40000000, size 102544 bytes
185 section: .data at 0x40019090, size 2788 bytes
186 total size: 105332 bytes (1.2 Mbit/s)
187 read 272 symbols
188 entry point: 0x40000000
189 grlib> run
190 2K performance run parameters for coremark.
191 CoreMark Size : 666
192 Total ticks : 19945918
193 Total time (secs): 19.945918
194 Iterations/Sec : 100.271143
195 Iterations : 2000
196 Compiler version : GCC4.4.2
197 Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
198 Memory location : STACK
199 seedcrc : 0xe9f5
200 [0]crclist : 0xe714
201 [0]crcmatrix : 0x1fd7
202 [0]crcstate : 0x8e3a
203 [0]crcfinal : 0x4983
204 Correct operation validated. See readme.txt for run and reporting rules.
205 CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
206
207 Program exited normally.
208 grlib>
209
1 This leon3 design is tailored to the Xilinx SP605 Spartan6 board
2
3 Simulation and synthesis
4 ------------------------
5
6 The design uses the Xilinx MIG memory interface with an AHB-2.0
7 interface. The MIG source code cannot be distributed due to the
8 prohibitive Xilinx license, so the MIG must be re-generated with
9 coregen before simulation and synthesis can be done.
10
11 To generate the MIG and install tne Xilinx unisim simulation
12 library, do as follows:
13
14 make mig
15 make install-secureip
16
17 This will ONLY work with ISE-13.2 installed, and the XILINX variable
18 properly set in the shell. To synthesize the design, do
19
20 make ise
21
22 and then
23
24 make ise-prog-fpga
25
26 to program the FPGA.
27
28 Design specifics
29 ----------------
30
31 * System reset is mapped to the CPU RESET button
32
33 * The AHB and processor is clocked by a 60 MHz clock, generated
34 from the 33 MHz SYSACE clock using a DCM. You can change the frequency
35 generation in the clocks menu of xconfig. The DDR3 (MIG) controller
36 runs at 667 MHz.
37
38 * The GRETH core is enabled and runs without problems at 100 Mbit.
39 Ethernet debug link is enabled and has IP 192.168.0.51.
40 1 Gbit operation is also possible (requires grlib com release),
41 uncomment related timing constraints in the leon3mp.ucf first.
42
43 * 16-bit flash prom can be read at address 0. It can be programmed
44 with GRMON version 1.1.16 or later.
45
46 * DDR3 is working with the provided Xilinx MIG DDR3 controller.
47 If you want to simulate this design, first install the secure
48 IP models with:
49
50 make install-secureip
51
52 Then rebuild the scripts and simulation model:
53
54 make distclean vsim
55
56 Modelsim v6.6e or newer is required to build the secure IP models.
57 Note that the regular leon3 test bench cannot be run in simulation
58 as the DDR3 model lacks data pre-load.
59
60 * The application UART1 is connected to the USB/UART connector
61
62 * The SVGA frame buffer uses a separate port on the DDR3 controller,
63 and therefore does not noticeably affect the performance of the processor.
64 Default output is analog VGA, to switch to DVI mode execute this
65 command in grmon:
66
67 i2c dvi init_l4itx_vga
68
69 * The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
70 Start grmon with -xilusb to connect.
71
72 * Output from GRMON is:
73
74 $ grmon -xilusb -u
75
76 GRMON LEON debug monitor v1.1.51 professional version (debug)
77
78 Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
79 For latest updates, go to http://www.gaisler.com/
80 Comments or bug-reports to support@gaisler.com
81
82 Xilinx cable: Cable type/rev : 0x3
83 JTAG chain: xc6slx45t xccace
84
85 GRLIB build version: 4111
86
87 initialising ...............
88 detected frequency: 50 MHz
89 SRAM waitstates: 1
90
91 Component Vendor
92 LEON3 SPARC V8 Processor Gaisler Research
93 AHB Debug JTAG TAP Gaisler Research
94 GR Ethernet MAC Gaisler Research
95 LEON2 Memory Controller European Space Agency
96 AHB/APB Bridge Gaisler Research
97 LEON3 Debug Support Unit Gaisler Research
98 Xilinx MIG DDR2 controller Gaisler Research
99 AHB/APB Bridge Gaisler Research
100 Generic APB UART Gaisler Research
101 Multi-processor Interrupt Ctrl Gaisler Research
102 Modular Timer Unit Gaisler Research
103 SVGA Controller Gaisler Research
104 AMBA Wrapper for OC I2C-master Gaisler Research
105 General purpose I/O port Gaisler Research
106 AHB status register Gaisler Research
107
108 Use command 'info sys' to print a detailed report of attached cores
109
110 grlib> inf sys
111 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
112 ahb master 0
113 01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
114 ahb master 1
115 02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
116 ahb master 2, irq 12
117 apb: 80000e00 - 80000f00
118 Device index: dev0
119 edcl ip 192.168.1.51, buffer 2 kbyte
120 00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
121 ahb: 00000000 - 20000000
122 apb: 80000000 - 80000100
123 16-bit prom @ 0x00000000
124 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
125 ahb: 80000000 - 80100000
126 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
127 ahb: 90000000 - a0000000
128 AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
129 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
130 icache 2 * 8 kbyte, 32 byte/line rnd
131 dcache 2 * 4 kbyte, 16 byte/line rnd
132 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
133 ahb: 40000000 - 48000000
134 apb: 80100000 - 80100100
135 DDR2: 128 Mbyte
136 0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
137 ahb: 80100000 - 80200000
138 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
139 irq 2
140 apb: 80000100 - 80000200
141 baud rate 38343, DSU mode (FIFO debug)
142 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
143 apb: 80000200 - 80000300
144 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
145 irq 8
146 apb: 80000300 - 80000400
147 8-bit scaler, 2 * 32-bit timers, divisor 50
148 06.01:063 Gaisler Research SVGA Controller (ver 0x0)
149 apb: 80000600 - 80000700
150 clk0: 50.00 MHz
151 09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
152 irq 14
153 apb: 80000900 - 80000a00
154 0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
155 apb: 80000a00 - 80000b00
156 0f.01:052 Gaisler Research AHB status register (ver 0x0)
157 irq 7
158 apb: 80000f00 - 80001000
159 grlib> fla
160
161 Intel-style 16-bit flash on D[31:16]
162
163 Manuf. Intel
164 Device Strataflash P30
165
166 Device ID 02e44603e127ffff
167 User ID ffffffffffffffff
168
169
170 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
171
172
173 CFI info
174 flash family : 1
175 flash size : 256 Mbit
176 erase regions : 2
177 erase blocks : 259
178 write buffer : 1024 bytes
179 lock-down : yes
180 region 0 : 255 blocks of 128 Kbytes
181 region 1 : 4 blocks of 32 Kbytes
182
183 grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
184 section: .text at 0x40000000, size 102544 bytes
185 section: .data at 0x40019090, size 2788 bytes
186 total size: 105332 bytes (1.2 Mbit/s)
187 read 272 symbols
188 entry point: 0x40000000
189 grlib> run
190 2K performance run parameters for coremark.
191 CoreMark Size : 666
192 Total ticks : 19945918
193 Total time (secs): 19.945918
194 Iterations/Sec : 100.271143
195 Iterations : 2000
196 Compiler version : GCC4.4.2
197 Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
198 Memory location : STACK
199 seedcrc : 0xe9f5
200 [0]crclist : 0xe714
201 [0]crcmatrix : 0x1fd7
202 [0]crcstate : 0x8e3a
203 [0]crcfinal : 0x4983
204 Correct operation validated. See readme.txt for run and reporting rules.
205 CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
206
207 Program exited normally.
208 grlib>
209
Show file before | Show file after | Hide comments
@@ -1,190 +1,190
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
18
19 -- LEON3 processor core
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
23 constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
25 constant CFG_BP : integer := CONFIG_IU_BP;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
72
73 -- AMBA settings
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
83
84 -- JTAG based DSU interface
85 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
86
87 -- Ethernet DSU
88 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
89 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
90 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
91 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
92 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
93 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
94
95 -- LEON2 memory controller
96 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
97 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
98 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
99 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
100 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
101 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
102 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
103 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
104 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
105
106 -- Xilinx MIG
107 constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
108 constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
109 constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
110 constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
111 constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
112 constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
113
114
115 -- AHB status register
116 constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
117 constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
118
119 -- AHB ROM
120 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
121 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
122 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
123 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
124 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
125
126 -- AHB RAM
127 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
128 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
129 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
130
131 -- Gaisler Ethernet core
132 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
133 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
134 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
135
136 -- UART 1
137 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
138 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
139
140 -- LEON3 interrupt controller
141 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
142 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
143
144 -- Modular timer
145 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
146 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
147 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
148 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
149 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
150 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
151 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
152 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
153
154 -- GPIO port
155 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
156 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
157 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
158
159 -- VGA and PS2/ interface
160 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
161 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
162 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
163
164 -- SPI memory controller
165 constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
166 constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
167 constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
168 constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
169 constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
170 constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
171 constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
172 constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
173
174 -- SPI controller
175 constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
176 constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
177 constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
178 constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
179 constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
180 constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
181 constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
182 constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
183 constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
184 constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
185 constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
186 constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
187
188 -- GRLIB debugging
189 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
190
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
18
19 -- LEON3 processor core
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
23 constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
25 constant CFG_BP : integer := CONFIG_IU_BP;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
72
73 -- AMBA settings
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
83
84 -- JTAG based DSU interface
85 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
86
87 -- Ethernet DSU
88 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
89 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
90 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
91 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
92 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
93 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
94
95 -- LEON2 memory controller
96 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
97 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
98 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
99 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
100 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
101 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
102 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
103 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
104 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
105
106 -- Xilinx MIG
107 constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
108 constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
109 constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
110 constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
111 constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
112 constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
113
114
115 -- AHB status register
116 constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
117 constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
118
119 -- AHB ROM
120 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
121 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
122 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
123 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
124 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
125
126 -- AHB RAM
127 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
128 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
129 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
130
131 -- Gaisler Ethernet core
132 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
133 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
134 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
135
136 -- UART 1
137 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
138 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
139
140 -- LEON3 interrupt controller
141 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
142 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
143
144 -- Modular timer
145 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
146 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
147 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
148 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
149 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
150 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
151 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
152 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
153
154 -- GPIO port
155 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
156 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
157 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
158
159 -- VGA and PS2/ interface
160 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
161 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
162 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
163
164 -- SPI memory controller
165 constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
166 constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
167 constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
168 constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
169 constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
170 constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
171 constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
172 constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
173
174 -- SPI controller
175 constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
176 constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
177 constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
178 constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
179 constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
180 constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
181 constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
182 constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
183 constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
184 constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
185 constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
186 constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
187
188 -- GRLIB debugging
189 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
190
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@@ -1,13 +1,13
1
2 SPARTAN6 50 MHz, MIG DDR2, 2x8 + 2x4 cache, GRFPU
3
4 LEON3 LEON3FTV2
5 Dhrystone 78.4 78.4
6 Whetstone DP 27.7 27.7
7 gzip 43.98 s 41.38 s
8 bzip2 248.22 s 200.10 s
9 176.gcc 208.62 s 180.48 s
10 coremark 100.12 i/s 100.12 i/s
11 aocs_v8 12388.7 i/s 12388.7 i/s
12 basicmath_large 13245.0 i/s 13245.0 i/s
13 linpack_unroll_dp_v8 3265 KFLOPS 3563 KFLOPS
1
2 SPARTAN6 50 MHz, MIG DDR2, 2x8 + 2x4 cache, GRFPU
3
4 LEON3 LEON3FTV2
5 Dhrystone 78.4 78.4
6 Whetstone DP 27.7 27.7
7 gzip 43.98 s 41.38 s
8 bzip2 248.22 s 200.10 s
9 176.gcc 208.62 s 180.48 s
10 coremark 100.12 i/s 100.12 i/s
11 aocs_v8 12388.7 i/s 12388.7 i/s
12 basicmath_large 13245.0 i/s 13245.0 i/s
13 linpack_unroll_dp_v8 3265 KFLOPS 3563 KFLOPS
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@@ -1,18 +1,18
1
2 main()
3
4 {
5 report_start();
6
7
8 // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
9 base_test();
10 /*
11 greth_test(0x80000e00);
12 spw_test(0x80100A00);
13 spw_test(0x80100B00);
14 spw_test(0x80100C00);
15 svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
16 */
17 report_end();
18 }
1
2 main()
3
4 {
5 report_start();
6
7
8 // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
9 base_test();
10 /*
11 greth_test(0x80000e00);
12 spw_test(0x80100A00);
13 spw_test(0x80100B00);
14 spw_test(0x80100C00);
15 svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
16 */
17 report_end();
18 }
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@@ -1,1051 +1,1051
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_AXDSP
14 #define CONFIG_SYN_TECH axdsp
15 #elif defined CONFIG_SYN_PROASICPLUS
16 #define CONFIG_SYN_TECH proasic
17 #elif defined CONFIG_SYN_ALTERA
18 #define CONFIG_SYN_TECH altera
19 #elif defined CONFIG_SYN_STRATIX
20 #define CONFIG_SYN_TECH stratix1
21 #elif defined CONFIG_SYN_STRATIXII
22 #define CONFIG_SYN_TECH stratix2
23 #elif defined CONFIG_SYN_STRATIXIII
24 #define CONFIG_SYN_TECH stratix3
25 #elif defined CONFIG_SYN_CYCLONEIII
26 #define CONFIG_SYN_TECH cyclone3
27 #elif defined CONFIG_SYN_EASIC45
28 #define CONFIG_SYN_TECH easic45
29 #elif defined CONFIG_SYN_EASIC90
30 #define CONFIG_SYN_TECH easic90
31 #elif defined CONFIG_SYN_IHP25
32 #define CONFIG_SYN_TECH ihp25
33 #elif defined CONFIG_SYN_IHP25RH
34 #define CONFIG_SYN_TECH ihp25rh
35 #elif defined CONFIG_SYN_CMOS9SF
36 #define CONFIG_SYN_TECH cmos9sf
37 #elif defined CONFIG_SYN_LATTICE
38 #define CONFIG_SYN_TECH lattice
39 #elif defined CONFIG_SYN_ECLIPSE
40 #define CONFIG_SYN_TECH eclipse
41 #elif defined CONFIG_SYN_PEREGRINE
42 #define CONFIG_SYN_TECH peregrine
43 #elif defined CONFIG_SYN_PROASIC
44 #define CONFIG_SYN_TECH proasic
45 #elif defined CONFIG_SYN_PROASIC3
46 #define CONFIG_SYN_TECH apa3
47 #elif defined CONFIG_SYN_PROASIC3E
48 #define CONFIG_SYN_TECH apa3e
49 #elif defined CONFIG_SYN_PROASIC3L
50 #define CONFIG_SYN_TECH apa3l
51 #elif defined CONFIG_SYN_IGLOO
52 #define CONFIG_SYN_TECH apa3
53 #elif defined CONFIG_SYN_FUSION
54 #define CONFIG_SYN_TECH actfus
55 #elif defined CONFIG_SYN_SPARTAN2
56 #define CONFIG_SYN_TECH virtex
57 #elif defined CONFIG_SYN_VIRTEX
58 #define CONFIG_SYN_TECH virtex
59 #elif defined CONFIG_SYN_VIRTEXE
60 #define CONFIG_SYN_TECH virtex
61 #elif defined CONFIG_SYN_SPARTAN3
62 #define CONFIG_SYN_TECH spartan3
63 #elif defined CONFIG_SYN_SPARTAN3E
64 #define CONFIG_SYN_TECH spartan3e
65 #elif defined CONFIG_SYN_SPARTAN6
66 #define CONFIG_SYN_TECH spartan6
67 #elif defined CONFIG_SYN_VIRTEX2
68 #define CONFIG_SYN_TECH virtex2
69 #elif defined CONFIG_SYN_VIRTEX4
70 #define CONFIG_SYN_TECH virtex4
71 #elif defined CONFIG_SYN_VIRTEX5
72 #define CONFIG_SYN_TECH virtex5
73 #elif defined CONFIG_SYN_VIRTEX6
74 #define CONFIG_SYN_TECH virtex6
75 #elif defined CONFIG_SYN_RH_LIB18T
76 #define CONFIG_SYN_TECH rhlib18t
77 #elif defined CONFIG_SYN_SMIC13
78 #define CONFIG_SYN_TECH smic013
79 #elif defined CONFIG_SYN_UT025CRH
80 #define CONFIG_SYN_TECH ut25
81 #elif defined CONFIG_SYN_UT130HBD
82 #define CONFIG_SYN_TECH ut130
83 #elif defined CONFIG_SYN_UT90NHBD
84 #define CONFIG_SYN_TECH ut90
85 #elif defined CONFIG_SYN_TSMC90
86 #define CONFIG_SYN_TECH tsmc90
87 #elif defined CONFIG_SYN_TM65GPLUS
88 #define CONFIG_SYN_TECH tm65gpl
89 #elif defined CONFIG_SYN_CUSTOM1
90 #define CONFIG_SYN_TECH custom1
91 #else
92 #error "unknown target technology"
93 #endif
94
95 #if defined CONFIG_SYN_INFER_RAM
96 #define CFG_RAM_TECH inferred
97 #elif defined CONFIG_MEM_UMC
98 #define CFG_RAM_TECH umc
99 #elif defined CONFIG_MEM_RHUMC
100 #define CFG_RAM_TECH rhumc
101 #elif defined CONFIG_MEM_VIRAGE
102 #define CFG_RAM_TECH memvirage
103 #elif defined CONFIG_MEM_ARTISAN
104 #define CFG_RAM_TECH memartisan
105 #elif defined CONFIG_MEM_CUSTOM1
106 #define CFG_RAM_TECH custom1
107 #elif defined CONFIG_MEM_VIRAGE90
108 #define CFG_RAM_TECH memvirage90
109 #elif defined CONFIG_MEM_INFERRED
110 #define CFG_RAM_TECH inferred
111 #else
112 #define CFG_RAM_TECH CONFIG_SYN_TECH
113 #endif
114
115 #if defined CONFIG_SYN_INFER_PADS
116 #define CFG_PAD_TECH inferred
117 #else
118 #define CFG_PAD_TECH CONFIG_SYN_TECH
119 #endif
120
121 #ifndef CONFIG_SYN_NO_ASYNC
122 #define CONFIG_SYN_NO_ASYNC 0
123 #endif
124
125 #ifndef CONFIG_SYN_SCAN
126 #define CONFIG_SYN_SCAN 0
127 #endif
128
129
130 #if defined CONFIG_CLK_ALTDLL
131 #define CFG_CLK_TECH CONFIG_SYN_TECH
132 #elif defined CONFIG_CLK_HCLKBUF
133 #define CFG_CLK_TECH axcel
134 #elif defined CONFIG_CLK_LATDLL
135 #define CFG_CLK_TECH lattice
136 #elif defined CONFIG_CLK_PRO3PLL
137 #define CFG_CLK_TECH apa3
138 #elif defined CONFIG_CLK_PRO3EPLL
139 #define CFG_CLK_TECH apa3e
140 #elif defined CONFIG_CLK_PRO3LPLL
141 #define CFG_CLK_TECH apa3l
142 #elif defined CONFIG_CLK_FUSPLL
143 #define CFG_CLK_TECH actfus
144 #elif defined CONFIG_CLK_CLKDLL
145 #define CFG_CLK_TECH virtex
146 #elif defined CONFIG_CLK_DCM
147 #define CFG_CLK_TECH CONFIG_SYN_TECH
148 #elif defined CONFIG_CLK_LIB18T
149 #define CFG_CLK_TECH rhlib18t
150 #elif defined CONFIG_CLK_RHUMC
151 #define CFG_CLK_TECH rhumc
152 #elif defined CONFIG_CLK_UT130HBD
153 #define CFG_CLK_TECH ut130
154 #else
155 #define CFG_CLK_TECH inferred
156 #endif
157
158 #ifndef CONFIG_CLK_MUL
159 #define CONFIG_CLK_MUL 2
160 #endif
161
162 #ifndef CONFIG_CLK_DIV
163 #define CONFIG_CLK_DIV 2
164 #endif
165
166 #ifndef CONFIG_OCLK_DIV
167 #define CONFIG_OCLK_DIV 1
168 #endif
169
170 #ifndef CONFIG_OCLKB_DIV
171 #define CONFIG_OCLKB_DIV 0
172 #endif
173
174 #ifndef CONFIG_OCLKC_DIV
175 #define CONFIG_OCLKC_DIV 0
176 #endif
177
178 #ifndef CONFIG_PCI_CLKDLL
179 #define CONFIG_PCI_CLKDLL 0
180 #endif
181
182 #ifndef CONFIG_PCI_SYSCLK
183 #define CONFIG_PCI_SYSCLK 0
184 #endif
185
186 #ifndef CONFIG_CLK_NOFB
187 #define CONFIG_CLK_NOFB 0
188 #endif
189 #ifndef CONFIG_LEON3
190 #define CONFIG_LEON3 0
191 #endif
192
193 #ifndef CONFIG_PROC_NUM
194 #define CONFIG_PROC_NUM 1
195 #endif
196
197 #ifndef CONFIG_IU_NWINDOWS
198 #define CONFIG_IU_NWINDOWS 8
199 #endif
200
201 #ifndef CONFIG_IU_RSTADDR
202 #define CONFIG_IU_RSTADDR 8
203 #endif
204
205 #ifndef CONFIG_IU_LDELAY
206 #define CONFIG_IU_LDELAY 1
207 #endif
208
209 #ifndef CONFIG_IU_WATCHPOINTS
210 #define CONFIG_IU_WATCHPOINTS 0
211 #endif
212
213 #ifdef CONFIG_IU_V8MULDIV
214 #ifdef CONFIG_IU_MUL_LATENCY_4
215 #define CFG_IU_V8 1
216 #elif defined CONFIG_IU_MUL_LATENCY_5
217 #define CFG_IU_V8 2
218 #elif defined CONFIG_IU_MUL_LATENCY_2
219 #define CFG_IU_V8 16#32#
220 #endif
221 #else
222 #define CFG_IU_V8 0
223 #endif
224
225 #ifdef CONFIG_IU_MUL_MODGEN
226 #define CFG_IU_MUL_STRUCT 1
227 #elif defined CONFIG_IU_MUL_TECHSPEC
228 #define CFG_IU_MUL_STRUCT 2
229 #elif defined CONFIG_IU_MUL_DW
230 #define CFG_IU_MUL_STRUCT 3
231 #else
232 #define CFG_IU_MUL_STRUCT 0
233 #endif
234
235 #ifndef CONFIG_PWD
236 #define CONFIG_PWD 0
237 #endif
238
239 #ifndef CONFIG_IU_MUL_MAC
240 #define CONFIG_IU_MUL_MAC 0
241 #endif
242
243 #ifndef CONFIG_IU_BP
244 #define CONFIG_IU_BP 0
245 #endif
246
247 #ifndef CONFIG_NOTAG
248 #define CONFIG_NOTAG 0
249 #endif
250
251 #ifndef CONFIG_IU_SVT
252 #define CONFIG_IU_SVT 0
253 #endif
254
255 #if defined CONFIG_FPU_GRFPC1
256 #define CONFIG_FPU_GRFPC 1
257 #elif defined CONFIG_FPU_GRFPC2
258 #define CONFIG_FPU_GRFPC 2
259 #else
260 #define CONFIG_FPU_GRFPC 0
261 #endif
262
263 #if defined CONFIG_FPU_GRFPU_INFMUL
264 #define CONFIG_FPU_GRFPU_MUL 0
265 #elif defined CONFIG_FPU_GRFPU_DWMUL
266 #define CONFIG_FPU_GRFPU_MUL 1
267 #elif defined CONFIG_FPU_GRFPU_MODGEN
268 #define CONFIG_FPU_GRFPU_MUL 2
269 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
270 #define CONFIG_FPU_GRFPU_MUL 3
271 #else
272 #define CONFIG_FPU_GRFPU_MUL 0
273 #endif
274
275 #if defined CONFIG_FPU_GRFPU_SH
276 #define CONFIG_FPU_GRFPU_SHARED 1
277 #else
278 #define CONFIG_FPU_GRFPU_SHARED 0
279 #endif
280
281 #if defined CONFIG_FPU_GRFPU
282 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
283 #elif defined CONFIG_FPU_MEIKO
284 #define CONFIG_FPU 15
285 #elif defined CONFIG_FPU_GRFPULITE
286 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
287 #else
288 #define CONFIG_FPU 0
289 #endif
290
291 #ifndef CONFIG_FPU_NETLIST
292 #define CONFIG_FPU_NETLIST 0
293 #endif
294
295 #ifndef CONFIG_ICACHE_ENABLE
296 #define CONFIG_ICACHE_ENABLE 0
297 #endif
298
299 #if defined CONFIG_ICACHE_ASSO1
300 #define CFG_IU_ISETS 1
301 #elif defined CONFIG_ICACHE_ASSO2
302 #define CFG_IU_ISETS 2
303 #elif defined CONFIG_ICACHE_ASSO3
304 #define CFG_IU_ISETS 3
305 #elif defined CONFIG_ICACHE_ASSO4
306 #define CFG_IU_ISETS 4
307 #else
308 #define CFG_IU_ISETS 1
309 #endif
310
311 #if defined CONFIG_ICACHE_SZ1
312 #define CFG_ICACHE_SZ 1
313 #elif defined CONFIG_ICACHE_SZ2
314 #define CFG_ICACHE_SZ 2
315 #elif defined CONFIG_ICACHE_SZ4
316 #define CFG_ICACHE_SZ 4
317 #elif defined CONFIG_ICACHE_SZ8
318 #define CFG_ICACHE_SZ 8
319 #elif defined CONFIG_ICACHE_SZ16
320 #define CFG_ICACHE_SZ 16
321 #elif defined CONFIG_ICACHE_SZ32
322 #define CFG_ICACHE_SZ 32
323 #elif defined CONFIG_ICACHE_SZ64
324 #define CFG_ICACHE_SZ 64
325 #elif defined CONFIG_ICACHE_SZ128
326 #define CFG_ICACHE_SZ 128
327 #elif defined CONFIG_ICACHE_SZ256
328 #define CFG_ICACHE_SZ 256
329 #else
330 #define CFG_ICACHE_SZ 1
331 #endif
332
333 #ifdef CONFIG_ICACHE_LZ16
334 #define CFG_ILINE_SZ 4
335 #else
336 #define CFG_ILINE_SZ 8
337 #endif
338
339 #if defined CONFIG_ICACHE_ALGODIR
340 #define CFG_ICACHE_ALGORND 3
341 #elif defined CONFIG_ICACHE_ALGORND
342 #define CFG_ICACHE_ALGORND 2
343 #elif defined CONFIG_ICACHE_ALGOLRR
344 #define CFG_ICACHE_ALGORND 1
345 #else
346 #define CFG_ICACHE_ALGORND 0
347 #endif
348
349 #ifndef CONFIG_ICACHE_LOCK
350 #define CONFIG_ICACHE_LOCK 0
351 #endif
352
353 #ifndef CONFIG_ICACHE_LRAM
354 #define CONFIG_ICACHE_LRAM 0
355 #endif
356
357 #ifndef CONFIG_ICACHE_LRSTART
358 #define CONFIG_ICACHE_LRSTART 8E
359 #endif
360
361 #if defined CONFIG_ICACHE_LRAM_SZ2
362 #define CFG_ILRAM_SIZE 2
363 #elif defined CONFIG_ICACHE_LRAM_SZ4
364 #define CFG_ILRAM_SIZE 4
365 #elif defined CONFIG_ICACHE_LRAM_SZ8
366 #define CFG_ILRAM_SIZE 8
367 #elif defined CONFIG_ICACHE_LRAM_SZ16
368 #define CFG_ILRAM_SIZE 16
369 #elif defined CONFIG_ICACHE_LRAM_SZ32
370 #define CFG_ILRAM_SIZE 32
371 #elif defined CONFIG_ICACHE_LRAM_SZ64
372 #define CFG_ILRAM_SIZE 64
373 #elif defined CONFIG_ICACHE_LRAM_SZ128
374 #define CFG_ILRAM_SIZE 128
375 #elif defined CONFIG_ICACHE_LRAM_SZ256
376 #define CFG_ILRAM_SIZE 256
377 #else
378 #define CFG_ILRAM_SIZE 1
379 #endif
380
381
382 #ifndef CONFIG_DCACHE_ENABLE
383 #define CONFIG_DCACHE_ENABLE 0
384 #endif
385
386 #if defined CONFIG_DCACHE_ASSO1
387 #define CFG_IU_DSETS 1
388 #elif defined CONFIG_DCACHE_ASSO2
389 #define CFG_IU_DSETS 2
390 #elif defined CONFIG_DCACHE_ASSO3
391 #define CFG_IU_DSETS 3
392 #elif defined CONFIG_DCACHE_ASSO4
393 #define CFG_IU_DSETS 4
394 #else
395 #define CFG_IU_DSETS 1
396 #endif
397
398 #if defined CONFIG_DCACHE_SZ1
399 #define CFG_DCACHE_SZ 1
400 #elif defined CONFIG_DCACHE_SZ2
401 #define CFG_DCACHE_SZ 2
402 #elif defined CONFIG_DCACHE_SZ4
403 #define CFG_DCACHE_SZ 4
404 #elif defined CONFIG_DCACHE_SZ8
405 #define CFG_DCACHE_SZ 8
406 #elif defined CONFIG_DCACHE_SZ16
407 #define CFG_DCACHE_SZ 16
408 #elif defined CONFIG_DCACHE_SZ32
409 #define CFG_DCACHE_SZ 32
410 #elif defined CONFIG_DCACHE_SZ64
411 #define CFG_DCACHE_SZ 64
412 #elif defined CONFIG_DCACHE_SZ128
413 #define CFG_DCACHE_SZ 128
414 #elif defined CONFIG_DCACHE_SZ256
415 #define CFG_DCACHE_SZ 256
416 #else
417 #define CFG_DCACHE_SZ 1
418 #endif
419
420 #ifdef CONFIG_DCACHE_LZ16
421 #define CFG_DLINE_SZ 4
422 #else
423 #define CFG_DLINE_SZ 8
424 #endif
425
426 #if defined CONFIG_DCACHE_ALGODIR
427 #define CFG_DCACHE_ALGORND 3
428 #elif defined CONFIG_DCACHE_ALGORND
429 #define CFG_DCACHE_ALGORND 2
430 #elif defined CONFIG_DCACHE_ALGOLRR
431 #define CFG_DCACHE_ALGORND 1
432 #else
433 #define CFG_DCACHE_ALGORND 0
434 #endif
435
436 #ifndef CONFIG_DCACHE_LOCK
437 #define CONFIG_DCACHE_LOCK 0
438 #endif
439
440 #ifndef CONFIG_DCACHE_SNOOP
441 #define CONFIG_DCACHE_SNOOP 0
442 #endif
443
444 #ifndef CONFIG_DCACHE_SNOOP_FAST
445 #define CONFIG_DCACHE_SNOOP_FAST 0
446 #endif
447
448 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
449 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
450 #endif
451
452 #ifndef CONFIG_CACHE_FIXED
453 #define CONFIG_CACHE_FIXED 0
454 #endif
455
456 #ifndef CONFIG_DCACHE_LRAM
457 #define CONFIG_DCACHE_LRAM 0
458 #endif
459
460 #ifndef CONFIG_DCACHE_LRSTART
461 #define CONFIG_DCACHE_LRSTART 8F
462 #endif
463
464 #if defined CONFIG_DCACHE_LRAM_SZ2
465 #define CFG_DLRAM_SIZE 2
466 #elif defined CONFIG_DCACHE_LRAM_SZ4
467 #define CFG_DLRAM_SIZE 4
468 #elif defined CONFIG_DCACHE_LRAM_SZ8
469 #define CFG_DLRAM_SIZE 8
470 #elif defined CONFIG_DCACHE_LRAM_SZ16
471 #define CFG_DLRAM_SIZE 16
472 #elif defined CONFIG_DCACHE_LRAM_SZ32
473 #define CFG_DLRAM_SIZE 32
474 #elif defined CONFIG_DCACHE_LRAM_SZ64
475 #define CFG_DLRAM_SIZE 64
476 #elif defined CONFIG_DCACHE_LRAM_SZ128
477 #define CFG_DLRAM_SIZE 128
478 #elif defined CONFIG_DCACHE_LRAM_SZ256
479 #define CFG_DLRAM_SIZE 256
480 #else
481 #define CFG_DLRAM_SIZE 1
482 #endif
483
484 #if defined CONFIG_MMU_PAGE_4K
485 #define CONFIG_MMU_PAGE 0
486 #elif defined CONFIG_MMU_PAGE_8K
487 #define CONFIG_MMU_PAGE 1
488 #elif defined CONFIG_MMU_PAGE_16K
489 #define CONFIG_MMU_PAGE 2
490 #elif defined CONFIG_MMU_PAGE_32K
491 #define CONFIG_MMU_PAGE 3
492 #elif defined CONFIG_MMU_PAGE_PROG
493 #define CONFIG_MMU_PAGE 4
494 #else
495 #define CONFIG_MMU_PAGE 0
496 #endif
497
498 #ifdef CONFIG_MMU_ENABLE
499 #define CONFIG_MMUEN 1
500
501 #ifdef CONFIG_MMU_SPLIT
502 #define CONFIG_TLB_TYPE 0
503 #endif
504 #ifdef CONFIG_MMU_COMBINED
505 #define CONFIG_TLB_TYPE 1
506 #endif
507
508 #ifdef CONFIG_MMU_REPARRAY
509 #define CONFIG_TLB_REP 0
510 #endif
511 #ifdef CONFIG_MMU_REPINCREMENT
512 #define CONFIG_TLB_REP 1
513 #endif
514
515 #ifdef CONFIG_MMU_I2
516 #define CONFIG_ITLBNUM 2
517 #endif
518 #ifdef CONFIG_MMU_I4
519 #define CONFIG_ITLBNUM 4
520 #endif
521 #ifdef CONFIG_MMU_I8
522 #define CONFIG_ITLBNUM 8
523 #endif
524 #ifdef CONFIG_MMU_I16
525 #define CONFIG_ITLBNUM 16
526 #endif
527 #ifdef CONFIG_MMU_I32
528 #define CONFIG_ITLBNUM 32
529 #endif
530
531 #define CONFIG_DTLBNUM 2
532 #ifdef CONFIG_MMU_D2
533 #undef CONFIG_DTLBNUM
534 #define CONFIG_DTLBNUM 2
535 #endif
536 #ifdef CONFIG_MMU_D4
537 #undef CONFIG_DTLBNUM
538 #define CONFIG_DTLBNUM 4
539 #endif
540 #ifdef CONFIG_MMU_D8
541 #undef CONFIG_DTLBNUM
542 #define CONFIG_DTLBNUM 8
543 #endif
544 #ifdef CONFIG_MMU_D16
545 #undef CONFIG_DTLBNUM
546 #define CONFIG_DTLBNUM 16
547 #endif
548 #ifdef CONFIG_MMU_D32
549 #undef CONFIG_DTLBNUM
550 #define CONFIG_DTLBNUM 32
551 #endif
552 #ifdef CONFIG_MMU_FASTWB
553 #define CFG_MMU_FASTWB 1
554 #else
555 #define CFG_MMU_FASTWB 0
556 #endif
557
558 #else
559 #define CONFIG_MMUEN 0
560 #define CONFIG_ITLBNUM 2
561 #define CONFIG_DTLBNUM 2
562 #define CONFIG_TLB_TYPE 1
563 #define CONFIG_TLB_REP 1
564 #define CFG_MMU_FASTWB 0
565 #endif
566
567 #ifndef CONFIG_DSU_ENABLE
568 #define CONFIG_DSU_ENABLE 0
569 #endif
570
571 #if defined CONFIG_DSU_ITRACESZ1
572 #define CFG_DSU_ITB 1
573 #elif CONFIG_DSU_ITRACESZ2
574 #define CFG_DSU_ITB 2
575 #elif CONFIG_DSU_ITRACESZ4
576 #define CFG_DSU_ITB 4
577 #elif CONFIG_DSU_ITRACESZ8
578 #define CFG_DSU_ITB 8
579 #elif CONFIG_DSU_ITRACESZ16
580 #define CFG_DSU_ITB 16
581 #else
582 #define CFG_DSU_ITB 0
583 #endif
584
585 #if defined CONFIG_DSU_ATRACESZ1
586 #define CFG_DSU_ATB 1
587 #elif CONFIG_DSU_ATRACESZ2
588 #define CFG_DSU_ATB 2
589 #elif CONFIG_DSU_ATRACESZ4
590 #define CFG_DSU_ATB 4
591 #elif CONFIG_DSU_ATRACESZ8
592 #define CFG_DSU_ATB 8
593 #elif CONFIG_DSU_ATRACESZ16
594 #define CFG_DSU_ATB 16
595 #else
596 #define CFG_DSU_ATB 0
597 #endif
598
599 #ifndef CONFIG_LEON3FT_EN
600 #define CONFIG_LEON3FT_EN 0
601 #endif
602
603 #if defined CONFIG_IUFT_PAR
604 #define CONFIG_IUFT_EN 1
605 #elif defined CONFIG_IUFT_DMR
606 #define CONFIG_IUFT_EN 2
607 #elif defined CONFIG_IUFT_BCH
608 #define CONFIG_IUFT_EN 3
609 #elif defined CONFIG_IUFT_TMR
610 #define CONFIG_IUFT_EN 4
611 #else
612 #define CONFIG_IUFT_EN 0
613 #endif
614 #ifndef CONFIG_RF_ERRINJ
615 #define CONFIG_RF_ERRINJ 0
616 #endif
617
618 #ifndef CONFIG_FPUFT_EN
619 #define CONFIG_FPUFT 0
620 #else
621 #ifdef CONFIG_FPU_GRFPU
622 #define CONFIG_FPUFT 2
623 #else
624 #define CONFIG_FPUFT 1
625 #endif
626 #endif
627
628 #ifndef CONFIG_CACHE_FT_EN
629 #define CONFIG_CACHE_FT_EN 0
630 #endif
631 #ifndef CONFIG_CACHE_ERRINJ
632 #define CONFIG_CACHE_ERRINJ 0
633 #endif
634
635 #ifndef CONFIG_LEON3_NETLIST
636 #define CONFIG_LEON3_NETLIST 0
637 #endif
638
639 #ifdef CONFIG_DEBUG_PC32
640 #define CFG_DEBUG_PC32 0
641 #else
642 #define CFG_DEBUG_PC32 2
643 #endif
644 #ifndef CONFIG_IU_DISAS
645 #define CONFIG_IU_DISAS 0
646 #endif
647 #ifndef CONFIG_IU_DISAS_NET
648 #define CONFIG_IU_DISAS_NET 0
649 #endif
650
651
652 #ifndef CONFIG_AHB_SPLIT
653 #define CONFIG_AHB_SPLIT 0
654 #endif
655
656 #ifndef CONFIG_AHB_RROBIN
657 #define CONFIG_AHB_RROBIN 0
658 #endif
659
660 #ifndef CONFIG_AHB_IOADDR
661 #define CONFIG_AHB_IOADDR FFF
662 #endif
663
664 #ifndef CONFIG_APB_HADDR
665 #define CONFIG_APB_HADDR 800
666 #endif
667
668 #ifndef CONFIG_AHB_MON
669 #define CONFIG_AHB_MON 0
670 #endif
671
672 #ifndef CONFIG_AHB_MONERR
673 #define CONFIG_AHB_MONERR 0
674 #endif
675
676 #ifndef CONFIG_AHB_MONWAR
677 #define CONFIG_AHB_MONWAR 0
678 #endif
679
680 #ifndef CONFIG_AHB_DTRACE
681 #define CONFIG_AHB_DTRACE 0
682 #endif
683
684 #ifndef CONFIG_DSU_JTAG
685 #define CONFIG_DSU_JTAG 0
686 #endif
687
688 #ifndef CONFIG_DSU_ETH
689 #define CONFIG_DSU_ETH 0
690 #endif
691
692 #ifndef CONFIG_DSU_IPMSB
693 #define CONFIG_DSU_IPMSB C0A8
694 #endif
695
696 #ifndef CONFIG_DSU_IPLSB
697 #define CONFIG_DSU_IPLSB 0033
698 #endif
699
700 #ifndef CONFIG_DSU_ETHMSB
701 #define CONFIG_DSU_ETHMSB 020000
702 #endif
703
704 #ifndef CONFIG_DSU_ETHLSB
705 #define CONFIG_DSU_ETHLSB 000009
706 #endif
707
708 #if defined CONFIG_DSU_ETHSZ1
709 #define CFG_DSU_ETHB 1
710 #elif CONFIG_DSU_ETHSZ2
711 #define CFG_DSU_ETHB 2
712 #elif CONFIG_DSU_ETHSZ4
713 #define CFG_DSU_ETHB 4
714 #elif CONFIG_DSU_ETHSZ8
715 #define CFG_DSU_ETHB 8
716 #elif CONFIG_DSU_ETHSZ16
717 #define CFG_DSU_ETHB 16
718 #elif CONFIG_DSU_ETHSZ32
719 #define CFG_DSU_ETHB 32
720 #else
721 #define CFG_DSU_ETHB 1
722 #endif
723
724 #ifndef CONFIG_DSU_ETH_PROG
725 #define CONFIG_DSU_ETH_PROG 0
726 #endif
727
728 #ifndef CONFIG_DSU_ETH_DIS
729 #define CONFIG_DSU_ETH_DIS 0
730 #endif
731
732 #ifndef CONFIG_MCTRL_LEON2
733 #define CONFIG_MCTRL_LEON2 0
734 #endif
735
736 #ifndef CONFIG_MCTRL_SDRAM
737 #define CONFIG_MCTRL_SDRAM 0
738 #endif
739
740 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
741 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
742 #endif
743
744 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
745 #define CONFIG_MCTRL_SDRAM_INVCLK 0
746 #endif
747
748 #ifndef CONFIG_MCTRL_SDRAM_BUS64
749 #define CONFIG_MCTRL_SDRAM_BUS64 0
750 #endif
751
752 #ifndef CONFIG_MCTRL_8BIT
753 #define CONFIG_MCTRL_8BIT 0
754 #endif
755
756 #ifndef CONFIG_MCTRL_16BIT
757 #define CONFIG_MCTRL_16BIT 0
758 #endif
759
760 #ifndef CONFIG_MCTRL_5CS
761 #define CONFIG_MCTRL_5CS 0
762 #endif
763
764 #ifndef CONFIG_MCTRL_EDAC
765 #define CONFIG_MCTRL_EDAC 0
766 #endif
767
768 #ifndef CONFIG_MCTRL_PAGE
769 #define CONFIG_MCTRL_PAGE 0
770 #endif
771
772 #ifndef CONFIG_MCTRL_PROGPAGE
773 #define CONFIG_MCTRL_PROGPAGE 0
774 #endif
775
776
777 #ifndef CONFIG_MIG_DDR2
778 #define CONFIG_MIG_DDR2 0
779 #endif
780
781 #ifndef CONFIG_MIG_RANKS
782 #define CONFIG_MIG_RANKS 1
783 #endif
784
785 #ifndef CONFIG_MIG_COLBITS
786 #define CONFIG_MIG_COLBITS 10
787 #endif
788
789 #ifndef CONFIG_MIG_ROWBITS
790 #define CONFIG_MIG_ROWBITS 13
791 #endif
792
793 #ifndef CONFIG_MIG_BANKBITS
794 #define CONFIG_MIG_BANKBITS 2
795 #endif
796
797 #ifndef CONFIG_MIG_HMASK
798 #define CONFIG_MIG_HMASK F00
799 #endif
800 #ifndef CONFIG_AHBSTAT_ENABLE
801 #define CONFIG_AHBSTAT_ENABLE 0
802 #endif
803
804 #ifndef CONFIG_AHBSTAT_NFTSLV
805 #define CONFIG_AHBSTAT_NFTSLV 1
806 #endif
807
808 #ifndef CONFIG_AHBROM_ENABLE
809 #define CONFIG_AHBROM_ENABLE 0
810 #endif
811
812 #ifndef CONFIG_AHBROM_START
813 #define CONFIG_AHBROM_START 000
814 #endif
815
816 #ifndef CONFIG_AHBROM_PIPE
817 #define CONFIG_AHBROM_PIPE 0
818 #endif
819
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
821 #define CONFIG_ROM_START 100
822 #else
823 #define CONFIG_ROM_START 000
824 #endif
825
826
827 #ifndef CONFIG_AHBRAM_ENABLE
828 #define CONFIG_AHBRAM_ENABLE 0
829 #endif
830
831 #ifndef CONFIG_AHBRAM_START
832 #define CONFIG_AHBRAM_START A00
833 #endif
834
835 #if defined CONFIG_AHBRAM_SZ1
836 #define CFG_AHBRAMSZ 1
837 #elif CONFIG_AHBRAM_SZ2
838 #define CFG_AHBRAMSZ 2
839 #elif CONFIG_AHBRAM_SZ4
840 #define CFG_AHBRAMSZ 4
841 #elif CONFIG_AHBRAM_SZ8
842 #define CFG_AHBRAMSZ 8
843 #elif CONFIG_AHBRAM_SZ16
844 #define CFG_AHBRAMSZ 16
845 #elif CONFIG_AHBRAM_SZ32
846 #define CFG_AHBRAMSZ 32
847 #elif CONFIG_AHBRAM_SZ64
848 #define CFG_AHBRAMSZ 64
849 #else
850 #define CFG_AHBRAMSZ 1
851 #endif
852
853 #ifndef CONFIG_GRETH_ENABLE
854 #define CONFIG_GRETH_ENABLE 0
855 #endif
856
857 #ifndef CONFIG_GRETH_GIGA
858 #define CONFIG_GRETH_GIGA 0
859 #endif
860
861 #if defined CONFIG_GRETH_FIFO4
862 #define CFG_GRETH_FIFO 4
863 #elif defined CONFIG_GRETH_FIFO8
864 #define CFG_GRETH_FIFO 8
865 #elif defined CONFIG_GRETH_FIFO16
866 #define CFG_GRETH_FIFO 16
867 #elif defined CONFIG_GRETH_FIFO32
868 #define CFG_GRETH_FIFO 32
869 #elif defined CONFIG_GRETH_FIFO64
870 #define CFG_GRETH_FIFO 64
871 #else
872 #define CFG_GRETH_FIFO 8
873 #endif
874
875 #ifndef CONFIG_UART1_ENABLE
876 #define CONFIG_UART1_ENABLE 0
877 #endif
878
879 #if defined CONFIG_UA1_FIFO1
880 #define CFG_UA1_FIFO 1
881 #elif defined CONFIG_UA1_FIFO2
882 #define CFG_UA1_FIFO 2
883 #elif defined CONFIG_UA1_FIFO4
884 #define CFG_UA1_FIFO 4
885 #elif defined CONFIG_UA1_FIFO8
886 #define CFG_UA1_FIFO 8
887 #elif defined CONFIG_UA1_FIFO16
888 #define CFG_UA1_FIFO 16
889 #elif defined CONFIG_UA1_FIFO32
890 #define CFG_UA1_FIFO 32
891 #else
892 #define CFG_UA1_FIFO 1
893 #endif
894
895 #ifndef CONFIG_IRQ3_ENABLE
896 #define CONFIG_IRQ3_ENABLE 0
897 #endif
898 #ifndef CONFIG_IRQ3_NSEC
899 #define CONFIG_IRQ3_NSEC 0
900 #endif
901 #ifndef CONFIG_GPT_ENABLE
902 #define CONFIG_GPT_ENABLE 0
903 #endif
904
905 #ifndef CONFIG_GPT_NTIM
906 #define CONFIG_GPT_NTIM 1
907 #endif
908
909 #ifndef CONFIG_GPT_SW
910 #define CONFIG_GPT_SW 8
911 #endif
912
913 #ifndef CONFIG_GPT_TW
914 #define CONFIG_GPT_TW 8
915 #endif
916
917 #ifndef CONFIG_GPT_IRQ
918 #define CONFIG_GPT_IRQ 8
919 #endif
920
921 #ifndef CONFIG_GPT_SEPIRQ
922 #define CONFIG_GPT_SEPIRQ 0
923 #endif
924 #ifndef CONFIG_GPT_ENABLE
925 #define CONFIG_GPT_ENABLE 0
926 #endif
927
928 #ifndef CONFIG_GPT_NTIM
929 #define CONFIG_GPT_NTIM 1
930 #endif
931
932 #ifndef CONFIG_GPT_SW
933 #define CONFIG_GPT_SW 8
934 #endif
935
936 #ifndef CONFIG_GPT_TW
937 #define CONFIG_GPT_TW 8
938 #endif
939
940 #ifndef CONFIG_GPT_IRQ
941 #define CONFIG_GPT_IRQ 8
942 #endif
943
944 #ifndef CONFIG_GPT_SEPIRQ
945 #define CONFIG_GPT_SEPIRQ 0
946 #endif
947
948 #ifndef CONFIG_GPT_WDOGEN
949 #define CONFIG_GPT_WDOGEN 0
950 #endif
951
952 #ifndef CONFIG_GPT_WDOG
953 #define CONFIG_GPT_WDOG 0
954 #endif
955
956 #ifndef CONFIG_GRGPIO_ENABLE
957 #define CONFIG_GRGPIO_ENABLE 0
958 #endif
959 #ifndef CONFIG_GRGPIO_IMASK
960 #define CONFIG_GRGPIO_IMASK 0000
961 #endif
962 #ifndef CONFIG_GRGPIO_WIDTH
963 #define CONFIG_GRGPIO_WIDTH 1
964 #endif
965
966 #ifndef CONFIG_VGA_ENABLE
967 #define CONFIG_VGA_ENABLE 0
968 #endif
969 #ifndef CONFIG_SVGA_ENABLE
970 #define CONFIG_SVGA_ENABLE 0
971 #endif
972 #ifndef CONFIG_KBD_ENABLE
973 #define CONFIG_KBD_ENABLE 0
974 #endif
975
976
977 #ifndef CONFIG_SPIMCTRL
978 #define CONFIG_SPIMCTRL 0
979 #endif
980
981 #ifndef CONFIG_SPIMCTRL_SDCARD
982 #define CONFIG_SPIMCTRL_SDCARD 0
983 #endif
984
985 #ifndef CONFIG_SPIMCTRL_READCMD
986 #define CONFIG_SPIMCTRL_READCMD 0
987 #endif
988
989 #ifndef CONFIG_SPIMCTRL_DUMMYBYTE
990 #define CONFIG_SPIMCTRL_DUMMYBYTE 0
991 #endif
992
993 #ifndef CONFIG_SPIMCTRL_DUALOUTPUT
994 #define CONFIG_SPIMCTRL_DUALOUTPUT 0
995 #endif
996
997 #ifndef CONFIG_SPIMCTRL_SCALER
998 #define CONFIG_SPIMCTRL_SCALER 1
999 #endif
1000
1001 #ifndef CONFIG_SPIMCTRL_ASCALER
1002 #define CONFIG_SPIMCTRL_ASCALER 1
1003 #endif
1004
1005 #ifndef CONFIG_SPIMCTRL_PWRUPCNT
1006 #define CONFIG_SPIMCTRL_PWRUPCNT 0
1007 #endif
1008 #ifndef CONFIG_SPICTRL_ENABLE
1009 #define CONFIG_SPICTRL_ENABLE 0
1010 #endif
1011 #ifndef CONFIG_SPICTRL_NUM
1012 #define CONFIG_SPICTRL_NUM 1
1013 #endif
1014 #ifndef CONFIG_SPICTRL_SLVS
1015 #define CONFIG_SPICTRL_SLVS 1
1016 #endif
1017 #ifndef CONFIG_SPICTRL_FIFO
1018 #define CONFIG_SPICTRL_FIFO 1
1019 #endif
1020 #ifndef CONFIG_SPICTRL_SLVREG
1021 #define CONFIG_SPICTRL_SLVREG 0
1022 #endif
1023 #ifndef CONFIG_SPICTRL_ODMODE
1024 #define CONFIG_SPICTRL_ODMODE 0
1025 #endif
1026 #ifndef CONFIG_SPICTRL_AM
1027 #define CONFIG_SPICTRL_AM 0
1028 #endif
1029 #ifndef CONFIG_SPICTRL_ASEL
1030 #define CONFIG_SPICTRL_ASEL 0
1031 #endif
1032 #ifndef CONFIG_SPICTRL_TWEN
1033 #define CONFIG_SPICTRL_TWEN 0
1034 #endif
1035 #ifndef CONFIG_SPICTRL_MAXWLEN
1036 #define CONFIG_SPICTRL_MAXWLEN 0
1037 #endif
1038 #ifndef CONFIG_SPICTRL_SYNCRAM
1039 #define CONFIG_SPICTRL_SYNCRAM 0
1040 #endif
1041 #if defined(CONFIG_SPICTRL_DMRFT)
1042 #define CONFIG_SPICTRL_FT 1
1043 #elif defined(CONFIG_SPICTRL_TMRFT)
1044 #define CONFIG_SPICTRL_FT 2
1045 #else
1046 #define CONFIG_SPICTRL_FT 0
1047 #endif
1048
1049 #ifndef CONFIG_DEBUG_UART
1050 #define CONFIG_DEBUG_UART 0
1051 #endif
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_AXDSP
14 #define CONFIG_SYN_TECH axdsp
15 #elif defined CONFIG_SYN_PROASICPLUS
16 #define CONFIG_SYN_TECH proasic
17 #elif defined CONFIG_SYN_ALTERA
18 #define CONFIG_SYN_TECH altera
19 #elif defined CONFIG_SYN_STRATIX
20 #define CONFIG_SYN_TECH stratix1
21 #elif defined CONFIG_SYN_STRATIXII
22 #define CONFIG_SYN_TECH stratix2
23 #elif defined CONFIG_SYN_STRATIXIII
24 #define CONFIG_SYN_TECH stratix3
25 #elif defined CONFIG_SYN_CYCLONEIII
26 #define CONFIG_SYN_TECH cyclone3
27 #elif defined CONFIG_SYN_EASIC45
28 #define CONFIG_SYN_TECH easic45
29 #elif defined CONFIG_SYN_EASIC90
30 #define CONFIG_SYN_TECH easic90
31 #elif defined CONFIG_SYN_IHP25
32 #define CONFIG_SYN_TECH ihp25
33 #elif defined CONFIG_SYN_IHP25RH
34 #define CONFIG_SYN_TECH ihp25rh
35 #elif defined CONFIG_SYN_CMOS9SF
36 #define CONFIG_SYN_TECH cmos9sf
37 #elif defined CONFIG_SYN_LATTICE
38 #define CONFIG_SYN_TECH lattice
39 #elif defined CONFIG_SYN_ECLIPSE
40 #define CONFIG_SYN_TECH eclipse
41 #elif defined CONFIG_SYN_PEREGRINE
42 #define CONFIG_SYN_TECH peregrine
43 #elif defined CONFIG_SYN_PROASIC
44 #define CONFIG_SYN_TECH proasic
45 #elif defined CONFIG_SYN_PROASIC3
46 #define CONFIG_SYN_TECH apa3
47 #elif defined CONFIG_SYN_PROASIC3E
48 #define CONFIG_SYN_TECH apa3e
49 #elif defined CONFIG_SYN_PROASIC3L
50 #define CONFIG_SYN_TECH apa3l
51 #elif defined CONFIG_SYN_IGLOO
52 #define CONFIG_SYN_TECH apa3
53 #elif defined CONFIG_SYN_FUSION
54 #define CONFIG_SYN_TECH actfus
55 #elif defined CONFIG_SYN_SPARTAN2
56 #define CONFIG_SYN_TECH virtex
57 #elif defined CONFIG_SYN_VIRTEX
58 #define CONFIG_SYN_TECH virtex
59 #elif defined CONFIG_SYN_VIRTEXE
60 #define CONFIG_SYN_TECH virtex
61 #elif defined CONFIG_SYN_SPARTAN3
62 #define CONFIG_SYN_TECH spartan3
63 #elif defined CONFIG_SYN_SPARTAN3E
64 #define CONFIG_SYN_TECH spartan3e
65 #elif defined CONFIG_SYN_SPARTAN6
66 #define CONFIG_SYN_TECH spartan6
67 #elif defined CONFIG_SYN_VIRTEX2
68 #define CONFIG_SYN_TECH virtex2
69 #elif defined CONFIG_SYN_VIRTEX4
70 #define CONFIG_SYN_TECH virtex4
71 #elif defined CONFIG_SYN_VIRTEX5
72 #define CONFIG_SYN_TECH virtex5
73 #elif defined CONFIG_SYN_VIRTEX6
74 #define CONFIG_SYN_TECH virtex6
75 #elif defined CONFIG_SYN_RH_LIB18T
76 #define CONFIG_SYN_TECH rhlib18t
77 #elif defined CONFIG_SYN_SMIC13
78 #define CONFIG_SYN_TECH smic013
79 #elif defined CONFIG_SYN_UT025CRH
80 #define CONFIG_SYN_TECH ut25
81 #elif defined CONFIG_SYN_UT130HBD
82 #define CONFIG_SYN_TECH ut130
83 #elif defined CONFIG_SYN_UT90NHBD
84 #define CONFIG_SYN_TECH ut90
85 #elif defined CONFIG_SYN_TSMC90
86 #define CONFIG_SYN_TECH tsmc90
87 #elif defined CONFIG_SYN_TM65GPLUS
88 #define CONFIG_SYN_TECH tm65gpl
89 #elif defined CONFIG_SYN_CUSTOM1
90 #define CONFIG_SYN_TECH custom1
91 #else
92 #error "unknown target technology"
93 #endif
94
95 #if defined CONFIG_SYN_INFER_RAM
96 #define CFG_RAM_TECH inferred
97 #elif defined CONFIG_MEM_UMC
98 #define CFG_RAM_TECH umc
99 #elif defined CONFIG_MEM_RHUMC
100 #define CFG_RAM_TECH rhumc
101 #elif defined CONFIG_MEM_VIRAGE
102 #define CFG_RAM_TECH memvirage
103 #elif defined CONFIG_MEM_ARTISAN
104 #define CFG_RAM_TECH memartisan
105 #elif defined CONFIG_MEM_CUSTOM1
106 #define CFG_RAM_TECH custom1
107 #elif defined CONFIG_MEM_VIRAGE90
108 #define CFG_RAM_TECH memvirage90
109 #elif defined CONFIG_MEM_INFERRED
110 #define CFG_RAM_TECH inferred
111 #else
112 #define CFG_RAM_TECH CONFIG_SYN_TECH
113 #endif
114
115 #if defined CONFIG_SYN_INFER_PADS
116 #define CFG_PAD_TECH inferred
117 #else
118 #define CFG_PAD_TECH CONFIG_SYN_TECH
119 #endif
120
121 #ifndef CONFIG_SYN_NO_ASYNC
122 #define CONFIG_SYN_NO_ASYNC 0
123 #endif
124
125 #ifndef CONFIG_SYN_SCAN
126 #define CONFIG_SYN_SCAN 0
127 #endif
128
129
130 #if defined CONFIG_CLK_ALTDLL
131 #define CFG_CLK_TECH CONFIG_SYN_TECH
132 #elif defined CONFIG_CLK_HCLKBUF
133 #define CFG_CLK_TECH axcel
134 #elif defined CONFIG_CLK_LATDLL
135 #define CFG_CLK_TECH lattice
136 #elif defined CONFIG_CLK_PRO3PLL
137 #define CFG_CLK_TECH apa3
138 #elif defined CONFIG_CLK_PRO3EPLL
139 #define CFG_CLK_TECH apa3e
140 #elif defined CONFIG_CLK_PRO3LPLL
141 #define CFG_CLK_TECH apa3l
142 #elif defined CONFIG_CLK_FUSPLL
143 #define CFG_CLK_TECH actfus
144 #elif defined CONFIG_CLK_CLKDLL
145 #define CFG_CLK_TECH virtex
146 #elif defined CONFIG_CLK_DCM
147 #define CFG_CLK_TECH CONFIG_SYN_TECH
148 #elif defined CONFIG_CLK_LIB18T
149 #define CFG_CLK_TECH rhlib18t
150 #elif defined CONFIG_CLK_RHUMC
151 #define CFG_CLK_TECH rhumc
152 #elif defined CONFIG_CLK_UT130HBD
153 #define CFG_CLK_TECH ut130
154 #else
155 #define CFG_CLK_TECH inferred
156 #endif
157
158 #ifndef CONFIG_CLK_MUL
159 #define CONFIG_CLK_MUL 2
160 #endif
161
162 #ifndef CONFIG_CLK_DIV
163 #define CONFIG_CLK_DIV 2
164 #endif
165
166 #ifndef CONFIG_OCLK_DIV
167 #define CONFIG_OCLK_DIV 1
168 #endif
169
170 #ifndef CONFIG_OCLKB_DIV
171 #define CONFIG_OCLKB_DIV 0
172 #endif
173
174 #ifndef CONFIG_OCLKC_DIV
175 #define CONFIG_OCLKC_DIV 0
176 #endif
177
178 #ifndef CONFIG_PCI_CLKDLL
179 #define CONFIG_PCI_CLKDLL 0
180 #endif
181
182 #ifndef CONFIG_PCI_SYSCLK
183 #define CONFIG_PCI_SYSCLK 0
184 #endif
185
186 #ifndef CONFIG_CLK_NOFB
187 #define CONFIG_CLK_NOFB 0
188 #endif
189 #ifndef CONFIG_LEON3
190 #define CONFIG_LEON3 0
191 #endif
192
193 #ifndef CONFIG_PROC_NUM
194 #define CONFIG_PROC_NUM 1
195 #endif
196
197 #ifndef CONFIG_IU_NWINDOWS
198 #define CONFIG_IU_NWINDOWS 8
199 #endif
200
201 #ifndef CONFIG_IU_RSTADDR
202 #define CONFIG_IU_RSTADDR 8
203 #endif
204
205 #ifndef CONFIG_IU_LDELAY
206 #define CONFIG_IU_LDELAY 1
207 #endif
208
209 #ifndef CONFIG_IU_WATCHPOINTS
210 #define CONFIG_IU_WATCHPOINTS 0
211 #endif
212
213 #ifdef CONFIG_IU_V8MULDIV
214 #ifdef CONFIG_IU_MUL_LATENCY_4
215 #define CFG_IU_V8 1
216 #elif defined CONFIG_IU_MUL_LATENCY_5
217 #define CFG_IU_V8 2
218 #elif defined CONFIG_IU_MUL_LATENCY_2
219 #define CFG_IU_V8 16#32#
220 #endif
221 #else
222 #define CFG_IU_V8 0
223 #endif
224
225 #ifdef CONFIG_IU_MUL_MODGEN
226 #define CFG_IU_MUL_STRUCT 1
227 #elif defined CONFIG_IU_MUL_TECHSPEC
228 #define CFG_IU_MUL_STRUCT 2
229 #elif defined CONFIG_IU_MUL_DW
230 #define CFG_IU_MUL_STRUCT 3
231 #else
232 #define CFG_IU_MUL_STRUCT 0
233 #endif
234
235 #ifndef CONFIG_PWD
236 #define CONFIG_PWD 0
237 #endif
238
239 #ifndef CONFIG_IU_MUL_MAC
240 #define CONFIG_IU_MUL_MAC 0
241 #endif
242
243 #ifndef CONFIG_IU_BP
244 #define CONFIG_IU_BP 0
245 #endif
246
247 #ifndef CONFIG_NOTAG
248 #define CONFIG_NOTAG 0
249 #endif
250
251 #ifndef CONFIG_IU_SVT
252 #define CONFIG_IU_SVT 0
253 #endif
254
255 #if defined CONFIG_FPU_GRFPC1
256 #define CONFIG_FPU_GRFPC 1
257 #elif defined CONFIG_FPU_GRFPC2
258 #define CONFIG_FPU_GRFPC 2
259 #else
260 #define CONFIG_FPU_GRFPC 0
261 #endif
262
263 #if defined CONFIG_FPU_GRFPU_INFMUL
264 #define CONFIG_FPU_GRFPU_MUL 0
265 #elif defined CONFIG_FPU_GRFPU_DWMUL
266 #define CONFIG_FPU_GRFPU_MUL 1
267 #elif defined CONFIG_FPU_GRFPU_MODGEN
268 #define CONFIG_FPU_GRFPU_MUL 2
269 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
270 #define CONFIG_FPU_GRFPU_MUL 3
271 #else
272 #define CONFIG_FPU_GRFPU_MUL 0
273 #endif
274
275 #if defined CONFIG_FPU_GRFPU_SH
276 #define CONFIG_FPU_GRFPU_SHARED 1
277 #else
278 #define CONFIG_FPU_GRFPU_SHARED 0
279 #endif
280
281 #if defined CONFIG_FPU_GRFPU
282 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
283 #elif defined CONFIG_FPU_MEIKO
284 #define CONFIG_FPU 15
285 #elif defined CONFIG_FPU_GRFPULITE
286 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
287 #else
288 #define CONFIG_FPU 0
289 #endif
290
291 #ifndef CONFIG_FPU_NETLIST
292 #define CONFIG_FPU_NETLIST 0
293 #endif
294
295 #ifndef CONFIG_ICACHE_ENABLE
296 #define CONFIG_ICACHE_ENABLE 0
297 #endif
298
299 #if defined CONFIG_ICACHE_ASSO1
300 #define CFG_IU_ISETS 1
301 #elif defined CONFIG_ICACHE_ASSO2
302 #define CFG_IU_ISETS 2
303 #elif defined CONFIG_ICACHE_ASSO3
304 #define CFG_IU_ISETS 3
305 #elif defined CONFIG_ICACHE_ASSO4
306 #define CFG_IU_ISETS 4
307 #else
308 #define CFG_IU_ISETS 1
309 #endif
310
311 #if defined CONFIG_ICACHE_SZ1
312 #define CFG_ICACHE_SZ 1
313 #elif defined CONFIG_ICACHE_SZ2
314 #define CFG_ICACHE_SZ 2
315 #elif defined CONFIG_ICACHE_SZ4
316 #define CFG_ICACHE_SZ 4
317 #elif defined CONFIG_ICACHE_SZ8
318 #define CFG_ICACHE_SZ 8
319 #elif defined CONFIG_ICACHE_SZ16
320 #define CFG_ICACHE_SZ 16
321 #elif defined CONFIG_ICACHE_SZ32
322 #define CFG_ICACHE_SZ 32
323 #elif defined CONFIG_ICACHE_SZ64
324 #define CFG_ICACHE_SZ 64
325 #elif defined CONFIG_ICACHE_SZ128
326 #define CFG_ICACHE_SZ 128
327 #elif defined CONFIG_ICACHE_SZ256
328 #define CFG_ICACHE_SZ 256
329 #else
330 #define CFG_ICACHE_SZ 1
331 #endif
332
333 #ifdef CONFIG_ICACHE_LZ16
334 #define CFG_ILINE_SZ 4
335 #else
336 #define CFG_ILINE_SZ 8
337 #endif
338
339 #if defined CONFIG_ICACHE_ALGODIR
340 #define CFG_ICACHE_ALGORND 3
341 #elif defined CONFIG_ICACHE_ALGORND
342 #define CFG_ICACHE_ALGORND 2
343 #elif defined CONFIG_ICACHE_ALGOLRR
344 #define CFG_ICACHE_ALGORND 1
345 #else
346 #define CFG_ICACHE_ALGORND 0
347 #endif
348
349 #ifndef CONFIG_ICACHE_LOCK
350 #define CONFIG_ICACHE_LOCK 0
351 #endif
352
353 #ifndef CONFIG_ICACHE_LRAM
354 #define CONFIG_ICACHE_LRAM 0
355 #endif
356
357 #ifndef CONFIG_ICACHE_LRSTART
358 #define CONFIG_ICACHE_LRSTART 8E
359 #endif
360
361 #if defined CONFIG_ICACHE_LRAM_SZ2
362 #define CFG_ILRAM_SIZE 2
363 #elif defined CONFIG_ICACHE_LRAM_SZ4
364 #define CFG_ILRAM_SIZE 4
365 #elif defined CONFIG_ICACHE_LRAM_SZ8
366 #define CFG_ILRAM_SIZE 8
367 #elif defined CONFIG_ICACHE_LRAM_SZ16
368 #define CFG_ILRAM_SIZE 16
369 #elif defined CONFIG_ICACHE_LRAM_SZ32
370 #define CFG_ILRAM_SIZE 32
371 #elif defined CONFIG_ICACHE_LRAM_SZ64
372 #define CFG_ILRAM_SIZE 64
373 #elif defined CONFIG_ICACHE_LRAM_SZ128
374 #define CFG_ILRAM_SIZE 128
375 #elif defined CONFIG_ICACHE_LRAM_SZ256
376 #define CFG_ILRAM_SIZE 256
377 #else
378 #define CFG_ILRAM_SIZE 1
379 #endif
380
381
382 #ifndef CONFIG_DCACHE_ENABLE
383 #define CONFIG_DCACHE_ENABLE 0
384 #endif
385
386 #if defined CONFIG_DCACHE_ASSO1
387 #define CFG_IU_DSETS 1
388 #elif defined CONFIG_DCACHE_ASSO2
389 #define CFG_IU_DSETS 2
390 #elif defined CONFIG_DCACHE_ASSO3
391 #define CFG_IU_DSETS 3
392 #elif defined CONFIG_DCACHE_ASSO4
393 #define CFG_IU_DSETS 4
394 #else
395 #define CFG_IU_DSETS 1
396 #endif
397
398 #if defined CONFIG_DCACHE_SZ1
399 #define CFG_DCACHE_SZ 1
400 #elif defined CONFIG_DCACHE_SZ2
401 #define CFG_DCACHE_SZ 2
402 #elif defined CONFIG_DCACHE_SZ4
403 #define CFG_DCACHE_SZ 4
404 #elif defined CONFIG_DCACHE_SZ8
405 #define CFG_DCACHE_SZ 8
406 #elif defined CONFIG_DCACHE_SZ16
407 #define CFG_DCACHE_SZ 16
408 #elif defined CONFIG_DCACHE_SZ32
409 #define CFG_DCACHE_SZ 32
410 #elif defined CONFIG_DCACHE_SZ64
411 #define CFG_DCACHE_SZ 64
412 #elif defined CONFIG_DCACHE_SZ128
413 #define CFG_DCACHE_SZ 128
414 #elif defined CONFIG_DCACHE_SZ256
415 #define CFG_DCACHE_SZ 256
416 #else
417 #define CFG_DCACHE_SZ 1
418 #endif
419
420 #ifdef CONFIG_DCACHE_LZ16
421 #define CFG_DLINE_SZ 4
422 #else
423 #define CFG_DLINE_SZ 8
424 #endif
425
426 #if defined CONFIG_DCACHE_ALGODIR
427 #define CFG_DCACHE_ALGORND 3
428 #elif defined CONFIG_DCACHE_ALGORND
429 #define CFG_DCACHE_ALGORND 2
430 #elif defined CONFIG_DCACHE_ALGOLRR
431 #define CFG_DCACHE_ALGORND 1
432 #else
433 #define CFG_DCACHE_ALGORND 0
434 #endif
435
436 #ifndef CONFIG_DCACHE_LOCK
437 #define CONFIG_DCACHE_LOCK 0
438 #endif
439
440 #ifndef CONFIG_DCACHE_SNOOP
441 #define CONFIG_DCACHE_SNOOP 0
442 #endif
443
444 #ifndef CONFIG_DCACHE_SNOOP_FAST
445 #define CONFIG_DCACHE_SNOOP_FAST 0
446 #endif
447
448 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
449 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
450 #endif
451
452 #ifndef CONFIG_CACHE_FIXED
453 #define CONFIG_CACHE_FIXED 0
454 #endif
455
456 #ifndef CONFIG_DCACHE_LRAM
457 #define CONFIG_DCACHE_LRAM 0
458 #endif
459
460 #ifndef CONFIG_DCACHE_LRSTART
461 #define CONFIG_DCACHE_LRSTART 8F
462 #endif
463
464 #if defined CONFIG_DCACHE_LRAM_SZ2
465 #define CFG_DLRAM_SIZE 2
466 #elif defined CONFIG_DCACHE_LRAM_SZ4
467 #define CFG_DLRAM_SIZE 4
468 #elif defined CONFIG_DCACHE_LRAM_SZ8
469 #define CFG_DLRAM_SIZE 8
470 #elif defined CONFIG_DCACHE_LRAM_SZ16
471 #define CFG_DLRAM_SIZE 16
472 #elif defined CONFIG_DCACHE_LRAM_SZ32
473 #define CFG_DLRAM_SIZE 32
474 #elif defined CONFIG_DCACHE_LRAM_SZ64
475 #define CFG_DLRAM_SIZE 64
476 #elif defined CONFIG_DCACHE_LRAM_SZ128
477 #define CFG_DLRAM_SIZE 128
478 #elif defined CONFIG_DCACHE_LRAM_SZ256
479 #define CFG_DLRAM_SIZE 256
480 #else
481 #define CFG_DLRAM_SIZE 1
482 #endif
483
484 #if defined CONFIG_MMU_PAGE_4K
485 #define CONFIG_MMU_PAGE 0
486 #elif defined CONFIG_MMU_PAGE_8K
487 #define CONFIG_MMU_PAGE 1
488 #elif defined CONFIG_MMU_PAGE_16K
489 #define CONFIG_MMU_PAGE 2
490 #elif defined CONFIG_MMU_PAGE_32K
491 #define CONFIG_MMU_PAGE 3
492 #elif defined CONFIG_MMU_PAGE_PROG
493 #define CONFIG_MMU_PAGE 4
494 #else
495 #define CONFIG_MMU_PAGE 0
496 #endif
497
498 #ifdef CONFIG_MMU_ENABLE
499 #define CONFIG_MMUEN 1
500
501 #ifdef CONFIG_MMU_SPLIT
502 #define CONFIG_TLB_TYPE 0
503 #endif
504 #ifdef CONFIG_MMU_COMBINED
505 #define CONFIG_TLB_TYPE 1
506 #endif
507
508 #ifdef CONFIG_MMU_REPARRAY
509 #define CONFIG_TLB_REP 0
510 #endif
511 #ifdef CONFIG_MMU_REPINCREMENT
512 #define CONFIG_TLB_REP 1
513 #endif
514
515 #ifdef CONFIG_MMU_I2
516 #define CONFIG_ITLBNUM 2
517 #endif
518 #ifdef CONFIG_MMU_I4
519 #define CONFIG_ITLBNUM 4
520 #endif
521 #ifdef CONFIG_MMU_I8
522 #define CONFIG_ITLBNUM 8
523 #endif
524 #ifdef CONFIG_MMU_I16
525 #define CONFIG_ITLBNUM 16
526 #endif
527 #ifdef CONFIG_MMU_I32
528 #define CONFIG_ITLBNUM 32
529 #endif
530
531 #define CONFIG_DTLBNUM 2
532 #ifdef CONFIG_MMU_D2
533 #undef CONFIG_DTLBNUM
534 #define CONFIG_DTLBNUM 2
535 #endif
536 #ifdef CONFIG_MMU_D4
537 #undef CONFIG_DTLBNUM
538 #define CONFIG_DTLBNUM 4
539 #endif
540 #ifdef CONFIG_MMU_D8
541 #undef CONFIG_DTLBNUM
542 #define CONFIG_DTLBNUM 8
543 #endif
544 #ifdef CONFIG_MMU_D16
545 #undef CONFIG_DTLBNUM
546 #define CONFIG_DTLBNUM 16
547 #endif
548 #ifdef CONFIG_MMU_D32
549 #undef CONFIG_DTLBNUM
550 #define CONFIG_DTLBNUM 32
551 #endif
552 #ifdef CONFIG_MMU_FASTWB
553 #define CFG_MMU_FASTWB 1
554 #else
555 #define CFG_MMU_FASTWB 0
556 #endif
557
558 #else
559 #define CONFIG_MMUEN 0
560 #define CONFIG_ITLBNUM 2
561 #define CONFIG_DTLBNUM 2
562 #define CONFIG_TLB_TYPE 1
563 #define CONFIG_TLB_REP 1
564 #define CFG_MMU_FASTWB 0
565 #endif
566
567 #ifndef CONFIG_DSU_ENABLE
568 #define CONFIG_DSU_ENABLE 0
569 #endif
570
571 #if defined CONFIG_DSU_ITRACESZ1
572 #define CFG_DSU_ITB 1
573 #elif CONFIG_DSU_ITRACESZ2
574 #define CFG_DSU_ITB 2
575 #elif CONFIG_DSU_ITRACESZ4
576 #define CFG_DSU_ITB 4
577 #elif CONFIG_DSU_ITRACESZ8
578 #define CFG_DSU_ITB 8
579 #elif CONFIG_DSU_ITRACESZ16
580 #define CFG_DSU_ITB 16
581 #else
582 #define CFG_DSU_ITB 0
583 #endif
584
585 #if defined CONFIG_DSU_ATRACESZ1
586 #define CFG_DSU_ATB 1
587 #elif CONFIG_DSU_ATRACESZ2
588 #define CFG_DSU_ATB 2
589 #elif CONFIG_DSU_ATRACESZ4
590 #define CFG_DSU_ATB 4
591 #elif CONFIG_DSU_ATRACESZ8
592 #define CFG_DSU_ATB 8
593 #elif CONFIG_DSU_ATRACESZ16
594 #define CFG_DSU_ATB 16
595 #else
596 #define CFG_DSU_ATB 0
597 #endif
598
599 #ifndef CONFIG_LEON3FT_EN
600 #define CONFIG_LEON3FT_EN 0
601 #endif
602
603 #if defined CONFIG_IUFT_PAR
604 #define CONFIG_IUFT_EN 1
605 #elif defined CONFIG_IUFT_DMR
606 #define CONFIG_IUFT_EN 2
607 #elif defined CONFIG_IUFT_BCH
608 #define CONFIG_IUFT_EN 3
609 #elif defined CONFIG_IUFT_TMR
610 #define CONFIG_IUFT_EN 4
611 #else
612 #define CONFIG_IUFT_EN 0
613 #endif
614 #ifndef CONFIG_RF_ERRINJ
615 #define CONFIG_RF_ERRINJ 0
616 #endif
617
618 #ifndef CONFIG_FPUFT_EN
619 #define CONFIG_FPUFT 0
620 #else
621 #ifdef CONFIG_FPU_GRFPU
622 #define CONFIG_FPUFT 2
623 #else
624 #define CONFIG_FPUFT 1
625 #endif
626 #endif
627
628 #ifndef CONFIG_CACHE_FT_EN
629 #define CONFIG_CACHE_FT_EN 0
630 #endif
631 #ifndef CONFIG_CACHE_ERRINJ
632 #define CONFIG_CACHE_ERRINJ 0
633 #endif
634
635 #ifndef CONFIG_LEON3_NETLIST
636 #define CONFIG_LEON3_NETLIST 0
637 #endif
638
639 #ifdef CONFIG_DEBUG_PC32
640 #define CFG_DEBUG_PC32 0
641 #else
642 #define CFG_DEBUG_PC32 2
643 #endif
644 #ifndef CONFIG_IU_DISAS
645 #define CONFIG_IU_DISAS 0
646 #endif
647 #ifndef CONFIG_IU_DISAS_NET
648 #define CONFIG_IU_DISAS_NET 0
649 #endif
650
651
652 #ifndef CONFIG_AHB_SPLIT
653 #define CONFIG_AHB_SPLIT 0
654 #endif
655
656 #ifndef CONFIG_AHB_RROBIN
657 #define CONFIG_AHB_RROBIN 0
658 #endif
659
660 #ifndef CONFIG_AHB_IOADDR
661 #define CONFIG_AHB_IOADDR FFF
662 #endif
663
664 #ifndef CONFIG_APB_HADDR
665 #define CONFIG_APB_HADDR 800
666 #endif
667
668 #ifndef CONFIG_AHB_MON
669 #define CONFIG_AHB_MON 0
670 #endif
671
672 #ifndef CONFIG_AHB_MONERR
673 #define CONFIG_AHB_MONERR 0
674 #endif
675
676 #ifndef CONFIG_AHB_MONWAR
677 #define CONFIG_AHB_MONWAR 0
678 #endif
679
680 #ifndef CONFIG_AHB_DTRACE
681 #define CONFIG_AHB_DTRACE 0
682 #endif
683
684 #ifndef CONFIG_DSU_JTAG
685 #define CONFIG_DSU_JTAG 0
686 #endif
687
688 #ifndef CONFIG_DSU_ETH
689 #define CONFIG_DSU_ETH 0
690 #endif
691
692 #ifndef CONFIG_DSU_IPMSB
693 #define CONFIG_DSU_IPMSB C0A8
694 #endif
695
696 #ifndef CONFIG_DSU_IPLSB
697 #define CONFIG_DSU_IPLSB 0033
698 #endif
699
700 #ifndef CONFIG_DSU_ETHMSB
701 #define CONFIG_DSU_ETHMSB 020000
702 #endif
703
704 #ifndef CONFIG_DSU_ETHLSB
705 #define CONFIG_DSU_ETHLSB 000009
706 #endif
707
708 #if defined CONFIG_DSU_ETHSZ1
709 #define CFG_DSU_ETHB 1
710 #elif CONFIG_DSU_ETHSZ2
711 #define CFG_DSU_ETHB 2
712 #elif CONFIG_DSU_ETHSZ4
713 #define CFG_DSU_ETHB 4
714 #elif CONFIG_DSU_ETHSZ8
715 #define CFG_DSU_ETHB 8
716 #elif CONFIG_DSU_ETHSZ16
717 #define CFG_DSU_ETHB 16
718 #elif CONFIG_DSU_ETHSZ32
719 #define CFG_DSU_ETHB 32
720 #else
721 #define CFG_DSU_ETHB 1
722 #endif
723
724 #ifndef CONFIG_DSU_ETH_PROG
725 #define CONFIG_DSU_ETH_PROG 0
726 #endif
727
728 #ifndef CONFIG_DSU_ETH_DIS
729 #define CONFIG_DSU_ETH_DIS 0
730 #endif
731
732 #ifndef CONFIG_MCTRL_LEON2
733 #define CONFIG_MCTRL_LEON2 0
734 #endif
735
736 #ifndef CONFIG_MCTRL_SDRAM
737 #define CONFIG_MCTRL_SDRAM 0
738 #endif
739
740 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
741 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
742 #endif
743
744 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
745 #define CONFIG_MCTRL_SDRAM_INVCLK 0
746 #endif
747
748 #ifndef CONFIG_MCTRL_SDRAM_BUS64
749 #define CONFIG_MCTRL_SDRAM_BUS64 0
750 #endif
751
752 #ifndef CONFIG_MCTRL_8BIT
753 #define CONFIG_MCTRL_8BIT 0
754 #endif
755
756 #ifndef CONFIG_MCTRL_16BIT
757 #define CONFIG_MCTRL_16BIT 0
758 #endif
759
760 #ifndef CONFIG_MCTRL_5CS
761 #define CONFIG_MCTRL_5CS 0
762 #endif
763
764 #ifndef CONFIG_MCTRL_EDAC
765 #define CONFIG_MCTRL_EDAC 0
766 #endif
767
768 #ifndef CONFIG_MCTRL_PAGE
769 #define CONFIG_MCTRL_PAGE 0
770 #endif
771
772 #ifndef CONFIG_MCTRL_PROGPAGE
773 #define CONFIG_MCTRL_PROGPAGE 0
774 #endif
775
776
777 #ifndef CONFIG_MIG_DDR2
778 #define CONFIG_MIG_DDR2 0
779 #endif
780
781 #ifndef CONFIG_MIG_RANKS
782 #define CONFIG_MIG_RANKS 1
783 #endif
784
785 #ifndef CONFIG_MIG_COLBITS
786 #define CONFIG_MIG_COLBITS 10
787 #endif
788
789 #ifndef CONFIG_MIG_ROWBITS
790 #define CONFIG_MIG_ROWBITS 13
791 #endif
792
793 #ifndef CONFIG_MIG_BANKBITS
794 #define CONFIG_MIG_BANKBITS 2
795 #endif
796
797 #ifndef CONFIG_MIG_HMASK
798 #define CONFIG_MIG_HMASK F00
799 #endif
800 #ifndef CONFIG_AHBSTAT_ENABLE
801 #define CONFIG_AHBSTAT_ENABLE 0
802 #endif
803
804 #ifndef CONFIG_AHBSTAT_NFTSLV
805 #define CONFIG_AHBSTAT_NFTSLV 1
806 #endif
807
808 #ifndef CONFIG_AHBROM_ENABLE
809 #define CONFIG_AHBROM_ENABLE 0
810 #endif
811
812 #ifndef CONFIG_AHBROM_START
813 #define CONFIG_AHBROM_START 000
814 #endif
815
816 #ifndef CONFIG_AHBROM_PIPE
817 #define CONFIG_AHBROM_PIPE 0
818 #endif
819
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
821 #define CONFIG_ROM_START 100
822 #else
823 #define CONFIG_ROM_START 000
824 #endif
825
826
827 #ifndef CONFIG_AHBRAM_ENABLE
828 #define CONFIG_AHBRAM_ENABLE 0
829 #endif
830
831 #ifndef CONFIG_AHBRAM_START
832 #define CONFIG_AHBRAM_START A00
833 #endif
834
835 #if defined CONFIG_AHBRAM_SZ1
836 #define CFG_AHBRAMSZ 1
837 #elif CONFIG_AHBRAM_SZ2
838 #define CFG_AHBRAMSZ 2
839 #elif CONFIG_AHBRAM_SZ4
840 #define CFG_AHBRAMSZ 4
841 #elif CONFIG_AHBRAM_SZ8
842 #define CFG_AHBRAMSZ 8
843 #elif CONFIG_AHBRAM_SZ16
844 #define CFG_AHBRAMSZ 16
845 #elif CONFIG_AHBRAM_SZ32
846 #define CFG_AHBRAMSZ 32
847 #elif CONFIG_AHBRAM_SZ64
848 #define CFG_AHBRAMSZ 64
849 #else
850 #define CFG_AHBRAMSZ 1
851 #endif
852
853 #ifndef CONFIG_GRETH_ENABLE
854 #define CONFIG_GRETH_ENABLE 0
855 #endif
856
857 #ifndef CONFIG_GRETH_GIGA
858 #define CONFIG_GRETH_GIGA 0
859 #endif
860
861 #if defined CONFIG_GRETH_FIFO4
862 #define CFG_GRETH_FIFO 4
863 #elif defined CONFIG_GRETH_FIFO8
864 #define CFG_GRETH_FIFO 8
865 #elif defined CONFIG_GRETH_FIFO16
866 #define CFG_GRETH_FIFO 16
867 #elif defined CONFIG_GRETH_FIFO32
868 #define CFG_GRETH_FIFO 32
869 #elif defined CONFIG_GRETH_FIFO64
870 #define CFG_GRETH_FIFO 64
871 #else
872 #define CFG_GRETH_FIFO 8
873 #endif
874
875 #ifndef CONFIG_UART1_ENABLE
876 #define CONFIG_UART1_ENABLE 0
877 #endif
878
879 #if defined CONFIG_UA1_FIFO1
880 #define CFG_UA1_FIFO 1
881 #elif defined CONFIG_UA1_FIFO2
882 #define CFG_UA1_FIFO 2
883 #elif defined CONFIG_UA1_FIFO4
884 #define CFG_UA1_FIFO 4
885 #elif defined CONFIG_UA1_FIFO8
886 #define CFG_UA1_FIFO 8
887 #elif defined CONFIG_UA1_FIFO16
888 #define CFG_UA1_FIFO 16
889 #elif defined CONFIG_UA1_FIFO32
890 #define CFG_UA1_FIFO 32
891 #else
892 #define CFG_UA1_FIFO 1
893 #endif
894
895 #ifndef CONFIG_IRQ3_ENABLE
896 #define CONFIG_IRQ3_ENABLE 0
897 #endif
898 #ifndef CONFIG_IRQ3_NSEC
899 #define CONFIG_IRQ3_NSEC 0
900 #endif
901 #ifndef CONFIG_GPT_ENABLE
902 #define CONFIG_GPT_ENABLE 0
903 #endif
904
905 #ifndef CONFIG_GPT_NTIM
906 #define CONFIG_GPT_NTIM 1
907 #endif
908
909 #ifndef CONFIG_GPT_SW
910 #define CONFIG_GPT_SW 8
911 #endif
912
913 #ifndef CONFIG_GPT_TW
914 #define CONFIG_GPT_TW 8
915 #endif
916
917 #ifndef CONFIG_GPT_IRQ
918 #define CONFIG_GPT_IRQ 8
919 #endif
920
921 #ifndef CONFIG_GPT_SEPIRQ
922 #define CONFIG_GPT_SEPIRQ 0
923 #endif
924 #ifndef CONFIG_GPT_ENABLE
925 #define CONFIG_GPT_ENABLE 0
926 #endif
927
928 #ifndef CONFIG_GPT_NTIM
929 #define CONFIG_GPT_NTIM 1
930 #endif
931
932 #ifndef CONFIG_GPT_SW
933 #define CONFIG_GPT_SW 8
934 #endif
935
936 #ifndef CONFIG_GPT_TW
937 #define CONFIG_GPT_TW 8
938 #endif
939
940 #ifndef CONFIG_GPT_IRQ
941 #define CONFIG_GPT_IRQ 8
942 #endif
943
944 #ifndef CONFIG_GPT_SEPIRQ
945 #define CONFIG_GPT_SEPIRQ 0
946 #endif
947
948 #ifndef CONFIG_GPT_WDOGEN
949 #define CONFIG_GPT_WDOGEN 0
950 #endif
951
952 #ifndef CONFIG_GPT_WDOG
953 #define CONFIG_GPT_WDOG 0
954 #endif
955
956 #ifndef CONFIG_GRGPIO_ENABLE
957 #define CONFIG_GRGPIO_ENABLE 0
958 #endif
959 #ifndef CONFIG_GRGPIO_IMASK
960 #define CONFIG_GRGPIO_IMASK 0000
961 #endif
962 #ifndef CONFIG_GRGPIO_WIDTH
963 #define CONFIG_GRGPIO_WIDTH 1
964 #endif
965
966 #ifndef CONFIG_VGA_ENABLE
967 #define CONFIG_VGA_ENABLE 0
968 #endif
969 #ifndef CONFIG_SVGA_ENABLE
970 #define CONFIG_SVGA_ENABLE 0
971 #endif
972 #ifndef CONFIG_KBD_ENABLE
973 #define CONFIG_KBD_ENABLE 0
974 #endif
975
976
977 #ifndef CONFIG_SPIMCTRL
978 #define CONFIG_SPIMCTRL 0
979 #endif
980
981 #ifndef CONFIG_SPIMCTRL_SDCARD
982 #define CONFIG_SPIMCTRL_SDCARD 0
983 #endif
984
985 #ifndef CONFIG_SPIMCTRL_READCMD
986 #define CONFIG_SPIMCTRL_READCMD 0
987 #endif
988
989 #ifndef CONFIG_SPIMCTRL_DUMMYBYTE
990 #define CONFIG_SPIMCTRL_DUMMYBYTE 0
991 #endif
992
993 #ifndef CONFIG_SPIMCTRL_DUALOUTPUT
994 #define CONFIG_SPIMCTRL_DUALOUTPUT 0
995 #endif
996
997 #ifndef CONFIG_SPIMCTRL_SCALER
998 #define CONFIG_SPIMCTRL_SCALER 1
999 #endif
1000
1001 #ifndef CONFIG_SPIMCTRL_ASCALER
1002 #define CONFIG_SPIMCTRL_ASCALER 1
1003 #endif
1004
1005 #ifndef CONFIG_SPIMCTRL_PWRUPCNT
1006 #define CONFIG_SPIMCTRL_PWRUPCNT 0
1007 #endif
1008 #ifndef CONFIG_SPICTRL_ENABLE
1009 #define CONFIG_SPICTRL_ENABLE 0
1010 #endif
1011 #ifndef CONFIG_SPICTRL_NUM
1012 #define CONFIG_SPICTRL_NUM 1
1013 #endif
1014 #ifndef CONFIG_SPICTRL_SLVS
1015 #define CONFIG_SPICTRL_SLVS 1
1016 #endif
1017 #ifndef CONFIG_SPICTRL_FIFO
1018 #define CONFIG_SPICTRL_FIFO 1
1019 #endif
1020 #ifndef CONFIG_SPICTRL_SLVREG
1021 #define CONFIG_SPICTRL_SLVREG 0
1022 #endif
1023 #ifndef CONFIG_SPICTRL_ODMODE
1024 #define CONFIG_SPICTRL_ODMODE 0
1025 #endif
1026 #ifndef CONFIG_SPICTRL_AM
1027 #define CONFIG_SPICTRL_AM 0
1028 #endif
1029 #ifndef CONFIG_SPICTRL_ASEL
1030 #define CONFIG_SPICTRL_ASEL 0
1031 #endif
1032 #ifndef CONFIG_SPICTRL_TWEN
1033 #define CONFIG_SPICTRL_TWEN 0
1034 #endif
1035 #ifndef CONFIG_SPICTRL_MAXWLEN
1036 #define CONFIG_SPICTRL_MAXWLEN 0
1037 #endif
1038 #ifndef CONFIG_SPICTRL_SYNCRAM
1039 #define CONFIG_SPICTRL_SYNCRAM 0
1040 #endif
1041 #if defined(CONFIG_SPICTRL_DMRFT)
1042 #define CONFIG_SPICTRL_FT 1
1043 #elif defined(CONFIG_SPICTRL_TMRFT)
1044 #define CONFIG_SPICTRL_FT 2
1045 #else
1046 #define CONFIG_SPICTRL_FT 0
1047 #endif
1048
1049 #ifndef CONFIG_DEBUG_UART
1050 #define CONFIG_DEBUG_UART 0
1051 #endif
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@@ -1,13 +1,13
1 leon3_soc :
2 ENABLE_AHB_UART = 0 (disabled)
3 ENABLE_APB_UART = 0 (disabled)
4 FPU_NETLIST = 1 (enabled)
5
6 apb_lfr_management :
7 lfr_cal_driver (enabled)
8
9 top :
10 LFR_rstn <= LFR_soft_rstn AND rstn_25;
11
12 GRSPW :
13 ft = 1 (enabled)
1 leon3_soc :
2 ENABLE_AHB_UART = 0 (disabled)
3 ENABLE_APB_UART = 0 (disabled)
4 FPU_NETLIST = 1 (enabled)
5
6 apb_lfr_management :
7 lfr_cal_driver (enabled)
8
9 top :
10 LFR_rstn <= LFR_soft_rstn AND rstn_25;
11
12 GRSPW :
13 ft = 1 (enabled)
Show file before | Show file after | Hide comments
@@ -1,13 +1,13
1 leon3_soc :
2 ENABLE_AHB_UART = 0 (disabled)
3 ENABLE_APB_UART = 0 (disabled)
4 FPU_NETLIST = 0 (enabled)
5
6 apb_lfr_management :
7 lfr_cal_driver (enabled)
8
9 top :
10 LFR_rstn <= LFR_soft_rstn AND rstn_25;
11
12 GRSPW :
13 ft = 1 (enabled)
1 leon3_soc :
2 ENABLE_AHB_UART = 0 (disabled)
3 ENABLE_APB_UART = 0 (disabled)
4 FPU_NETLIST = 0 (enabled)
5
6 apb_lfr_management :
7 lfr_cal_driver (enabled)
8
9 top :
10 LFR_rstn <= LFR_soft_rstn AND rstn_25;
11
12 GRSPW :
13 ft = 1 (enabled)
Show file before | Show file after | Hide comments
@@ -1,16 +1,16
1 leon3_soc :
2 ENABLE_AHB_UART = 0 (disabled)
3 ENABLE_APB_UART = 0 (disabled)
4 FPU_NETLIST = 0 (enabled)
5
6 apb_lfr_management :
7 lfr_cal_driver (enabled)
8
9 top :
10 LFR_rstn <= LFR_soft_rstn AND rstn_25;
11
12 GRSPW :
13 ft = 1 (enabled)
14
15 Constraint file :
16 LFR_EQM_altran_syn_fanout.sdc
1 leon3_soc :
2 ENABLE_AHB_UART = 0 (disabled)
3 ENABLE_APB_UART = 0 (disabled)
4 FPU_NETLIST = 0 (enabled)
5
6 apb_lfr_management :
7 lfr_cal_driver (enabled)
8
9 top :
10 LFR_rstn <= LFR_soft_rstn AND rstn_25;
11
12 GRSPW :
13 ft = 1 (enabled)
14
15 Constraint file :
16 LFR_EQM_altran_syn_fanout.sdc
Show file before | Show file after | Hide comments
@@ -2,9 +2,9
2 2 VHDLIB=../..
3 3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
5 TOP=testbench
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
@@ -12,31 +12,34 EFFORT=high
12 12 XSTOPT=
13 13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=
16 VHDLSIMFILES= tb.vhd
15 VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
16 VHDLSIMFILES= tb.vhd
17 17 SIMTOP=testbench
18 18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
21 21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 22 CLEAN=soft-clean
23 23
24 TECHLIBS = proasic3e
24 TECHLIBS = axcelerator
25 25
26 26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
27 tmtc openchip hynix ihp gleichmann micron usbhc opencores
28 28
29 29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
30 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
31 31 ./amba_lcd_16x2_ctrlr \
32 32 ./general_purpose/lpp_AMR \
33 33 ./general_purpose/lpp_balise \
34 34 ./general_purpose/lpp_delay \
35 35 ./lpp_bootloader \
36 ./lfr_management \
37 ./lpp_sim \
38 ./lpp_sim/CY7C1061DV33 \
36 39 ./lpp_cna \
37 40 ./lpp_uart \
38 41 ./lpp_usb \
39 ./dsp/lpp_fft_rtax \
42 ./dsp/lpp_fft \
40 43
41 44 FILESKIP = i2cmst.vhd \
42 45 APB_MULTI_DIODE.vhd \
Show file before | Show file after | Hide comments
@@ -1,11 +1,15
1 1
2 LIBRARY ieee;
2 LIBRARY ieee;
3 3 USE ieee.std_logic_1164.ALL;
4 USE IEEE.MATH_REAL.ALL;
5 USE ieee.numeric_std.ALL;
4 use ieee.numeric_std.all;
5 USE IEEE.std_logic_signed.ALL;
6 USE IEEE.MATH_real.ALL;
6 7
7 8 LIBRARY techmap;
8 USE techmap.gencomp.ALL;
9 USE techmap.gencomp.ALL;
10
11 library std;
12 use std.textio.all;
9 13
10 14 LIBRARY lpp;
11 15 USE lpp.iir_filter.ALL;
@@ -14,7 +18,6 USE lpp.FILTERcfg.ALL;
14 18 USE lpp.lpp_lfr_filter_coeff.ALL;
15 19 USE lpp.general_purpose.ALL;
16 20 USE lpp.data_type_pkg.ALL;
17 USE lpp.chirp_pkg.ALL;
18 21 USE lpp.lpp_lfr_pkg.ALL;
19 22 USE lpp.general_purpose.ALL;
20 23
@@ -22,61 +25,64 ENTITY testbench IS
22 25 END;
23 26
24 27 ARCHITECTURE behav OF testbench IS
25
26 COMPONENT IIR_CEL_TEST
27 PORT (
28 rstn : IN STD_LOGIC;
29 clk : IN STD_LOGIC;
30 sample_in_val : IN STD_LOGIC;
31 sample_in : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
32 sample_out_val : OUT STD_LOGIC;
33 sample_out : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0));
34 END COMPONENT;
35
36 COMPONENT IIR_CEL_TEST_v3
37 PORT (
38 rstn : IN STD_LOGIC;
39 clk : IN STD_LOGIC;
40 sample_in1_val : IN STD_LOGIC;
41 sample_in1 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
42 sample_in2_val : IN STD_LOGIC;
43 sample_in2 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0);
44 sample_out1_val : OUT STD_LOGIC;
45 sample_out1 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0);
46 sample_out2_val : OUT STD_LOGIC;
47 sample_out2 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0));
48 END COMPONENT;
49
28
29 SIGNAL TSTAMP : INTEGER:=0;
50 30 SIGNAL clk : STD_LOGIC := '0';
51 31 SIGNAL clk_24k : STD_LOGIC := '0';
52 32 SIGNAL clk_24k_r : STD_LOGIC := '0';
53 33 SIGNAL rstn : STD_LOGIC;
54 34
35 SIGNAL signal_gen : Samples(7 DOWNTO 0);
36 SIGNAL offset_gen : Samples(7 DOWNTO 0);
37
55 38 SIGNAL sample : Samples(7 DOWNTO 0);
39
56 40 SIGNAL sample_val : STD_LOGIC;
57 SIGNAL sample_val_2 : STD_LOGIC;
58 41
59 SIGNAL data_chirp : STD_LOGIC_VECTOR(15 DOWNTO 0);
60 SIGNAL data_chirp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
42 SIGNAL sample_f0_val : STD_LOGIC;
43 SIGNAL sample_f1_val : STD_LOGIC;
44 SIGNAL sample_f2_val : STD_LOGIC;
45 SIGNAL sample_f3_val : STD_LOGIC;
61 46
62 SIGNAL sample_s : samplT(7 DOWNTO 0, 17 DOWNTO 0);
63 SIGNAL sample_out_s : samplT(7 DOWNTO 0, 17 DOWNTO 0);
64 SIGNAL sample_out_s2 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
65 SIGNAL sample_out_val : STD_LOGIC;
47 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
48 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
49 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
50 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
51
52 SIGNAL sample_f0 : Samples(5 DOWNTO 0);
53 SIGNAL sample_f1 : Samples(5 DOWNTO 0);
54 SIGNAL sample_f2 : Samples(5 DOWNTO 0);
55 SIGNAL sample_f3 : Samples(5 DOWNTO 0);
66 56
67 57
68 SIGNAL sample_out1_val : STD_LOGIC;
69 SIGNAL sample_out2_val : STD_LOGIC;
70 SIGNAL sample_out1 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
71 SIGNAL sample_out2 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
72 SIGNAL sample_out1_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0);
73 SIGNAL sample_out2_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0);
74
75 SIGNAL sample_s_v3 : samplT(7 DOWNTO 0, 17 DOWNTO 0);
76 SIGNAL sample_val_v3 : STD_LOGIC;
77 SIGNAL sample_val_v3_2 : STD_LOGIC;
78 58
79 59 SIGNAL temp : STD_LOGIC;
60
61
62 COMPONENT generator IS
63 GENERIC (
64 AMPLITUDE : INTEGER := 100;
65 NB_BITS : INTEGER := 16);
66
67 PORT (
68 clk : IN STD_LOGIC;
69 rstn : IN STD_LOGIC;
70 run : IN STD_LOGIC;
71
72 data_ack : IN STD_LOGIC;
73 offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
74 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
75 );
76 END COMPONENT;
77
78
79 file log_input : TEXT open write_mode is "log_input.txt";
80 file log_output_f0 : TEXT open write_mode is "log_output_f0.txt";
81 file log_output_f1 : TEXT open write_mode is "log_output_f1.txt";
82 file log_output_f2 : TEXT open write_mode is "log_output_f2.txt";
83 file log_output_f3 : TEXT open write_mode is "log_output_f3.txt";
84
85
80 86 BEGIN
81 87
82 88 -----------------------------------------------------------------------------
@@ -91,23 +97,41 BEGIN
91 97 WAIT UNTIL clk = '1';
92 98 WAIT UNTIL clk = '1';
93 99 rstn <= '1';
94 WAIT FOR 30 ms;
100 WAIT FOR 2000 ms;
95 101 REPORT "*** END simulation ***" SEVERITY failure;
96 102 WAIT;
97 103 END PROCESS;
104 -----------------------------------------------------------------------------
105
106
98 107 -----------------------------------------------------------------------------
99
108 -- COMMON TIMESTAMPS
109 -----------------------------------------------------------------------------
110
111 PROCESS(clk)
112 BEGIN
113 IF clk'event and clk ='1' THEN
114 TSTAMP <= TSTAMP+1;
115 END IF;
116 END PROCESS;
117 -----------------------------------------------------------------------------
118
100 119
101 120 -----------------------------------------------------------------------------
102 121 -- LPP_LFR_FILTER
103 122 -----------------------------------------------------------------------------
104 123 lpp_lfr_filter_1: lpp_lfr_filter
105 GENERIC MAP (
106 Mem_use => use_CEL)
124 GENERIC MAP (
125 --tech => 0,
126 --Mem_use => use_CEL,
127 tech => axcel,
128 Mem_use => use_RAM,
129 RTL_DESIGN_LIGHT =>0
130 )
107 131 PORT MAP (
108 132 sample => sample,
109 133 sample_val => sample_val,
110
134 sample_time => (others=>'0'),
111 135 clk => clk,
112 136 rstn => rstn,
113 137
@@ -117,14 +141,16 BEGIN
117 141 data_shaping_R1 => '0',
118 142 data_shaping_R2 => '0',
119 143
120 sample_f0_val => OPEN,
121 sample_f1_val => OPEN,
122 sample_f2_val => OPEN,
123 sample_f3_val => OPEN,
124 sample_f0_wdata => OPEN,
125 sample_f1_wdata => OPEN,
126 sample_f2_wdata => OPEN,
127 sample_f3_wdata => OPEN);
144 sample_f0_val => sample_f0_val,
145 sample_f1_val => sample_f1_val,
146 sample_f2_val => sample_f2_val,
147 sample_f3_val => sample_f3_val,
148
149 sample_f0_wdata => sample_f0_wdata,
150 sample_f1_wdata => sample_f1_wdata,
151 sample_f2_wdata => sample_f2_wdata,
152 sample_f3_wdata => sample_f3_wdata
153 );
128 154 -----------------------------------------------------------------------------
129 155
130 156
@@ -137,27 +163,22 BEGIN
137 163 BEGIN -- PROCESS
138 164 IF rstn = '0' THEN -- asynchronous reset (active low)
139 165 sample_val <= '0';
140 sample_val_2 <= '0';
141 166 clk_24k_r <= '0';
142 167 temp <= '0';
143 168 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
144 169 clk_24k_r <= clk_24k;
145 170 IF clk_24k = '1' AND clk_24k_r = '0' THEN
146 171 sample_val <= '1';
147 sample_val_2 <= temp;
148 172 temp <= NOT temp;
149 173 ELSE
150 174 sample_val <= '0';
151 sample_val_2 <= '0';
152 175 END IF;
153 176 END IF;
154 177 END PROCESS;
155 178 -----------------------------------------------------------------------------
156 chirp_1: chirp
179 generators: FOR I IN 0 TO 7 GENERATE
180 gen1: generator
157 181 GENERIC MAP (
158 LOW_FREQUENCY_LIMIT => 0,
159 HIGH_FREQUENCY_LIMIT => 2000,
160 NB_POINT_TO_GEN => 10000,
161 182 AMPLITUDE => 100,
162 183 NB_BITS => 16)
163 184 PORT MAP (
@@ -165,97 +186,90 BEGIN
165 186 rstn => rstn,
166 187 run => '1',
167 188 data_ack => sample_val,
168 data => data_chirp);
169
170 chirp_2: chirp
171 GENERIC MAP (
172 LOW_FREQUENCY_LIMIT => 0,
173 HIGH_FREQUENCY_LIMIT => 2000,
174 NB_POINT_TO_GEN => 100000,
175 AMPLITUDE => 200,
176 NB_BITS => 16)
177 PORT MAP (
178 clk => clk,
179 rstn => rstn,
180 run => '1',
181 data_ack => sample_val,
182 data => data_chirp_2);
189 offset => offset_gen(I),
190 data => signal_gen(I)
191 );
192 offset_gen(I) <= std_logic_vector( to_signed((I*200),16) );
193 END GENERATE generators;
194
195 output_splitter: FOR CHAN IN 0 TO 5 GENERATE
196 bits_splitter: FOR BIT IN 0 TO 15 GENERATE
197 sample_f0(CHAN)(BIT) <= sample_f0_wdata((CHAN*16) + BIT);
198 sample_f1(CHAN)(BIT) <= sample_f1_wdata((CHAN*16) + BIT);
199 sample_f2(CHAN)(BIT) <= sample_f2_wdata((CHAN*16) + BIT);
200 sample_f3(CHAN)(BIT) <= sample_f3_wdata((CHAN*16) + BIT);
201 END GENERATE bits_splitter;
202 END GENERATE output_splitter;
183 203
184 all_channel: FOR I IN 0 TO 3 GENERATE
185 sample(2*I) <= data_chirp;
186 sample(2*I+1) <= data_chirp_2;
187 END GENERATE all_channel;
188 -----------------------------------------------------------------------------
189
190 all_channel_test: FOR I IN 0 TO 3 GENERATE
191 all_bit_test: FOR J IN 0 TO 15 GENERATE
192 sample_s(2*I ,J) <= data_chirp(J);
193 sample_s(2*I+1,J) <= data_chirp_2(J);
194 END GENERATE all_bit_test;
195 sample_s(2*I,16) <= data_chirp(15);
196 sample_s(2*I,17) <= data_chirp(15);
197 sample_s(2*I+1,16) <= data_chirp_2(15);
198 sample_s(2*I+1,17) <= data_chirp_2(15);
199 END GENERATE all_channel_test;
200 204
201 IIR_CEL_TEST_1: IIR_CEL_TEST
202 PORT MAP (
203 rstn => rstn,
204 clk => clk,
205 sample_in_val => sample_val,
206 sample_in => sample_s,
207 sample_out_val => sample_out_val,
208 sample_out => sample_out_s);
205 sample <= signal_gen;
209 206
210 PROCESS (clk, rstn)
211 BEGIN -- PROCESS
212 IF rstn = '0' THEN -- asynchronous reset (active low)
213 all_channel: FOR I IN 0 TO 7 LOOP
214 all_bit: FOR J IN 0 TO 17 LOOP
215 sample_out_s2(I,J) <= '0';
216 END LOOP all_bit;
217 END LOOP all_channel;
218
219 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
220 IF sample_out_val = '1' THEN
221 sample_out_s2 <= sample_out_s;
222 END IF;
223 END IF;
224 END PROCESS;
207 -----------------------------------------------------------------------------
208 -- RECORD SIGNALS
225 209 -----------------------------------------------------------------------------
226 IIR_CEL_TEST_v3_1: IIR_CEL_TEST_v3
227 PORT MAP (
228 rstn => rstn,
229 clk => clk,
230 sample_in1_val => sample_val_v3,
231 sample_in1 => sample_s_v3,
232 sample_in2_val => sample_val_v3_2,
233 sample_in2 => sample_s_v3,
234 sample_out1_val => sample_out1_val,
235 sample_out1 => sample_out1,
236 sample_out2_val => sample_out2_val,
237 sample_out2 => sample_out2);
210
211 process(sample_val)
212 variable line_var : line;
213 begin
214 if sample_val'event and sample_val='1' then
215 write(line_var,integer'image(TSTAMP) );
216 for I IN 0 TO 7 loop
217 write(line_var, " " & integer'image(to_integer(signed(signal_gen(I)))));
218 end loop;
219 writeline(log_input,line_var);
220 end if;
221 end process;
222
223 process(sample_f0_val)
224 variable line_var : line;
225 begin
226 if sample_f0_val'event and sample_f0_val='1' then
227 write(line_var,integer'image(TSTAMP) );
228 for I IN 0 TO 5 loop
229 write(line_var, " " & integer'image(to_integer(signed(sample_f0(I)))));
230 end loop;
231 writeline(log_output_f0,line_var);
232 end if;
233 end process;
234
235
236 process(sample_f1_val)
237 variable line_var : line;
238 begin
239 if sample_f1_val'event and sample_f1_val='1' then
240 write(line_var,integer'image(TSTAMP) );
241 for I IN 0 TO 5 loop
242 write(line_var, " " & integer'image(to_integer(signed(sample_f1(I)))));
243 end loop;
244 writeline(log_output_f1,line_var);
245 end if;
246 end process;
247
248
249 process(sample_f2_val)
250 variable line_var : line;
251 begin
252 if sample_f2_val'event and sample_f2_val='1' then
253 write(line_var,integer'image(TSTAMP) );
254 for I IN 0 TO 5 loop
255 write(line_var, " " & integer'image(to_integer(signed(sample_f2(I)))));
256 end loop;
257 writeline(log_output_f2,line_var);
258 end if;
259 end process;
260
261 process(sample_f3_val)
262 variable line_var : line;
263 begin
264 if sample_f3_val'event and sample_f3_val='1' then
265 write(line_var,integer'image(TSTAMP) );
266 for I IN 0 TO 5 loop
267 write(line_var, " " & integer'image(to_integer(signed(sample_f3(I)))));
268 end loop;
269 writeline(log_output_f3,line_var);
270 end if;
271 end process;
238 272
239 PROCESS (clk, rstn)
240 BEGIN -- PROCESS
241 IF rstn = '0' THEN -- asynchronous reset (active low)
242
243 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
244 IF sample_val = '1' THEN
245 sample_s_v3 <= sample_s;
246 END IF;
247 sample_val_v3 <= sample_val;
248 sample_val_v3_2 <= sample_val_2;
249
250 IF sample_out1_val = '1' THEN
251 sample_out1_reg <= sample_out1;
252 END IF;
253 IF sample_out2_val = '1' THEN
254 sample_out2_reg <= sample_out2;
255 END IF;
256 END IF;
257
258 END PROCESS;
259 273
260 274
261 275
Show file before | Show file after | Hide comments
@@ -1,209 +1,209
1 This leon3 design is tailored to the Xilinx SP605 Spartan6 board
2
3 Simulation and synthesis
4 ------------------------
5
6 The design uses the Xilinx MIG memory interface with an AHB-2.0
7 interface. The MIG source code cannot be distributed due to the
8 prohibitive Xilinx license, so the MIG must be re-generated with
9 coregen before simulation and synthesis can be done.
10
11 To generate the MIG and install tne Xilinx unisim simulation
12 library, do as follows:
13
14 make mig
15 make install-secureip
16
17 This will ONLY work with ISE-13.2 installed, and the XILINX variable
18 properly set in the shell. To synthesize the design, do
19
20 make ise
21
22 and then
23
24 make ise-prog-fpga
25
26 to program the FPGA.
27
28 Design specifics
29 ----------------
30
31 * System reset is mapped to the CPU RESET button
32
33 * The AHB and processor is clocked by a 60 MHz clock, generated
34 from the 33 MHz SYSACE clock using a DCM. You can change the frequency
35 generation in the clocks menu of xconfig. The DDR3 (MIG) controller
36 runs at 667 MHz.
37
38 * The GRETH core is enabled and runs without problems at 100 Mbit.
39 Ethernet debug link is enabled and has IP 192.168.0.51.
40 1 Gbit operation is also possible (requires grlib com release),
41 uncomment related timing constraints in the leon3mp.ucf first.
42
43 * 16-bit flash prom can be read at address 0. It can be programmed
44 with GRMON version 1.1.16 or later.
45
46 * DDR3 is working with the provided Xilinx MIG DDR3 controller.
47 If you want to simulate this design, first install the secure
48 IP models with:
49
50 make install-secureip
51
52 Then rebuild the scripts and simulation model:
53
54 make distclean vsim
55
56 Modelsim v6.6e or newer is required to build the secure IP models.
57 Note that the regular leon3 test bench cannot be run in simulation
58 as the DDR3 model lacks data pre-load.
59
60 * The application UART1 is connected to the USB/UART connector
61
62 * The SVGA frame buffer uses a separate port on the DDR3 controller,
63 and therefore does not noticeably affect the performance of the processor.
64 Default output is analog VGA, to switch to DVI mode execute this
65 command in grmon:
66
67 i2c dvi init_l4itx_vga
68
69 * The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
70 Start grmon with -xilusb to connect.
71
72 * Output from GRMON is:
73
74 $ grmon -xilusb -u
75
76 GRMON LEON debug monitor v1.1.51 professional version (debug)
77
78 Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
79 For latest updates, go to http://www.gaisler.com/
80 Comments or bug-reports to support@gaisler.com
81
82 Xilinx cable: Cable type/rev : 0x3
83 JTAG chain: xc6slx45t xccace
84
85 GRLIB build version: 4111
86
87 initialising ...............
88 detected frequency: 50 MHz
89 SRAM waitstates: 1
90
91 Component Vendor
92 LEON3 SPARC V8 Processor Gaisler Research
93 AHB Debug JTAG TAP Gaisler Research
94 GR Ethernet MAC Gaisler Research
95 LEON2 Memory Controller European Space Agency
96 AHB/APB Bridge Gaisler Research
97 LEON3 Debug Support Unit Gaisler Research
98 Xilinx MIG DDR2 controller Gaisler Research
99 AHB/APB Bridge Gaisler Research
100 Generic APB UART Gaisler Research
101 Multi-processor Interrupt Ctrl Gaisler Research
102 Modular Timer Unit Gaisler Research
103 SVGA Controller Gaisler Research
104 AMBA Wrapper for OC I2C-master Gaisler Research
105 General purpose I/O port Gaisler Research
106 AHB status register Gaisler Research
107
108 Use command 'info sys' to print a detailed report of attached cores
109
110 grlib> inf sys
111 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
112 ahb master 0
113 01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
114 ahb master 1
115 02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
116 ahb master 2, irq 12
117 apb: 80000e00 - 80000f00
118 Device index: dev0
119 edcl ip 192.168.1.51, buffer 2 kbyte
120 00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
121 ahb: 00000000 - 20000000
122 apb: 80000000 - 80000100
123 16-bit prom @ 0x00000000
124 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
125 ahb: 80000000 - 80100000
126 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
127 ahb: 90000000 - a0000000
128 AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
129 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
130 icache 2 * 8 kbyte, 32 byte/line rnd
131 dcache 2 * 4 kbyte, 16 byte/line rnd
132 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
133 ahb: 40000000 - 48000000
134 apb: 80100000 - 80100100
135 DDR2: 128 Mbyte
136 0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
137 ahb: 80100000 - 80200000
138 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
139 irq 2
140 apb: 80000100 - 80000200
141 baud rate 38343, DSU mode (FIFO debug)
142 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
143 apb: 80000200 - 80000300
144 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
145 irq 8
146 apb: 80000300 - 80000400
147 8-bit scaler, 2 * 32-bit timers, divisor 50
148 06.01:063 Gaisler Research SVGA Controller (ver 0x0)
149 apb: 80000600 - 80000700
150 clk0: 50.00 MHz
151 09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
152 irq 14
153 apb: 80000900 - 80000a00
154 0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
155 apb: 80000a00 - 80000b00
156 0f.01:052 Gaisler Research AHB status register (ver 0x0)
157 irq 7
158 apb: 80000f00 - 80001000
159 grlib> fla
160
161 Intel-style 16-bit flash on D[31:16]
162
163 Manuf. Intel
164 Device Strataflash P30
165
166 Device ID 02e44603e127ffff
167 User ID ffffffffffffffff
168
169
170 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
171
172
173 CFI info
174 flash family : 1
175 flash size : 256 Mbit
176 erase regions : 2
177 erase blocks : 259
178 write buffer : 1024 bytes
179 lock-down : yes
180 region 0 : 255 blocks of 128 Kbytes
181 region 1 : 4 blocks of 32 Kbytes
182
183 grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
184 section: .text at 0x40000000, size 102544 bytes
185 section: .data at 0x40019090, size 2788 bytes
186 total size: 105332 bytes (1.2 Mbit/s)
187 read 272 symbols
188 entry point: 0x40000000
189 grlib> run
190 2K performance run parameters for coremark.
191 CoreMark Size : 666
192 Total ticks : 19945918
193 Total time (secs): 19.945918
194 Iterations/Sec : 100.271143
195 Iterations : 2000
196 Compiler version : GCC4.4.2
197 Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
198 Memory location : STACK
199 seedcrc : 0xe9f5
200 [0]crclist : 0xe714
201 [0]crcmatrix : 0x1fd7
202 [0]crcstate : 0x8e3a
203 [0]crcfinal : 0x4983
204 Correct operation validated. See readme.txt for run and reporting rules.
205 CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
206
207 Program exited normally.
208 grlib>
209
1 This leon3 design is tailored to the Xilinx SP605 Spartan6 board
2
3 Simulation and synthesis
4 ------------------------
5
6 The design uses the Xilinx MIG memory interface with an AHB-2.0
7 interface. The MIG source code cannot be distributed due to the
8 prohibitive Xilinx license, so the MIG must be re-generated with
9 coregen before simulation and synthesis can be done.
10
11 To generate the MIG and install tne Xilinx unisim simulation
12 library, do as follows:
13
14 make mig
15 make install-secureip
16
17 This will ONLY work with ISE-13.2 installed, and the XILINX variable
18 properly set in the shell. To synthesize the design, do
19
20 make ise
21
22 and then
23
24 make ise-prog-fpga
25
26 to program the FPGA.
27
28 Design specifics
29 ----------------
30
31 * System reset is mapped to the CPU RESET button
32
33 * The AHB and processor is clocked by a 60 MHz clock, generated
34 from the 33 MHz SYSACE clock using a DCM. You can change the frequency
35 generation in the clocks menu of xconfig. The DDR3 (MIG) controller
36 runs at 667 MHz.
37
38 * The GRETH core is enabled and runs without problems at 100 Mbit.
39 Ethernet debug link is enabled and has IP 192.168.0.51.
40 1 Gbit operation is also possible (requires grlib com release),
41 uncomment related timing constraints in the leon3mp.ucf first.
42
43 * 16-bit flash prom can be read at address 0. It can be programmed
44 with GRMON version 1.1.16 or later.
45
46 * DDR3 is working with the provided Xilinx MIG DDR3 controller.
47 If you want to simulate this design, first install the secure
48 IP models with:
49
50 make install-secureip
51
52 Then rebuild the scripts and simulation model:
53
54 make distclean vsim
55
56 Modelsim v6.6e or newer is required to build the secure IP models.
57 Note that the regular leon3 test bench cannot be run in simulation
58 as the DDR3 model lacks data pre-load.
59
60 * The application UART1 is connected to the USB/UART connector
61
62 * The SVGA frame buffer uses a separate port on the DDR3 controller,
63 and therefore does not noticeably affect the performance of the processor.
64 Default output is analog VGA, to switch to DVI mode execute this
65 command in grmon:
66
67 i2c dvi init_l4itx_vga
68
69 * The JTAG DSU interface is enabled and accesible via the USB/JTAG port.
70 Start grmon with -xilusb to connect.
71
72 * Output from GRMON is:
73
74 $ grmon -xilusb -u
75
76 GRMON LEON debug monitor v1.1.51 professional version (debug)
77
78 Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved.
79 For latest updates, go to http://www.gaisler.com/
80 Comments or bug-reports to support@gaisler.com
81
82 Xilinx cable: Cable type/rev : 0x3
83 JTAG chain: xc6slx45t xccace
84
85 GRLIB build version: 4111
86
87 initialising ...............
88 detected frequency: 50 MHz
89 SRAM waitstates: 1
90
91 Component Vendor
92 LEON3 SPARC V8 Processor Gaisler Research
93 AHB Debug JTAG TAP Gaisler Research
94 GR Ethernet MAC Gaisler Research
95 LEON2 Memory Controller European Space Agency
96 AHB/APB Bridge Gaisler Research
97 LEON3 Debug Support Unit Gaisler Research
98 Xilinx MIG DDR2 controller Gaisler Research
99 AHB/APB Bridge Gaisler Research
100 Generic APB UART Gaisler Research
101 Multi-processor Interrupt Ctrl Gaisler Research
102 Modular Timer Unit Gaisler Research
103 SVGA Controller Gaisler Research
104 AMBA Wrapper for OC I2C-master Gaisler Research
105 General purpose I/O port Gaisler Research
106 AHB status register Gaisler Research
107
108 Use command 'info sys' to print a detailed report of attached cores
109
110 grlib> inf sys
111 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
112 ahb master 0
113 01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1)
114 ahb master 1
115 02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
116 ahb master 2, irq 12
117 apb: 80000e00 - 80000f00
118 Device index: dev0
119 edcl ip 192.168.1.51, buffer 2 kbyte
120 00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
121 ahb: 00000000 - 20000000
122 apb: 80000000 - 80000100
123 16-bit prom @ 0x00000000
124 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
125 ahb: 80000000 - 80100000
126 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
127 ahb: 90000000 - a0000000
128 AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0
129 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
130 icache 2 * 8 kbyte, 32 byte/line rnd
131 dcache 2 * 4 kbyte, 16 byte/line rnd
132 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0)
133 ahb: 40000000 - 48000000
134 apb: 80100000 - 80100100
135 DDR2: 128 Mbyte
136 0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
137 ahb: 80100000 - 80200000
138 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
139 irq 2
140 apb: 80000100 - 80000200
141 baud rate 38343, DSU mode (FIFO debug)
142 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
143 apb: 80000200 - 80000300
144 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
145 irq 8
146 apb: 80000300 - 80000400
147 8-bit scaler, 2 * 32-bit timers, divisor 50
148 06.01:063 Gaisler Research SVGA Controller (ver 0x0)
149 apb: 80000600 - 80000700
150 clk0: 50.00 MHz
151 09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3)
152 irq 14
153 apb: 80000900 - 80000a00
154 0a.01:01a Gaisler Research General purpose I/O port (ver 0x1)
155 apb: 80000a00 - 80000b00
156 0f.01:052 Gaisler Research AHB status register (ver 0x0)
157 irq 7
158 apb: 80000f00 - 80001000
159 grlib> fla
160
161 Intel-style 16-bit flash on D[31:16]
162
163 Manuf. Intel
164 Device Strataflash P30
165
166 Device ID 02e44603e127ffff
167 User ID ffffffffffffffff
168
169
170 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
171
172
173 CFI info
174 flash family : 1
175 flash size : 256 Mbit
176 erase regions : 2
177 erase blocks : 259
178 write buffer : 1024 bytes
179 lock-down : yes
180 region 0 : 255 blocks of 128 Kbytes
181 region 1 : 4 blocks of 32 Kbytes
182
183 grlib> lo ~/ibm/src/bench/leonbench/coremark.exe
184 section: .text at 0x40000000, size 102544 bytes
185 section: .data at 0x40019090, size 2788 bytes
186 total size: 105332 bytes (1.2 Mbit/s)
187 read 272 symbols
188 entry point: 0x40000000
189 grlib> run
190 2K performance run parameters for coremark.
191 CoreMark Size : 666
192 Total ticks : 19945918
193 Total time (secs): 19.945918
194 Iterations/Sec : 100.271143
195 Iterations : 2000
196 Compiler version : GCC4.4.2
197 Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float
198 Memory location : STACK
199 seedcrc : 0xe9f5
200 [0]crclist : 0xe714
201 [0]crcmatrix : 0x1fd7
202 [0]crcstate : 0x8e3a
203 [0]crcfinal : 0x4983
204 Correct operation validated. See readme.txt for run and reporting rules.
205 CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack
206
207 Program exited normally.
208 grlib>
209
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@@ -1,190 +1,190
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
18
19 -- LEON3 processor core
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
23 constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
25 constant CFG_BP : integer := CONFIG_IU_BP;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
72
73 -- AMBA settings
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
83
84 -- JTAG based DSU interface
85 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
86
87 -- Ethernet DSU
88 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
89 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
90 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
91 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
92 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
93 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
94
95 -- LEON2 memory controller
96 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
97 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
98 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
99 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
100 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
101 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
102 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
103 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
104 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
105
106 -- Xilinx MIG
107 constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
108 constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
109 constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
110 constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
111 constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
112 constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
113
114
115 -- AHB status register
116 constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
117 constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
118
119 -- AHB ROM
120 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
121 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
122 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
123 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
124 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
125
126 -- AHB RAM
127 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
128 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
129 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
130
131 -- Gaisler Ethernet core
132 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
133 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
134 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
135
136 -- UART 1
137 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
138 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
139
140 -- LEON3 interrupt controller
141 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
142 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
143
144 -- Modular timer
145 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
146 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
147 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
148 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
149 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
150 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
151 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
152 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
153
154 -- GPIO port
155 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
156 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
157 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
158
159 -- VGA and PS2/ interface
160 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
161 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
162 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
163
164 -- SPI memory controller
165 constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
166 constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
167 constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
168 constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
169 constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
170 constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
171 constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
172 constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
173
174 -- SPI controller
175 constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
176 constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
177 constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
178 constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
179 constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
180 constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
181 constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
182 constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
183 constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
184 constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
185 constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
186 constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
187
188 -- GRLIB debugging
189 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
190
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
18
19 -- LEON3 processor core
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
23 constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
25 constant CFG_BP : integer := CONFIG_IU_BP;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
72
73 -- AMBA settings
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
83
84 -- JTAG based DSU interface
85 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
86
87 -- Ethernet DSU
88 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
89 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
90 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
91 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
92 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
93 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
94
95 -- LEON2 memory controller
96 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
97 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
98 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
99 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
100 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
101 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
102 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
103 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
104 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
105
106 -- Xilinx MIG
107 constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
108 constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
109 constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
110 constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
111 constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
112 constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
113
114
115 -- AHB status register
116 constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
117 constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
118
119 -- AHB ROM
120 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
121 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
122 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
123 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
124 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
125
126 -- AHB RAM
127 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
128 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
129 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
130
131 -- Gaisler Ethernet core
132 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
133 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
134 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
135
136 -- UART 1
137 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
138 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
139
140 -- LEON3 interrupt controller
141 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
142 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
143
144 -- Modular timer
145 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
146 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
147 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
148 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
149 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
150 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
151 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
152 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
153
154 -- GPIO port
155 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
156 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
157 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
158
159 -- VGA and PS2/ interface
160 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
161 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
162 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
163
164 -- SPI memory controller
165 constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
166 constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
167 constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
168 constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
169 constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
170 constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
171 constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
172 constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
173
174 -- SPI controller
175 constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
176 constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM;
177 constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
178 constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
179 constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
180 constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
181 constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
182 constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
183 constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN;
184 constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN;
185 constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM;
186 constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT;
187
188 -- GRLIB debugging
189 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
190
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@@ -1,403 +1,403
1 <HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
2 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3 <center><big><big><b>System Settings</b></big></big></center><br>
4 <A NAME="Environment Settings"></A>
5 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
6 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
7 <TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
8 </tr>
9 <tr bgcolor='#ffff99'>
10 <td><b>Environment Variable</b></td>
11 <td><b>xst</b></td>
12 <td><b>ngdbuild</b></td>
13 <td><b>map</b></td>
14 <td><b>par</b></td>
15 </tr>
16 <tr>
17 <td>LD_LIBRARY_PATH</td>
18 <td>/opt/Xilinx/14.2/ISE_DS/ISE//lib/lin64:<br>/usr/lib64/alliance/lib</td>
19 <td>/opt/Xilinx/14.2/ISE_DS/ISE//lib/lin64:<br>/usr/lib64/alliance/lib</td>
20 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
21 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
22 </tr>
23 <tr>
24 <td>PATH</td>
25 <td>/opt/Xilinx/14.2/ISE_DS/ISE//bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/kerberos/sbin:<br>/usr/kerberos/bin:<br>/usr/lib64/ccache:<br>/usr/libexec/lightdm:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/usr/lib64/alliance/bin:<br>/usr/libexec/sdcc:<br>/opt/sparc-elf-4.4.2/bin:<br>/usr/local/MATLAB/R2012b/bin:<br>/opt/gcc-arm-none-eabi-4_7-2012q4/bin:<br>/home/jeandet/.local/bin:<br>/home/jeandet/bin</td>
26 <td>/opt/Xilinx/14.2/ISE_DS/ISE//bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/kerberos/sbin:<br>/usr/kerberos/bin:<br>/usr/lib64/ccache:<br>/usr/libexec/lightdm:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/usr/lib64/alliance/bin:<br>/usr/libexec/sdcc:<br>/opt/sparc-elf-4.4.2/bin:<br>/usr/local/MATLAB/R2012b/bin:<br>/opt/gcc-arm-none-eabi-4_7-2012q4/bin:<br>/home/jeandet/.local/bin:<br>/home/jeandet/bin</td>
27 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
28 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
29 </tr>
30 <tr>
31 <td>XILINX</td>
32 <td>/opt/Xilinx/14.2/ISE_DS/ISE/</td>
33 <td>/opt/Xilinx/14.2/ISE_DS/ISE/</td>
34 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
35 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
36 </tr>
37 </TABLE>
38 <A NAME="Synthesis Property Settings"></A>
39 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
40 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
41 <TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
42 </tr>
43 <tr bgcolor='#ffff99'>
44 <td><b>Switch Name</b></td>
45 <td><b>Property Name</b></td>
46 <td><b>Value</b></td>
47 <td><b>Default Value</b></td>
48 </tr>
49 <tr>
50 <td>-ifn</td>
51 <td>&nbsp;</td>
52 <td>leon3mp.prj</td>
53 <td>&nbsp;</td>
54 </tr>
55 <tr>
56 <td>-ofn</td>
57 <td>&nbsp;</td>
58 <td>leon3mp</td>
59 <td>&nbsp;</td>
60 </tr>
61 <tr>
62 <td>-ofmt</td>
63 <td>&nbsp;</td>
64 <td>NGC</td>
65 <td>NGC</td>
66 </tr>
67 <tr>
68 <td>-p</td>
69 <td>&nbsp;</td>
70 <td>xc6slx45-3-fgg484</td>
71 <td>&nbsp;</td>
72 </tr>
73 <tr>
74 <td>-top</td>
75 <td>&nbsp;</td>
76 <td>leon3mp</td>
77 <td>&nbsp;</td>
78 </tr>
79 <tr>
80 <td>-opt_mode</td>
81 <td>Optimization Goal</td>
82 <td>Speed</td>
83 <td>Speed</td>
84 </tr>
85 <tr>
86 <td>-opt_level</td>
87 <td>Optimization Effort</td>
88 <td>1</td>
89 <td>1</td>
90 </tr>
91 <tr>
92 <td>-power</td>
93 <td>Power Reduction</td>
94 <td>NO</td>
95 <td>No</td>
96 </tr>
97 <tr>
98 <td>-iuc</td>
99 <td>Use synthesis Constraints File</td>
100 <td>NO</td>
101 <td>No</td>
102 </tr>
103 <tr>
104 <td>-keep_hierarchy</td>
105 <td>Keep Hierarchy</td>
106 <td>No</td>
107 <td>No</td>
108 </tr>
109 <tr>
110 <td>-netlist_hierarchy</td>
111 <td>Netlist Hierarchy</td>
112 <td>As_Optimized</td>
113 <td>As_Optimized</td>
114 </tr>
115 <tr>
116 <td>-rtlview</td>
117 <td>Generate RTL Schematic</td>
118 <td>Yes</td>
119 <td>No</td>
120 </tr>
121 <tr>
122 <td>-glob_opt</td>
123 <td>Global Optimization Goal</td>
124 <td>AllClockNets</td>
125 <td>AllClockNets</td>
126 </tr>
127 <tr>
128 <td>-read_cores</td>
129 <td>Read Cores</td>
130 <td>YES</td>
131 <td>Yes</td>
132 </tr>
133 <tr>
134 <td>-write_timing_constraints</td>
135 <td>Write Timing Constraints</td>
136 <td>NO</td>
137 <td>No</td>
138 </tr>
139 <tr>
140 <td>-cross_clock_analysis</td>
141 <td>Cross Clock Analysis</td>
142 <td>NO</td>
143 <td>No</td>
144 </tr>
145 <tr>
146 <td>-bus_delimiter</td>
147 <td>Bus Delimiter</td>
148 <td>()</td>
149 <td>&lt;&gt;</td>
150 </tr>
151 <tr>
152 <td>-slice_utilization_ratio</td>
153 <td>Slice Utilization Ratio</td>
154 <td>100</td>
155 <td>100</td>
156 </tr>
157 <tr>
158 <td>-bram_utilization_ratio</td>
159 <td>BRAM Utilization Ratio</td>
160 <td>100</td>
161 <td>100</td>
162 </tr>
163 <tr>
164 <td>-dsp_utilization_ratio</td>
165 <td>DSP Utilization Ratio</td>
166 <td>100</td>
167 <td>100</td>
168 </tr>
169 <tr>
170 <td>-reduce_control_sets</td>
171 <td>&nbsp;</td>
172 <td>Auto</td>
173 <td>Auto</td>
174 </tr>
175 <tr>
176 <td>-fsm_extract</td>
177 <td>&nbsp;</td>
178 <td>NO</td>
179 <td>Yes</td>
180 </tr>
181 <tr>
182 <td>-fsm_style</td>
183 <td>&nbsp;</td>
184 <td>LUT</td>
185 <td>LUT</td>
186 </tr>
187 <tr>
188 <td>-ram_extract</td>
189 <td>&nbsp;</td>
190 <td>Yes</td>
191 <td>Yes</td>
192 </tr>
193 <tr>
194 <td>-ram_style</td>
195 <td>&nbsp;</td>
196 <td>Auto</td>
197 <td>Auto</td>
198 </tr>
199 <tr>
200 <td>-rom_extract</td>
201 <td>&nbsp;</td>
202 <td>Yes</td>
203 <td>Yes</td>
204 </tr>
205 <tr>
206 <td>-shreg_extract</td>
207 <td>&nbsp;</td>
208 <td>YES</td>
209 <td>Yes</td>
210 </tr>
211 <tr>
212 <td>-rom_style</td>
213 <td>&nbsp;</td>
214 <td>Auto</td>
215 <td>Auto</td>
216 </tr>
217 <tr>
218 <td>-auto_bram_packing</td>
219 <td>&nbsp;</td>
220 <td>NO</td>
221 <td>No</td>
222 </tr>
223 <tr>
224 <td>-resource_sharing</td>
225 <td>&nbsp;</td>
226 <td>YES</td>
227 <td>Yes</td>
228 </tr>
229 <tr>
230 <td>-async_to_sync</td>
231 <td>&nbsp;</td>
232 <td>NO</td>
233 <td>No</td>
234 </tr>
235 <tr>
236 <td>-use_dsp48</td>
237 <td>&nbsp;</td>
238 <td>Auto</td>
239 <td>Auto</td>
240 </tr>
241 <tr>
242 <td>-iobuf</td>
243 <td>&nbsp;</td>
244 <td>YES</td>
245 <td>Yes</td>
246 </tr>
247 <tr>
248 <td>-max_fanout</td>
249 <td>&nbsp;</td>
250 <td>100000</td>
251 <td>100000</td>
252 </tr>
253 <tr>
254 <td>-bufg</td>
255 <td>&nbsp;</td>
256 <td>16</td>
257 <td>16</td>
258 </tr>
259 <tr>
260 <td>-register_duplication</td>
261 <td>&nbsp;</td>
262 <td>YES</td>
263 <td>Yes</td>
264 </tr>
265 <tr>
266 <td>-register_balancing</td>
267 <td>&nbsp;</td>
268 <td>No</td>
269 <td>No</td>
270 </tr>
271 <tr>
272 <td>-optimize_primitives</td>
273 <td>&nbsp;</td>
274 <td>NO</td>
275 <td>No</td>
276 </tr>
277 <tr>
278 <td>-use_clock_enable</td>
279 <td>&nbsp;</td>
280 <td>Auto</td>
281 <td>Auto</td>
282 </tr>
283 <tr>
284 <td>-use_sync_set</td>
285 <td>&nbsp;</td>
286 <td>Auto</td>
287 <td>Auto</td>
288 </tr>
289 <tr>
290 <td>-use_sync_reset</td>
291 <td>&nbsp;</td>
292 <td>Auto</td>
293 <td>Auto</td>
294 </tr>
295 <tr>
296 <td>-iob</td>
297 <td>&nbsp;</td>
298 <td>True</td>
299 <td>Auto</td>
300 </tr>
301 <tr>
302 <td>-equivalent_register_removal</td>
303 <td>&nbsp;</td>
304 <td>YES</td>
305 <td>Yes</td>
306 </tr>
307 <tr>
308 <td>-slice_utilization_ratio_maxmargin</td>
309 <td>&nbsp;</td>
310 <td>5</td>
311 <td>0</td>
312 </tr>
313 </TABLE>
314 <A NAME="Translation Property Settings"></A>
315 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
316 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
317 <TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
318 </tr>
319 <tr bgcolor='#ffff99'>
320 <td><b>Switch Name</b></td>
321 <td><b>Property Name</b></td>
322 <td><b>Value</b></td>
323 <td><b>Default Value</b></td>
324 </tr>
325 <tr>
326 <td>-aul</td>
327 <td>Allow Unmatched LOC Constraints</td>
328 <td>true</td>
329 <td>false</td>
330 </tr>
331 <tr>
332 <td>-intstyle</td>
333 <td>&nbsp;</td>
334 <td>ise</td>
335 <td>None</td>
336 </tr>
337 <tr>
338 <td>-dd</td>
339 <td>&nbsp;</td>
340 <td>_ngo</td>
341 <td>None</td>
342 </tr>
343 <tr>
344 <td>-p</td>
345 <td>&nbsp;</td>
346 <td>xc6slx45-fgg484-3</td>
347 <td>None</td>
348 </tr>
349 <tr>
350 <td>-sd</td>
351 <td>Macro Search Path</td>
352 <td>../../netlists/xilinx/Spartan3</td>
353 <td>None</td>
354 </tr>
355 <tr>
356 <td>-uc</td>
357 <td>&nbsp;</td>
358 <td>leon3mp.ucf</td>
359 <td>None</td>
360 </tr>
361 </TABLE>
362 <A NAME="Operating System Information"></A>
363 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
364 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
365 <TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
366 </tr>
367 <tr bgcolor='#ffff99'>
368 <td><b>Operating System Information</b></td>
369 <td><b>xst</b></td>
370 <td><b>ngdbuild</b></td>
371 <td><b>map</b></td>
372 <td><b>par</b></td>
373 </tr>
374 <tr>
375 <td>CPU Architecture/Speed</td>
376 <td>Intel(R) Core(TM) i5-2557M CPU @ 1.70GHz/1701.000 MHz</td>
377 <td>Intel(R) Core(TM) i5-2557M CPU @ 1.70GHz/800.000 MHz</td>
378 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
379 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
380 </tr>
381 <tr>
382 <td>Host</td>
383 <td>pc-de-jeandet3.lab-lpp.local</td>
384 <td>pc-de-jeandet3.lab-lpp.local</td>
385 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
386 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
387 </tr>
388 <tr>
389 <td>OS Name</td>
390 <td>Fedora</td>
391 <td>Fedora</td>
392 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
393 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
394 </tr>
395 <tr>
396 <td>OS Release</td>
397 <td>Fedora release 18 (Spherical Cow)</td>
398 <td>Fedora release 18 (Spherical Cow)</td>
399 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
400 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
401 </tr>
402 </TABLE>
1 <HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
2 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3 <center><big><big><b>System Settings</b></big></big></center><br>
4 <A NAME="Environment Settings"></A>
5 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
6 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
7 <TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
8 </tr>
9 <tr bgcolor='#ffff99'>
10 <td><b>Environment Variable</b></td>
11 <td><b>xst</b></td>
12 <td><b>ngdbuild</b></td>
13 <td><b>map</b></td>
14 <td><b>par</b></td>
15 </tr>
16 <tr>
17 <td>LD_LIBRARY_PATH</td>
18 <td>/opt/Xilinx/14.2/ISE_DS/ISE//lib/lin64:<br>/usr/lib64/alliance/lib</td>
19 <td>/opt/Xilinx/14.2/ISE_DS/ISE//lib/lin64:<br>/usr/lib64/alliance/lib</td>
20 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
21 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
22 </tr>
23 <tr>
24 <td>PATH</td>
25 <td>/opt/Xilinx/14.2/ISE_DS/ISE//bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/kerberos/sbin:<br>/usr/kerberos/bin:<br>/usr/lib64/ccache:<br>/usr/libexec/lightdm:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/usr/lib64/alliance/bin:<br>/usr/libexec/sdcc:<br>/opt/sparc-elf-4.4.2/bin:<br>/usr/local/MATLAB/R2012b/bin:<br>/opt/gcc-arm-none-eabi-4_7-2012q4/bin:<br>/home/jeandet/.local/bin:<br>/home/jeandet/bin</td>
26 <td>/opt/Xilinx/14.2/ISE_DS/ISE//bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/kerberos/sbin:<br>/usr/kerberos/bin:<br>/usr/lib64/ccache:<br>/usr/libexec/lightdm:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/usr/lib64/alliance/bin:<br>/usr/libexec/sdcc:<br>/opt/sparc-elf-4.4.2/bin:<br>/usr/local/MATLAB/R2012b/bin:<br>/opt/gcc-arm-none-eabi-4_7-2012q4/bin:<br>/home/jeandet/.local/bin:<br>/home/jeandet/bin</td>
27 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
28 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
29 </tr>
30 <tr>
31 <td>XILINX</td>
32 <td>/opt/Xilinx/14.2/ISE_DS/ISE/</td>
33 <td>/opt/Xilinx/14.2/ISE_DS/ISE/</td>
34 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
35 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
36 </tr>
37 </TABLE>
38 <A NAME="Synthesis Property Settings"></A>
39 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
40 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
41 <TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
42 </tr>
43 <tr bgcolor='#ffff99'>
44 <td><b>Switch Name</b></td>
45 <td><b>Property Name</b></td>
46 <td><b>Value</b></td>
47 <td><b>Default Value</b></td>
48 </tr>
49 <tr>
50 <td>-ifn</td>
51 <td>&nbsp;</td>
52 <td>leon3mp.prj</td>
53 <td>&nbsp;</td>
54 </tr>
55 <tr>
56 <td>-ofn</td>
57 <td>&nbsp;</td>
58 <td>leon3mp</td>
59 <td>&nbsp;</td>
60 </tr>
61 <tr>
62 <td>-ofmt</td>
63 <td>&nbsp;</td>
64 <td>NGC</td>
65 <td>NGC</td>
66 </tr>
67 <tr>
68 <td>-p</td>
69 <td>&nbsp;</td>
70 <td>xc6slx45-3-fgg484</td>
71 <td>&nbsp;</td>
72 </tr>
73 <tr>
74 <td>-top</td>
75 <td>&nbsp;</td>
76 <td>leon3mp</td>
77 <td>&nbsp;</td>
78 </tr>
79 <tr>
80 <td>-opt_mode</td>
81 <td>Optimization Goal</td>
82 <td>Speed</td>
83 <td>Speed</td>
84 </tr>
85 <tr>
86 <td>-opt_level</td>
87 <td>Optimization Effort</td>
88 <td>1</td>
89 <td>1</td>
90 </tr>
91 <tr>
92 <td>-power</td>
93 <td>Power Reduction</td>
94 <td>NO</td>
95 <td>No</td>
96 </tr>
97 <tr>
98 <td>-iuc</td>
99 <td>Use synthesis Constraints File</td>
100 <td>NO</td>
101 <td>No</td>
102 </tr>
103 <tr>
104 <td>-keep_hierarchy</td>
105 <td>Keep Hierarchy</td>
106 <td>No</td>
107 <td>No</td>
108 </tr>
109 <tr>
110 <td>-netlist_hierarchy</td>
111 <td>Netlist Hierarchy</td>
112 <td>As_Optimized</td>
113 <td>As_Optimized</td>
114 </tr>
115 <tr>
116 <td>-rtlview</td>
117 <td>Generate RTL Schematic</td>
118 <td>Yes</td>
119 <td>No</td>
120 </tr>
121 <tr>
122 <td>-glob_opt</td>
123 <td>Global Optimization Goal</td>
124 <td>AllClockNets</td>
125 <td>AllClockNets</td>
126 </tr>
127 <tr>
128 <td>-read_cores</td>
129 <td>Read Cores</td>
130 <td>YES</td>
131 <td>Yes</td>
132 </tr>
133 <tr>
134 <td>-write_timing_constraints</td>
135 <td>Write Timing Constraints</td>
136 <td>NO</td>
137 <td>No</td>
138 </tr>
139 <tr>
140 <td>-cross_clock_analysis</td>
141 <td>Cross Clock Analysis</td>
142 <td>NO</td>
143 <td>No</td>
144 </tr>
145 <tr>
146 <td>-bus_delimiter</td>
147 <td>Bus Delimiter</td>
148 <td>()</td>
149 <td>&lt;&gt;</td>
150 </tr>
151 <tr>
152 <td>-slice_utilization_ratio</td>
153 <td>Slice Utilization Ratio</td>
154 <td>100</td>
155 <td>100</td>
156 </tr>
157 <tr>
158 <td>-bram_utilization_ratio</td>
159 <td>BRAM Utilization Ratio</td>
160 <td>100</td>
161 <td>100</td>
162 </tr>
163 <tr>
164 <td>-dsp_utilization_ratio</td>
165 <td>DSP Utilization Ratio</td>
166 <td>100</td>
167 <td>100</td>
168 </tr>
169 <tr>
170 <td>-reduce_control_sets</td>
171 <td>&nbsp;</td>
172 <td>Auto</td>
173 <td>Auto</td>
174 </tr>
175 <tr>
176 <td>-fsm_extract</td>
177 <td>&nbsp;</td>
178 <td>NO</td>
179 <td>Yes</td>
180 </tr>
181 <tr>
182 <td>-fsm_style</td>
183 <td>&nbsp;</td>
184 <td>LUT</td>
185 <td>LUT</td>
186 </tr>
187 <tr>
188 <td>-ram_extract</td>
189 <td>&nbsp;</td>
190 <td>Yes</td>
191 <td>Yes</td>
192 </tr>
193 <tr>
194 <td>-ram_style</td>
195 <td>&nbsp;</td>
196 <td>Auto</td>
197 <td>Auto</td>
198 </tr>
199 <tr>
200 <td>-rom_extract</td>
201 <td>&nbsp;</td>
202 <td>Yes</td>
203 <td>Yes</td>
204 </tr>
205 <tr>
206 <td>-shreg_extract</td>
207 <td>&nbsp;</td>
208 <td>YES</td>
209 <td>Yes</td>
210 </tr>
211 <tr>
212 <td>-rom_style</td>
213 <td>&nbsp;</td>
214 <td>Auto</td>
215 <td>Auto</td>
216 </tr>
217 <tr>
218 <td>-auto_bram_packing</td>
219 <td>&nbsp;</td>
220 <td>NO</td>
221 <td>No</td>
222 </tr>
223 <tr>
224 <td>-resource_sharing</td>
225 <td>&nbsp;</td>
226 <td>YES</td>
227 <td>Yes</td>
228 </tr>
229 <tr>
230 <td>-async_to_sync</td>
231 <td>&nbsp;</td>
232 <td>NO</td>
233 <td>No</td>
234 </tr>
235 <tr>
236 <td>-use_dsp48</td>
237 <td>&nbsp;</td>
238 <td>Auto</td>
239 <td>Auto</td>
240 </tr>
241 <tr>
242 <td>-iobuf</td>
243 <td>&nbsp;</td>
244 <td>YES</td>
245 <td>Yes</td>
246 </tr>
247 <tr>
248 <td>-max_fanout</td>
249 <td>&nbsp;</td>
250 <td>100000</td>
251 <td>100000</td>
252 </tr>
253 <tr>
254 <td>-bufg</td>
255 <td>&nbsp;</td>
256 <td>16</td>
257 <td>16</td>
258 </tr>
259 <tr>
260 <td>-register_duplication</td>
261 <td>&nbsp;</td>
262 <td>YES</td>
263 <td>Yes</td>
264 </tr>
265 <tr>
266 <td>-register_balancing</td>
267 <td>&nbsp;</td>
268 <td>No</td>
269 <td>No</td>
270 </tr>
271 <tr>
272 <td>-optimize_primitives</td>
273 <td>&nbsp;</td>
274 <td>NO</td>
275 <td>No</td>
276 </tr>
277 <tr>
278 <td>-use_clock_enable</td>
279 <td>&nbsp;</td>
280 <td>Auto</td>
281 <td>Auto</td>
282 </tr>
283 <tr>
284 <td>-use_sync_set</td>
285 <td>&nbsp;</td>
286 <td>Auto</td>
287 <td>Auto</td>
288 </tr>
289 <tr>
290 <td>-use_sync_reset</td>
291 <td>&nbsp;</td>
292 <td>Auto</td>
293 <td>Auto</td>
294 </tr>
295 <tr>
296 <td>-iob</td>
297 <td>&nbsp;</td>
298 <td>True</td>
299 <td>Auto</td>
300 </tr>
301 <tr>
302 <td>-equivalent_register_removal</td>
303 <td>&nbsp;</td>
304 <td>YES</td>
305 <td>Yes</td>
306 </tr>
307 <tr>
308 <td>-slice_utilization_ratio_maxmargin</td>
309 <td>&nbsp;</td>
310 <td>5</td>
311 <td>0</td>
312 </tr>
313 </TABLE>
314 <A NAME="Translation Property Settings"></A>
315 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
316 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
317 <TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
318 </tr>
319 <tr bgcolor='#ffff99'>
320 <td><b>Switch Name</b></td>
321 <td><b>Property Name</b></td>
322 <td><b>Value</b></td>
323 <td><b>Default Value</b></td>
324 </tr>
325 <tr>
326 <td>-aul</td>
327 <td>Allow Unmatched LOC Constraints</td>
328 <td>true</td>
329 <td>false</td>
330 </tr>
331 <tr>
332 <td>-intstyle</td>
333 <td>&nbsp;</td>
334 <td>ise</td>
335 <td>None</td>
336 </tr>
337 <tr>
338 <td>-dd</td>
339 <td>&nbsp;</td>
340 <td>_ngo</td>
341 <td>None</td>
342 </tr>
343 <tr>
344 <td>-p</td>
345 <td>&nbsp;</td>
346 <td>xc6slx45-fgg484-3</td>
347 <td>None</td>
348 </tr>
349 <tr>
350 <td>-sd</td>
351 <td>Macro Search Path</td>
352 <td>../../netlists/xilinx/Spartan3</td>
353 <td>None</td>
354 </tr>
355 <tr>
356 <td>-uc</td>
357 <td>&nbsp;</td>
358 <td>leon3mp.ucf</td>
359 <td>None</td>
360 </tr>
361 </TABLE>
362 <A NAME="Operating System Information"></A>
363 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
364 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
365 <TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
366 </tr>
367 <tr bgcolor='#ffff99'>
368 <td><b>Operating System Information</b></td>
369 <td><b>xst</b></td>
370 <td><b>ngdbuild</b></td>
371 <td><b>map</b></td>
372 <td><b>par</b></td>
373 </tr>
374 <tr>
375 <td>CPU Architecture/Speed</td>
376 <td>Intel(R) Core(TM) i5-2557M CPU @ 1.70GHz/1701.000 MHz</td>
377 <td>Intel(R) Core(TM) i5-2557M CPU @ 1.70GHz/800.000 MHz</td>
378 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
379 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
380 </tr>
381 <tr>
382 <td>Host</td>
383 <td>pc-de-jeandet3.lab-lpp.local</td>
384 <td>pc-de-jeandet3.lab-lpp.local</td>
385 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
386 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
387 </tr>
388 <tr>
389 <td>OS Name</td>
390 <td>Fedora</td>
391 <td>Fedora</td>
392 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
393 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
394 </tr>
395 <tr>
396 <td>OS Release</td>
397 <td>Fedora release 18 (Spherical Cow)</td>
398 <td>Fedora release 18 (Spherical Cow)</td>
399 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
400 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
401 </tr>
402 </TABLE>
403 403 </BODY> </HTML> No newline at end of file
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@@ -1,10 +1,10
1 #define MCFG1 0x10380033
2 #define MCFG2 0xe6B86e60
3 #define MCFG3 0x000ff000
4 #define ASDCFG 0x80000000
5 #define DSDCFG 0xe6A06e60
6 #define L2MCTRLIO 0x80000000
7 #define IRQCTRL 0x80000200
8 #define RAMSTART 0x40000000
9 #define RAMSIZE 0x00100000
10
1 #define MCFG1 0x10380033
2 #define MCFG2 0xe6B86e60
3 #define MCFG3 0x000ff000
4 #define ASDCFG 0x80000000
5 #define DSDCFG 0xe6A06e60
6 #define L2MCTRLIO 0x80000000
7 #define IRQCTRL 0x80000200
8 #define RAMSTART 0x40000000
9 #define RAMSIZE 0x00100000
10
Show file before | Show file after | Hide comments
@@ -1,13 +1,13
1
2 SPARTAN6 50 MHz, MIG DDR2, 2x8 + 2x4 cache, GRFPU
3
4 LEON3 LEON3FTV2
5 Dhrystone 78.4 78.4
6 Whetstone DP 27.7 27.7
7 gzip 43.98 s 41.38 s
8 bzip2 248.22 s 200.10 s
9 176.gcc 208.62 s 180.48 s
10 coremark 100.12 i/s 100.12 i/s
11 aocs_v8 12388.7 i/s 12388.7 i/s
12 basicmath_large 13245.0 i/s 13245.0 i/s
13 linpack_unroll_dp_v8 3265 KFLOPS 3563 KFLOPS
1
2 SPARTAN6 50 MHz, MIG DDR2, 2x8 + 2x4 cache, GRFPU
3
4 LEON3 LEON3FTV2
5 Dhrystone 78.4 78.4
6 Whetstone DP 27.7 27.7
7 gzip 43.98 s 41.38 s
8 bzip2 248.22 s 200.10 s
9 176.gcc 208.62 s 180.48 s
10 coremark 100.12 i/s 100.12 i/s
11 aocs_v8 12388.7 i/s 12388.7 i/s
12 basicmath_large 13245.0 i/s 13245.0 i/s
13 linpack_unroll_dp_v8 3265 KFLOPS 3563 KFLOPS
Show file before | Show file after | Hide comments
@@ -1,18 +1,18
1
2 main()
3
4 {
5 report_start();
6
7
8 // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
9 base_test();
10 /*
11 greth_test(0x80000e00);
12 spw_test(0x80100A00);
13 spw_test(0x80100B00);
14 spw_test(0x80100C00);
15 svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
16 */
17 report_end();
18 }
1
2 main()
3
4 {
5 report_start();
6
7
8 // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
9 base_test();
10 /*
11 greth_test(0x80000e00);
12 spw_test(0x80100A00);
13 spw_test(0x80100B00);
14 spw_test(0x80100C00);
15 svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
16 */
17 report_end();
18 }
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (2102 lines changed) Show them Hide them
@@ -1,1051 +1,1051
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_AXDSP
14 #define CONFIG_SYN_TECH axdsp
15 #elif defined CONFIG_SYN_PROASICPLUS
16 #define CONFIG_SYN_TECH proasic
17 #elif defined CONFIG_SYN_ALTERA
18 #define CONFIG_SYN_TECH altera
19 #elif defined CONFIG_SYN_STRATIX
20 #define CONFIG_SYN_TECH stratix1
21 #elif defined CONFIG_SYN_STRATIXII
22 #define CONFIG_SYN_TECH stratix2
23 #elif defined CONFIG_SYN_STRATIXIII
24 #define CONFIG_SYN_TECH stratix3
25 #elif defined CONFIG_SYN_CYCLONEIII
26 #define CONFIG_SYN_TECH cyclone3
27 #elif defined CONFIG_SYN_EASIC45
28 #define CONFIG_SYN_TECH easic45
29 #elif defined CONFIG_SYN_EASIC90
30 #define CONFIG_SYN_TECH easic90
31 #elif defined CONFIG_SYN_IHP25
32 #define CONFIG_SYN_TECH ihp25
33 #elif defined CONFIG_SYN_IHP25RH
34 #define CONFIG_SYN_TECH ihp25rh
35 #elif defined CONFIG_SYN_CMOS9SF
36 #define CONFIG_SYN_TECH cmos9sf
37 #elif defined CONFIG_SYN_LATTICE
38 #define CONFIG_SYN_TECH lattice
39 #elif defined CONFIG_SYN_ECLIPSE
40 #define CONFIG_SYN_TECH eclipse
41 #elif defined CONFIG_SYN_PEREGRINE
42 #define CONFIG_SYN_TECH peregrine
43 #elif defined CONFIG_SYN_PROASIC
44 #define CONFIG_SYN_TECH proasic
45 #elif defined CONFIG_SYN_PROASIC3
46 #define CONFIG_SYN_TECH apa3
47 #elif defined CONFIG_SYN_PROASIC3E
48 #define CONFIG_SYN_TECH apa3e
49 #elif defined CONFIG_SYN_PROASIC3L
50 #define CONFIG_SYN_TECH apa3l
51 #elif defined CONFIG_SYN_IGLOO
52 #define CONFIG_SYN_TECH apa3
53 #elif defined CONFIG_SYN_FUSION
54 #define CONFIG_SYN_TECH actfus
55 #elif defined CONFIG_SYN_SPARTAN2
56 #define CONFIG_SYN_TECH virtex
57 #elif defined CONFIG_SYN_VIRTEX
58 #define CONFIG_SYN_TECH virtex
59 #elif defined CONFIG_SYN_VIRTEXE
60 #define CONFIG_SYN_TECH virtex
61 #elif defined CONFIG_SYN_SPARTAN3
62 #define CONFIG_SYN_TECH spartan3
63 #elif defined CONFIG_SYN_SPARTAN3E
64 #define CONFIG_SYN_TECH spartan3e
65 #elif defined CONFIG_SYN_SPARTAN6
66 #define CONFIG_SYN_TECH spartan6
67 #elif defined CONFIG_SYN_VIRTEX2
68 #define CONFIG_SYN_TECH virtex2
69 #elif defined CONFIG_SYN_VIRTEX4
70 #define CONFIG_SYN_TECH virtex4
71 #elif defined CONFIG_SYN_VIRTEX5
72 #define CONFIG_SYN_TECH virtex5
73 #elif defined CONFIG_SYN_VIRTEX6
74 #define CONFIG_SYN_TECH virtex6
75 #elif defined CONFIG_SYN_RH_LIB18T
76 #define CONFIG_SYN_TECH rhlib18t
77 #elif defined CONFIG_SYN_SMIC13
78 #define CONFIG_SYN_TECH smic013
79 #elif defined CONFIG_SYN_UT025CRH
80 #define CONFIG_SYN_TECH ut25
81 #elif defined CONFIG_SYN_UT130HBD
82 #define CONFIG_SYN_TECH ut130
83 #elif defined CONFIG_SYN_UT90NHBD
84 #define CONFIG_SYN_TECH ut90
85 #elif defined CONFIG_SYN_TSMC90
86 #define CONFIG_SYN_TECH tsmc90
87 #elif defined CONFIG_SYN_TM65GPLUS
88 #define CONFIG_SYN_TECH tm65gpl
89 #elif defined CONFIG_SYN_CUSTOM1
90 #define CONFIG_SYN_TECH custom1
91 #else
92 #error "unknown target technology"
93 #endif
94
95 #if defined CONFIG_SYN_INFER_RAM
96 #define CFG_RAM_TECH inferred
97 #elif defined CONFIG_MEM_UMC
98 #define CFG_RAM_TECH umc
99 #elif defined CONFIG_MEM_RHUMC
100 #define CFG_RAM_TECH rhumc
101 #elif defined CONFIG_MEM_VIRAGE
102 #define CFG_RAM_TECH memvirage
103 #elif defined CONFIG_MEM_ARTISAN
104 #define CFG_RAM_TECH memartisan
105 #elif defined CONFIG_MEM_CUSTOM1
106 #define CFG_RAM_TECH custom1
107 #elif defined CONFIG_MEM_VIRAGE90
108 #define CFG_RAM_TECH memvirage90
109 #elif defined CONFIG_MEM_INFERRED
110 #define CFG_RAM_TECH inferred
111 #else
112 #define CFG_RAM_TECH CONFIG_SYN_TECH
113 #endif
114
115 #if defined CONFIG_SYN_INFER_PADS
116 #define CFG_PAD_TECH inferred
117 #else
118 #define CFG_PAD_TECH CONFIG_SYN_TECH
119 #endif
120
121 #ifndef CONFIG_SYN_NO_ASYNC
122 #define CONFIG_SYN_NO_ASYNC 0
123 #endif
124
125 #ifndef CONFIG_SYN_SCAN
126 #define CONFIG_SYN_SCAN 0
127 #endif
128
129
130 #if defined CONFIG_CLK_ALTDLL
131 #define CFG_CLK_TECH CONFIG_SYN_TECH
132 #elif defined CONFIG_CLK_HCLKBUF
133 #define CFG_CLK_TECH axcel
134 #elif defined CONFIG_CLK_LATDLL
135 #define CFG_CLK_TECH lattice
136 #elif defined CONFIG_CLK_PRO3PLL
137 #define CFG_CLK_TECH apa3
138 #elif defined CONFIG_CLK_PRO3EPLL
139 #define CFG_CLK_TECH apa3e
140 #elif defined CONFIG_CLK_PRO3LPLL
141 #define CFG_CLK_TECH apa3l
142 #elif defined CONFIG_CLK_FUSPLL
143 #define CFG_CLK_TECH actfus
144 #elif defined CONFIG_CLK_CLKDLL
145 #define CFG_CLK_TECH virtex
146 #elif defined CONFIG_CLK_DCM
147 #define CFG_CLK_TECH CONFIG_SYN_TECH
148 #elif defined CONFIG_CLK_LIB18T
149 #define CFG_CLK_TECH rhlib18t
150 #elif defined CONFIG_CLK_RHUMC
151 #define CFG_CLK_TECH rhumc
152 #elif defined CONFIG_CLK_UT130HBD
153 #define CFG_CLK_TECH ut130
154 #else
155 #define CFG_CLK_TECH inferred
156 #endif
157
158 #ifndef CONFIG_CLK_MUL
159 #define CONFIG_CLK_MUL 2
160 #endif
161
162 #ifndef CONFIG_CLK_DIV
163 #define CONFIG_CLK_DIV 2
164 #endif
165
166 #ifndef CONFIG_OCLK_DIV
167 #define CONFIG_OCLK_DIV 1
168 #endif
169
170 #ifndef CONFIG_OCLKB_DIV
171 #define CONFIG_OCLKB_DIV 0
172 #endif
173
174 #ifndef CONFIG_OCLKC_DIV
175 #define CONFIG_OCLKC_DIV 0
176 #endif
177
178 #ifndef CONFIG_PCI_CLKDLL
179 #define CONFIG_PCI_CLKDLL 0
180 #endif
181
182 #ifndef CONFIG_PCI_SYSCLK
183 #define CONFIG_PCI_SYSCLK 0
184 #endif
185
186 #ifndef CONFIG_CLK_NOFB
187 #define CONFIG_CLK_NOFB 0
188 #endif
189 #ifndef CONFIG_LEON3
190 #define CONFIG_LEON3 0
191 #endif
192
193 #ifndef CONFIG_PROC_NUM
194 #define CONFIG_PROC_NUM 1
195 #endif
196
197 #ifndef CONFIG_IU_NWINDOWS
198 #define CONFIG_IU_NWINDOWS 8
199 #endif
200
201 #ifndef CONFIG_IU_RSTADDR
202 #define CONFIG_IU_RSTADDR 8
203 #endif
204
205 #ifndef CONFIG_IU_LDELAY
206 #define CONFIG_IU_LDELAY 1
207 #endif
208
209 #ifndef CONFIG_IU_WATCHPOINTS
210 #define CONFIG_IU_WATCHPOINTS 0
211 #endif
212
213 #ifdef CONFIG_IU_V8MULDIV
214 #ifdef CONFIG_IU_MUL_LATENCY_4
215 #define CFG_IU_V8 1
216 #elif defined CONFIG_IU_MUL_LATENCY_5
217 #define CFG_IU_V8 2
218 #elif defined CONFIG_IU_MUL_LATENCY_2
219 #define CFG_IU_V8 16#32#
220 #endif
221 #else
222 #define CFG_IU_V8 0
223 #endif
224
225 #ifdef CONFIG_IU_MUL_MODGEN
226 #define CFG_IU_MUL_STRUCT 1
227 #elif defined CONFIG_IU_MUL_TECHSPEC
228 #define CFG_IU_MUL_STRUCT 2
229 #elif defined CONFIG_IU_MUL_DW
230 #define CFG_IU_MUL_STRUCT 3
231 #else
232 #define CFG_IU_MUL_STRUCT 0
233 #endif
234
235 #ifndef CONFIG_PWD
236 #define CONFIG_PWD 0
237 #endif
238
239 #ifndef CONFIG_IU_MUL_MAC
240 #define CONFIG_IU_MUL_MAC 0
241 #endif
242
243 #ifndef CONFIG_IU_BP
244 #define CONFIG_IU_BP 0
245 #endif
246
247 #ifndef CONFIG_NOTAG
248 #define CONFIG_NOTAG 0
249 #endif
250
251 #ifndef CONFIG_IU_SVT
252 #define CONFIG_IU_SVT 0
253 #endif
254
255 #if defined CONFIG_FPU_GRFPC1
256 #define CONFIG_FPU_GRFPC 1
257 #elif defined CONFIG_FPU_GRFPC2
258 #define CONFIG_FPU_GRFPC 2
259 #else
260 #define CONFIG_FPU_GRFPC 0
261 #endif
262
263 #if defined CONFIG_FPU_GRFPU_INFMUL
264 #define CONFIG_FPU_GRFPU_MUL 0
265 #elif defined CONFIG_FPU_GRFPU_DWMUL
266 #define CONFIG_FPU_GRFPU_MUL 1
267 #elif defined CONFIG_FPU_GRFPU_MODGEN
268 #define CONFIG_FPU_GRFPU_MUL 2
269 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
270 #define CONFIG_FPU_GRFPU_MUL 3
271 #else
272 #define CONFIG_FPU_GRFPU_MUL 0
273 #endif
274
275 #if defined CONFIG_FPU_GRFPU_SH
276 #define CONFIG_FPU_GRFPU_SHARED 1
277 #else
278 #define CONFIG_FPU_GRFPU_SHARED 0
279 #endif
280
281 #if defined CONFIG_FPU_GRFPU
282 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
283 #elif defined CONFIG_FPU_MEIKO
284 #define CONFIG_FPU 15
285 #elif defined CONFIG_FPU_GRFPULITE
286 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
287 #else
288 #define CONFIG_FPU 0
289 #endif
290
291 #ifndef CONFIG_FPU_NETLIST
292 #define CONFIG_FPU_NETLIST 0
293 #endif
294
295 #ifndef CONFIG_ICACHE_ENABLE
296 #define CONFIG_ICACHE_ENABLE 0
297 #endif
298
299 #if defined CONFIG_ICACHE_ASSO1
300 #define CFG_IU_ISETS 1
301 #elif defined CONFIG_ICACHE_ASSO2
302 #define CFG_IU_ISETS 2
303 #elif defined CONFIG_ICACHE_ASSO3
304 #define CFG_IU_ISETS 3
305 #elif defined CONFIG_ICACHE_ASSO4
306 #define CFG_IU_ISETS 4
307 #else
308 #define CFG_IU_ISETS 1
309 #endif
310
311 #if defined CONFIG_ICACHE_SZ1
312 #define CFG_ICACHE_SZ 1
313 #elif defined CONFIG_ICACHE_SZ2
314 #define CFG_ICACHE_SZ 2
315 #elif defined CONFIG_ICACHE_SZ4
316 #define CFG_ICACHE_SZ 4
317 #elif defined CONFIG_ICACHE_SZ8
318 #define CFG_ICACHE_SZ 8
319 #elif defined CONFIG_ICACHE_SZ16
320 #define CFG_ICACHE_SZ 16
321 #elif defined CONFIG_ICACHE_SZ32
322 #define CFG_ICACHE_SZ 32
323 #elif defined CONFIG_ICACHE_SZ64
324 #define CFG_ICACHE_SZ 64
325 #elif defined CONFIG_ICACHE_SZ128
326 #define CFG_ICACHE_SZ 128
327 #elif defined CONFIG_ICACHE_SZ256
328 #define CFG_ICACHE_SZ 256
329 #else
330 #define CFG_ICACHE_SZ 1
331 #endif
332
333 #ifdef CONFIG_ICACHE_LZ16
334 #define CFG_ILINE_SZ 4
335 #else
336 #define CFG_ILINE_SZ 8
337 #endif
338
339 #if defined CONFIG_ICACHE_ALGODIR
340 #define CFG_ICACHE_ALGORND 3
341 #elif defined CONFIG_ICACHE_ALGORND
342 #define CFG_ICACHE_ALGORND 2
343 #elif defined CONFIG_ICACHE_ALGOLRR
344 #define CFG_ICACHE_ALGORND 1
345 #else
346 #define CFG_ICACHE_ALGORND 0
347 #endif
348
349 #ifndef CONFIG_ICACHE_LOCK
350 #define CONFIG_ICACHE_LOCK 0
351 #endif
352
353 #ifndef CONFIG_ICACHE_LRAM
354 #define CONFIG_ICACHE_LRAM 0
355 #endif
356
357 #ifndef CONFIG_ICACHE_LRSTART
358 #define CONFIG_ICACHE_LRSTART 8E
359 #endif
360
361 #if defined CONFIG_ICACHE_LRAM_SZ2
362 #define CFG_ILRAM_SIZE 2
363 #elif defined CONFIG_ICACHE_LRAM_SZ4
364 #define CFG_ILRAM_SIZE 4
365 #elif defined CONFIG_ICACHE_LRAM_SZ8
366 #define CFG_ILRAM_SIZE 8
367 #elif defined CONFIG_ICACHE_LRAM_SZ16
368 #define CFG_ILRAM_SIZE 16
369 #elif defined CONFIG_ICACHE_LRAM_SZ32
370 #define CFG_ILRAM_SIZE 32
371 #elif defined CONFIG_ICACHE_LRAM_SZ64
372 #define CFG_ILRAM_SIZE 64
373 #elif defined CONFIG_ICACHE_LRAM_SZ128
374 #define CFG_ILRAM_SIZE 128
375 #elif defined CONFIG_ICACHE_LRAM_SZ256
376 #define CFG_ILRAM_SIZE 256
377 #else
378 #define CFG_ILRAM_SIZE 1
379 #endif
380
381
382 #ifndef CONFIG_DCACHE_ENABLE
383 #define CONFIG_DCACHE_ENABLE 0
384 #endif
385
386 #if defined CONFIG_DCACHE_ASSO1
387 #define CFG_IU_DSETS 1
388 #elif defined CONFIG_DCACHE_ASSO2
389 #define CFG_IU_DSETS 2
390 #elif defined CONFIG_DCACHE_ASSO3
391 #define CFG_IU_DSETS 3
392 #elif defined CONFIG_DCACHE_ASSO4
393 #define CFG_IU_DSETS 4
394 #else
395 #define CFG_IU_DSETS 1
396 #endif
397
398 #if defined CONFIG_DCACHE_SZ1
399 #define CFG_DCACHE_SZ 1
400 #elif defined CONFIG_DCACHE_SZ2
401 #define CFG_DCACHE_SZ 2
402 #elif defined CONFIG_DCACHE_SZ4
403 #define CFG_DCACHE_SZ 4
404 #elif defined CONFIG_DCACHE_SZ8
405 #define CFG_DCACHE_SZ 8
406 #elif defined CONFIG_DCACHE_SZ16
407 #define CFG_DCACHE_SZ 16
408 #elif defined CONFIG_DCACHE_SZ32
409 #define CFG_DCACHE_SZ 32
410 #elif defined CONFIG_DCACHE_SZ64
411 #define CFG_DCACHE_SZ 64
412 #elif defined CONFIG_DCACHE_SZ128
413 #define CFG_DCACHE_SZ 128
414 #elif defined CONFIG_DCACHE_SZ256
415 #define CFG_DCACHE_SZ 256
416 #else
417 #define CFG_DCACHE_SZ 1
418 #endif
419
420 #ifdef CONFIG_DCACHE_LZ16
421 #define CFG_DLINE_SZ 4
422 #else
423 #define CFG_DLINE_SZ 8
424 #endif
425
426 #if defined CONFIG_DCACHE_ALGODIR
427 #define CFG_DCACHE_ALGORND 3
428 #elif defined CONFIG_DCACHE_ALGORND
429 #define CFG_DCACHE_ALGORND 2
430 #elif defined CONFIG_DCACHE_ALGOLRR
431 #define CFG_DCACHE_ALGORND 1
432 #else
433 #define CFG_DCACHE_ALGORND 0
434 #endif
435
436 #ifndef CONFIG_DCACHE_LOCK
437 #define CONFIG_DCACHE_LOCK 0
438 #endif
439
440 #ifndef CONFIG_DCACHE_SNOOP
441 #define CONFIG_DCACHE_SNOOP 0
442 #endif
443
444 #ifndef CONFIG_DCACHE_SNOOP_FAST
445 #define CONFIG_DCACHE_SNOOP_FAST 0
446 #endif
447
448 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
449 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
450 #endif
451
452 #ifndef CONFIG_CACHE_FIXED
453 #define CONFIG_CACHE_FIXED 0
454 #endif
455
456 #ifndef CONFIG_DCACHE_LRAM
457 #define CONFIG_DCACHE_LRAM 0
458 #endif
459
460 #ifndef CONFIG_DCACHE_LRSTART
461 #define CONFIG_DCACHE_LRSTART 8F
462 #endif
463
464 #if defined CONFIG_DCACHE_LRAM_SZ2
465 #define CFG_DLRAM_SIZE 2
466 #elif defined CONFIG_DCACHE_LRAM_SZ4
467 #define CFG_DLRAM_SIZE 4
468 #elif defined CONFIG_DCACHE_LRAM_SZ8
469 #define CFG_DLRAM_SIZE 8
470 #elif defined CONFIG_DCACHE_LRAM_SZ16
471 #define CFG_DLRAM_SIZE 16
472 #elif defined CONFIG_DCACHE_LRAM_SZ32
473 #define CFG_DLRAM_SIZE 32
474 #elif defined CONFIG_DCACHE_LRAM_SZ64
475 #define CFG_DLRAM_SIZE 64
476 #elif defined CONFIG_DCACHE_LRAM_SZ128
477 #define CFG_DLRAM_SIZE 128
478 #elif defined CONFIG_DCACHE_LRAM_SZ256
479 #define CFG_DLRAM_SIZE 256
480 #else
481 #define CFG_DLRAM_SIZE 1
482 #endif
483
484 #if defined CONFIG_MMU_PAGE_4K
485 #define CONFIG_MMU_PAGE 0
486 #elif defined CONFIG_MMU_PAGE_8K
487 #define CONFIG_MMU_PAGE 1
488 #elif defined CONFIG_MMU_PAGE_16K
489 #define CONFIG_MMU_PAGE 2
490 #elif defined CONFIG_MMU_PAGE_32K
491 #define CONFIG_MMU_PAGE 3
492 #elif defined CONFIG_MMU_PAGE_PROG
493 #define CONFIG_MMU_PAGE 4
494 #else
495 #define CONFIG_MMU_PAGE 0
496 #endif
497
498 #ifdef CONFIG_MMU_ENABLE
499 #define CONFIG_MMUEN 1
500
501 #ifdef CONFIG_MMU_SPLIT
502 #define CONFIG_TLB_TYPE 0
503 #endif
504 #ifdef CONFIG_MMU_COMBINED
505 #define CONFIG_TLB_TYPE 1
506 #endif
507
508 #ifdef CONFIG_MMU_REPARRAY
509 #define CONFIG_TLB_REP 0
510 #endif
511 #ifdef CONFIG_MMU_REPINCREMENT
512 #define CONFIG_TLB_REP 1
513 #endif
514
515 #ifdef CONFIG_MMU_I2
516 #define CONFIG_ITLBNUM 2
517 #endif
518 #ifdef CONFIG_MMU_I4
519 #define CONFIG_ITLBNUM 4
520 #endif
521 #ifdef CONFIG_MMU_I8
522 #define CONFIG_ITLBNUM 8
523 #endif
524 #ifdef CONFIG_MMU_I16
525 #define CONFIG_ITLBNUM 16
526 #endif
527 #ifdef CONFIG_MMU_I32
528 #define CONFIG_ITLBNUM 32
529 #endif
530
531 #define CONFIG_DTLBNUM 2
532 #ifdef CONFIG_MMU_D2
533 #undef CONFIG_DTLBNUM
534 #define CONFIG_DTLBNUM 2
535 #endif
536 #ifdef CONFIG_MMU_D4
537 #undef CONFIG_DTLBNUM
538 #define CONFIG_DTLBNUM 4
539 #endif
540 #ifdef CONFIG_MMU_D8
541 #undef CONFIG_DTLBNUM
542 #define CONFIG_DTLBNUM 8
543 #endif
544 #ifdef CONFIG_MMU_D16
545 #undef CONFIG_DTLBNUM
546 #define CONFIG_DTLBNUM 16
547 #endif
548 #ifdef CONFIG_MMU_D32
549 #undef CONFIG_DTLBNUM
550 #define CONFIG_DTLBNUM 32
551 #endif
552 #ifdef CONFIG_MMU_FASTWB
553 #define CFG_MMU_FASTWB 1
554 #else
555 #define CFG_MMU_FASTWB 0
556 #endif
557
558 #else
559 #define CONFIG_MMUEN 0
560 #define CONFIG_ITLBNUM 2
561 #define CONFIG_DTLBNUM 2
562 #define CONFIG_TLB_TYPE 1
563 #define CONFIG_TLB_REP 1
564 #define CFG_MMU_FASTWB 0
565 #endif
566
567 #ifndef CONFIG_DSU_ENABLE
568 #define CONFIG_DSU_ENABLE 0
569 #endif
570
571 #if defined CONFIG_DSU_ITRACESZ1
572 #define CFG_DSU_ITB 1
573 #elif CONFIG_DSU_ITRACESZ2
574 #define CFG_DSU_ITB 2
575 #elif CONFIG_DSU_ITRACESZ4
576 #define CFG_DSU_ITB 4
577 #elif CONFIG_DSU_ITRACESZ8
578 #define CFG_DSU_ITB 8
579 #elif CONFIG_DSU_ITRACESZ16
580 #define CFG_DSU_ITB 16
581 #else
582 #define CFG_DSU_ITB 0
583 #endif
584
585 #if defined CONFIG_DSU_ATRACESZ1
586 #define CFG_DSU_ATB 1
587 #elif CONFIG_DSU_ATRACESZ2
588 #define CFG_DSU_ATB 2
589 #elif CONFIG_DSU_ATRACESZ4
590 #define CFG_DSU_ATB 4
591 #elif CONFIG_DSU_ATRACESZ8
592 #define CFG_DSU_ATB 8
593 #elif CONFIG_DSU_ATRACESZ16
594 #define CFG_DSU_ATB 16
595 #else
596 #define CFG_DSU_ATB 0
597 #endif
598
599 #ifndef CONFIG_LEON3FT_EN
600 #define CONFIG_LEON3FT_EN 0
601 #endif
602
603 #if defined CONFIG_IUFT_PAR
604 #define CONFIG_IUFT_EN 1
605 #elif defined CONFIG_IUFT_DMR
606 #define CONFIG_IUFT_EN 2
607 #elif defined CONFIG_IUFT_BCH
608 #define CONFIG_IUFT_EN 3
609 #elif defined CONFIG_IUFT_TMR
610 #define CONFIG_IUFT_EN 4
611 #else
612 #define CONFIG_IUFT_EN 0
613 #endif
614 #ifndef CONFIG_RF_ERRINJ
615 #define CONFIG_RF_ERRINJ 0
616 #endif
617
618 #ifndef CONFIG_FPUFT_EN
619 #define CONFIG_FPUFT 0
620 #else
621 #ifdef CONFIG_FPU_GRFPU
622 #define CONFIG_FPUFT 2
623 #else
624 #define CONFIG_FPUFT 1
625 #endif
626 #endif
627
628 #ifndef CONFIG_CACHE_FT_EN
629 #define CONFIG_CACHE_FT_EN 0
630 #endif
631 #ifndef CONFIG_CACHE_ERRINJ
632 #define CONFIG_CACHE_ERRINJ 0
633 #endif
634
635 #ifndef CONFIG_LEON3_NETLIST
636 #define CONFIG_LEON3_NETLIST 0
637 #endif
638
639 #ifdef CONFIG_DEBUG_PC32
640 #define CFG_DEBUG_PC32 0
641 #else
642 #define CFG_DEBUG_PC32 2
643 #endif
644 #ifndef CONFIG_IU_DISAS
645 #define CONFIG_IU_DISAS 0
646 #endif
647 #ifndef CONFIG_IU_DISAS_NET
648 #define CONFIG_IU_DISAS_NET 0
649 #endif
650
651
652 #ifndef CONFIG_AHB_SPLIT
653 #define CONFIG_AHB_SPLIT 0
654 #endif
655
656 #ifndef CONFIG_AHB_RROBIN
657 #define CONFIG_AHB_RROBIN 0
658 #endif
659
660 #ifndef CONFIG_AHB_IOADDR
661 #define CONFIG_AHB_IOADDR FFF
662 #endif
663
664 #ifndef CONFIG_APB_HADDR
665 #define CONFIG_APB_HADDR 800
666 #endif
667
668 #ifndef CONFIG_AHB_MON
669 #define CONFIG_AHB_MON 0
670 #endif
671
672 #ifndef CONFIG_AHB_MONERR
673 #define CONFIG_AHB_MONERR 0
674 #endif
675
676 #ifndef CONFIG_AHB_MONWAR
677 #define CONFIG_AHB_MONWAR 0
678 #endif
679
680 #ifndef CONFIG_AHB_DTRACE
681 #define CONFIG_AHB_DTRACE 0
682 #endif
683
684 #ifndef CONFIG_DSU_JTAG
685 #define CONFIG_DSU_JTAG 0
686 #endif
687
688 #ifndef CONFIG_DSU_ETH
689 #define CONFIG_DSU_ETH 0
690 #endif
691
692 #ifndef CONFIG_DSU_IPMSB
693 #define CONFIG_DSU_IPMSB C0A8
694 #endif
695
696 #ifndef CONFIG_DSU_IPLSB
697 #define CONFIG_DSU_IPLSB 0033
698 #endif
699
700 #ifndef CONFIG_DSU_ETHMSB
701 #define CONFIG_DSU_ETHMSB 020000
702 #endif
703
704 #ifndef CONFIG_DSU_ETHLSB
705 #define CONFIG_DSU_ETHLSB 000009
706 #endif
707
708 #if defined CONFIG_DSU_ETHSZ1
709 #define CFG_DSU_ETHB 1
710 #elif CONFIG_DSU_ETHSZ2
711 #define CFG_DSU_ETHB 2
712 #elif CONFIG_DSU_ETHSZ4
713 #define CFG_DSU_ETHB 4
714 #elif CONFIG_DSU_ETHSZ8
715 #define CFG_DSU_ETHB 8
716 #elif CONFIG_DSU_ETHSZ16
717 #define CFG_DSU_ETHB 16
718 #elif CONFIG_DSU_ETHSZ32
719 #define CFG_DSU_ETHB 32
720 #else
721 #define CFG_DSU_ETHB 1
722 #endif
723
724 #ifndef CONFIG_DSU_ETH_PROG
725 #define CONFIG_DSU_ETH_PROG 0
726 #endif
727
728 #ifndef CONFIG_DSU_ETH_DIS
729 #define CONFIG_DSU_ETH_DIS 0
730 #endif
731
732 #ifndef CONFIG_MCTRL_LEON2
733 #define CONFIG_MCTRL_LEON2 0
734 #endif
735
736 #ifndef CONFIG_MCTRL_SDRAM
737 #define CONFIG_MCTRL_SDRAM 0
738 #endif
739
740 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
741 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
742 #endif
743
744 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
745 #define CONFIG_MCTRL_SDRAM_INVCLK 0
746 #endif
747
748 #ifndef CONFIG_MCTRL_SDRAM_BUS64
749 #define CONFIG_MCTRL_SDRAM_BUS64 0
750 #endif
751
752 #ifndef CONFIG_MCTRL_8BIT
753 #define CONFIG_MCTRL_8BIT 0
754 #endif
755
756 #ifndef CONFIG_MCTRL_16BIT
757 #define CONFIG_MCTRL_16BIT 0
758 #endif
759
760 #ifndef CONFIG_MCTRL_5CS
761 #define CONFIG_MCTRL_5CS 0
762 #endif
763
764 #ifndef CONFIG_MCTRL_EDAC
765 #define CONFIG_MCTRL_EDAC 0
766 #endif
767
768 #ifndef CONFIG_MCTRL_PAGE
769 #define CONFIG_MCTRL_PAGE 0
770 #endif
771
772 #ifndef CONFIG_MCTRL_PROGPAGE
773 #define CONFIG_MCTRL_PROGPAGE 0
774 #endif
775
776
777 #ifndef CONFIG_MIG_DDR2
778 #define CONFIG_MIG_DDR2 0
779 #endif
780
781 #ifndef CONFIG_MIG_RANKS
782 #define CONFIG_MIG_RANKS 1
783 #endif
784
785 #ifndef CONFIG_MIG_COLBITS
786 #define CONFIG_MIG_COLBITS 10
787 #endif
788
789 #ifndef CONFIG_MIG_ROWBITS
790 #define CONFIG_MIG_ROWBITS 13
791 #endif
792
793 #ifndef CONFIG_MIG_BANKBITS
794 #define CONFIG_MIG_BANKBITS 2
795 #endif
796
797 #ifndef CONFIG_MIG_HMASK
798 #define CONFIG_MIG_HMASK F00
799 #endif
800 #ifndef CONFIG_AHBSTAT_ENABLE
801 #define CONFIG_AHBSTAT_ENABLE 0
802 #endif
803
804 #ifndef CONFIG_AHBSTAT_NFTSLV
805 #define CONFIG_AHBSTAT_NFTSLV 1
806 #endif
807
808 #ifndef CONFIG_AHBROM_ENABLE
809 #define CONFIG_AHBROM_ENABLE 0
810 #endif
811
812 #ifndef CONFIG_AHBROM_START
813 #define CONFIG_AHBROM_START 000
814 #endif
815
816 #ifndef CONFIG_AHBROM_PIPE
817 #define CONFIG_AHBROM_PIPE 0
818 #endif
819
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
821 #define CONFIG_ROM_START 100
822 #else
823 #define CONFIG_ROM_START 000
824 #endif
825
826
827 #ifndef CONFIG_AHBRAM_ENABLE
828 #define CONFIG_AHBRAM_ENABLE 0
829 #endif
830
831 #ifndef CONFIG_AHBRAM_START
832 #define CONFIG_AHBRAM_START A00
833 #endif
834
835 #if defined CONFIG_AHBRAM_SZ1
836 #define CFG_AHBRAMSZ 1
837 #elif CONFIG_AHBRAM_SZ2
838 #define CFG_AHBRAMSZ 2
839 #elif CONFIG_AHBRAM_SZ4
840 #define CFG_AHBRAMSZ 4
841 #elif CONFIG_AHBRAM_SZ8
842 #define CFG_AHBRAMSZ 8
843 #elif CONFIG_AHBRAM_SZ16
844 #define CFG_AHBRAMSZ 16
845 #elif CONFIG_AHBRAM_SZ32
846 #define CFG_AHBRAMSZ 32
847 #elif CONFIG_AHBRAM_SZ64
848 #define CFG_AHBRAMSZ 64
849 #else
850 #define CFG_AHBRAMSZ 1
851 #endif
852
853 #ifndef CONFIG_GRETH_ENABLE
854 #define CONFIG_GRETH_ENABLE 0
855 #endif
856
857 #ifndef CONFIG_GRETH_GIGA
858 #define CONFIG_GRETH_GIGA 0
859 #endif
860
861 #if defined CONFIG_GRETH_FIFO4
862 #define CFG_GRETH_FIFO 4
863 #elif defined CONFIG_GRETH_FIFO8
864 #define CFG_GRETH_FIFO 8
865 #elif defined CONFIG_GRETH_FIFO16
866 #define CFG_GRETH_FIFO 16
867 #elif defined CONFIG_GRETH_FIFO32
868 #define CFG_GRETH_FIFO 32
869 #elif defined CONFIG_GRETH_FIFO64
870 #define CFG_GRETH_FIFO 64
871 #else
872 #define CFG_GRETH_FIFO 8
873 #endif
874
875 #ifndef CONFIG_UART1_ENABLE
876 #define CONFIG_UART1_ENABLE 0
877 #endif
878
879 #if defined CONFIG_UA1_FIFO1
880 #define CFG_UA1_FIFO 1
881 #elif defined CONFIG_UA1_FIFO2
882 #define CFG_UA1_FIFO 2
883 #elif defined CONFIG_UA1_FIFO4
884 #define CFG_UA1_FIFO 4
885 #elif defined CONFIG_UA1_FIFO8
886 #define CFG_UA1_FIFO 8
887 #elif defined CONFIG_UA1_FIFO16
888 #define CFG_UA1_FIFO 16
889 #elif defined CONFIG_UA1_FIFO32
890 #define CFG_UA1_FIFO 32
891 #else
892 #define CFG_UA1_FIFO 1
893 #endif
894
895 #ifndef CONFIG_IRQ3_ENABLE
896 #define CONFIG_IRQ3_ENABLE 0
897 #endif
898 #ifndef CONFIG_IRQ3_NSEC
899 #define CONFIG_IRQ3_NSEC 0
900 #endif
901 #ifndef CONFIG_GPT_ENABLE
902 #define CONFIG_GPT_ENABLE 0
903 #endif
904
905 #ifndef CONFIG_GPT_NTIM
906 #define CONFIG_GPT_NTIM 1
907 #endif
908
909 #ifndef CONFIG_GPT_SW
910 #define CONFIG_GPT_SW 8
911 #endif
912
913 #ifndef CONFIG_GPT_TW
914 #define CONFIG_GPT_TW 8
915 #endif
916
917 #ifndef CONFIG_GPT_IRQ
918 #define CONFIG_GPT_IRQ 8
919 #endif
920
921 #ifndef CONFIG_GPT_SEPIRQ
922 #define CONFIG_GPT_SEPIRQ 0
923 #endif
924 #ifndef CONFIG_GPT_ENABLE
925 #define CONFIG_GPT_ENABLE 0
926 #endif
927
928 #ifndef CONFIG_GPT_NTIM
929 #define CONFIG_GPT_NTIM 1
930 #endif
931
932 #ifndef CONFIG_GPT_SW
933 #define CONFIG_GPT_SW 8
934 #endif
935
936 #ifndef CONFIG_GPT_TW
937 #define CONFIG_GPT_TW 8
938 #endif
939
940 #ifndef CONFIG_GPT_IRQ
941 #define CONFIG_GPT_IRQ 8
942 #endif
943
944 #ifndef CONFIG_GPT_SEPIRQ
945 #define CONFIG_GPT_SEPIRQ 0
946 #endif
947
948 #ifndef CONFIG_GPT_WDOGEN
949 #define CONFIG_GPT_WDOGEN 0
950 #endif
951
952 #ifndef CONFIG_GPT_WDOG
953 #define CONFIG_GPT_WDOG 0
954 #endif
955
956 #ifndef CONFIG_GRGPIO_ENABLE
957 #define CONFIG_GRGPIO_ENABLE 0
958 #endif
959 #ifndef CONFIG_GRGPIO_IMASK
960 #define CONFIG_GRGPIO_IMASK 0000
961 #endif
962 #ifndef CONFIG_GRGPIO_WIDTH
963 #define CONFIG_GRGPIO_WIDTH 1
964 #endif
965
966 #ifndef CONFIG_VGA_ENABLE
967 #define CONFIG_VGA_ENABLE 0
968 #endif
969 #ifndef CONFIG_SVGA_ENABLE
970 #define CONFIG_SVGA_ENABLE 0
971 #endif
972 #ifndef CONFIG_KBD_ENABLE
973 #define CONFIG_KBD_ENABLE 0
974 #endif
975
976
977 #ifndef CONFIG_SPIMCTRL
978 #define CONFIG_SPIMCTRL 0
979 #endif
980
981 #ifndef CONFIG_SPIMCTRL_SDCARD
982 #define CONFIG_SPIMCTRL_SDCARD 0
983 #endif
984
985 #ifndef CONFIG_SPIMCTRL_READCMD
986 #define CONFIG_SPIMCTRL_READCMD 0
987 #endif
988
989 #ifndef CONFIG_SPIMCTRL_DUMMYBYTE
990 #define CONFIG_SPIMCTRL_DUMMYBYTE 0
991 #endif
992
993 #ifndef CONFIG_SPIMCTRL_DUALOUTPUT
994 #define CONFIG_SPIMCTRL_DUALOUTPUT 0
995 #endif
996
997 #ifndef CONFIG_SPIMCTRL_SCALER
998 #define CONFIG_SPIMCTRL_SCALER 1
999 #endif
1000
1001 #ifndef CONFIG_SPIMCTRL_ASCALER
1002 #define CONFIG_SPIMCTRL_ASCALER 1
1003 #endif
1004
1005 #ifndef CONFIG_SPIMCTRL_PWRUPCNT
1006 #define CONFIG_SPIMCTRL_PWRUPCNT 0
1007 #endif
1008 #ifndef CONFIG_SPICTRL_ENABLE
1009 #define CONFIG_SPICTRL_ENABLE 0
1010 #endif
1011 #ifndef CONFIG_SPICTRL_NUM
1012 #define CONFIG_SPICTRL_NUM 1
1013 #endif
1014 #ifndef CONFIG_SPICTRL_SLVS
1015 #define CONFIG_SPICTRL_SLVS 1
1016 #endif
1017 #ifndef CONFIG_SPICTRL_FIFO
1018 #define CONFIG_SPICTRL_FIFO 1
1019 #endif
1020 #ifndef CONFIG_SPICTRL_SLVREG
1021 #define CONFIG_SPICTRL_SLVREG 0
1022 #endif
1023 #ifndef CONFIG_SPICTRL_ODMODE
1024 #define CONFIG_SPICTRL_ODMODE 0
1025 #endif
1026 #ifndef CONFIG_SPICTRL_AM
1027 #define CONFIG_SPICTRL_AM 0
1028 #endif
1029 #ifndef CONFIG_SPICTRL_ASEL
1030 #define CONFIG_SPICTRL_ASEL 0
1031 #endif
1032 #ifndef CONFIG_SPICTRL_TWEN
1033 #define CONFIG_SPICTRL_TWEN 0
1034 #endif
1035 #ifndef CONFIG_SPICTRL_MAXWLEN
1036 #define CONFIG_SPICTRL_MAXWLEN 0
1037 #endif
1038 #ifndef CONFIG_SPICTRL_SYNCRAM
1039 #define CONFIG_SPICTRL_SYNCRAM 0
1040 #endif
1041 #if defined(CONFIG_SPICTRL_DMRFT)
1042 #define CONFIG_SPICTRL_FT 1
1043 #elif defined(CONFIG_SPICTRL_TMRFT)
1044 #define CONFIG_SPICTRL_FT 2
1045 #else
1046 #define CONFIG_SPICTRL_FT 0
1047 #endif
1048
1049 #ifndef CONFIG_DEBUG_UART
1050 #define CONFIG_DEBUG_UART 0
1051 #endif
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_AXDSP
14 #define CONFIG_SYN_TECH axdsp
15 #elif defined CONFIG_SYN_PROASICPLUS
16 #define CONFIG_SYN_TECH proasic
17 #elif defined CONFIG_SYN_ALTERA
18 #define CONFIG_SYN_TECH altera
19 #elif defined CONFIG_SYN_STRATIX
20 #define CONFIG_SYN_TECH stratix1
21 #elif defined CONFIG_SYN_STRATIXII
22 #define CONFIG_SYN_TECH stratix2
23 #elif defined CONFIG_SYN_STRATIXIII
24 #define CONFIG_SYN_TECH stratix3
25 #elif defined CONFIG_SYN_CYCLONEIII
26 #define CONFIG_SYN_TECH cyclone3
27 #elif defined CONFIG_SYN_EASIC45
28 #define CONFIG_SYN_TECH easic45
29 #elif defined CONFIG_SYN_EASIC90
30 #define CONFIG_SYN_TECH easic90
31 #elif defined CONFIG_SYN_IHP25
32 #define CONFIG_SYN_TECH ihp25
33 #elif defined CONFIG_SYN_IHP25RH
34 #define CONFIG_SYN_TECH ihp25rh
35 #elif defined CONFIG_SYN_CMOS9SF
36 #define CONFIG_SYN_TECH cmos9sf
37 #elif defined CONFIG_SYN_LATTICE
38 #define CONFIG_SYN_TECH lattice
39 #elif defined CONFIG_SYN_ECLIPSE
40 #define CONFIG_SYN_TECH eclipse
41 #elif defined CONFIG_SYN_PEREGRINE
42 #define CONFIG_SYN_TECH peregrine
43 #elif defined CONFIG_SYN_PROASIC
44 #define CONFIG_SYN_TECH proasic
45 #elif defined CONFIG_SYN_PROASIC3
46 #define CONFIG_SYN_TECH apa3
47 #elif defined CONFIG_SYN_PROASIC3E
48 #define CONFIG_SYN_TECH apa3e
49 #elif defined CONFIG_SYN_PROASIC3L
50 #define CONFIG_SYN_TECH apa3l
51 #elif defined CONFIG_SYN_IGLOO
52 #define CONFIG_SYN_TECH apa3
53 #elif defined CONFIG_SYN_FUSION
54 #define CONFIG_SYN_TECH actfus
55 #elif defined CONFIG_SYN_SPARTAN2
56 #define CONFIG_SYN_TECH virtex
57 #elif defined CONFIG_SYN_VIRTEX
58 #define CONFIG_SYN_TECH virtex
59 #elif defined CONFIG_SYN_VIRTEXE
60 #define CONFIG_SYN_TECH virtex
61 #elif defined CONFIG_SYN_SPARTAN3
62 #define CONFIG_SYN_TECH spartan3
63 #elif defined CONFIG_SYN_SPARTAN3E
64 #define CONFIG_SYN_TECH spartan3e
65 #elif defined CONFIG_SYN_SPARTAN6
66 #define CONFIG_SYN_TECH spartan6
67 #elif defined CONFIG_SYN_VIRTEX2
68 #define CONFIG_SYN_TECH virtex2
69 #elif defined CONFIG_SYN_VIRTEX4
70 #define CONFIG_SYN_TECH virtex4
71 #elif defined CONFIG_SYN_VIRTEX5
72 #define CONFIG_SYN_TECH virtex5
73 #elif defined CONFIG_SYN_VIRTEX6
74 #define CONFIG_SYN_TECH virtex6
75 #elif defined CONFIG_SYN_RH_LIB18T
76 #define CONFIG_SYN_TECH rhlib18t
77 #elif defined CONFIG_SYN_SMIC13
78 #define CONFIG_SYN_TECH smic013
79 #elif defined CONFIG_SYN_UT025CRH
80 #define CONFIG_SYN_TECH ut25
81 #elif defined CONFIG_SYN_UT130HBD
82 #define CONFIG_SYN_TECH ut130
83 #elif defined CONFIG_SYN_UT90NHBD
84 #define CONFIG_SYN_TECH ut90
85 #elif defined CONFIG_SYN_TSMC90
86 #define CONFIG_SYN_TECH tsmc90
87 #elif defined CONFIG_SYN_TM65GPLUS
88 #define CONFIG_SYN_TECH tm65gpl
89 #elif defined CONFIG_SYN_CUSTOM1
90 #define CONFIG_SYN_TECH custom1
91 #else
92 #error "unknown target technology"
93 #endif
94
95 #if defined CONFIG_SYN_INFER_RAM
96 #define CFG_RAM_TECH inferred
97 #elif defined CONFIG_MEM_UMC
98 #define CFG_RAM_TECH umc
99 #elif defined CONFIG_MEM_RHUMC
100 #define CFG_RAM_TECH rhumc
101 #elif defined CONFIG_MEM_VIRAGE
102 #define CFG_RAM_TECH memvirage
103 #elif defined CONFIG_MEM_ARTISAN
104 #define CFG_RAM_TECH memartisan
105 #elif defined CONFIG_MEM_CUSTOM1
106 #define CFG_RAM_TECH custom1
107 #elif defined CONFIG_MEM_VIRAGE90
108 #define CFG_RAM_TECH memvirage90
109 #elif defined CONFIG_MEM_INFERRED
110 #define CFG_RAM_TECH inferred
111 #else
112 #define CFG_RAM_TECH CONFIG_SYN_TECH
113 #endif
114
115 #if defined CONFIG_SYN_INFER_PADS
116 #define CFG_PAD_TECH inferred
117 #else
118 #define CFG_PAD_TECH CONFIG_SYN_TECH
119 #endif
120
121 #ifndef CONFIG_SYN_NO_ASYNC
122 #define CONFIG_SYN_NO_ASYNC 0
123 #endif
124
125 #ifndef CONFIG_SYN_SCAN
126 #define CONFIG_SYN_SCAN 0
127 #endif
128
129
130 #if defined CONFIG_CLK_ALTDLL
131 #define CFG_CLK_TECH CONFIG_SYN_TECH
132 #elif defined CONFIG_CLK_HCLKBUF
133 #define CFG_CLK_TECH axcel
134 #elif defined CONFIG_CLK_LATDLL
135 #define CFG_CLK_TECH lattice
136 #elif defined CONFIG_CLK_PRO3PLL
137 #define CFG_CLK_TECH apa3
138 #elif defined CONFIG_CLK_PRO3EPLL
139 #define CFG_CLK_TECH apa3e
140 #elif defined CONFIG_CLK_PRO3LPLL
141 #define CFG_CLK_TECH apa3l
142 #elif defined CONFIG_CLK_FUSPLL
143 #define CFG_CLK_TECH actfus
144 #elif defined CONFIG_CLK_CLKDLL
145 #define CFG_CLK_TECH virtex
146 #elif defined CONFIG_CLK_DCM
147 #define CFG_CLK_TECH CONFIG_SYN_TECH
148 #elif defined CONFIG_CLK_LIB18T
149 #define CFG_CLK_TECH rhlib18t
150 #elif defined CONFIG_CLK_RHUMC
151 #define CFG_CLK_TECH rhumc
152 #elif defined CONFIG_CLK_UT130HBD
153 #define CFG_CLK_TECH ut130
154 #else
155 #define CFG_CLK_TECH inferred
156 #endif
157
158 #ifndef CONFIG_CLK_MUL
159 #define CONFIG_CLK_MUL 2
160 #endif
161
162 #ifndef CONFIG_CLK_DIV
163 #define CONFIG_CLK_DIV 2
164 #endif
165
166 #ifndef CONFIG_OCLK_DIV
167 #define CONFIG_OCLK_DIV 1
168 #endif
169
170 #ifndef CONFIG_OCLKB_DIV
171 #define CONFIG_OCLKB_DIV 0
172 #endif
173
174 #ifndef CONFIG_OCLKC_DIV
175 #define CONFIG_OCLKC_DIV 0
176 #endif
177
178 #ifndef CONFIG_PCI_CLKDLL
179 #define CONFIG_PCI_CLKDLL 0
180 #endif
181
182 #ifndef CONFIG_PCI_SYSCLK
183 #define CONFIG_PCI_SYSCLK 0
184 #endif
185
186 #ifndef CONFIG_CLK_NOFB
187 #define CONFIG_CLK_NOFB 0
188 #endif
189 #ifndef CONFIG_LEON3
190 #define CONFIG_LEON3 0
191 #endif
192
193 #ifndef CONFIG_PROC_NUM
194 #define CONFIG_PROC_NUM 1
195 #endif
196
197 #ifndef CONFIG_IU_NWINDOWS
198 #define CONFIG_IU_NWINDOWS 8
199 #endif
200
201 #ifndef CONFIG_IU_RSTADDR
202 #define CONFIG_IU_RSTADDR 8
203 #endif
204
205 #ifndef CONFIG_IU_LDELAY
206 #define CONFIG_IU_LDELAY 1
207 #endif
208
209 #ifndef CONFIG_IU_WATCHPOINTS
210 #define CONFIG_IU_WATCHPOINTS 0
211 #endif
212
213 #ifdef CONFIG_IU_V8MULDIV
214 #ifdef CONFIG_IU_MUL_LATENCY_4
215 #define CFG_IU_V8 1
216 #elif defined CONFIG_IU_MUL_LATENCY_5
217 #define CFG_IU_V8 2
218 #elif defined CONFIG_IU_MUL_LATENCY_2
219 #define CFG_IU_V8 16#32#
220 #endif
221 #else
222 #define CFG_IU_V8 0
223 #endif
224
225 #ifdef CONFIG_IU_MUL_MODGEN
226 #define CFG_IU_MUL_STRUCT 1
227 #elif defined CONFIG_IU_MUL_TECHSPEC
228 #define CFG_IU_MUL_STRUCT 2
229 #elif defined CONFIG_IU_MUL_DW
230 #define CFG_IU_MUL_STRUCT 3
231 #else
232 #define CFG_IU_MUL_STRUCT 0
233 #endif
234
235 #ifndef CONFIG_PWD
236 #define CONFIG_PWD 0
237 #endif
238
239 #ifndef CONFIG_IU_MUL_MAC
240 #define CONFIG_IU_MUL_MAC 0
241 #endif
242
243 #ifndef CONFIG_IU_BP
244 #define CONFIG_IU_BP 0
245 #endif
246
247 #ifndef CONFIG_NOTAG
248 #define CONFIG_NOTAG 0
249 #endif
250
251 #ifndef CONFIG_IU_SVT
252 #define CONFIG_IU_SVT 0
253 #endif
254
255 #if defined CONFIG_FPU_GRFPC1
256 #define CONFIG_FPU_GRFPC 1
257 #elif defined CONFIG_FPU_GRFPC2
258 #define CONFIG_FPU_GRFPC 2
259 #else
260 #define CONFIG_FPU_GRFPC 0
261 #endif
262
263 #if defined CONFIG_FPU_GRFPU_INFMUL
264 #define CONFIG_FPU_GRFPU_MUL 0
265 #elif defined CONFIG_FPU_GRFPU_DWMUL
266 #define CONFIG_FPU_GRFPU_MUL 1
267 #elif defined CONFIG_FPU_GRFPU_MODGEN
268 #define CONFIG_FPU_GRFPU_MUL 2
269 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
270 #define CONFIG_FPU_GRFPU_MUL 3
271 #else
272 #define CONFIG_FPU_GRFPU_MUL 0
273 #endif
274
275 #if defined CONFIG_FPU_GRFPU_SH
276 #define CONFIG_FPU_GRFPU_SHARED 1
277 #else
278 #define CONFIG_FPU_GRFPU_SHARED 0
279 #endif
280
281 #if defined CONFIG_FPU_GRFPU
282 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
283 #elif defined CONFIG_FPU_MEIKO
284 #define CONFIG_FPU 15
285 #elif defined CONFIG_FPU_GRFPULITE
286 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
287 #else
288 #define CONFIG_FPU 0
289 #endif
290
291 #ifndef CONFIG_FPU_NETLIST
292 #define CONFIG_FPU_NETLIST 0
293 #endif
294
295 #ifndef CONFIG_ICACHE_ENABLE
296 #define CONFIG_ICACHE_ENABLE 0
297 #endif
298
299 #if defined CONFIG_ICACHE_ASSO1
300 #define CFG_IU_ISETS 1
301 #elif defined CONFIG_ICACHE_ASSO2
302 #define CFG_IU_ISETS 2
303 #elif defined CONFIG_ICACHE_ASSO3
304 #define CFG_IU_ISETS 3
305 #elif defined CONFIG_ICACHE_ASSO4
306 #define CFG_IU_ISETS 4
307 #else
308 #define CFG_IU_ISETS 1
309 #endif
310
311 #if defined CONFIG_ICACHE_SZ1
312 #define CFG_ICACHE_SZ 1
313 #elif defined CONFIG_ICACHE_SZ2
314 #define CFG_ICACHE_SZ 2
315 #elif defined CONFIG_ICACHE_SZ4
316 #define CFG_ICACHE_SZ 4
317 #elif defined CONFIG_ICACHE_SZ8
318 #define CFG_ICACHE_SZ 8
319 #elif defined CONFIG_ICACHE_SZ16
320 #define CFG_ICACHE_SZ 16
321 #elif defined CONFIG_ICACHE_SZ32
322 #define CFG_ICACHE_SZ 32
323 #elif defined CONFIG_ICACHE_SZ64
324 #define CFG_ICACHE_SZ 64
325 #elif defined CONFIG_ICACHE_SZ128
326 #define CFG_ICACHE_SZ 128
327 #elif defined CONFIG_ICACHE_SZ256
328 #define CFG_ICACHE_SZ 256
329 #else
330 #define CFG_ICACHE_SZ 1
331 #endif
332
333 #ifdef CONFIG_ICACHE_LZ16
334 #define CFG_ILINE_SZ 4
335 #else
336 #define CFG_ILINE_SZ 8
337 #endif
338
339 #if defined CONFIG_ICACHE_ALGODIR
340 #define CFG_ICACHE_ALGORND 3
341 #elif defined CONFIG_ICACHE_ALGORND
342 #define CFG_ICACHE_ALGORND 2
343 #elif defined CONFIG_ICACHE_ALGOLRR
344 #define CFG_ICACHE_ALGORND 1
345 #else
346 #define CFG_ICACHE_ALGORND 0
347 #endif
348
349 #ifndef CONFIG_ICACHE_LOCK
350 #define CONFIG_ICACHE_LOCK 0
351 #endif
352
353 #ifndef CONFIG_ICACHE_LRAM
354 #define CONFIG_ICACHE_LRAM 0
355 #endif
356
357 #ifndef CONFIG_ICACHE_LRSTART
358 #define CONFIG_ICACHE_LRSTART 8E
359 #endif
360
361 #if defined CONFIG_ICACHE_LRAM_SZ2
362 #define CFG_ILRAM_SIZE 2
363 #elif defined CONFIG_ICACHE_LRAM_SZ4
364 #define CFG_ILRAM_SIZE 4
365 #elif defined CONFIG_ICACHE_LRAM_SZ8
366 #define CFG_ILRAM_SIZE 8
367 #elif defined CONFIG_ICACHE_LRAM_SZ16
368 #define CFG_ILRAM_SIZE 16
369 #elif defined CONFIG_ICACHE_LRAM_SZ32
370 #define CFG_ILRAM_SIZE 32
371 #elif defined CONFIG_ICACHE_LRAM_SZ64
372 #define CFG_ILRAM_SIZE 64
373 #elif defined CONFIG_ICACHE_LRAM_SZ128
374 #define CFG_ILRAM_SIZE 128
375 #elif defined CONFIG_ICACHE_LRAM_SZ256
376 #define CFG_ILRAM_SIZE 256
377 #else
378 #define CFG_ILRAM_SIZE 1
379 #endif
380
381
382 #ifndef CONFIG_DCACHE_ENABLE
383 #define CONFIG_DCACHE_ENABLE 0
384 #endif
385
386 #if defined CONFIG_DCACHE_ASSO1
387 #define CFG_IU_DSETS 1
388 #elif defined CONFIG_DCACHE_ASSO2
389 #define CFG_IU_DSETS 2
390 #elif defined CONFIG_DCACHE_ASSO3
391 #define CFG_IU_DSETS 3
392 #elif defined CONFIG_DCACHE_ASSO4
393 #define CFG_IU_DSETS 4
394 #else
395 #define CFG_IU_DSETS 1
396 #endif
397
398 #if defined CONFIG_DCACHE_SZ1
399 #define CFG_DCACHE_SZ 1
400 #elif defined CONFIG_DCACHE_SZ2
401 #define CFG_DCACHE_SZ 2
402 #elif defined CONFIG_DCACHE_SZ4
403 #define CFG_DCACHE_SZ 4
404 #elif defined CONFIG_DCACHE_SZ8
405 #define CFG_DCACHE_SZ 8
406 #elif defined CONFIG_DCACHE_SZ16
407 #define CFG_DCACHE_SZ 16
408 #elif defined CONFIG_DCACHE_SZ32
409 #define CFG_DCACHE_SZ 32
410 #elif defined CONFIG_DCACHE_SZ64
411 #define CFG_DCACHE_SZ 64
412 #elif defined CONFIG_DCACHE_SZ128
413 #define CFG_DCACHE_SZ 128
414 #elif defined CONFIG_DCACHE_SZ256
415 #define CFG_DCACHE_SZ 256
416 #else
417 #define CFG_DCACHE_SZ 1
418 #endif
419
420 #ifdef CONFIG_DCACHE_LZ16
421 #define CFG_DLINE_SZ 4
422 #else
423 #define CFG_DLINE_SZ 8
424 #endif
425
426 #if defined CONFIG_DCACHE_ALGODIR
427 #define CFG_DCACHE_ALGORND 3
428 #elif defined CONFIG_DCACHE_ALGORND
429 #define CFG_DCACHE_ALGORND 2
430 #elif defined CONFIG_DCACHE_ALGOLRR
431 #define CFG_DCACHE_ALGORND 1
432 #else
433 #define CFG_DCACHE_ALGORND 0
434 #endif
435
436 #ifndef CONFIG_DCACHE_LOCK
437 #define CONFIG_DCACHE_LOCK 0
438 #endif
439
440 #ifndef CONFIG_DCACHE_SNOOP
441 #define CONFIG_DCACHE_SNOOP 0
442 #endif
443
444 #ifndef CONFIG_DCACHE_SNOOP_FAST
445 #define CONFIG_DCACHE_SNOOP_FAST 0
446 #endif
447
448 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
449 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
450 #endif
451
452 #ifndef CONFIG_CACHE_FIXED
453 #define CONFIG_CACHE_FIXED 0
454 #endif
455
456 #ifndef CONFIG_DCACHE_LRAM
457 #define CONFIG_DCACHE_LRAM 0
458 #endif
459
460 #ifndef CONFIG_DCACHE_LRSTART
461 #define CONFIG_DCACHE_LRSTART 8F
462 #endif
463
464 #if defined CONFIG_DCACHE_LRAM_SZ2
465 #define CFG_DLRAM_SIZE 2
466 #elif defined CONFIG_DCACHE_LRAM_SZ4
467 #define CFG_DLRAM_SIZE 4
468 #elif defined CONFIG_DCACHE_LRAM_SZ8
469 #define CFG_DLRAM_SIZE 8
470 #elif defined CONFIG_DCACHE_LRAM_SZ16
471 #define CFG_DLRAM_SIZE 16
472 #elif defined CONFIG_DCACHE_LRAM_SZ32
473 #define CFG_DLRAM_SIZE 32
474 #elif defined CONFIG_DCACHE_LRAM_SZ64
475 #define CFG_DLRAM_SIZE 64
476 #elif defined CONFIG_DCACHE_LRAM_SZ128
477 #define CFG_DLRAM_SIZE 128
478 #elif defined CONFIG_DCACHE_LRAM_SZ256
479 #define CFG_DLRAM_SIZE 256
480 #else
481 #define CFG_DLRAM_SIZE 1
482 #endif
483
484 #if defined CONFIG_MMU_PAGE_4K
485 #define CONFIG_MMU_PAGE 0
486 #elif defined CONFIG_MMU_PAGE_8K
487 #define CONFIG_MMU_PAGE 1
488 #elif defined CONFIG_MMU_PAGE_16K
489 #define CONFIG_MMU_PAGE 2
490 #elif defined CONFIG_MMU_PAGE_32K
491 #define CONFIG_MMU_PAGE 3
492 #elif defined CONFIG_MMU_PAGE_PROG
493 #define CONFIG_MMU_PAGE 4
494 #else
495 #define CONFIG_MMU_PAGE 0
496 #endif
497
498 #ifdef CONFIG_MMU_ENABLE
499 #define CONFIG_MMUEN 1
500
501 #ifdef CONFIG_MMU_SPLIT
502 #define CONFIG_TLB_TYPE 0
503 #endif
504 #ifdef CONFIG_MMU_COMBINED
505 #define CONFIG_TLB_TYPE 1
506 #endif
507
508 #ifdef CONFIG_MMU_REPARRAY
509 #define CONFIG_TLB_REP 0
510 #endif
511 #ifdef CONFIG_MMU_REPINCREMENT
512 #define CONFIG_TLB_REP 1
513 #endif
514
515 #ifdef CONFIG_MMU_I2
516 #define CONFIG_ITLBNUM 2
517 #endif
518 #ifdef CONFIG_MMU_I4
519 #define CONFIG_ITLBNUM 4
520 #endif
521 #ifdef CONFIG_MMU_I8
522 #define CONFIG_ITLBNUM 8
523 #endif
524 #ifdef CONFIG_MMU_I16
525 #define CONFIG_ITLBNUM 16
526 #endif
527 #ifdef CONFIG_MMU_I32
528 #define CONFIG_ITLBNUM 32
529 #endif
530
531 #define CONFIG_DTLBNUM 2
532 #ifdef CONFIG_MMU_D2
533 #undef CONFIG_DTLBNUM
534 #define CONFIG_DTLBNUM 2
535 #endif
536 #ifdef CONFIG_MMU_D4
537 #undef CONFIG_DTLBNUM
538 #define CONFIG_DTLBNUM 4
539 #endif
540 #ifdef CONFIG_MMU_D8
541 #undef CONFIG_DTLBNUM
542 #define CONFIG_DTLBNUM 8
543 #endif
544 #ifdef CONFIG_MMU_D16
545 #undef CONFIG_DTLBNUM
546 #define CONFIG_DTLBNUM 16
547 #endif
548 #ifdef CONFIG_MMU_D32
549 #undef CONFIG_DTLBNUM
550 #define CONFIG_DTLBNUM 32
551 #endif
552 #ifdef CONFIG_MMU_FASTWB
553 #define CFG_MMU_FASTWB 1
554 #else
555 #define CFG_MMU_FASTWB 0
556 #endif
557
558 #else
559 #define CONFIG_MMUEN 0
560 #define CONFIG_ITLBNUM 2
561 #define CONFIG_DTLBNUM 2
562 #define CONFIG_TLB_TYPE 1
563 #define CONFIG_TLB_REP 1
564 #define CFG_MMU_FASTWB 0
565 #endif
566
567 #ifndef CONFIG_DSU_ENABLE
568 #define CONFIG_DSU_ENABLE 0
569 #endif
570
571 #if defined CONFIG_DSU_ITRACESZ1
572 #define CFG_DSU_ITB 1
573 #elif CONFIG_DSU_ITRACESZ2
574 #define CFG_DSU_ITB 2
575 #elif CONFIG_DSU_ITRACESZ4
576 #define CFG_DSU_ITB 4
577 #elif CONFIG_DSU_ITRACESZ8
578 #define CFG_DSU_ITB 8
579 #elif CONFIG_DSU_ITRACESZ16
580 #define CFG_DSU_ITB 16
581 #else
582 #define CFG_DSU_ITB 0
583 #endif
584
585 #if defined CONFIG_DSU_ATRACESZ1
586 #define CFG_DSU_ATB 1
587 #elif CONFIG_DSU_ATRACESZ2
588 #define CFG_DSU_ATB 2
589 #elif CONFIG_DSU_ATRACESZ4
590 #define CFG_DSU_ATB 4
591 #elif CONFIG_DSU_ATRACESZ8
592 #define CFG_DSU_ATB 8
593 #elif CONFIG_DSU_ATRACESZ16
594 #define CFG_DSU_ATB 16
595 #else
596 #define CFG_DSU_ATB 0
597 #endif
598
599 #ifndef CONFIG_LEON3FT_EN
600 #define CONFIG_LEON3FT_EN 0
601 #endif
602
603 #if defined CONFIG_IUFT_PAR
604 #define CONFIG_IUFT_EN 1
605 #elif defined CONFIG_IUFT_DMR
606 #define CONFIG_IUFT_EN 2
607 #elif defined CONFIG_IUFT_BCH
608 #define CONFIG_IUFT_EN 3
609 #elif defined CONFIG_IUFT_TMR
610 #define CONFIG_IUFT_EN 4
611 #else
612 #define CONFIG_IUFT_EN 0
613 #endif
614 #ifndef CONFIG_RF_ERRINJ
615 #define CONFIG_RF_ERRINJ 0
616 #endif
617
618 #ifndef CONFIG_FPUFT_EN
619 #define CONFIG_FPUFT 0
620 #else
621 #ifdef CONFIG_FPU_GRFPU
622 #define CONFIG_FPUFT 2
623 #else
624 #define CONFIG_FPUFT 1
625 #endif
626 #endif
627
628 #ifndef CONFIG_CACHE_FT_EN
629 #define CONFIG_CACHE_FT_EN 0
630 #endif
631 #ifndef CONFIG_CACHE_ERRINJ
632 #define CONFIG_CACHE_ERRINJ 0
633 #endif
634
635 #ifndef CONFIG_LEON3_NETLIST
636 #define CONFIG_LEON3_NETLIST 0
637 #endif
638
639 #ifdef CONFIG_DEBUG_PC32
640 #define CFG_DEBUG_PC32 0
641 #else
642 #define CFG_DEBUG_PC32 2
643 #endif
644 #ifndef CONFIG_IU_DISAS
645 #define CONFIG_IU_DISAS 0
646 #endif
647 #ifndef CONFIG_IU_DISAS_NET
648 #define CONFIG_IU_DISAS_NET 0
649 #endif
650
651
652 #ifndef CONFIG_AHB_SPLIT
653 #define CONFIG_AHB_SPLIT 0
654 #endif
655
656 #ifndef CONFIG_AHB_RROBIN
657 #define CONFIG_AHB_RROBIN 0
658 #endif
659
660 #ifndef CONFIG_AHB_IOADDR
661 #define CONFIG_AHB_IOADDR FFF
662 #endif
663
664 #ifndef CONFIG_APB_HADDR
665 #define CONFIG_APB_HADDR 800
666 #endif
667
668 #ifndef CONFIG_AHB_MON
669 #define CONFIG_AHB_MON 0
670 #endif
671
672 #ifndef CONFIG_AHB_MONERR
673 #define CONFIG_AHB_MONERR 0
674 #endif
675
676 #ifndef CONFIG_AHB_MONWAR
677 #define CONFIG_AHB_MONWAR 0
678 #endif
679
680 #ifndef CONFIG_AHB_DTRACE
681 #define CONFIG_AHB_DTRACE 0
682 #endif
683
684 #ifndef CONFIG_DSU_JTAG
685 #define CONFIG_DSU_JTAG 0
686 #endif
687
688 #ifndef CONFIG_DSU_ETH
689 #define CONFIG_DSU_ETH 0
690 #endif
691
692 #ifndef CONFIG_DSU_IPMSB
693 #define CONFIG_DSU_IPMSB C0A8
694 #endif
695
696 #ifndef CONFIG_DSU_IPLSB
697 #define CONFIG_DSU_IPLSB 0033
698 #endif
699
700 #ifndef CONFIG_DSU_ETHMSB
701 #define CONFIG_DSU_ETHMSB 020000
702 #endif
703
704 #ifndef CONFIG_DSU_ETHLSB
705 #define CONFIG_DSU_ETHLSB 000009
706 #endif
707
708 #if defined CONFIG_DSU_ETHSZ1
709 #define CFG_DSU_ETHB 1
710 #elif CONFIG_DSU_ETHSZ2
711 #define CFG_DSU_ETHB 2
712 #elif CONFIG_DSU_ETHSZ4
713 #define CFG_DSU_ETHB 4
714 #elif CONFIG_DSU_ETHSZ8
715 #define CFG_DSU_ETHB 8
716 #elif CONFIG_DSU_ETHSZ16
717 #define CFG_DSU_ETHB 16
718 #elif CONFIG_DSU_ETHSZ32
719 #define CFG_DSU_ETHB 32
720 #else
721 #define CFG_DSU_ETHB 1
722 #endif
723
724 #ifndef CONFIG_DSU_ETH_PROG
725 #define CONFIG_DSU_ETH_PROG 0
726 #endif
727
728 #ifndef CONFIG_DSU_ETH_DIS
729 #define CONFIG_DSU_ETH_DIS 0
730 #endif
731
732 #ifndef CONFIG_MCTRL_LEON2
733 #define CONFIG_MCTRL_LEON2 0
734 #endif
735
736 #ifndef CONFIG_MCTRL_SDRAM
737 #define CONFIG_MCTRL_SDRAM 0
738 #endif
739
740 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
741 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
742 #endif
743
744 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
745 #define CONFIG_MCTRL_SDRAM_INVCLK 0
746 #endif
747
748 #ifndef CONFIG_MCTRL_SDRAM_BUS64
749 #define CONFIG_MCTRL_SDRAM_BUS64 0
750 #endif
751
752 #ifndef CONFIG_MCTRL_8BIT
753 #define CONFIG_MCTRL_8BIT 0
754 #endif
755
756 #ifndef CONFIG_MCTRL_16BIT
757 #define CONFIG_MCTRL_16BIT 0
758 #endif
759
760 #ifndef CONFIG_MCTRL_5CS
761 #define CONFIG_MCTRL_5CS 0
762 #endif
763
764 #ifndef CONFIG_MCTRL_EDAC
765 #define CONFIG_MCTRL_EDAC 0
766 #endif
767
768 #ifndef CONFIG_MCTRL_PAGE
769 #define CONFIG_MCTRL_PAGE 0
770 #endif
771
772 #ifndef CONFIG_MCTRL_PROGPAGE
773 #define CONFIG_MCTRL_PROGPAGE 0
774 #endif
775
776
777 #ifndef CONFIG_MIG_DDR2
778 #define CONFIG_MIG_DDR2 0
779 #endif
780
781 #ifndef CONFIG_MIG_RANKS
782 #define CONFIG_MIG_RANKS 1
783 #endif
784
785 #ifndef CONFIG_MIG_COLBITS
786 #define CONFIG_MIG_COLBITS 10
787 #endif
788
789 #ifndef CONFIG_MIG_ROWBITS
790 #define CONFIG_MIG_ROWBITS 13
791 #endif
792
793 #ifndef CONFIG_MIG_BANKBITS
794 #define CONFIG_MIG_BANKBITS 2
795 #endif
796
797 #ifndef CONFIG_MIG_HMASK
798 #define CONFIG_MIG_HMASK F00
799 #endif
800 #ifndef CONFIG_AHBSTAT_ENABLE
801 #define CONFIG_AHBSTAT_ENABLE 0
802 #endif
803
804 #ifndef CONFIG_AHBSTAT_NFTSLV
805 #define CONFIG_AHBSTAT_NFTSLV 1
806 #endif
807
808 #ifndef CONFIG_AHBROM_ENABLE
809 #define CONFIG_AHBROM_ENABLE 0
810 #endif
811
812 #ifndef CONFIG_AHBROM_START
813 #define CONFIG_AHBROM_START 000
814 #endif
815
816 #ifndef CONFIG_AHBROM_PIPE
817 #define CONFIG_AHBROM_PIPE 0
818 #endif
819
820 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
821 #define CONFIG_ROM_START 100
822 #else
823 #define CONFIG_ROM_START 000
824 #endif
825
826
827 #ifndef CONFIG_AHBRAM_ENABLE
828 #define CONFIG_AHBRAM_ENABLE 0
829 #endif
830
831 #ifndef CONFIG_AHBRAM_START
832 #define CONFIG_AHBRAM_START A00
833 #endif
834
835 #if defined CONFIG_AHBRAM_SZ1
836 #define CFG_AHBRAMSZ 1
837 #elif CONFIG_AHBRAM_SZ2
838 #define CFG_AHBRAMSZ 2
839 #elif CONFIG_AHBRAM_SZ4
840 #define CFG_AHBRAMSZ 4
841 #elif CONFIG_AHBRAM_SZ8
842 #define CFG_AHBRAMSZ 8
843 #elif CONFIG_AHBRAM_SZ16
844 #define CFG_AHBRAMSZ 16
845 #elif CONFIG_AHBRAM_SZ32
846 #define CFG_AHBRAMSZ 32
847 #elif CONFIG_AHBRAM_SZ64
848 #define CFG_AHBRAMSZ 64
849 #else
850 #define CFG_AHBRAMSZ 1
851 #endif
852
853 #ifndef CONFIG_GRETH_ENABLE
854 #define CONFIG_GRETH_ENABLE 0
855 #endif
856
857 #ifndef CONFIG_GRETH_GIGA
858 #define CONFIG_GRETH_GIGA 0
859 #endif
860
861 #if defined CONFIG_GRETH_FIFO4
862 #define CFG_GRETH_FIFO 4
863 #elif defined CONFIG_GRETH_FIFO8
864 #define CFG_GRETH_FIFO 8
865 #elif defined CONFIG_GRETH_FIFO16
866 #define CFG_GRETH_FIFO 16
867 #elif defined CONFIG_GRETH_FIFO32
868 #define CFG_GRETH_FIFO 32
869 #elif defined CONFIG_GRETH_FIFO64
870 #define CFG_GRETH_FIFO 64
871 #else
872 #define CFG_GRETH_FIFO 8
873 #endif
874
875 #ifndef CONFIG_UART1_ENABLE
876 #define CONFIG_UART1_ENABLE 0
877 #endif
878
879 #if defined CONFIG_UA1_FIFO1
880 #define CFG_UA1_FIFO 1
881 #elif defined CONFIG_UA1_FIFO2
882 #define CFG_UA1_FIFO 2
883 #elif defined CONFIG_UA1_FIFO4
884 #define CFG_UA1_FIFO 4
885 #elif defined CONFIG_UA1_FIFO8
886 #define CFG_UA1_FIFO 8
887 #elif defined CONFIG_UA1_FIFO16
888 #define CFG_UA1_FIFO 16
889 #elif defined CONFIG_UA1_FIFO32
890 #define CFG_UA1_FIFO 32
891 #else
892 #define CFG_UA1_FIFO 1
893 #endif
894
895 #ifndef CONFIG_IRQ3_ENABLE
896 #define CONFIG_IRQ3_ENABLE 0
897 #endif
898 #ifndef CONFIG_IRQ3_NSEC
899 #define CONFIG_IRQ3_NSEC 0
900 #endif
901 #ifndef CONFIG_GPT_ENABLE
902 #define CONFIG_GPT_ENABLE 0
903 #endif
904
905 #ifndef CONFIG_GPT_NTIM
906 #define CONFIG_GPT_NTIM 1
907 #endif
908
909 #ifndef CONFIG_GPT_SW
910 #define CONFIG_GPT_SW 8
911 #endif
912
913 #ifndef CONFIG_GPT_TW
914 #define CONFIG_GPT_TW 8
915 #endif
916
917 #ifndef CONFIG_GPT_IRQ
918 #define CONFIG_GPT_IRQ 8
919 #endif
920
921 #ifndef CONFIG_GPT_SEPIRQ
922 #define CONFIG_GPT_SEPIRQ 0
923 #endif
924 #ifndef CONFIG_GPT_ENABLE
925 #define CONFIG_GPT_ENABLE 0
926 #endif
927
928 #ifndef CONFIG_GPT_NTIM
929 #define CONFIG_GPT_NTIM 1
930 #endif
931
932 #ifndef CONFIG_GPT_SW
933 #define CONFIG_GPT_SW 8
934 #endif
935
936 #ifndef CONFIG_GPT_TW
937 #define CONFIG_GPT_TW 8
938 #endif
939
940 #ifndef CONFIG_GPT_IRQ
941 #define CONFIG_GPT_IRQ 8
942 #endif
943
944 #ifndef CONFIG_GPT_SEPIRQ
945 #define CONFIG_GPT_SEPIRQ 0
946 #endif
947
948 #ifndef CONFIG_GPT_WDOGEN
949 #define CONFIG_GPT_WDOGEN 0
950 #endif
951
952 #ifndef CONFIG_GPT_WDOG
953 #define CONFIG_GPT_WDOG 0
954 #endif
955
956 #ifndef CONFIG_GRGPIO_ENABLE
957 #define CONFIG_GRGPIO_ENABLE 0
958 #endif
959 #ifndef CONFIG_GRGPIO_IMASK
960 #define CONFIG_GRGPIO_IMASK 0000
961 #endif
962 #ifndef CONFIG_GRGPIO_WIDTH
963 #define CONFIG_GRGPIO_WIDTH 1
964 #endif
965
966 #ifndef CONFIG_VGA_ENABLE
967 #define CONFIG_VGA_ENABLE 0
968 #endif
969 #ifndef CONFIG_SVGA_ENABLE
970 #define CONFIG_SVGA_ENABLE 0
971 #endif
972 #ifndef CONFIG_KBD_ENABLE
973 #define CONFIG_KBD_ENABLE 0
974 #endif
975
976
977 #ifndef CONFIG_SPIMCTRL
978 #define CONFIG_SPIMCTRL 0
979 #endif
980
981 #ifndef CONFIG_SPIMCTRL_SDCARD
982 #define CONFIG_SPIMCTRL_SDCARD 0
983 #endif
984
985 #ifndef CONFIG_SPIMCTRL_READCMD
986 #define CONFIG_SPIMCTRL_READCMD 0
987 #endif
988
989 #ifndef CONFIG_SPIMCTRL_DUMMYBYTE
990 #define CONFIG_SPIMCTRL_DUMMYBYTE 0
991 #endif
992
993 #ifndef CONFIG_SPIMCTRL_DUALOUTPUT
994 #define CONFIG_SPIMCTRL_DUALOUTPUT 0
995 #endif
996
997 #ifndef CONFIG_SPIMCTRL_SCALER
998 #define CONFIG_SPIMCTRL_SCALER 1
999 #endif
1000
1001 #ifndef CONFIG_SPIMCTRL_ASCALER
1002 #define CONFIG_SPIMCTRL_ASCALER 1
1003 #endif
1004
1005 #ifndef CONFIG_SPIMCTRL_PWRUPCNT
1006 #define CONFIG_SPIMCTRL_PWRUPCNT 0
1007 #endif
1008 #ifndef CONFIG_SPICTRL_ENABLE
1009 #define CONFIG_SPICTRL_ENABLE 0
1010 #endif
1011 #ifndef CONFIG_SPICTRL_NUM
1012 #define CONFIG_SPICTRL_NUM 1
1013 #endif
1014 #ifndef CONFIG_SPICTRL_SLVS
1015 #define CONFIG_SPICTRL_SLVS 1
1016 #endif
1017 #ifndef CONFIG_SPICTRL_FIFO
1018 #define CONFIG_SPICTRL_FIFO 1
1019 #endif
1020 #ifndef CONFIG_SPICTRL_SLVREG
1021 #define CONFIG_SPICTRL_SLVREG 0
1022 #endif
1023 #ifndef CONFIG_SPICTRL_ODMODE
1024 #define CONFIG_SPICTRL_ODMODE 0
1025 #endif
1026 #ifndef CONFIG_SPICTRL_AM
1027 #define CONFIG_SPICTRL_AM 0
1028 #endif
1029 #ifndef CONFIG_SPICTRL_ASEL
1030 #define CONFIG_SPICTRL_ASEL 0
1031 #endif
1032 #ifndef CONFIG_SPICTRL_TWEN
1033 #define CONFIG_SPICTRL_TWEN 0
1034 #endif
1035 #ifndef CONFIG_SPICTRL_MAXWLEN
1036 #define CONFIG_SPICTRL_MAXWLEN 0
1037 #endif
1038 #ifndef CONFIG_SPICTRL_SYNCRAM
1039 #define CONFIG_SPICTRL_SYNCRAM 0
1040 #endif
1041 #if defined(CONFIG_SPICTRL_DMRFT)
1042 #define CONFIG_SPICTRL_FT 1
1043 #elif defined(CONFIG_SPICTRL_TMRFT)
1044 #define CONFIG_SPICTRL_FT 2
1045 #else
1046 #define CONFIG_SPICTRL_FT 0
1047 #endif
1048
1049 #ifndef CONFIG_DEBUG_UART
1050 #define CONFIG_DEBUG_UART 0
1051 #endif
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@@ -1,169 +1,169
1
2 This leon3 design is tailored to the Digilent Spartan3-1600E Evaluation board:
3
4 http://www.digilentinc.com/Products/Detail.cfm?Prod=S3E1600&Nav1=Products&Nav2=Programmable
5
6 Design specifics:
7
8 * System reset is mapped to SW_SOUTH (reset)
9
10 * DSU break is mapped to SW_EAST
11
12 * LED 0/1 indicates console UART RX and TX activity.
13
14 * LED 2/3 indicates DSU UART RX and TX activity.
15
16 * LED 4 indicates processor in debug mode
17
18 * LED 7 indicates processor in error mode
19
20 * The GRETH core is enabled and runs without problems at 100 Mbit.
21 Ethernet debug link is enabled, default IP is 192.168.0.51.
22
23 * 16-bit flash prom can be read at address 0. It can be programmed
24 with GRMON version 1.1.16 or later.
25
26 * DDR is mapped at address 0x40000000 (64 Mbyte) and is clocked
27 at 100 MHz. The processor and AMBA system runs on a different
28 clock, and can typically reach 40 MHz. The processor clock
29 is generated from the 50 MHz clock oscillator, scaled with the
30 DCM factors (4/5) in xconfig.
31
32 * The APBPS2 PS/2 core is attached to the PS/2 connector
33
34 * The SVGA frame buffer runs fine with 800x600 resolution. Due to the
35 limited number of clock buffers, no other resoltion is supported.
36 Note that the board does not have a video DAC, so only the MSB bit (7)
37 of the three colour channels is connected to the VGA connector.
38
39 A test patter can be generated using grmon-1.1.18 or later with:
40
41 draw test_screen 800 16
42
43 * The DSU uart is connected to the female RS232 connected.
44 The application UART1 is connected to the male RS232 connector.
45
46 * The JTAG DSU interface is enabled.
47
48 * Output from GRMON info sys is:
49
50
51 ethernet startup.
52 GRLIB build version: 4090
53
54 initialising ..............
55 detected frequency: 40 MHz
56
57 Component Vendor
58 LEON3 SPARC V8 Processor Gaisler Research
59 AHB Debug UART Gaisler Research
60 AHB Debug JTAG TAP Gaisler Research
61 SVGA Controller Gaisler Research
62 GR Ethernet MAC Gaisler Research
63 AHB/APB Bridge Gaisler Research
64 LEON3 Debug Support Unit Gaisler Research
65 DDR266 Controller Gaisler Research
66 LEON2 Memory Controller European Space Agency
67 Generic APB UART Gaisler Research
68 Multi-processor Interrupt Ctrl Gaisler Research
69 Modular Timer Unit Gaisler Research
70 PS/2 interface Gaisler Research
71 General purpose I/O port Gaisler Research
72
73 Use command 'info sys' to print a detailed report of attached cores
74
75 grlib> inf sys
76 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
77 ahb master 0
78 01.01:007 Gaisler Research AHB Debug UART (ver 0x0)
79 ahb master 1
80 apb: 80000700 - 80000800
81 baud rate 115200, ahb frequency 40.00
82 02.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0)
83 ahb master 2
84 03.01:063 Gaisler Research SVGA Controller (ver 0x0)
85 ahb master 3
86 apb: 80000600 - 80000700
87 clk0: 40.00 MHz
88 04.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
89 ahb master 4, irq 12
90 apb: 80000f00 - 80001000
91 edcl ip 192.168.0.51, buffer 2 kbyte
92 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
93 ahb: 80000000 - 80100000
94 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
95 ahb: 90000000 - a0000000
96 AHB trace 256 lines, 32-bit bus, stack pointer 0x43fffff0
97 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1, GRFPU-lite
98 icache 2 * 4 kbyte, 32 byte/line rnd
99 dcache 2 * 4 kbyte, 16 byte/line rnd
100 04.01:025 Gaisler Research DDR266 Controller (ver 0x0)
101 ahb: 40000000 - 50000000
102 ahb: fff00100 - fff00200
103 16-bit DDR : 1 * 64 Mbyte @ 0x40000000
104 100 MHz, col 10, ref 7.8 us, trfc 80 ns
105 05.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
106 ahb: 00000000 - 20000000
107 ahb: 20000000 - 40000000
108 ahb: 60000000 - 70000000
109 apb: 80000000 - 80000100
110 16-bit prom @ 0x00000000
111 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
112 irq 2
113 apb: 80000100 - 80000200
114 baud rate 38461, DSU mode (FIFO debug)
115 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
116 apb: 80000200 - 80000300
117 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
118 irq 8
119 apb: 80000300 - 80000400
120 8-bit scaler, 2 * 32-bit timers, divisor 40
121 05.01:060 Gaisler Research PS/2 interface (ver 0x2)
122 irq 5
123 apb: 80000500 - 80000600
124 0b.01:01a Gaisler Research General purpose I/O port (ver 0x0)
125 apb: 80000b00 - 80000c00
126 grlib>
127
128 grlib> flas
129
130 Intel-style 16-bit flash on D[31:16]
131
132 Manuf. Intel
133 Device MT28F128J3 )
134
135 Device ID 0418ffff008844d1
136 User ID ffffffffffffffff
137
138
139 1 x 16 Mbyte = 16 Mbyte total @ 0x00000000
140
141
142 CFI info
143 flash family : 1
144 flash size : 128 Mbit
145 erase regions : 1
146 erase blocks : 128
147 write buffer : 32 bytes
148 region 0 : 128 blocks of 128 Kbytes
149
150 grlib>
151
152 grlib> lo ~/examples/dhry412
153 section: .text at 0x40000000, size 53296 bytes
154 section: .data at 0x4000d030, size 2764 bytes
155 total size: 56060 bytes (63.3 Mbit/s)
156 read 262 symbols
157 entry point: 0x40000000
158 grlib> run
159 Execution starts, 1000000 runs through Dhrystone
160 Total execution time: 10.5 s
161 Microseconds for one run through Dhrystone: 10.5
162 Dhrystones per Second: 95073.0
163
164 Dhrystones MIPS : 54.1
165
166
167 Program exited normally.
168 grlib>
169
1
2 This leon3 design is tailored to the Digilent Spartan3-1600E Evaluation board:
3
4 http://www.digilentinc.com/Products/Detail.cfm?Prod=S3E1600&Nav1=Products&Nav2=Programmable
5
6 Design specifics:
7
8 * System reset is mapped to SW_SOUTH (reset)
9
10 * DSU break is mapped to SW_EAST
11
12 * LED 0/1 indicates console UART RX and TX activity.
13
14 * LED 2/3 indicates DSU UART RX and TX activity.
15
16 * LED 4 indicates processor in debug mode
17
18 * LED 7 indicates processor in error mode
19
20 * The GRETH core is enabled and runs without problems at 100 Mbit.
21 Ethernet debug link is enabled, default IP is 192.168.0.51.
22
23 * 16-bit flash prom can be read at address 0. It can be programmed
24 with GRMON version 1.1.16 or later.
25
26 * DDR is mapped at address 0x40000000 (64 Mbyte) and is clocked
27 at 100 MHz. The processor and AMBA system runs on a different
28 clock, and can typically reach 40 MHz. The processor clock
29 is generated from the 50 MHz clock oscillator, scaled with the
30 DCM factors (4/5) in xconfig.
31
32 * The APBPS2 PS/2 core is attached to the PS/2 connector
33
34 * The SVGA frame buffer runs fine with 800x600 resolution. Due to the
35 limited number of clock buffers, no other resoltion is supported.
36 Note that the board does not have a video DAC, so only the MSB bit (7)
37 of the three colour channels is connected to the VGA connector.
38
39 A test patter can be generated using grmon-1.1.18 or later with:
40
41 draw test_screen 800 16
42
43 * The DSU uart is connected to the female RS232 connected.
44 The application UART1 is connected to the male RS232 connector.
45
46 * The JTAG DSU interface is enabled.
47
48 * Output from GRMON info sys is:
49
50
51 ethernet startup.
52 GRLIB build version: 4090
53
54 initialising ..............
55 detected frequency: 40 MHz
56
57 Component Vendor
58 LEON3 SPARC V8 Processor Gaisler Research
59 AHB Debug UART Gaisler Research
60 AHB Debug JTAG TAP Gaisler Research
61 SVGA Controller Gaisler Research
62 GR Ethernet MAC Gaisler Research
63 AHB/APB Bridge Gaisler Research
64 LEON3 Debug Support Unit Gaisler Research
65 DDR266 Controller Gaisler Research
66 LEON2 Memory Controller European Space Agency
67 Generic APB UART Gaisler Research
68 Multi-processor Interrupt Ctrl Gaisler Research
69 Modular Timer Unit Gaisler Research
70 PS/2 interface Gaisler Research
71 General purpose I/O port Gaisler Research
72
73 Use command 'info sys' to print a detailed report of attached cores
74
75 grlib> inf sys
76 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
77 ahb master 0
78 01.01:007 Gaisler Research AHB Debug UART (ver 0x0)
79 ahb master 1
80 apb: 80000700 - 80000800
81 baud rate 115200, ahb frequency 40.00
82 02.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0)
83 ahb master 2
84 03.01:063 Gaisler Research SVGA Controller (ver 0x0)
85 ahb master 3
86 apb: 80000600 - 80000700
87 clk0: 40.00 MHz
88 04.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
89 ahb master 4, irq 12
90 apb: 80000f00 - 80001000
91 edcl ip 192.168.0.51, buffer 2 kbyte
92 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
93 ahb: 80000000 - 80100000
94 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
95 ahb: 90000000 - a0000000
96 AHB trace 256 lines, 32-bit bus, stack pointer 0x43fffff0
97 CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1, GRFPU-lite
98 icache 2 * 4 kbyte, 32 byte/line rnd
99 dcache 2 * 4 kbyte, 16 byte/line rnd
100 04.01:025 Gaisler Research DDR266 Controller (ver 0x0)
101 ahb: 40000000 - 50000000
102 ahb: fff00100 - fff00200
103 16-bit DDR : 1 * 64 Mbyte @ 0x40000000
104 100 MHz, col 10, ref 7.8 us, trfc 80 ns
105 05.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
106 ahb: 00000000 - 20000000
107 ahb: 20000000 - 40000000
108 ahb: 60000000 - 70000000
109 apb: 80000000 - 80000100
110 16-bit prom @ 0x00000000
111 01.01:00c Gaisler Research Generic APB UART (ver 0x1)
112 irq 2
113 apb: 80000100 - 80000200
114 baud rate 38461, DSU mode (FIFO debug)
115 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
116 apb: 80000200 - 80000300
117 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
118 irq 8
119 apb: 80000300 - 80000400
120 8-bit scaler, 2 * 32-bit timers, divisor 40
121 05.01:060 Gaisler Research PS/2 interface (ver 0x2)
122 irq 5
123 apb: 80000500 - 80000600
124 0b.01:01a Gaisler Research General purpose I/O port (ver 0x0)
125 apb: 80000b00 - 80000c00
126 grlib>
127
128 grlib> flas
129
130 Intel-style 16-bit flash on D[31:16]
131
132 Manuf. Intel
133 Device MT28F128J3 )
134
135 Device ID 0418ffff008844d1
136 User ID ffffffffffffffff
137
138
139 1 x 16 Mbyte = 16 Mbyte total @ 0x00000000
140
141
142 CFI info
143 flash family : 1
144 flash size : 128 Mbit
145 erase regions : 1
146 erase blocks : 128
147 write buffer : 32 bytes
148 region 0 : 128 blocks of 128 Kbytes
149
150 grlib>
151
152 grlib> lo ~/examples/dhry412
153 section: .text at 0x40000000, size 53296 bytes
154 section: .data at 0x4000d030, size 2764 bytes
155 total size: 56060 bytes (63.3 Mbit/s)
156 read 262 symbols
157 entry point: 0x40000000
158 grlib> run
159 Execution starts, 1000000 runs through Dhrystone
160 Total execution time: 10.5 s
161 Microseconds for one run through Dhrystone: 10.5
162 Dhrystones per Second: 95073.0
163
164 Dhrystones MIPS : 54.1
165
166
167 Program exited normally.
168 grlib>
169
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@@ -1,164 +1,164
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
18
19 -- LEON3 processor core
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
23 constant CFG_V8 : integer := CFG_IU_V8;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
25 constant CFG_BP : integer := CONFIG_IU_BP;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
72
73 -- AMBA settings
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
83
84 -- DSU UART
85 constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
86
87 -- JTAG based DSU interface
88 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
89
90 -- Ethernet DSU
91 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
92 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
93 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
94 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
95 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
96 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
97
98 -- LEON2 memory controller
99 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
100 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
101 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
102 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
103 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
104 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
105 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
106 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
107 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
108
109 -- DDR controller
110 constant CFG_DDRSP : integer := CONFIG_DDRSP;
111 constant CFG_DDRSP_INIT : integer := CONFIG_DDRSP_INIT;
112 constant CFG_DDRSP_FREQ : integer := CONFIG_DDRSP_FREQ;
113 constant CFG_DDRSP_COL : integer := CONFIG_DDRSP_COL;
114 constant CFG_DDRSP_SIZE : integer := CONFIG_DDRSP_MBYTE;
115 constant CFG_DDRSP_RSKEW : integer := CONFIG_DDRSP_RSKEW;
116
117 -- AHB ROM
118 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
119 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
120 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
121 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
122 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
123
124 -- AHB RAM
125 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
126 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
127 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
128
129 -- Gaisler Ethernet core
130 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
131 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
132 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
133
134 -- UART 1
135 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
136 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
137
138 -- LEON3 interrupt controller
139 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
140 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
141
142 -- Modular timer
143 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
144 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
145 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
146 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
147 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
148 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
149 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
150 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
151
152 -- GPIO port
153 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
154 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
155 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
156
157 -- VGA and PS2/ interface
158 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
159 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
160 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
161
162 -- GRLIB debugging
163 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
164
1 -- Technology and synthesis options
2 constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3 constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4 constant CFG_PADTECH : integer := CFG_PAD_TECH;
5 constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6 constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7
8 -- Clock generator
9 constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10 constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11 constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12 constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13 constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
14 constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
15 constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
16 constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
17 constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
18
19 -- LEON3 processor core
20 constant CFG_LEON3 : integer := CONFIG_LEON3;
21 constant CFG_NCPU : integer := CONFIG_PROC_NUM;
22 constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
23 constant CFG_V8 : integer := CFG_IU_V8;
24 constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
25 constant CFG_BP : integer := CONFIG_IU_BP;
26 constant CFG_SVT : integer := CONFIG_IU_SVT;
27 constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
28 constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
29 constant CFG_NOTAG : integer := CONFIG_NOTAG;
30 constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
31 constant CFG_PWD : integer := CONFIG_PWD*2;
32 constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
33 constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
34 constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
35 constant CFG_ISETS : integer := CFG_IU_ISETS;
36 constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
37 constant CFG_ILINE : integer := CFG_ILINE_SZ;
38 constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
39 constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
40 constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
41 constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
42 constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
43 constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
44 constant CFG_DSETS : integer := CFG_IU_DSETS;
45 constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
46 constant CFG_DLINE : integer := CFG_DLINE_SZ;
47 constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
48 constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
49 constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
50 constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
51 constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
52 constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
53 constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
54 constant CFG_MMUEN : integer := CONFIG_MMUEN;
55 constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
56 constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
57 constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
58 constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
59 constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
60 constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
61 constant CFG_ITBSZ : integer := CFG_DSU_ITB;
62 constant CFG_ATBSZ : integer := CFG_DSU_ATB;
63 constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
64 constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
65 constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
66 constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
67 constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
68 constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
69 constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
70 constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
71 constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
72
73 -- AMBA settings
74 constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
75 constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
76 constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
77 constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
78 constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
79 constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
80 constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
81 constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
82 constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
83
84 -- DSU UART
85 constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
86
87 -- JTAG based DSU interface
88 constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
89
90 -- Ethernet DSU
91 constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
92 constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
93 constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
94 constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
95 constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
96 constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
97
98 -- LEON2 memory controller
99 constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
100 constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
101 constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
102 constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
103 constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
104 constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
105 constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
106 constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
107 constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
108
109 -- DDR controller
110 constant CFG_DDRSP : integer := CONFIG_DDRSP;
111 constant CFG_DDRSP_INIT : integer := CONFIG_DDRSP_INIT;
112 constant CFG_DDRSP_FREQ : integer := CONFIG_DDRSP_FREQ;
113 constant CFG_DDRSP_COL : integer := CONFIG_DDRSP_COL;
114 constant CFG_DDRSP_SIZE : integer := CONFIG_DDRSP_MBYTE;
115 constant CFG_DDRSP_RSKEW : integer := CONFIG_DDRSP_RSKEW;
116
117 -- AHB ROM
118 constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
119 constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
120 constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
121 constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
122 constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
123
124 -- AHB RAM
125 constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
126 constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
127 constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
128
129 -- Gaisler Ethernet core
130 constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
131 constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
132 constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
133
134 -- UART 1
135 constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
136 constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
137
138 -- LEON3 interrupt controller
139 constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
140 constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
141
142 -- Modular timer
143 constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
144 constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
145 constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
146 constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
147 constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
148 constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
149 constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
150 constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
151
152 -- GPIO port
153 constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
154 constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
155 constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
156
157 -- VGA and PS2/ interface
158 constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
159 constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
160 constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
161
162 -- GRLIB debugging
163 constant CFG_DUART : integer := CONFIG_DEBUG_UART;
164
Show file before | Show file after | Hide comments
@@ -1,227 +1,227
1 [Library]
2 grlib = modelsim/grlib
3 unisim = modelsim/unisim
4 dw02 = modelsim/dw02
5 synplify = modelsim/synplify
6 techmap = modelsim/techmap
7 eth = modelsim/eth
8 gaisler = modelsim/gaisler
9 esa = modelsim/esa
10 fmf = modelsim/fmf
11 spansion = modelsim/spansion
12 gsi = modelsim/gsi
13 lpp = modelsim/lpp
14 cypress = modelsim/cypress
15 hynix = modelsim/hynix
16 micron = modelsim/micron
17 work = modelsim/work
18 std = $MODEL_TECH/../std
19 ieee = $MODEL_TECH/../ieee
20 vital2000 = $MODEL_TECH/../vital2000
21 verilog = $MODEL_TECH/../verilog
22 arithmetic = $MODEL_TECH/../arithmetic
23 mgc_portable = $MODEL_TECH/../mgc_portable
24 std_developerskit = $MODEL_TECH/../std_developerskit
25 synopsys = $MODEL_TECH/../synopsys
26
27 [vcom]
28 ; Turn on VHDL-1993 as the default. Normally is off.
29 VHDL93 = 1
30
31 ; Show source line containing error. Default is off.
32 Show_source = 1
33
34 ; Turn off unbound-component warnings. Default is on.
35 Show_Warning1 = 0
36
37 ; Turn off process-without-a-wait-statement warnings. Default is on.
38 ; Show_Warning2 = 0
39
40 ; Turn off null-range warnings. Default is on.
41 ; Show_Warning3 = 0
42
43 ; Turn off no-space-in-time-literal warnings. Default is on.
44 ; Show_Warning4 = 0
45
46 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
47 Show_Warning5 = 0
48
49 ; Turn off optimization for IEEE std_logic_1164 package. Default is on.
50 ; Optimize_1164 = 0
51
52 ; Turn on resolving of ambiguous function overloading in favor of the
53 ; "explicit" function declaration (not the one automatically created by
54 ; the compiler for each type declaration). Default is off.
55 Explicit = 1
56
57 ; Turn off VITAL compliance checking. Default is checking on.
58 ; NoVitalCheck = 1
59
60 ; Ignore VITAL compliance checking errors. Default is to not ignore.
61 ; IgnoreVitalErrors = 1
62
63 ; Turn off VITAL compliance checking warnings. Default is to show warnings.
64 ; Show_VitalChecksWarnings = false
65
66 ; Turn off acceleration of the VITAL packages. Default is to accelerate.
67 ; NoVital = 1
68
69 ; Turn off inclusion of debugging info within design units. Default is to include.
70 ; NoDebug = 1
71
72 ; Turn off "loading..." messages. Default is messages on.
73 Quiet = 1
74
75 ; Turn on some limited synthesis rule compliance checking. Checks only:
76 ; -- signals used (read) by a process must be in the sensitivity list
77 ; CheckSynthesis = 1
78
79 [vlog]
80
81 ; Turn off inclusion of debugging info within design units. Default is to include.
82 ; NoDebug = 1
83
84 ; Turn off "loading..." messages. Default is messages on.
85 Quiet = 1
86
87 ; Turn on Verilog hazard checking (order-dependent accessing of global vars).
88 ; Default is off.
89 ; Hazard = 1
90
91 ; Turn on converting regular Verilog identifiers to uppercase. Allows case
92 ; insensitivity for module names. Default is no conversion.
93 ; UpCase = 1
94
95 [vsim]
96
97 ; vopt flow
98 ; Set to turn on automatic optimization of a design.
99 ; Default is off (pre-6.0 flow without vopt).
100 VoptFlow = 0
101
102 ; Simulator resolution
103 ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
104 Resolution = 1ps
105
106 ; User time unit for run commands
107 ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
108 ; unit specified for Resolution. For example, if Resolution is 100ps,
109 ; then UserTimeUnit defaults to ps.
110 UserTimeUnit = ns
111
112 ; Default run length
113 RunLength = 100
114
115 ; Maximum iterations that can be run without advancing simulation time
116 IterationLimit = 5000
117
118 ; Directive to license manager:
119 ; vhdl Immediately reserve a VHDL license
120 ; vlog Immediately reserve a Verilog license
121 ; plus Immediately reserve a VHDL and Verilog license
122 ; nomgc Do not look for Mentor Graphics Licenses
123 ; nomti Do not look for Model Technology Licenses
124 ; noqueue Do not wait in the license queue when a license isn't available
125 ; License = plus
126
127 ; Stop the simulator after an assertion message
128 ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
129 BreakOnAssertion = 3
130
131 ; Assertion Message Format
132 ; %S - Severity Level
133 ; %R - Report Message
134 ; %T - Time of assertion
135 ; %D - Delta
136 ; %I - Instance or Region pathname (if available)
137 ; %% - print '%' character
138 ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
139
140 ; Default radix for all windows and commands...
141 ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
142 DefaultRadix = symbolic
143
144 ; VSIM Startup command
145 ; Startup = do startup.do
146
147 ; File for saving command transcript
148 TranscriptFile = transcript
149
150 ; Specify whether paths in simulator commands should be described
151 ; in VHDL or Verilog format. For VHDL, PathSeparator = /
152 ; for Verilog, PathSeparator = .
153 PathSeparator = /
154
155 ; Disable assertion messages
156 ; IgnoreNote = 1
157 ; IgnoreWarning = 1
158 ; IgnoreError = 1
159 ; IgnoreFailure = 1
160
161 ; Default force kind. May be freeze, drive, or deposit
162 ; or in other terms, fixed, wired or charged.
163 ; DefaultForceKind = freeze
164
165 ; If zero, open files when elaborated
166 ; else open files on first read or write
167 ; DelayFileOpen = 0
168
169 ; Control VHDL files opened for write
170 ; 0 = Buffered, 1 = Unbuffered
171 UnbufferedOutput = 0
172
173 ; This controls the number of characters of a signal name
174 ; shown in the waveform window and the postscript plot.
175 ; The default value or a value of zero tells VSIM to display
176 ; the full name.
177 ; WaveSignalNameWidth = 10
178
179 ; Turn off warnings from the std_logic_arith, std_logic_unsigned
180 ; and std_logic_signed packages.
181 ; StdArithNoWarnings = 1
182
183 ; Turn off warnings from the IEEE numeric_std and numeric_bit
184 ; packages.
185 ; NumericStdNoWarnings = 1
186
187 ; Control the format of a generate statement label. Don't quote it.
188 ; GenerateFormat = %s__%d
189
190 ; Specify whether checkpoint files should be compressed.
191 ; The default is to be compressed.
192 ; CheckpointCompressMode = 0
193
194 ; List of dynamically loaded objects for Verilog PLI applications
195 ; Veriuser = veriuser.sl
196
197 [lmc]
198 ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
199 libsm = $MODEL_TECH/libsm.sl
200 ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
201 ; libsm = $MODEL_TECH/libsm.dll
202 ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
203 ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
204 ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
205 ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
206 ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
207 ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
208 ; Logic Modeling's SmartModel SWIFT software (Sun4 SunOS)
209 ; do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib
210 ; and run "vsim.swift".
211 ; Logic Modeling's SmartModel SWIFT software (Windows NT)
212 ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
213
214 ; ModelSim's interface to Logic Modeling's hardware modeler SFI software
215 libhm = $MODEL_TECH/libhm.sl
216 ; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
217 ; libhm = $MODEL_TECH/libhm.dll
218 ; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
219 ; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
220 ; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
221 ; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
222 ; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
223 ; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
224 ; Logic Modeling's hardware modeler SFI software (Sun4 SunOS)
225 ; libsfi = <sfi_dir>/lib/sun4.sunos/libsfi.so
226 ; Logic Modeling's hardware modeler SFI software (Window NT)
227 ; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
1 [Library]
2 grlib = modelsim/grlib
3 unisim = modelsim/unisim
4 dw02 = modelsim/dw02
5 synplify = modelsim/synplify
6 techmap = modelsim/techmap
7 eth = modelsim/eth
8 gaisler = modelsim/gaisler
9 esa = modelsim/esa
10 fmf = modelsim/fmf
11 spansion = modelsim/spansion
12 gsi = modelsim/gsi
13 lpp = modelsim/lpp
14 cypress = modelsim/cypress
15 hynix = modelsim/hynix
16 micron = modelsim/micron
17 work = modelsim/work
18 std = $MODEL_TECH/../std
19 ieee = $MODEL_TECH/../ieee
20 vital2000 = $MODEL_TECH/../vital2000
21 verilog = $MODEL_TECH/../verilog
22 arithmetic = $MODEL_TECH/../arithmetic
23 mgc_portable = $MODEL_TECH/../mgc_portable
24 std_developerskit = $MODEL_TECH/../std_developerskit
25 synopsys = $MODEL_TECH/../synopsys
26
27 [vcom]
28 ; Turn on VHDL-1993 as the default. Normally is off.
29 VHDL93 = 1
30
31 ; Show source line containing error. Default is off.
32 Show_source = 1
33
34 ; Turn off unbound-component warnings. Default is on.
35 Show_Warning1 = 0
36
37 ; Turn off process-without-a-wait-statement warnings. Default is on.
38 ; Show_Warning2 = 0
39
40 ; Turn off null-range warnings. Default is on.
41 ; Show_Warning3 = 0
42
43 ; Turn off no-space-in-time-literal warnings. Default is on.
44 ; Show_Warning4 = 0
45
46 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
47 Show_Warning5 = 0
48
49 ; Turn off optimization for IEEE std_logic_1164 package. Default is on.
50 ; Optimize_1164 = 0
51
52 ; Turn on resolving of ambiguous function overloading in favor of the
53 ; "explicit" function declaration (not the one automatically created by
54 ; the compiler for each type declaration). Default is off.
55 Explicit = 1
56
57 ; Turn off VITAL compliance checking. Default is checking on.
58 ; NoVitalCheck = 1
59
60 ; Ignore VITAL compliance checking errors. Default is to not ignore.
61 ; IgnoreVitalErrors = 1
62
63 ; Turn off VITAL compliance checking warnings. Default is to show warnings.
64 ; Show_VitalChecksWarnings = false
65
66 ; Turn off acceleration of the VITAL packages. Default is to accelerate.
67 ; NoVital = 1
68
69 ; Turn off inclusion of debugging info within design units. Default is to include.
70 ; NoDebug = 1
71
72 ; Turn off "loading..." messages. Default is messages on.
73 Quiet = 1
74
75 ; Turn on some limited synthesis rule compliance checking. Checks only:
76 ; -- signals used (read) by a process must be in the sensitivity list
77 ; CheckSynthesis = 1
78
79 [vlog]
80
81 ; Turn off inclusion of debugging info within design units. Default is to include.
82 ; NoDebug = 1
83
84 ; Turn off "loading..." messages. Default is messages on.
85 Quiet = 1
86
87 ; Turn on Verilog hazard checking (order-dependent accessing of global vars).
88 ; Default is off.
89 ; Hazard = 1
90
91 ; Turn on converting regular Verilog identifiers to uppercase. Allows case
92 ; insensitivity for module names. Default is no conversion.
93 ; UpCase = 1
94
95 [vsim]
96
97 ; vopt flow
98 ; Set to turn on automatic optimization of a design.
99 ; Default is off (pre-6.0 flow without vopt).
100 VoptFlow = 0
101
102 ; Simulator resolution
103 ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
104 Resolution = 1ps
105
106 ; User time unit for run commands
107 ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
108 ; unit specified for Resolution. For example, if Resolution is 100ps,
109 ; then UserTimeUnit defaults to ps.
110 UserTimeUnit = ns
111
112 ; Default run length
113 RunLength = 100
114
115 ; Maximum iterations that can be run without advancing simulation time
116 IterationLimit = 5000
117
118 ; Directive to license manager:
119 ; vhdl Immediately reserve a VHDL license
120 ; vlog Immediately reserve a Verilog license
121 ; plus Immediately reserve a VHDL and Verilog license
122 ; nomgc Do not look for Mentor Graphics Licenses
123 ; nomti Do not look for Model Technology Licenses
124 ; noqueue Do not wait in the license queue when a license isn't available
125 ; License = plus
126
127 ; Stop the simulator after an assertion message
128 ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
129 BreakOnAssertion = 3
130
131 ; Assertion Message Format
132 ; %S - Severity Level
133 ; %R - Report Message
134 ; %T - Time of assertion
135 ; %D - Delta
136 ; %I - Instance or Region pathname (if available)
137 ; %% - print '%' character
138 ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
139
140 ; Default radix for all windows and commands...
141 ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
142 DefaultRadix = symbolic
143
144 ; VSIM Startup command
145 ; Startup = do startup.do
146
147 ; File for saving command transcript
148 TranscriptFile = transcript
149
150 ; Specify whether paths in simulator commands should be described
151 ; in VHDL or Verilog format. For VHDL, PathSeparator = /
152 ; for Verilog, PathSeparator = .
153 PathSeparator = /
154
155 ; Disable assertion messages
156 ; IgnoreNote = 1
157 ; IgnoreWarning = 1
158 ; IgnoreError = 1
159 ; IgnoreFailure = 1
160
161 ; Default force kind. May be freeze, drive, or deposit
162 ; or in other terms, fixed, wired or charged.
163 ; DefaultForceKind = freeze
164
165 ; If zero, open files when elaborated
166 ; else open files on first read or write
167 ; DelayFileOpen = 0
168
169 ; Control VHDL files opened for write
170 ; 0 = Buffered, 1 = Unbuffered
171 UnbufferedOutput = 0
172
173 ; This controls the number of characters of a signal name
174 ; shown in the waveform window and the postscript plot.
175 ; The default value or a value of zero tells VSIM to display
176 ; the full name.
177 ; WaveSignalNameWidth = 10
178
179 ; Turn off warnings from the std_logic_arith, std_logic_unsigned
180 ; and std_logic_signed packages.
181 ; StdArithNoWarnings = 1
182
183 ; Turn off warnings from the IEEE numeric_std and numeric_bit
184 ; packages.
185 ; NumericStdNoWarnings = 1
186
187 ; Control the format of a generate statement label. Don't quote it.
188 ; GenerateFormat = %s__%d
189
190 ; Specify whether checkpoint files should be compressed.
191 ; The default is to be compressed.
192 ; CheckpointCompressMode = 0
193
194 ; List of dynamically loaded objects for Verilog PLI applications
195 ; Veriuser = veriuser.sl
196
197 [lmc]
198 ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
199 libsm = $MODEL_TECH/libsm.sl
200 ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
201 ; libsm = $MODEL_TECH/libsm.dll
202 ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
203 ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
204 ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
205 ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
206 ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
207 ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
208 ; Logic Modeling's SmartModel SWIFT software (Sun4 SunOS)
209 ; do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib
210 ; and run "vsim.swift".
211 ; Logic Modeling's SmartModel SWIFT software (Windows NT)
212 ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
213
214 ; ModelSim's interface to Logic Modeling's hardware modeler SFI software
215 libhm = $MODEL_TECH/libhm.sl
216 ; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
217 ; libhm = $MODEL_TECH/libhm.dll
218 ; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
219 ; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
220 ; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
221 ; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
222 ; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
223 ; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
224 ; Logic Modeling's hardware modeler SFI software (Sun4 SunOS)
225 ; libsfi = <sfi_dir>/lib/sun4.sunos/libsfi.so
226 ; Logic Modeling's hardware modeler SFI software (Window NT)
227 ; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
Show file before | Show file after | Hide comments
@@ -1,10 +1,10
1 #define MCFG1 0x10380133
2 #define MCFG2 0xe6B80e60
3 #define MCFG3 0x000ff000
4 #define ASDCFG 0xfff00100
5 #define DSDCFG 0xe6A06e60
6 #define L2MCTRLIO 0x80000000
7 #define IRQCTRL 0x80000200
8 #define RAMSTART 0x40000000
9 #define RAMSIZE 0x00100000
10
1 #define MCFG1 0x10380133
2 #define MCFG2 0xe6B80e60
3 #define MCFG3 0x000ff000
4 #define ASDCFG 0xfff00100
5 #define DSDCFG 0xe6A06e60
6 #define L2MCTRLIO 0x80000000
7 #define IRQCTRL 0x80000200
8 #define RAMSTART 0x40000000
9 #define RAMSIZE 0x00100000
10
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@@ -1,10 +1,10
1
2 main()
3
4 {
5 report_start();
6
7 base_test();
8
9 report_end();
10 }
1
2 main()
3
4 {
5 report_start();
6
7 base_test();
8
9 report_end();
10 }
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (1898 lines changed) Show them Hide them
@@ -1,949 +1,949
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_AXDSP
14 #define CONFIG_SYN_TECH axdsp
15 #elif defined CONFIG_SYN_PROASICPLUS
16 #define CONFIG_SYN_TECH proasic
17 #elif defined CONFIG_SYN_ALTERA
18 #define CONFIG_SYN_TECH altera
19 #elif defined CONFIG_SYN_STRATIX
20 #define CONFIG_SYN_TECH stratix1
21 #elif defined CONFIG_SYN_STRATIXII
22 #define CONFIG_SYN_TECH stratix2
23 #elif defined CONFIG_SYN_STRATIXIII
24 #define CONFIG_SYN_TECH stratix3
25 #elif defined CONFIG_SYN_CYCLONEIII
26 #define CONFIG_SYN_TECH cyclone3
27 #elif defined CONFIG_SYN_EASIC90
28 #define CONFIG_SYN_TECH easic90
29 #elif defined CONFIG_SYN_IHP25
30 #define CONFIG_SYN_TECH ihp25
31 #elif defined CONFIG_SYN_IHP25RH
32 #define CONFIG_SYN_TECH ihp25rh
33 #elif defined CONFIG_SYN_CMOS9SF
34 #define CONFIG_SYN_TECH cmos9sf
35 #elif defined CONFIG_SYN_LATTICE
36 #define CONFIG_SYN_TECH lattice
37 #elif defined CONFIG_SYN_ECLIPSE
38 #define CONFIG_SYN_TECH eclipse
39 #elif defined CONFIG_SYN_PEREGRINE
40 #define CONFIG_SYN_TECH peregrine
41 #elif defined CONFIG_SYN_PROASIC
42 #define CONFIG_SYN_TECH proasic
43 #elif defined CONFIG_SYN_PROASIC3
44 #define CONFIG_SYN_TECH apa3
45 #elif defined CONFIG_SYN_PROASIC3E
46 #define CONFIG_SYN_TECH apa3e
47 #elif defined CONFIG_SYN_PROASIC3L
48 #define CONFIG_SYN_TECH apa3l
49 #elif defined CONFIG_SYN_IGLOO
50 #define CONFIG_SYN_TECH apa3
51 #elif defined CONFIG_SYN_FUSION
52 #define CONFIG_SYN_TECH actfus
53 #elif defined CONFIG_SYN_SPARTAN2
54 #define CONFIG_SYN_TECH virtex
55 #elif defined CONFIG_SYN_VIRTEX
56 #define CONFIG_SYN_TECH virtex
57 #elif defined CONFIG_SYN_VIRTEXE
58 #define CONFIG_SYN_TECH virtex
59 #elif defined CONFIG_SYN_SPARTAN3
60 #define CONFIG_SYN_TECH spartan3
61 #elif defined CONFIG_SYN_SPARTAN3E
62 #define CONFIG_SYN_TECH spartan3e
63 #elif defined CONFIG_SYN_SPARTAN6
64 #define CONFIG_SYN_TECH spartan6
65 #elif defined CONFIG_SYN_VIRTEX2
66 #define CONFIG_SYN_TECH virtex2
67 #elif defined CONFIG_SYN_VIRTEX4
68 #define CONFIG_SYN_TECH virtex4
69 #elif defined CONFIG_SYN_VIRTEX5
70 #define CONFIG_SYN_TECH virtex5
71 #elif defined CONFIG_SYN_VIRTEX6
72 #define CONFIG_SYN_TECH virtex6
73 #elif defined CONFIG_SYN_RH_LIB18T
74 #define CONFIG_SYN_TECH rhlib18t
75 #elif defined CONFIG_SYN_SMIC13
76 #define CONFIG_SYN_TECH smic013
77 #elif defined CONFIG_SYN_UT025CRH
78 #define CONFIG_SYN_TECH ut25
79 #elif defined CONFIG_SYN_TSMC90
80 #define CONFIG_SYN_TECH tsmc90
81 #elif defined CONFIG_SYN_TM65GPLUS
82 #define CONFIG_SYN_TECH tm65gpl
83 #elif defined CONFIG_SYN_CUSTOM1
84 #define CONFIG_SYN_TECH custom1
85 #else
86 #error "unknown target technology"
87 #endif
88
89 #if defined CONFIG_SYN_INFER_RAM
90 #define CFG_RAM_TECH inferred
91 #elif defined CONFIG_MEM_UMC
92 #define CFG_RAM_TECH umc
93 #elif defined CONFIG_MEM_RHUMC
94 #define CFG_RAM_TECH rhumc
95 #elif defined CONFIG_MEM_VIRAGE
96 #define CFG_RAM_TECH memvirage
97 #elif defined CONFIG_MEM_ARTISAN
98 #define CFG_RAM_TECH memartisan
99 #elif defined CONFIG_MEM_CUSTOM1
100 #define CFG_RAM_TECH custom1
101 #elif defined CONFIG_MEM_VIRAGE90
102 #define CFG_RAM_TECH memvirage90
103 #elif defined CONFIG_MEM_INFERRED
104 #define CFG_RAM_TECH inferred
105 #else
106 #define CFG_RAM_TECH CONFIG_SYN_TECH
107 #endif
108
109 #if defined CONFIG_SYN_INFER_PADS
110 #define CFG_PAD_TECH inferred
111 #else
112 #define CFG_PAD_TECH CONFIG_SYN_TECH
113 #endif
114
115 #ifndef CONFIG_SYN_NO_ASYNC
116 #define CONFIG_SYN_NO_ASYNC 0
117 #endif
118
119 #ifndef CONFIG_SYN_SCAN
120 #define CONFIG_SYN_SCAN 0
121 #endif
122
123
124 #if defined CONFIG_CLK_ALTDLL
125 #define CFG_CLK_TECH CONFIG_SYN_TECH
126 #elif defined CONFIG_CLK_HCLKBUF
127 #define CFG_CLK_TECH axcel
128 #elif defined CONFIG_CLK_LATDLL
129 #define CFG_CLK_TECH lattice
130 #elif defined CONFIG_CLK_PRO3PLL
131 #define CFG_CLK_TECH apa3
132 #elif defined CONFIG_CLK_PRO3EPLL
133 #define CFG_CLK_TECH apa3e
134 #elif defined CONFIG_CLK_PRO3LPLL
135 #define CFG_CLK_TECH apa3l
136 #elif defined CONFIG_CLK_FUSPLL
137 #define CFG_CLK_TECH actfus
138 #elif defined CONFIG_CLK_CLKDLL
139 #define CFG_CLK_TECH virtex
140 #elif defined CONFIG_CLK_DCM
141 #define CFG_CLK_TECH CONFIG_SYN_TECH
142 #elif defined CONFIG_CLK_LIB18T
143 #define CFG_CLK_TECH rhlib18t
144 #elif defined CONFIG_CLK_RHUMC
145 #define CFG_CLK_TECH rhumc
146 #else
147 #define CFG_CLK_TECH inferred
148 #endif
149
150 #ifndef CONFIG_CLK_MUL
151 #define CONFIG_CLK_MUL 2
152 #endif
153
154 #ifndef CONFIG_CLK_DIV
155 #define CONFIG_CLK_DIV 2
156 #endif
157
158 #ifndef CONFIG_OCLK_DIV
159 #define CONFIG_OCLK_DIV 1
160 #endif
161
162 #ifndef CONFIG_OCLKB_DIV
163 #define CONFIG_OCLKB_DIV 0
164 #endif
165
166 #ifndef CONFIG_OCLKC_DIV
167 #define CONFIG_OCLKC_DIV 0
168 #endif
169
170 #ifndef CONFIG_PCI_CLKDLL
171 #define CONFIG_PCI_CLKDLL 0
172 #endif
173
174 #ifndef CONFIG_PCI_SYSCLK
175 #define CONFIG_PCI_SYSCLK 0
176 #endif
177
178 #ifndef CONFIG_CLK_NOFB
179 #define CONFIG_CLK_NOFB 0
180 #endif
181 #ifndef CONFIG_LEON3
182 #define CONFIG_LEON3 0
183 #endif
184
185 #ifndef CONFIG_PROC_NUM
186 #define CONFIG_PROC_NUM 1
187 #endif
188
189 #ifndef CONFIG_IU_NWINDOWS
190 #define CONFIG_IU_NWINDOWS 8
191 #endif
192
193 #ifndef CONFIG_IU_RSTADDR
194 #define CONFIG_IU_RSTADDR 8
195 #endif
196
197 #ifndef CONFIG_IU_LDELAY
198 #define CONFIG_IU_LDELAY 1
199 #endif
200
201 #ifndef CONFIG_IU_WATCHPOINTS
202 #define CONFIG_IU_WATCHPOINTS 0
203 #endif
204
205 #ifdef CONFIG_IU_V8MULDIV
206 #ifdef CONFIG_IU_MUL_LATENCY_4
207 #define CFG_IU_V8 1
208 #elif defined CONFIG_IU_MUL_LATENCY_5
209 #define CFG_IU_V8 2
210 #elif defined CONFIG_IU_MUL_LATENCY_2
211 #define CFG_IU_V8 16#32#
212 #endif
213 #else
214 #define CFG_IU_V8 0
215 #endif
216
217 #ifndef CONFIG_PWD
218 #define CONFIG_PWD 0
219 #endif
220
221 #ifndef CONFIG_IU_MUL_MAC
222 #define CONFIG_IU_MUL_MAC 0
223 #endif
224
225 #ifndef CONFIG_IU_BP
226 #define CONFIG_IU_BP 0
227 #endif
228
229 #ifndef CONFIG_NOTAG
230 #define CONFIG_NOTAG 0
231 #endif
232
233 #ifndef CONFIG_IU_SVT
234 #define CONFIG_IU_SVT 0
235 #endif
236
237 #if defined CONFIG_FPU_GRFPC1
238 #define CONFIG_FPU_GRFPC 1
239 #elif defined CONFIG_FPU_GRFPC2
240 #define CONFIG_FPU_GRFPC 2
241 #else
242 #define CONFIG_FPU_GRFPC 0
243 #endif
244
245 #if defined CONFIG_FPU_GRFPU_INFMUL
246 #define CONFIG_FPU_GRFPU_MUL 0
247 #elif defined CONFIG_FPU_GRFPU_DWMUL
248 #define CONFIG_FPU_GRFPU_MUL 1
249 #elif defined CONFIG_FPU_GRFPU_MODGEN
250 #define CONFIG_FPU_GRFPU_MUL 2
251 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
252 #define CONFIG_FPU_GRFPU_MUL 3
253 #else
254 #define CONFIG_FPU_GRFPU_MUL 0
255 #endif
256
257 #if defined CONFIG_FPU_GRFPU_SH
258 #define CONFIG_FPU_GRFPU_SHARED 1
259 #else
260 #define CONFIG_FPU_GRFPU_SHARED 0
261 #endif
262
263 #if defined CONFIG_FPU_GRFPU
264 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
265 #elif defined CONFIG_FPU_MEIKO
266 #define CONFIG_FPU 15
267 #elif defined CONFIG_FPU_GRFPULITE
268 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
269 #else
270 #define CONFIG_FPU 0
271 #endif
272
273 #ifndef CONFIG_FPU_NETLIST
274 #define CONFIG_FPU_NETLIST 0
275 #endif
276
277 #ifndef CONFIG_ICACHE_ENABLE
278 #define CONFIG_ICACHE_ENABLE 0
279 #endif
280
281 #if defined CONFIG_ICACHE_ASSO1
282 #define CFG_IU_ISETS 1
283 #elif defined CONFIG_ICACHE_ASSO2
284 #define CFG_IU_ISETS 2
285 #elif defined CONFIG_ICACHE_ASSO3
286 #define CFG_IU_ISETS 3
287 #elif defined CONFIG_ICACHE_ASSO4
288 #define CFG_IU_ISETS 4
289 #else
290 #define CFG_IU_ISETS 1
291 #endif
292
293 #if defined CONFIG_ICACHE_SZ1
294 #define CFG_ICACHE_SZ 1
295 #elif defined CONFIG_ICACHE_SZ2
296 #define CFG_ICACHE_SZ 2
297 #elif defined CONFIG_ICACHE_SZ4
298 #define CFG_ICACHE_SZ 4
299 #elif defined CONFIG_ICACHE_SZ8
300 #define CFG_ICACHE_SZ 8
301 #elif defined CONFIG_ICACHE_SZ16
302 #define CFG_ICACHE_SZ 16
303 #elif defined CONFIG_ICACHE_SZ32
304 #define CFG_ICACHE_SZ 32
305 #elif defined CONFIG_ICACHE_SZ64
306 #define CFG_ICACHE_SZ 64
307 #elif defined CONFIG_ICACHE_SZ128
308 #define CFG_ICACHE_SZ 128
309 #elif defined CONFIG_ICACHE_SZ256
310 #define CFG_ICACHE_SZ 256
311 #else
312 #define CFG_ICACHE_SZ 1
313 #endif
314
315 #ifdef CONFIG_ICACHE_LZ16
316 #define CFG_ILINE_SZ 4
317 #else
318 #define CFG_ILINE_SZ 8
319 #endif
320
321 #if defined CONFIG_ICACHE_ALGORND
322 #define CFG_ICACHE_ALGORND 2
323 #elif defined CONFIG_ICACHE_ALGOLRR
324 #define CFG_ICACHE_ALGORND 1
325 #else
326 #define CFG_ICACHE_ALGORND 0
327 #endif
328
329 #ifndef CONFIG_ICACHE_LOCK
330 #define CONFIG_ICACHE_LOCK 0
331 #endif
332
333 #ifndef CONFIG_ICACHE_LRAM
334 #define CONFIG_ICACHE_LRAM 0
335 #endif
336
337 #ifndef CONFIG_ICACHE_LRSTART
338 #define CONFIG_ICACHE_LRSTART 8E
339 #endif
340
341 #if defined CONFIG_ICACHE_LRAM_SZ2
342 #define CFG_ILRAM_SIZE 2
343 #elif defined CONFIG_ICACHE_LRAM_SZ4
344 #define CFG_ILRAM_SIZE 4
345 #elif defined CONFIG_ICACHE_LRAM_SZ8
346 #define CFG_ILRAM_SIZE 8
347 #elif defined CONFIG_ICACHE_LRAM_SZ16
348 #define CFG_ILRAM_SIZE 16
349 #elif defined CONFIG_ICACHE_LRAM_SZ32
350 #define CFG_ILRAM_SIZE 32
351 #elif defined CONFIG_ICACHE_LRAM_SZ64
352 #define CFG_ILRAM_SIZE 64
353 #elif defined CONFIG_ICACHE_LRAM_SZ128
354 #define CFG_ILRAM_SIZE 128
355 #elif defined CONFIG_ICACHE_LRAM_SZ256
356 #define CFG_ILRAM_SIZE 256
357 #else
358 #define CFG_ILRAM_SIZE 1
359 #endif
360
361
362 #ifndef CONFIG_DCACHE_ENABLE
363 #define CONFIG_DCACHE_ENABLE 0
364 #endif
365
366 #if defined CONFIG_DCACHE_ASSO1
367 #define CFG_IU_DSETS 1
368 #elif defined CONFIG_DCACHE_ASSO2
369 #define CFG_IU_DSETS 2
370 #elif defined CONFIG_DCACHE_ASSO3
371 #define CFG_IU_DSETS 3
372 #elif defined CONFIG_DCACHE_ASSO4
373 #define CFG_IU_DSETS 4
374 #else
375 #define CFG_IU_DSETS 1
376 #endif
377
378 #if defined CONFIG_DCACHE_SZ1
379 #define CFG_DCACHE_SZ 1
380 #elif defined CONFIG_DCACHE_SZ2
381 #define CFG_DCACHE_SZ 2
382 #elif defined CONFIG_DCACHE_SZ4
383 #define CFG_DCACHE_SZ 4
384 #elif defined CONFIG_DCACHE_SZ8
385 #define CFG_DCACHE_SZ 8
386 #elif defined CONFIG_DCACHE_SZ16
387 #define CFG_DCACHE_SZ 16
388 #elif defined CONFIG_DCACHE_SZ32
389 #define CFG_DCACHE_SZ 32
390 #elif defined CONFIG_DCACHE_SZ64
391 #define CFG_DCACHE_SZ 64
392 #elif defined CONFIG_DCACHE_SZ128
393 #define CFG_DCACHE_SZ 128
394 #elif defined CONFIG_DCACHE_SZ256
395 #define CFG_DCACHE_SZ 256
396 #else
397 #define CFG_DCACHE_SZ 1
398 #endif
399
400 #ifdef CONFIG_DCACHE_LZ16
401 #define CFG_DLINE_SZ 4
402 #else
403 #define CFG_DLINE_SZ 8
404 #endif
405
406 #if defined CONFIG_DCACHE_ALGORND
407 #define CFG_DCACHE_ALGORND 2
408 #elif defined CONFIG_DCACHE_ALGOLRR
409 #define CFG_DCACHE_ALGORND 1
410 #else
411 #define CFG_DCACHE_ALGORND 0
412 #endif
413
414 #ifndef CONFIG_DCACHE_LOCK
415 #define CONFIG_DCACHE_LOCK 0
416 #endif
417
418 #ifndef CONFIG_DCACHE_SNOOP
419 #define CONFIG_DCACHE_SNOOP 0
420 #endif
421
422 #ifndef CONFIG_DCACHE_SNOOP_FAST
423 #define CONFIG_DCACHE_SNOOP_FAST 0
424 #endif
425
426 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
427 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
428 #endif
429
430 #ifndef CONFIG_CACHE_FIXED
431 #define CONFIG_CACHE_FIXED 0
432 #endif
433
434 #ifndef CONFIG_DCACHE_LRAM
435 #define CONFIG_DCACHE_LRAM 0
436 #endif
437
438 #ifndef CONFIG_DCACHE_LRSTART
439 #define CONFIG_DCACHE_LRSTART 8F
440 #endif
441
442 #if defined CONFIG_DCACHE_LRAM_SZ2
443 #define CFG_DLRAM_SIZE 2
444 #elif defined CONFIG_DCACHE_LRAM_SZ4
445 #define CFG_DLRAM_SIZE 4
446 #elif defined CONFIG_DCACHE_LRAM_SZ8
447 #define CFG_DLRAM_SIZE 8
448 #elif defined CONFIG_DCACHE_LRAM_SZ16
449 #define CFG_DLRAM_SIZE 16
450 #elif defined CONFIG_DCACHE_LRAM_SZ32
451 #define CFG_DLRAM_SIZE 32
452 #elif defined CONFIG_DCACHE_LRAM_SZ64
453 #define CFG_DLRAM_SIZE 64
454 #elif defined CONFIG_DCACHE_LRAM_SZ128
455 #define CFG_DLRAM_SIZE 128
456 #elif defined CONFIG_DCACHE_LRAM_SZ256
457 #define CFG_DLRAM_SIZE 256
458 #else
459 #define CFG_DLRAM_SIZE 1
460 #endif
461
462 #if defined CONFIG_MMU_PAGE_4K
463 #define CONFIG_MMU_PAGE 0
464 #elif defined CONFIG_MMU_PAGE_8K
465 #define CONFIG_MMU_PAGE 1
466 #elif defined CONFIG_MMU_PAGE_16K
467 #define CONFIG_MMU_PAGE 2
468 #elif defined CONFIG_MMU_PAGE_32K
469 #define CONFIG_MMU_PAGE 3
470 #elif defined CONFIG_MMU_PAGE_PROG
471 #define CONFIG_MMU_PAGE 4
472 #else
473 #define CONFIG_MMU_PAGE 0
474 #endif
475
476 #ifdef CONFIG_MMU_ENABLE
477 #define CONFIG_MMUEN 1
478
479 #ifdef CONFIG_MMU_SPLIT
480 #define CONFIG_TLB_TYPE 0
481 #endif
482 #ifdef CONFIG_MMU_COMBINED
483 #define CONFIG_TLB_TYPE 1
484 #endif
485
486 #ifdef CONFIG_MMU_REPARRAY
487 #define CONFIG_TLB_REP 0
488 #endif
489 #ifdef CONFIG_MMU_REPINCREMENT
490 #define CONFIG_TLB_REP 1
491 #endif
492
493 #ifdef CONFIG_MMU_I2
494 #define CONFIG_ITLBNUM 2
495 #endif
496 #ifdef CONFIG_MMU_I4
497 #define CONFIG_ITLBNUM 4
498 #endif
499 #ifdef CONFIG_MMU_I8
500 #define CONFIG_ITLBNUM 8
501 #endif
502 #ifdef CONFIG_MMU_I16
503 #define CONFIG_ITLBNUM 16
504 #endif
505 #ifdef CONFIG_MMU_I32
506 #define CONFIG_ITLBNUM 32
507 #endif
508
509 #define CONFIG_DTLBNUM 2
510 #ifdef CONFIG_MMU_D2
511 #undef CONFIG_DTLBNUM
512 #define CONFIG_DTLBNUM 2
513 #endif
514 #ifdef CONFIG_MMU_D4
515 #undef CONFIG_DTLBNUM
516 #define CONFIG_DTLBNUM 4
517 #endif
518 #ifdef CONFIG_MMU_D8
519 #undef CONFIG_DTLBNUM
520 #define CONFIG_DTLBNUM 8
521 #endif
522 #ifdef CONFIG_MMU_D16
523 #undef CONFIG_DTLBNUM
524 #define CONFIG_DTLBNUM 16
525 #endif
526 #ifdef CONFIG_MMU_D32
527 #undef CONFIG_DTLBNUM
528 #define CONFIG_DTLBNUM 32
529 #endif
530 #ifdef CONFIG_MMU_FASTWB
531 #define CFG_MMU_FASTWB 1
532 #else
533 #define CFG_MMU_FASTWB 0
534 #endif
535
536 #else
537 #define CONFIG_MMUEN 0
538 #define CONFIG_ITLBNUM 2
539 #define CONFIG_DTLBNUM 2
540 #define CONFIG_TLB_TYPE 1
541 #define CONFIG_TLB_REP 1
542 #define CFG_MMU_FASTWB 0
543 #endif
544
545 #ifndef CONFIG_DSU_ENABLE
546 #define CONFIG_DSU_ENABLE 0
547 #endif
548
549 #if defined CONFIG_DSU_ITRACESZ1
550 #define CFG_DSU_ITB 1
551 #elif CONFIG_DSU_ITRACESZ2
552 #define CFG_DSU_ITB 2
553 #elif CONFIG_DSU_ITRACESZ4
554 #define CFG_DSU_ITB 4
555 #elif CONFIG_DSU_ITRACESZ8
556 #define CFG_DSU_ITB 8
557 #elif CONFIG_DSU_ITRACESZ16
558 #define CFG_DSU_ITB 16
559 #else
560 #define CFG_DSU_ITB 0
561 #endif
562
563 #if defined CONFIG_DSU_ATRACESZ1
564 #define CFG_DSU_ATB 1
565 #elif CONFIG_DSU_ATRACESZ2
566 #define CFG_DSU_ATB 2
567 #elif CONFIG_DSU_ATRACESZ4
568 #define CFG_DSU_ATB 4
569 #elif CONFIG_DSU_ATRACESZ8
570 #define CFG_DSU_ATB 8
571 #elif CONFIG_DSU_ATRACESZ16
572 #define CFG_DSU_ATB 16
573 #else
574 #define CFG_DSU_ATB 0
575 #endif
576
577 #ifndef CONFIG_LEON3FT_EN
578 #define CONFIG_LEON3FT_EN 0
579 #endif
580
581 #if defined CONFIG_IUFT_PAR
582 #define CONFIG_IUFT_EN 1
583 #elif defined CONFIG_IUFT_DMR
584 #define CONFIG_IUFT_EN 2
585 #elif defined CONFIG_IUFT_BCH
586 #define CONFIG_IUFT_EN 3
587 #elif defined CONFIG_IUFT_TMR
588 #define CONFIG_IUFT_EN 4
589 #else
590 #define CONFIG_IUFT_EN 0
591 #endif
592 #ifndef CONFIG_RF_ERRINJ
593 #define CONFIG_RF_ERRINJ 0
594 #endif
595
596 #ifndef CONFIG_FPUFT_EN
597 #define CONFIG_FPUFT 0
598 #else
599 #ifdef CONFIG_FPU_GRFPU
600 #define CONFIG_FPUFT 2
601 #else
602 #define CONFIG_FPUFT 1
603 #endif
604 #endif
605
606 #ifndef CONFIG_CACHE_FT_EN
607 #define CONFIG_CACHE_FT_EN 0
608 #endif
609 #ifndef CONFIG_CACHE_ERRINJ
610 #define CONFIG_CACHE_ERRINJ 0
611 #endif
612
613 #ifndef CONFIG_LEON3_NETLIST
614 #define CONFIG_LEON3_NETLIST 0
615 #endif
616
617 #ifdef CONFIG_DEBUG_PC32
618 #define CFG_DEBUG_PC32 0
619 #else
620 #define CFG_DEBUG_PC32 2
621 #endif
622 #ifndef CONFIG_IU_DISAS
623 #define CONFIG_IU_DISAS 0
624 #endif
625 #ifndef CONFIG_IU_DISAS_NET
626 #define CONFIG_IU_DISAS_NET 0
627 #endif
628
629
630 #ifndef CONFIG_AHB_SPLIT
631 #define CONFIG_AHB_SPLIT 0
632 #endif
633
634 #ifndef CONFIG_AHB_RROBIN
635 #define CONFIG_AHB_RROBIN 0
636 #endif
637
638 #ifndef CONFIG_AHB_IOADDR
639 #define CONFIG_AHB_IOADDR FFF
640 #endif
641
642 #ifndef CONFIG_APB_HADDR
643 #define CONFIG_APB_HADDR 800
644 #endif
645
646 #ifndef CONFIG_AHB_MON
647 #define CONFIG_AHB_MON 0
648 #endif
649
650 #ifndef CONFIG_AHB_MONERR
651 #define CONFIG_AHB_MONERR 0
652 #endif
653
654 #ifndef CONFIG_AHB_MONWAR
655 #define CONFIG_AHB_MONWAR 0
656 #endif
657
658 #ifndef CONFIG_AHB_DTRACE
659 #define CONFIG_AHB_DTRACE 0
660 #endif
661
662 #ifndef CONFIG_DSU_UART
663 #define CONFIG_DSU_UART 0
664 #endif
665
666
667 #ifndef CONFIG_DSU_JTAG
668 #define CONFIG_DSU_JTAG 0
669 #endif
670
671 #ifndef CONFIG_DSU_ETH
672 #define CONFIG_DSU_ETH 0
673 #endif
674
675 #ifndef CONFIG_DSU_IPMSB
676 #define CONFIG_DSU_IPMSB C0A8
677 #endif
678
679 #ifndef CONFIG_DSU_IPLSB
680 #define CONFIG_DSU_IPLSB 0033
681 #endif
682
683 #ifndef CONFIG_DSU_ETHMSB
684 #define CONFIG_DSU_ETHMSB 020000
685 #endif
686
687 #ifndef CONFIG_DSU_ETHLSB
688 #define CONFIG_DSU_ETHLSB 000009
689 #endif
690
691 #if defined CONFIG_DSU_ETHSZ1
692 #define CFG_DSU_ETHB 1
693 #elif CONFIG_DSU_ETHSZ2
694 #define CFG_DSU_ETHB 2
695 #elif CONFIG_DSU_ETHSZ4
696 #define CFG_DSU_ETHB 4
697 #elif CONFIG_DSU_ETHSZ8
698 #define CFG_DSU_ETHB 8
699 #elif CONFIG_DSU_ETHSZ16
700 #define CFG_DSU_ETHB 16
701 #elif CONFIG_DSU_ETHSZ32
702 #define CFG_DSU_ETHB 32
703 #else
704 #define CFG_DSU_ETHB 1
705 #endif
706
707 #ifndef CONFIG_DSU_ETH_PROG
708 #define CONFIG_DSU_ETH_PROG 0
709 #endif
710
711 #ifndef CONFIG_MCTRL_LEON2
712 #define CONFIG_MCTRL_LEON2 0
713 #endif
714
715 #ifndef CONFIG_MCTRL_SDRAM
716 #define CONFIG_MCTRL_SDRAM 0
717 #endif
718
719 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
720 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
721 #endif
722
723 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
724 #define CONFIG_MCTRL_SDRAM_INVCLK 0
725 #endif
726
727 #ifndef CONFIG_MCTRL_SDRAM_BUS64
728 #define CONFIG_MCTRL_SDRAM_BUS64 0
729 #endif
730
731 #ifndef CONFIG_MCTRL_8BIT
732 #define CONFIG_MCTRL_8BIT 0
733 #endif
734
735 #ifndef CONFIG_MCTRL_16BIT
736 #define CONFIG_MCTRL_16BIT 0
737 #endif
738
739 #ifndef CONFIG_MCTRL_5CS
740 #define CONFIG_MCTRL_5CS 0
741 #endif
742
743 #ifndef CONFIG_MCTRL_EDAC
744 #define CONFIG_MCTRL_EDAC 0
745 #endif
746
747 #ifndef CONFIG_MCTRL_PAGE
748 #define CONFIG_MCTRL_PAGE 0
749 #endif
750
751 #ifndef CONFIG_MCTRL_PROGPAGE
752 #define CONFIG_MCTRL_PROGPAGE 0
753 #endif
754
755 #ifndef CONFIG_DDRSP
756 #define CONFIG_DDRSP 0
757 #endif
758
759 #ifndef CONFIG_DDRSP_INIT
760 #define CONFIG_DDRSP_INIT 0
761 #endif
762
763 #ifndef CONFIG_DDRSP_FREQ
764 #define CONFIG_DDRSP_FREQ 100
765 #endif
766
767 #ifndef CONFIG_DDRSP_COL
768 #define CONFIG_DDRSP_COL 9
769 #endif
770
771 #ifndef CONFIG_DDRSP_MBYTE
772 #define CONFIG_DDRSP_MBYTE 8
773 #endif
774
775 #ifndef CONFIG_DDRSP_RSKEW
776 #define CONFIG_DDRSP_RSKEW 0
777 #endif
778 #ifndef CONFIG_AHBROM_ENABLE
779 #define CONFIG_AHBROM_ENABLE 0
780 #endif
781
782 #ifndef CONFIG_AHBROM_START
783 #define CONFIG_AHBROM_START 000
784 #endif
785
786 #ifndef CONFIG_AHBROM_PIPE
787 #define CONFIG_AHBROM_PIPE 0
788 #endif
789
790 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
791 #define CONFIG_ROM_START 100
792 #else
793 #define CONFIG_ROM_START 000
794 #endif
795
796
797 #ifndef CONFIG_AHBRAM_ENABLE
798 #define CONFIG_AHBRAM_ENABLE 0
799 #endif
800
801 #ifndef CONFIG_AHBRAM_START
802 #define CONFIG_AHBRAM_START A00
803 #endif
804
805 #if defined CONFIG_AHBRAM_SZ1
806 #define CFG_AHBRAMSZ 1
807 #elif CONFIG_AHBRAM_SZ2
808 #define CFG_AHBRAMSZ 2
809 #elif CONFIG_AHBRAM_SZ4
810 #define CFG_AHBRAMSZ 4
811 #elif CONFIG_AHBRAM_SZ8
812 #define CFG_AHBRAMSZ 8
813 #elif CONFIG_AHBRAM_SZ16
814 #define CFG_AHBRAMSZ 16
815 #elif CONFIG_AHBRAM_SZ32
816 #define CFG_AHBRAMSZ 32
817 #elif CONFIG_AHBRAM_SZ64
818 #define CFG_AHBRAMSZ 64
819 #else
820 #define CFG_AHBRAMSZ 1
821 #endif
822
823 #ifndef CONFIG_GRETH_ENABLE
824 #define CONFIG_GRETH_ENABLE 0
825 #endif
826
827 #ifndef CONFIG_GRETH_GIGA
828 #define CONFIG_GRETH_GIGA 0
829 #endif
830
831 #if defined CONFIG_GRETH_FIFO4
832 #define CFG_GRETH_FIFO 4
833 #elif defined CONFIG_GRETH_FIFO8
834 #define CFG_GRETH_FIFO 8
835 #elif defined CONFIG_GRETH_FIFO16
836 #define CFG_GRETH_FIFO 16
837 #elif defined CONFIG_GRETH_FIFO32
838 #define CFG_GRETH_FIFO 32
839 #elif defined CONFIG_GRETH_FIFO64
840 #define CFG_GRETH_FIFO 64
841 #else
842 #define CFG_GRETH_FIFO 8
843 #endif
844
845 #ifndef CONFIG_UART1_ENABLE
846 #define CONFIG_UART1_ENABLE 0
847 #endif
848
849 #if defined CONFIG_UA1_FIFO1
850 #define CFG_UA1_FIFO 1
851 #elif defined CONFIG_UA1_FIFO2
852 #define CFG_UA1_FIFO 2
853 #elif defined CONFIG_UA1_FIFO4
854 #define CFG_UA1_FIFO 4
855 #elif defined CONFIG_UA1_FIFO8
856 #define CFG_UA1_FIFO 8
857 #elif defined CONFIG_UA1_FIFO16
858 #define CFG_UA1_FIFO 16
859 #elif defined CONFIG_UA1_FIFO32
860 #define CFG_UA1_FIFO 32
861 #else
862 #define CFG_UA1_FIFO 1
863 #endif
864
865 #ifndef CONFIG_IRQ3_ENABLE
866 #define CONFIG_IRQ3_ENABLE 0
867 #endif
868 #ifndef CONFIG_IRQ3_NSEC
869 #define CONFIG_IRQ3_NSEC 0
870 #endif
871 #ifndef CONFIG_GPT_ENABLE
872 #define CONFIG_GPT_ENABLE 0
873 #endif
874
875 #ifndef CONFIG_GPT_NTIM
876 #define CONFIG_GPT_NTIM 1
877 #endif
878
879 #ifndef CONFIG_GPT_SW
880 #define CONFIG_GPT_SW 8
881 #endif
882
883 #ifndef CONFIG_GPT_TW
884 #define CONFIG_GPT_TW 8
885 #endif
886
887 #ifndef CONFIG_GPT_IRQ
888 #define CONFIG_GPT_IRQ 8
889 #endif
890
891 #ifndef CONFIG_GPT_SEPIRQ
892 #define CONFIG_GPT_SEPIRQ 0
893 #endif
894 #ifndef CONFIG_GPT_ENABLE
895 #define CONFIG_GPT_ENABLE 0
896 #endif
897
898 #ifndef CONFIG_GPT_NTIM
899 #define CONFIG_GPT_NTIM 1
900 #endif
901
902 #ifndef CONFIG_GPT_SW
903 #define CONFIG_GPT_SW 8
904 #endif
905
906 #ifndef CONFIG_GPT_TW
907 #define CONFIG_GPT_TW 8
908 #endif
909
910 #ifndef CONFIG_GPT_IRQ
911 #define CONFIG_GPT_IRQ 8
912 #endif
913
914 #ifndef CONFIG_GPT_SEPIRQ
915 #define CONFIG_GPT_SEPIRQ 0
916 #endif
917
918 #ifndef CONFIG_GPT_WDOGEN
919 #define CONFIG_GPT_WDOGEN 0
920 #endif
921
922 #ifndef CONFIG_GPT_WDOG
923 #define CONFIG_GPT_WDOG 0
924 #endif
925
926 #ifndef CONFIG_GRGPIO_ENABLE
927 #define CONFIG_GRGPIO_ENABLE 0
928 #endif
929 #ifndef CONFIG_GRGPIO_IMASK
930 #define CONFIG_GRGPIO_IMASK 0000
931 #endif
932 #ifndef CONFIG_GRGPIO_WIDTH
933 #define CONFIG_GRGPIO_WIDTH 1
934 #endif
935
936 #ifndef CONFIG_VGA_ENABLE
937 #define CONFIG_VGA_ENABLE 0
938 #endif
939 #ifndef CONFIG_SVGA_ENABLE
940 #define CONFIG_SVGA_ENABLE 0
941 #endif
942 #ifndef CONFIG_KBD_ENABLE
943 #define CONFIG_KBD_ENABLE 0
944 #endif
945
946
947 #ifndef CONFIG_DEBUG_UART
948 #define CONFIG_DEBUG_UART 0
949 #endif
1 #if defined CONFIG_SYN_INFERRED
2 #define CONFIG_SYN_TECH inferred
3 #elif defined CONFIG_SYN_UMC
4 #define CONFIG_SYN_TECH umc
5 #elif defined CONFIG_SYN_RHUMC
6 #define CONFIG_SYN_TECH rhumc
7 #elif defined CONFIG_SYN_ATC18
8 #define CONFIG_SYN_TECH atc18s
9 #elif defined CONFIG_SYN_ATC18RHA
10 #define CONFIG_SYN_TECH atc18rha
11 #elif defined CONFIG_SYN_AXCEL
12 #define CONFIG_SYN_TECH axcel
13 #elif defined CONFIG_SYN_AXDSP
14 #define CONFIG_SYN_TECH axdsp
15 #elif defined CONFIG_SYN_PROASICPLUS
16 #define CONFIG_SYN_TECH proasic
17 #elif defined CONFIG_SYN_ALTERA
18 #define CONFIG_SYN_TECH altera
19 #elif defined CONFIG_SYN_STRATIX
20 #define CONFIG_SYN_TECH stratix1
21 #elif defined CONFIG_SYN_STRATIXII
22 #define CONFIG_SYN_TECH stratix2
23 #elif defined CONFIG_SYN_STRATIXIII
24 #define CONFIG_SYN_TECH stratix3
25 #elif defined CONFIG_SYN_CYCLONEIII
26 #define CONFIG_SYN_TECH cyclone3
27 #elif defined CONFIG_SYN_EASIC90
28 #define CONFIG_SYN_TECH easic90
29 #elif defined CONFIG_SYN_IHP25
30 #define CONFIG_SYN_TECH ihp25
31 #elif defined CONFIG_SYN_IHP25RH
32 #define CONFIG_SYN_TECH ihp25rh
33 #elif defined CONFIG_SYN_CMOS9SF
34 #define CONFIG_SYN_TECH cmos9sf
35 #elif defined CONFIG_SYN_LATTICE
36 #define CONFIG_SYN_TECH lattice
37 #elif defined CONFIG_SYN_ECLIPSE
38 #define CONFIG_SYN_TECH eclipse
39 #elif defined CONFIG_SYN_PEREGRINE
40 #define CONFIG_SYN_TECH peregrine
41 #elif defined CONFIG_SYN_PROASIC
42 #define CONFIG_SYN_TECH proasic
43 #elif defined CONFIG_SYN_PROASIC3
44 #define CONFIG_SYN_TECH apa3
45 #elif defined CONFIG_SYN_PROASIC3E
46 #define CONFIG_SYN_TECH apa3e
47 #elif defined CONFIG_SYN_PROASIC3L
48 #define CONFIG_SYN_TECH apa3l
49 #elif defined CONFIG_SYN_IGLOO
50 #define CONFIG_SYN_TECH apa3
51 #elif defined CONFIG_SYN_FUSION
52 #define CONFIG_SYN_TECH actfus
53 #elif defined CONFIG_SYN_SPARTAN2
54 #define CONFIG_SYN_TECH virtex
55 #elif defined CONFIG_SYN_VIRTEX
56 #define CONFIG_SYN_TECH virtex
57 #elif defined CONFIG_SYN_VIRTEXE
58 #define CONFIG_SYN_TECH virtex
59 #elif defined CONFIG_SYN_SPARTAN3
60 #define CONFIG_SYN_TECH spartan3
61 #elif defined CONFIG_SYN_SPARTAN3E
62 #define CONFIG_SYN_TECH spartan3e
63 #elif defined CONFIG_SYN_SPARTAN6
64 #define CONFIG_SYN_TECH spartan6
65 #elif defined CONFIG_SYN_VIRTEX2
66 #define CONFIG_SYN_TECH virtex2
67 #elif defined CONFIG_SYN_VIRTEX4
68 #define CONFIG_SYN_TECH virtex4
69 #elif defined CONFIG_SYN_VIRTEX5
70 #define CONFIG_SYN_TECH virtex5
71 #elif defined CONFIG_SYN_VIRTEX6
72 #define CONFIG_SYN_TECH virtex6
73 #elif defined CONFIG_SYN_RH_LIB18T
74 #define CONFIG_SYN_TECH rhlib18t
75 #elif defined CONFIG_SYN_SMIC13
76 #define CONFIG_SYN_TECH smic013
77 #elif defined CONFIG_SYN_UT025CRH
78 #define CONFIG_SYN_TECH ut25
79 #elif defined CONFIG_SYN_TSMC90
80 #define CONFIG_SYN_TECH tsmc90
81 #elif defined CONFIG_SYN_TM65GPLUS
82 #define CONFIG_SYN_TECH tm65gpl
83 #elif defined CONFIG_SYN_CUSTOM1
84 #define CONFIG_SYN_TECH custom1
85 #else
86 #error "unknown target technology"
87 #endif
88
89 #if defined CONFIG_SYN_INFER_RAM
90 #define CFG_RAM_TECH inferred
91 #elif defined CONFIG_MEM_UMC
92 #define CFG_RAM_TECH umc
93 #elif defined CONFIG_MEM_RHUMC
94 #define CFG_RAM_TECH rhumc
95 #elif defined CONFIG_MEM_VIRAGE
96 #define CFG_RAM_TECH memvirage
97 #elif defined CONFIG_MEM_ARTISAN
98 #define CFG_RAM_TECH memartisan
99 #elif defined CONFIG_MEM_CUSTOM1
100 #define CFG_RAM_TECH custom1
101 #elif defined CONFIG_MEM_VIRAGE90
102 #define CFG_RAM_TECH memvirage90
103 #elif defined CONFIG_MEM_INFERRED
104 #define CFG_RAM_TECH inferred
105 #else
106 #define CFG_RAM_TECH CONFIG_SYN_TECH
107 #endif
108
109 #if defined CONFIG_SYN_INFER_PADS
110 #define CFG_PAD_TECH inferred
111 #else
112 #define CFG_PAD_TECH CONFIG_SYN_TECH
113 #endif
114
115 #ifndef CONFIG_SYN_NO_ASYNC
116 #define CONFIG_SYN_NO_ASYNC 0
117 #endif
118
119 #ifndef CONFIG_SYN_SCAN
120 #define CONFIG_SYN_SCAN 0
121 #endif
122
123
124 #if defined CONFIG_CLK_ALTDLL
125 #define CFG_CLK_TECH CONFIG_SYN_TECH
126 #elif defined CONFIG_CLK_HCLKBUF
127 #define CFG_CLK_TECH axcel
128 #elif defined CONFIG_CLK_LATDLL
129 #define CFG_CLK_TECH lattice
130 #elif defined CONFIG_CLK_PRO3PLL
131 #define CFG_CLK_TECH apa3
132 #elif defined CONFIG_CLK_PRO3EPLL
133 #define CFG_CLK_TECH apa3e
134 #elif defined CONFIG_CLK_PRO3LPLL
135 #define CFG_CLK_TECH apa3l
136 #elif defined CONFIG_CLK_FUSPLL
137 #define CFG_CLK_TECH actfus
138 #elif defined CONFIG_CLK_CLKDLL
139 #define CFG_CLK_TECH virtex
140 #elif defined CONFIG_CLK_DCM
141 #define CFG_CLK_TECH CONFIG_SYN_TECH
142 #elif defined CONFIG_CLK_LIB18T
143 #define CFG_CLK_TECH rhlib18t
144 #elif defined CONFIG_CLK_RHUMC
145 #define CFG_CLK_TECH rhumc
146 #else
147 #define CFG_CLK_TECH inferred
148 #endif
149
150 #ifndef CONFIG_CLK_MUL
151 #define CONFIG_CLK_MUL 2
152 #endif
153
154 #ifndef CONFIG_CLK_DIV
155 #define CONFIG_CLK_DIV 2
156 #endif
157
158 #ifndef CONFIG_OCLK_DIV
159 #define CONFIG_OCLK_DIV 1
160 #endif
161
162 #ifndef CONFIG_OCLKB_DIV
163 #define CONFIG_OCLKB_DIV 0
164 #endif
165
166 #ifndef CONFIG_OCLKC_DIV
167 #define CONFIG_OCLKC_DIV 0
168 #endif
169
170 #ifndef CONFIG_PCI_CLKDLL
171 #define CONFIG_PCI_CLKDLL 0
172 #endif
173
174 #ifndef CONFIG_PCI_SYSCLK
175 #define CONFIG_PCI_SYSCLK 0
176 #endif
177
178 #ifndef CONFIG_CLK_NOFB
179 #define CONFIG_CLK_NOFB 0
180 #endif
181 #ifndef CONFIG_LEON3
182 #define CONFIG_LEON3 0
183 #endif
184
185 #ifndef CONFIG_PROC_NUM
186 #define CONFIG_PROC_NUM 1
187 #endif
188
189 #ifndef CONFIG_IU_NWINDOWS
190 #define CONFIG_IU_NWINDOWS 8
191 #endif
192
193 #ifndef CONFIG_IU_RSTADDR
194 #define CONFIG_IU_RSTADDR 8
195 #endif
196
197 #ifndef CONFIG_IU_LDELAY
198 #define CONFIG_IU_LDELAY 1
199 #endif
200
201 #ifndef CONFIG_IU_WATCHPOINTS
202 #define CONFIG_IU_WATCHPOINTS 0
203 #endif
204
205 #ifdef CONFIG_IU_V8MULDIV
206 #ifdef CONFIG_IU_MUL_LATENCY_4
207 #define CFG_IU_V8 1
208 #elif defined CONFIG_IU_MUL_LATENCY_5
209 #define CFG_IU_V8 2
210 #elif defined CONFIG_IU_MUL_LATENCY_2
211 #define CFG_IU_V8 16#32#
212 #endif
213 #else
214 #define CFG_IU_V8 0
215 #endif
216
217 #ifndef CONFIG_PWD
218 #define CONFIG_PWD 0
219 #endif
220
221 #ifndef CONFIG_IU_MUL_MAC
222 #define CONFIG_IU_MUL_MAC 0
223 #endif
224
225 #ifndef CONFIG_IU_BP
226 #define CONFIG_IU_BP 0
227 #endif
228
229 #ifndef CONFIG_NOTAG
230 #define CONFIG_NOTAG 0
231 #endif
232
233 #ifndef CONFIG_IU_SVT
234 #define CONFIG_IU_SVT 0
235 #endif
236
237 #if defined CONFIG_FPU_GRFPC1
238 #define CONFIG_FPU_GRFPC 1
239 #elif defined CONFIG_FPU_GRFPC2
240 #define CONFIG_FPU_GRFPC 2
241 #else
242 #define CONFIG_FPU_GRFPC 0
243 #endif
244
245 #if defined CONFIG_FPU_GRFPU_INFMUL
246 #define CONFIG_FPU_GRFPU_MUL 0
247 #elif defined CONFIG_FPU_GRFPU_DWMUL
248 #define CONFIG_FPU_GRFPU_MUL 1
249 #elif defined CONFIG_FPU_GRFPU_MODGEN
250 #define CONFIG_FPU_GRFPU_MUL 2
251 #elif defined CONFIG_FPU_GRFPU_TECHSPEC
252 #define CONFIG_FPU_GRFPU_MUL 3
253 #else
254 #define CONFIG_FPU_GRFPU_MUL 0
255 #endif
256
257 #if defined CONFIG_FPU_GRFPU_SH
258 #define CONFIG_FPU_GRFPU_SHARED 1
259 #else
260 #define CONFIG_FPU_GRFPU_SHARED 0
261 #endif
262
263 #if defined CONFIG_FPU_GRFPU
264 #define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
265 #elif defined CONFIG_FPU_MEIKO
266 #define CONFIG_FPU 15
267 #elif defined CONFIG_FPU_GRFPULITE
268 #define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
269 #else
270 #define CONFIG_FPU 0
271 #endif
272
273 #ifndef CONFIG_FPU_NETLIST
274 #define CONFIG_FPU_NETLIST 0
275 #endif
276
277 #ifndef CONFIG_ICACHE_ENABLE
278 #define CONFIG_ICACHE_ENABLE 0
279 #endif
280
281 #if defined CONFIG_ICACHE_ASSO1
282 #define CFG_IU_ISETS 1
283 #elif defined CONFIG_ICACHE_ASSO2
284 #define CFG_IU_ISETS 2
285 #elif defined CONFIG_ICACHE_ASSO3
286 #define CFG_IU_ISETS 3
287 #elif defined CONFIG_ICACHE_ASSO4
288 #define CFG_IU_ISETS 4
289 #else
290 #define CFG_IU_ISETS 1
291 #endif
292
293 #if defined CONFIG_ICACHE_SZ1
294 #define CFG_ICACHE_SZ 1
295 #elif defined CONFIG_ICACHE_SZ2
296 #define CFG_ICACHE_SZ 2
297 #elif defined CONFIG_ICACHE_SZ4
298 #define CFG_ICACHE_SZ 4
299 #elif defined CONFIG_ICACHE_SZ8
300 #define CFG_ICACHE_SZ 8
301 #elif defined CONFIG_ICACHE_SZ16
302 #define CFG_ICACHE_SZ 16
303 #elif defined CONFIG_ICACHE_SZ32
304 #define CFG_ICACHE_SZ 32
305 #elif defined CONFIG_ICACHE_SZ64
306 #define CFG_ICACHE_SZ 64
307 #elif defined CONFIG_ICACHE_SZ128
308 #define CFG_ICACHE_SZ 128
309 #elif defined CONFIG_ICACHE_SZ256
310 #define CFG_ICACHE_SZ 256
311 #else
312 #define CFG_ICACHE_SZ 1
313 #endif
314
315 #ifdef CONFIG_ICACHE_LZ16
316 #define CFG_ILINE_SZ 4
317 #else
318 #define CFG_ILINE_SZ 8
319 #endif
320
321 #if defined CONFIG_ICACHE_ALGORND
322 #define CFG_ICACHE_ALGORND 2
323 #elif defined CONFIG_ICACHE_ALGOLRR
324 #define CFG_ICACHE_ALGORND 1
325 #else
326 #define CFG_ICACHE_ALGORND 0
327 #endif
328
329 #ifndef CONFIG_ICACHE_LOCK
330 #define CONFIG_ICACHE_LOCK 0
331 #endif
332
333 #ifndef CONFIG_ICACHE_LRAM
334 #define CONFIG_ICACHE_LRAM 0
335 #endif
336
337 #ifndef CONFIG_ICACHE_LRSTART
338 #define CONFIG_ICACHE_LRSTART 8E
339 #endif
340
341 #if defined CONFIG_ICACHE_LRAM_SZ2
342 #define CFG_ILRAM_SIZE 2
343 #elif defined CONFIG_ICACHE_LRAM_SZ4
344 #define CFG_ILRAM_SIZE 4
345 #elif defined CONFIG_ICACHE_LRAM_SZ8
346 #define CFG_ILRAM_SIZE 8
347 #elif defined CONFIG_ICACHE_LRAM_SZ16
348 #define CFG_ILRAM_SIZE 16
349 #elif defined CONFIG_ICACHE_LRAM_SZ32
350 #define CFG_ILRAM_SIZE 32
351 #elif defined CONFIG_ICACHE_LRAM_SZ64
352 #define CFG_ILRAM_SIZE 64
353 #elif defined CONFIG_ICACHE_LRAM_SZ128
354 #define CFG_ILRAM_SIZE 128
355 #elif defined CONFIG_ICACHE_LRAM_SZ256
356 #define CFG_ILRAM_SIZE 256
357 #else
358 #define CFG_ILRAM_SIZE 1
359 #endif
360
361
362 #ifndef CONFIG_DCACHE_ENABLE
363 #define CONFIG_DCACHE_ENABLE 0
364 #endif
365
366 #if defined CONFIG_DCACHE_ASSO1
367 #define CFG_IU_DSETS 1
368 #elif defined CONFIG_DCACHE_ASSO2
369 #define CFG_IU_DSETS 2
370 #elif defined CONFIG_DCACHE_ASSO3
371 #define CFG_IU_DSETS 3
372 #elif defined CONFIG_DCACHE_ASSO4
373 #define CFG_IU_DSETS 4
374 #else
375 #define CFG_IU_DSETS 1
376 #endif
377
378 #if defined CONFIG_DCACHE_SZ1
379 #define CFG_DCACHE_SZ 1
380 #elif defined CONFIG_DCACHE_SZ2
381 #define CFG_DCACHE_SZ 2
382 #elif defined CONFIG_DCACHE_SZ4
383 #define CFG_DCACHE_SZ 4
384 #elif defined CONFIG_DCACHE_SZ8
385 #define CFG_DCACHE_SZ 8
386 #elif defined CONFIG_DCACHE_SZ16
387 #define CFG_DCACHE_SZ 16
388 #elif defined CONFIG_DCACHE_SZ32
389 #define CFG_DCACHE_SZ 32
390 #elif defined CONFIG_DCACHE_SZ64
391 #define CFG_DCACHE_SZ 64
392 #elif defined CONFIG_DCACHE_SZ128
393 #define CFG_DCACHE_SZ 128
394 #elif defined CONFIG_DCACHE_SZ256
395 #define CFG_DCACHE_SZ 256
396 #else
397 #define CFG_DCACHE_SZ 1
398 #endif
399
400 #ifdef CONFIG_DCACHE_LZ16
401 #define CFG_DLINE_SZ 4
402 #else
403 #define CFG_DLINE_SZ 8
404 #endif
405
406 #if defined CONFIG_DCACHE_ALGORND
407 #define CFG_DCACHE_ALGORND 2
408 #elif defined CONFIG_DCACHE_ALGOLRR
409 #define CFG_DCACHE_ALGORND 1
410 #else
411 #define CFG_DCACHE_ALGORND 0
412 #endif
413
414 #ifndef CONFIG_DCACHE_LOCK
415 #define CONFIG_DCACHE_LOCK 0
416 #endif
417
418 #ifndef CONFIG_DCACHE_SNOOP
419 #define CONFIG_DCACHE_SNOOP 0
420 #endif
421
422 #ifndef CONFIG_DCACHE_SNOOP_FAST
423 #define CONFIG_DCACHE_SNOOP_FAST 0
424 #endif
425
426 #ifndef CONFIG_DCACHE_SNOOP_SEPTAG
427 #define CONFIG_DCACHE_SNOOP_SEPTAG 0
428 #endif
429
430 #ifndef CONFIG_CACHE_FIXED
431 #define CONFIG_CACHE_FIXED 0
432 #endif
433
434 #ifndef CONFIG_DCACHE_LRAM
435 #define CONFIG_DCACHE_LRAM 0
436 #endif
437
438 #ifndef CONFIG_DCACHE_LRSTART
439 #define CONFIG_DCACHE_LRSTART 8F
440 #endif
441
442 #if defined CONFIG_DCACHE_LRAM_SZ2
443 #define CFG_DLRAM_SIZE 2
444 #elif defined CONFIG_DCACHE_LRAM_SZ4
445 #define CFG_DLRAM_SIZE 4
446 #elif defined CONFIG_DCACHE_LRAM_SZ8
447 #define CFG_DLRAM_SIZE 8
448 #elif defined CONFIG_DCACHE_LRAM_SZ16
449 #define CFG_DLRAM_SIZE 16
450 #elif defined CONFIG_DCACHE_LRAM_SZ32
451 #define CFG_DLRAM_SIZE 32
452 #elif defined CONFIG_DCACHE_LRAM_SZ64
453 #define CFG_DLRAM_SIZE 64
454 #elif defined CONFIG_DCACHE_LRAM_SZ128
455 #define CFG_DLRAM_SIZE 128
456 #elif defined CONFIG_DCACHE_LRAM_SZ256
457 #define CFG_DLRAM_SIZE 256
458 #else
459 #define CFG_DLRAM_SIZE 1
460 #endif
461
462 #if defined CONFIG_MMU_PAGE_4K
463 #define CONFIG_MMU_PAGE 0
464 #elif defined CONFIG_MMU_PAGE_8K
465 #define CONFIG_MMU_PAGE 1
466 #elif defined CONFIG_MMU_PAGE_16K
467 #define CONFIG_MMU_PAGE 2
468 #elif defined CONFIG_MMU_PAGE_32K
469 #define CONFIG_MMU_PAGE 3
470 #elif defined CONFIG_MMU_PAGE_PROG
471 #define CONFIG_MMU_PAGE 4
472 #else
473 #define CONFIG_MMU_PAGE 0
474 #endif
475
476 #ifdef CONFIG_MMU_ENABLE
477 #define CONFIG_MMUEN 1
478
479 #ifdef CONFIG_MMU_SPLIT
480 #define CONFIG_TLB_TYPE 0
481 #endif
482 #ifdef CONFIG_MMU_COMBINED
483 #define CONFIG_TLB_TYPE 1
484 #endif
485
486 #ifdef CONFIG_MMU_REPARRAY
487 #define CONFIG_TLB_REP 0
488 #endif
489 #ifdef CONFIG_MMU_REPINCREMENT
490 #define CONFIG_TLB_REP 1
491 #endif
492
493 #ifdef CONFIG_MMU_I2
494 #define CONFIG_ITLBNUM 2
495 #endif
496 #ifdef CONFIG_MMU_I4
497 #define CONFIG_ITLBNUM 4
498 #endif
499 #ifdef CONFIG_MMU_I8
500 #define CONFIG_ITLBNUM 8
501 #endif
502 #ifdef CONFIG_MMU_I16
503 #define CONFIG_ITLBNUM 16
504 #endif
505 #ifdef CONFIG_MMU_I32
506 #define CONFIG_ITLBNUM 32
507 #endif
508
509 #define CONFIG_DTLBNUM 2
510 #ifdef CONFIG_MMU_D2
511 #undef CONFIG_DTLBNUM
512 #define CONFIG_DTLBNUM 2
513 #endif
514 #ifdef CONFIG_MMU_D4
515 #undef CONFIG_DTLBNUM
516 #define CONFIG_DTLBNUM 4
517 #endif
518 #ifdef CONFIG_MMU_D8
519 #undef CONFIG_DTLBNUM
520 #define CONFIG_DTLBNUM 8
521 #endif
522 #ifdef CONFIG_MMU_D16
523 #undef CONFIG_DTLBNUM
524 #define CONFIG_DTLBNUM 16
525 #endif
526 #ifdef CONFIG_MMU_D32
527 #undef CONFIG_DTLBNUM
528 #define CONFIG_DTLBNUM 32
529 #endif
530 #ifdef CONFIG_MMU_FASTWB
531 #define CFG_MMU_FASTWB 1
532 #else
533 #define CFG_MMU_FASTWB 0
534 #endif
535
536 #else
537 #define CONFIG_MMUEN 0
538 #define CONFIG_ITLBNUM 2
539 #define CONFIG_DTLBNUM 2
540 #define CONFIG_TLB_TYPE 1
541 #define CONFIG_TLB_REP 1
542 #define CFG_MMU_FASTWB 0
543 #endif
544
545 #ifndef CONFIG_DSU_ENABLE
546 #define CONFIG_DSU_ENABLE 0
547 #endif
548
549 #if defined CONFIG_DSU_ITRACESZ1
550 #define CFG_DSU_ITB 1
551 #elif CONFIG_DSU_ITRACESZ2
552 #define CFG_DSU_ITB 2
553 #elif CONFIG_DSU_ITRACESZ4
554 #define CFG_DSU_ITB 4
555 #elif CONFIG_DSU_ITRACESZ8
556 #define CFG_DSU_ITB 8
557 #elif CONFIG_DSU_ITRACESZ16
558 #define CFG_DSU_ITB 16
559 #else
560 #define CFG_DSU_ITB 0
561 #endif
562
563 #if defined CONFIG_DSU_ATRACESZ1
564 #define CFG_DSU_ATB 1
565 #elif CONFIG_DSU_ATRACESZ2
566 #define CFG_DSU_ATB 2
567 #elif CONFIG_DSU_ATRACESZ4
568 #define CFG_DSU_ATB 4
569 #elif CONFIG_DSU_ATRACESZ8
570 #define CFG_DSU_ATB 8
571 #elif CONFIG_DSU_ATRACESZ16
572 #define CFG_DSU_ATB 16
573 #else
574 #define CFG_DSU_ATB 0
575 #endif
576
577 #ifndef CONFIG_LEON3FT_EN
578 #define CONFIG_LEON3FT_EN 0
579 #endif
580
581 #if defined CONFIG_IUFT_PAR
582 #define CONFIG_IUFT_EN 1
583 #elif defined CONFIG_IUFT_DMR
584 #define CONFIG_IUFT_EN 2
585 #elif defined CONFIG_IUFT_BCH
586 #define CONFIG_IUFT_EN 3
587 #elif defined CONFIG_IUFT_TMR
588 #define CONFIG_IUFT_EN 4
589 #else
590 #define CONFIG_IUFT_EN 0
591 #endif
592 #ifndef CONFIG_RF_ERRINJ
593 #define CONFIG_RF_ERRINJ 0
594 #endif
595
596 #ifndef CONFIG_FPUFT_EN
597 #define CONFIG_FPUFT 0
598 #else
599 #ifdef CONFIG_FPU_GRFPU
600 #define CONFIG_FPUFT 2
601 #else
602 #define CONFIG_FPUFT 1
603 #endif
604 #endif
605
606 #ifndef CONFIG_CACHE_FT_EN
607 #define CONFIG_CACHE_FT_EN 0
608 #endif
609 #ifndef CONFIG_CACHE_ERRINJ
610 #define CONFIG_CACHE_ERRINJ 0
611 #endif
612
613 #ifndef CONFIG_LEON3_NETLIST
614 #define CONFIG_LEON3_NETLIST 0
615 #endif
616
617 #ifdef CONFIG_DEBUG_PC32
618 #define CFG_DEBUG_PC32 0
619 #else
620 #define CFG_DEBUG_PC32 2
621 #endif
622 #ifndef CONFIG_IU_DISAS
623 #define CONFIG_IU_DISAS 0
624 #endif
625 #ifndef CONFIG_IU_DISAS_NET
626 #define CONFIG_IU_DISAS_NET 0
627 #endif
628
629
630 #ifndef CONFIG_AHB_SPLIT
631 #define CONFIG_AHB_SPLIT 0
632 #endif
633
634 #ifndef CONFIG_AHB_RROBIN
635 #define CONFIG_AHB_RROBIN 0
636 #endif
637
638 #ifndef CONFIG_AHB_IOADDR
639 #define CONFIG_AHB_IOADDR FFF
640 #endif
641
642 #ifndef CONFIG_APB_HADDR
643 #define CONFIG_APB_HADDR 800
644 #endif
645
646 #ifndef CONFIG_AHB_MON
647 #define CONFIG_AHB_MON 0
648 #endif
649
650 #ifndef CONFIG_AHB_MONERR
651 #define CONFIG_AHB_MONERR 0
652 #endif
653
654 #ifndef CONFIG_AHB_MONWAR
655 #define CONFIG_AHB_MONWAR 0
656 #endif
657
658 #ifndef CONFIG_AHB_DTRACE
659 #define CONFIG_AHB_DTRACE 0
660 #endif
661
662 #ifndef CONFIG_DSU_UART
663 #define CONFIG_DSU_UART 0
664 #endif
665
666
667 #ifndef CONFIG_DSU_JTAG
668 #define CONFIG_DSU_JTAG 0
669 #endif
670
671 #ifndef CONFIG_DSU_ETH
672 #define CONFIG_DSU_ETH 0
673 #endif
674
675 #ifndef CONFIG_DSU_IPMSB
676 #define CONFIG_DSU_IPMSB C0A8
677 #endif
678
679 #ifndef CONFIG_DSU_IPLSB
680 #define CONFIG_DSU_IPLSB 0033
681 #endif
682
683 #ifndef CONFIG_DSU_ETHMSB
684 #define CONFIG_DSU_ETHMSB 020000
685 #endif
686
687 #ifndef CONFIG_DSU_ETHLSB
688 #define CONFIG_DSU_ETHLSB 000009
689 #endif
690
691 #if defined CONFIG_DSU_ETHSZ1
692 #define CFG_DSU_ETHB 1
693 #elif CONFIG_DSU_ETHSZ2
694 #define CFG_DSU_ETHB 2
695 #elif CONFIG_DSU_ETHSZ4
696 #define CFG_DSU_ETHB 4
697 #elif CONFIG_DSU_ETHSZ8
698 #define CFG_DSU_ETHB 8
699 #elif CONFIG_DSU_ETHSZ16
700 #define CFG_DSU_ETHB 16
701 #elif CONFIG_DSU_ETHSZ32
702 #define CFG_DSU_ETHB 32
703 #else
704 #define CFG_DSU_ETHB 1
705 #endif
706
707 #ifndef CONFIG_DSU_ETH_PROG
708 #define CONFIG_DSU_ETH_PROG 0
709 #endif
710
711 #ifndef CONFIG_MCTRL_LEON2
712 #define CONFIG_MCTRL_LEON2 0
713 #endif
714
715 #ifndef CONFIG_MCTRL_SDRAM
716 #define CONFIG_MCTRL_SDRAM 0
717 #endif
718
719 #ifndef CONFIG_MCTRL_SDRAM_SEPBUS
720 #define CONFIG_MCTRL_SDRAM_SEPBUS 0
721 #endif
722
723 #ifndef CONFIG_MCTRL_SDRAM_INVCLK
724 #define CONFIG_MCTRL_SDRAM_INVCLK 0
725 #endif
726
727 #ifndef CONFIG_MCTRL_SDRAM_BUS64
728 #define CONFIG_MCTRL_SDRAM_BUS64 0
729 #endif
730
731 #ifndef CONFIG_MCTRL_8BIT
732 #define CONFIG_MCTRL_8BIT 0
733 #endif
734
735 #ifndef CONFIG_MCTRL_16BIT
736 #define CONFIG_MCTRL_16BIT 0
737 #endif
738
739 #ifndef CONFIG_MCTRL_5CS
740 #define CONFIG_MCTRL_5CS 0
741 #endif
742
743 #ifndef CONFIG_MCTRL_EDAC
744 #define CONFIG_MCTRL_EDAC 0
745 #endif
746
747 #ifndef CONFIG_MCTRL_PAGE
748 #define CONFIG_MCTRL_PAGE 0
749 #endif
750
751 #ifndef CONFIG_MCTRL_PROGPAGE
752 #define CONFIG_MCTRL_PROGPAGE 0
753 #endif
754
755 #ifndef CONFIG_DDRSP
756 #define CONFIG_DDRSP 0
757 #endif
758
759 #ifndef CONFIG_DDRSP_INIT
760 #define CONFIG_DDRSP_INIT 0
761 #endif
762
763 #ifndef CONFIG_DDRSP_FREQ
764 #define CONFIG_DDRSP_FREQ 100
765 #endif
766
767 #ifndef CONFIG_DDRSP_COL
768 #define CONFIG_DDRSP_COL 9
769 #endif
770
771 #ifndef CONFIG_DDRSP_MBYTE
772 #define CONFIG_DDRSP_MBYTE 8
773 #endif
774
775 #ifndef CONFIG_DDRSP_RSKEW
776 #define CONFIG_DDRSP_RSKEW 0
777 #endif
778 #ifndef CONFIG_AHBROM_ENABLE
779 #define CONFIG_AHBROM_ENABLE 0
780 #endif
781
782 #ifndef CONFIG_AHBROM_START
783 #define CONFIG_AHBROM_START 000
784 #endif
785
786 #ifndef CONFIG_AHBROM_PIPE
787 #define CONFIG_AHBROM_PIPE 0
788 #endif
789
790 #if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
791 #define CONFIG_ROM_START 100
792 #else
793 #define CONFIG_ROM_START 000
794 #endif
795
796
797 #ifndef CONFIG_AHBRAM_ENABLE
798 #define CONFIG_AHBRAM_ENABLE 0
799 #endif
800
801 #ifndef CONFIG_AHBRAM_START
802 #define CONFIG_AHBRAM_START A00
803 #endif
804
805 #if defined CONFIG_AHBRAM_SZ1
806 #define CFG_AHBRAMSZ 1
807 #elif CONFIG_AHBRAM_SZ2
808 #define CFG_AHBRAMSZ 2
809 #elif CONFIG_AHBRAM_SZ4
810 #define CFG_AHBRAMSZ 4
811 #elif CONFIG_AHBRAM_SZ8
812 #define CFG_AHBRAMSZ 8
813 #elif CONFIG_AHBRAM_SZ16
814 #define CFG_AHBRAMSZ 16
815 #elif CONFIG_AHBRAM_SZ32
816 #define CFG_AHBRAMSZ 32
817 #elif CONFIG_AHBRAM_SZ64
818 #define CFG_AHBRAMSZ 64
819 #else
820 #define CFG_AHBRAMSZ 1
821 #endif
822
823 #ifndef CONFIG_GRETH_ENABLE
824 #define CONFIG_GRETH_ENABLE 0
825 #endif
826
827 #ifndef CONFIG_GRETH_GIGA
828 #define CONFIG_GRETH_GIGA 0
829 #endif
830
831 #if defined CONFIG_GRETH_FIFO4
832 #define CFG_GRETH_FIFO 4
833 #elif defined CONFIG_GRETH_FIFO8
834 #define CFG_GRETH_FIFO 8
835 #elif defined CONFIG_GRETH_FIFO16
836 #define CFG_GRETH_FIFO 16
837 #elif defined CONFIG_GRETH_FIFO32
838 #define CFG_GRETH_FIFO 32
839 #elif defined CONFIG_GRETH_FIFO64
840 #define CFG_GRETH_FIFO 64
841 #else
842 #define CFG_GRETH_FIFO 8
843 #endif
844
845 #ifndef CONFIG_UART1_ENABLE
846 #define CONFIG_UART1_ENABLE 0
847 #endif
848
849 #if defined CONFIG_UA1_FIFO1
850 #define CFG_UA1_FIFO 1
851 #elif defined CONFIG_UA1_FIFO2
852 #define CFG_UA1_FIFO 2
853 #elif defined CONFIG_UA1_FIFO4
854 #define CFG_UA1_FIFO 4
855 #elif defined CONFIG_UA1_FIFO8
856 #define CFG_UA1_FIFO 8
857 #elif defined CONFIG_UA1_FIFO16
858 #define CFG_UA1_FIFO 16
859 #elif defined CONFIG_UA1_FIFO32
860 #define CFG_UA1_FIFO 32
861 #else
862 #define CFG_UA1_FIFO 1
863 #endif
864
865 #ifndef CONFIG_IRQ3_ENABLE
866 #define CONFIG_IRQ3_ENABLE 0
867 #endif
868 #ifndef CONFIG_IRQ3_NSEC
869 #define CONFIG_IRQ3_NSEC 0
870 #endif
871 #ifndef CONFIG_GPT_ENABLE
872 #define CONFIG_GPT_ENABLE 0
873 #endif
874
875 #ifndef CONFIG_GPT_NTIM
876 #define CONFIG_GPT_NTIM 1
877 #endif
878
879 #ifndef CONFIG_GPT_SW
880 #define CONFIG_GPT_SW 8
881 #endif
882
883 #ifndef CONFIG_GPT_TW
884 #define CONFIG_GPT_TW 8
885 #endif
886
887 #ifndef CONFIG_GPT_IRQ
888 #define CONFIG_GPT_IRQ 8
889 #endif
890
891 #ifndef CONFIG_GPT_SEPIRQ
892 #define CONFIG_GPT_SEPIRQ 0
893 #endif
894 #ifndef CONFIG_GPT_ENABLE
895 #define CONFIG_GPT_ENABLE 0
896 #endif
897
898 #ifndef CONFIG_GPT_NTIM
899 #define CONFIG_GPT_NTIM 1
900 #endif
901
902 #ifndef CONFIG_GPT_SW
903 #define CONFIG_GPT_SW 8
904 #endif
905
906 #ifndef CONFIG_GPT_TW
907 #define CONFIG_GPT_TW 8
908 #endif
909
910 #ifndef CONFIG_GPT_IRQ
911 #define CONFIG_GPT_IRQ 8
912 #endif
913
914 #ifndef CONFIG_GPT_SEPIRQ
915 #define CONFIG_GPT_SEPIRQ 0
916 #endif
917
918 #ifndef CONFIG_GPT_WDOGEN
919 #define CONFIG_GPT_WDOGEN 0
920 #endif
921
922 #ifndef CONFIG_GPT_WDOG
923 #define CONFIG_GPT_WDOG 0
924 #endif
925
926 #ifndef CONFIG_GRGPIO_ENABLE
927 #define CONFIG_GRGPIO_ENABLE 0
928 #endif
929 #ifndef CONFIG_GRGPIO_IMASK
930 #define CONFIG_GRGPIO_IMASK 0000
931 #endif
932 #ifndef CONFIG_GRGPIO_WIDTH
933 #define CONFIG_GRGPIO_WIDTH 1
934 #endif
935
936 #ifndef CONFIG_VGA_ENABLE
937 #define CONFIG_VGA_ENABLE 0
938 #endif
939 #ifndef CONFIG_SVGA_ENABLE
940 #define CONFIG_SVGA_ENABLE 0
941 #endif
942 #ifndef CONFIG_KBD_ENABLE
943 #define CONFIG_KBD_ENABLE 0
944 #endif
945
946
947 #ifndef CONFIG_DEBUG_UART
948 #define CONFIG_DEBUG_UART 0
949 #endif
Show file before | Show file after | Hide comments
@@ -1,56 +1,56
1 <?xml version="1.0" encoding="UTF-8" ?>
2 <document>
3 <!--The data in this file is primarily intended for consumption by Xilinx tools.
4 The structure and the elements are likely to change over the next few releases.
5 This means code written to parse this file will need to be revisited each subsequent release.-->
6 <application name="pn" timeStamp="Wed Dec 8 09:10:18 2010">
7 <section name="Project Information" visible="false">
8 <property name="ProjectID" value="314B616C181AFB6097A4EDCB224EA28B" type="project"/>
9 <property name="ProjectIteration" value="11" type="project"/>
10 <property name="ProjectFile" value="/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.xise" type="project"/>
11 <property name="ProjectCreationTimestamp" value="2010-12-02T08:01:13" type="project"/>
12 </section>
13 <section name="Project Statistics" visible="true">
14 <property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
15 <property name="PROP_FitterReportFormat" value="HTML" type="process"/>
16 <property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
17 <property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
18 <property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
19 <property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
20 <property name="PROP_SelectedInstanceHierarchicalPath" value="/APB_IIR_CEL/filter" type="process"/>
21 <property name="PROP_Simulator" value="Modelsim-SE Mixed" type="design"/>
22 <property name="PROP_SynthFsmEncode" value="None" type="process"/>
23 <property name="PROP_SynthTopFile" value="changed" type="process"/>
24 <property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
25 <property name="PROP_UseSmartGuide" value="false" type="design"/>
26 <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
27 <property name="PROP_intProjectCreationTimestamp" value="2010-12-02T08:01:13" type="design"/>
28 <property name="PROP_intWbtProjectID" value="314B616C181AFB6097A4EDCB224EA28B" type="design"/>
29 <property name="PROP_intWbtProjectIteration" value="11" type="process"/>
30 <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
31 <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
32 <property name="PROP_map_otherCmdLineOptions" value="-timing" type="process"/>
33 <property name="PROP_selectedSimRootSourceNode_behav" value="lpp.IIR_CEL_FILTER" type="process"/>
34 <property name="PROP_xilxBitgCfg_GenOpt_DRC" value="false" type="process"/>
35 <property name="PROP_xilxBitgCfg_GenOpt_ReadBack" value="true" type="process"/>
36 <property name="PROP_xilxBitgStart_Clk_DriveDone" value="true" type="process"/>
37 <property name="PROP_xilxMapPackRegInto" value="For Inputs and Outputs" type="process"/>
38 <property name="PROP_xilxNgdbldMacro" value="changed" type="process"/>
39 <property name="PROP_xilxNgdbld_AUL" value="true" type="process"/>
40 <property name="PROP_xstBusDelimiter" value="()" type="process"/>
41 <property name="PROP_xstPackIORegister" value="Yes" type="process"/>
42 <property name="PROP_xst_otherCmdLineOptions" value="-uc leon3mp.xcf" type="process"/>
43 <property name="PROP_AutoTop" value="false" type="design"/>
44 <property name="PROP_DevFamily" value="Spartan3E" type="design"/>
45 <property name="PROP_xilxBitgCfg_GenOpt_MaskFile" value="true" type="process"/>
46 <property name="PROP_DevDevice" value="xc3s1600e" type="design"/>
47 <property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
48 <property name="PROP_DevPackage" value="fg320" type="design"/>
49 <property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
50 <property name="PROP_DevSpeed" value="-4" type="design"/>
51 <property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
52 <property name="FILE_UCF" value="1" type="source"/>
53 <property name="FILE_VHDL" value="302" type="source"/>
54 </section>
55 </application>
56 </document>
1 <?xml version="1.0" encoding="UTF-8" ?>
2 <document>
3 <!--The data in this file is primarily intended for consumption by Xilinx tools.
4 The structure and the elements are likely to change over the next few releases.
5 This means code written to parse this file will need to be revisited each subsequent release.-->
6 <application name="pn" timeStamp="Wed Dec 8 09:10:18 2010">
7 <section name="Project Information" visible="false">
8 <property name="ProjectID" value="314B616C181AFB6097A4EDCB224EA28B" type="project"/>
9 <property name="ProjectIteration" value="11" type="project"/>
10 <property name="ProjectFile" value="/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.xise" type="project"/>
11 <property name="ProjectCreationTimestamp" value="2010-12-02T08:01:13" type="project"/>
12 </section>
13 <section name="Project Statistics" visible="true">
14 <property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
15 <property name="PROP_FitterReportFormat" value="HTML" type="process"/>
16 <property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
17 <property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
18 <property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
19 <property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
20 <property name="PROP_SelectedInstanceHierarchicalPath" value="/APB_IIR_CEL/filter" type="process"/>
21 <property name="PROP_Simulator" value="Modelsim-SE Mixed" type="design"/>
22 <property name="PROP_SynthFsmEncode" value="None" type="process"/>
23 <property name="PROP_SynthTopFile" value="changed" type="process"/>
24 <property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
25 <property name="PROP_UseSmartGuide" value="false" type="design"/>
26 <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
27 <property name="PROP_intProjectCreationTimestamp" value="2010-12-02T08:01:13" type="design"/>
28 <property name="PROP_intWbtProjectID" value="314B616C181AFB6097A4EDCB224EA28B" type="design"/>
29 <property name="PROP_intWbtProjectIteration" value="11" type="process"/>
30 <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
31 <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
32 <property name="PROP_map_otherCmdLineOptions" value="-timing" type="process"/>
33 <property name="PROP_selectedSimRootSourceNode_behav" value="lpp.IIR_CEL_FILTER" type="process"/>
34 <property name="PROP_xilxBitgCfg_GenOpt_DRC" value="false" type="process"/>
35 <property name="PROP_xilxBitgCfg_GenOpt_ReadBack" value="true" type="process"/>
36 <property name="PROP_xilxBitgStart_Clk_DriveDone" value="true" type="process"/>
37 <property name="PROP_xilxMapPackRegInto" value="For Inputs and Outputs" type="process"/>
38 <property name="PROP_xilxNgdbldMacro" value="changed" type="process"/>
39 <property name="PROP_xilxNgdbld_AUL" value="true" type="process"/>
40 <property name="PROP_xstBusDelimiter" value="()" type="process"/>
41 <property name="PROP_xstPackIORegister" value="Yes" type="process"/>
42 <property name="PROP_xst_otherCmdLineOptions" value="-uc leon3mp.xcf" type="process"/>
43 <property name="PROP_AutoTop" value="false" type="design"/>
44 <property name="PROP_DevFamily" value="Spartan3E" type="design"/>
45 <property name="PROP_xilxBitgCfg_GenOpt_MaskFile" value="true" type="process"/>
46 <property name="PROP_DevDevice" value="xc3s1600e" type="design"/>
47 <property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
48 <property name="PROP_DevPackage" value="fg320" type="design"/>
49 <property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
50 <property name="PROP_DevSpeed" value="-4" type="design"/>
51 <property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
52 <property name="FILE_UCF" value="1" type="source"/>
53 <property name="FILE_VHDL" value="302" type="source"/>
54 </section>
55 </application>
56 </document>
Show file before | Show file after | Hide comments
@@ -71,6 +71,7 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_
71 71 virg_pos : IN INTEGER;
72 72 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
73 73 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
74 init_mem_done : out STD_LOGIC;
74 75 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
75 76 ram_write : IN STD_LOGIC;
76 77 ram_read : IN STD_LOGIC;
@@ -97,6 +98,7 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_
97 98 sample_in_rot : OUT STD_LOGIC;
98 99 sample_out_val : OUT STD_LOGIC;
99 100 sample_out_rot : OUT STD_LOGIC;
101 init_mem_done : in STD_LOGIC; --TODO
100 102 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 103 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 104 ram_write : OUT STD_LOGIC;
@@ -130,6 +132,8 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_
130 132
131 133 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
132 134
135 signal init_mem_done : std_logic;
136
133 137 BEGIN
134 138
135 139 IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
@@ -147,6 +151,7 BEGIN
147 151 coefs => coefs,
148 152 --CTRL
149 153 in_sel_src => in_sel_src,
154 init_mem_done => init_mem_done, --TODO
150 155 ram_sel_Wdata => ram_sel_Wdata,
151 156 ram_write => ram_write,
152 157 ram_read => ram_read,
@@ -174,6 +179,8 BEGIN
174 179 sample_in_rot => sample_in_rotate,
175 180 sample_out_val => sample_out_val_s,
176 181 sample_out_rot => sample_out_rot_s,
182
183 init_mem_done => init_mem_done, --TODO
177 184
178 185 in_sel_src => in_sel_src,
179 186 ram_sel_Wdata => ram_sel_Wdata,
Show file before | Show file after | Hide comments
@@ -41,6 +41,8 ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
41 41 sample_out_val : OUT STD_LOGIC;
42 42 sample_out_rot : OUT STD_LOGIC;
43 43
44 init_mem_done : in STD_LOGIC; --TODO
45
44 46 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
45 47 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
46 48 ram_write : OUT STD_LOGIC;
@@ -117,7 +119,7 BEGIN
117 119 ram_sel_Wdata <= "00";
118 120 ram_write <= '0';
119 121 waddr_previous <= "00";
120 IF sample_in_val = '1' THEN
122 IF sample_in_val = '1' and init_mem_done = '1' THEN
121 123 raddr_rst <= '0';
122 124 alu_sel_input <= '1';
123 125 ram_read <= '1';
@@ -312,4 +314,4 BEGIN
312 314 END IF;
313 315 END PROCESS;
314 316
315 END ar_IIR_CEL_CTRLR_v2_CONTROL; No newline at end of file
317 END ar_IIR_CEL_CTRLR_v2_CONTROL;
Show file before | Show file after | Hide comments
@@ -46,6 +46,7 ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
46 46 -- CONTROL
47 47 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 48 --
49 init_mem_done : out STD_LOGIC;
49 50 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 51 ram_write : IN STD_LOGIC;
51 52 ram_read : IN STD_LOGIC;
@@ -73,6 +74,7 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLO
73 74 PORT (
74 75 rstn : IN STD_LOGIC;
75 76 clk : IN STD_LOGIC;
77 init_mem_done : out STD_LOGIC;
76 78 ram_write : IN STD_LOGIC;
77 79 ram_read : IN STD_LOGIC;
78 80 raddr_rst : IN STD_LOGIC;
@@ -131,6 +133,7 BEGIN
131 133 PORT MAP (
132 134 clk => clk,
133 135 rstn => rstn,
136 init_mem_done => init_mem_done,
134 137 ram_write => ram_write,
135 138 ram_read => ram_read,
136 139 raddr_rst => raddr_rst,
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@@ -69,6 +69,7 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_
69 69 PORT (
70 70 rstn : IN STD_LOGIC;
71 71 clk : IN STD_LOGIC;
72 init_mem_done : out STD_LOGIC;
72 73 ram_write : IN STD_LOGIC;
73 74 ram_read : IN STD_LOGIC;
74 75 raddr_rst : IN STD_LOGIC;
@@ -113,6 +114,9 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_
113 114 sample_in_rot : OUT STD_LOGIC;
114 115 sample_out_val : OUT STD_LOGIC;
115 116 sample_out_rot : OUT STD_LOGIC;
117
118 init_mem_done : in STD_LOGIC; --TODO
119
116 120 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
117 121 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
118 122 ram_write : OUT STD_LOGIC;
@@ -182,12 +186,14 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_
182 186 SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
183 187
184 188 --SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
185
189 signal init_mem_done : std_logic;
190 signal init_mem_done_1 : std_logic;
191 signal init_mem_done_2 : std_logic;
186 192 BEGIN
187 193
188 194 -----------------------------------------------------------------------------
189 channel_val(0) <= sample_in1_val;
190 channel_val(1) <= sample_in2_val;
195 channel_val(0) <= sample_in1_val when init_mem_done = '1' else '0';
196 channel_val(1) <= sample_in2_val when init_mem_done = '1' else '0';
191 197 all_channel_input_valid : FOR I IN 1 DOWNTO 0 GENERATE
192 198 PROCESS (clk, rstn)
193 199 BEGIN -- PROCESS
@@ -285,6 +291,8 BEGIN
285 291 raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';
286 292 waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";
287 293
294 init_mem_done <= init_mem_done_1 and init_mem_done_2;
295
288 296 RAM_CTRLR_v2_1 : RAM_CTRLR_v2
289 297 GENERIC MAP (
290 298 tech => tech,
@@ -293,6 +301,7 BEGIN
293 301 PORT MAP (
294 302 clk => clk,
295 303 rstn => rstn,
304 init_mem_done => init_mem_done_1,
296 305 ram_write => ram_write_1,
297 306 ram_read => ram_read_1,
298 307 raddr_rst => raddr_rst_1,
@@ -309,6 +318,7 BEGIN
309 318 PORT MAP (
310 319 clk => clk,
311 320 rstn => rstn,
321 init_mem_done => init_mem_done_2,
312 322 ram_write => ram_write_2,
313 323 ram_read => ram_read_2,
314 324 raddr_rst => raddr_rst_2,
@@ -359,6 +369,8 BEGIN
359 369 sample_out_val => sample_out_val_s,
360 370 sample_out_rot => sample_out_rot_s,
361 371
372 init_mem_done => init_mem_done,
373
362 374 in_sel_src => in_sel_src,
363 375 ram_sel_Wdata => ram_sel_Wdata,
364 376 ram_write => ram_write,
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@@ -38,6 +38,8 ENTITY RAM_CTRLR_v2 IS
38 38 PORT(
39 39 rstn : IN STD_LOGIC;
40 40 clk : IN STD_LOGIC;
41 -- ram init done
42 init_mem_done: out STD_LOGIC;
41 43 -- R/W Ctrl
42 44 ram_write : IN STD_LOGIC;
43 45 ram_read : IN STD_LOGIC;
@@ -56,24 +58,28 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRL
56 58
57 59 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
58 60 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
59 SIGNAL WEN, REN : STD_LOGIC;
61 SIGNAL WEN, REN : STD_LOGIC;
60 62 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
61 63 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 64 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
65
66 signal rst_mem_done_s : std_logic;
67 signal ram_write_s : std_logic;
63 68
64 69 BEGIN
65 70
66 sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
67 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
71 init_mem_done <= rst_mem_done_s;
72
73 sample_out <= RD(Input_SZ_1-1 DOWNTO 0) when rst_mem_done_s = '1' else (others => '0');
74 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in when rst_mem_done_s = '1' else (others => '0');
75 ram_write_s <= ram_write when rst_mem_done_s = '1' else '1';
68 76 -----------------------------------------------------------------------------
69 77 -- RAM
70 78 -----------------------------------------------------------------------------
71 79
72 80 memCEL : IF Mem_use = use_CEL GENERATE
73 WEN <= NOT ram_write;
81 WEN <= NOT ram_write_s;
74 82 REN <= NOT ram_read;
75 -- RAMblk : RAM_CEL_N
76 -- GENERIC MAP(Input_SZ_1)
77 83 RAMblk : RAM_CEL
78 84 GENERIC MAP(Input_SZ_1, 8)
79 85 PORT MAP(
@@ -91,7 +97,7 BEGIN
91 97 memRAM : IF Mem_use = use_RAM GENERATE
92 98 SRAM : syncram_2p
93 99 GENERIC MAP(tech, 8, Input_SZ_1)
94 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
100 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write_s, WADDR, WD);
95 101 END GENERATE;
96 102
97 103 -----------------------------------------------------------------------------
@@ -100,13 +106,22 BEGIN
100 106 PROCESS (clk, rstn)
101 107 BEGIN -- PROCESS
102 108 IF rstn = '0' THEN -- asynchronous reset (active low)
103 counter <= (OTHERS => '0');
109 counter <= (OTHERS => '0');
110 rst_mem_done_s <= '0';
104 111 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
105 IF raddr_rst = '1' THEN
106 counter <= (OTHERS => '0');
107 ELSIF raddr_add1 = '1' THEN
112 if rst_mem_done_s = '0' then
108 113 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
109 END IF;
114 else
115 IF raddr_rst = '1' THEN
116 counter <= (OTHERS => '0');
117 ELSIF raddr_add1 = '1' THEN
118 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
119 END IF;
120 end if;
121 if counter = x"FF" then
122 rst_mem_done_s <= '1';
123 end if;
124
110 125 END IF;
111 126 END PROCESS;
112 127 RADDR <= counter;
@@ -114,7 +129,8 BEGIN
114 129 -----------------------------------------------------------------------------
115 130 -- WADDR
116 131 -----------------------------------------------------------------------------
117 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
132 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)) when rst_mem_done_s = '0' else
133 STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
118 134 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
119 135 STD_LOGIC_VECTOR(UNSIGNED(counter));
120 136
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