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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.numeric_std.all;
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USE IEEE.std_logic_signed.ALL;
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USE IEEE.MATH_real.ALL;
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ENTITY generator IS
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GENERIC (
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AMPLITUDE : INTEGER := 100;
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NB_BITS : INTEGER := 16);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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data_ack : IN STD_LOGIC;
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offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
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data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
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);
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END generator;
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ARCHITECTURE beh OF generator IS
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SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
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BEGIN -- beh
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PROCESS (clk, rstn)
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variable seed1, seed2: positive; -- seed values for random generator
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variable rand: real; -- random real-number value in range 0 to 1.0
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BEGIN -- PROCESS
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uniform(seed1, seed2, rand);--more entropy by skipping values
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IF rstn = '0' THEN -- asynchronous reset (active low)
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reg <= (OTHERS => '0');
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF run = '0' THEN
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reg <= (OTHERS => '0');
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ELSE
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IF data_ack = '1' THEN
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reg <= std_logic_vector(to_signed(INTEGER( (REAL(AMPLITUDE) * rand) + REAL(to_integer(SIGNED(offset))) ),NB_BITS));
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END IF;
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END IF;
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END IF;
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END PROCESS;
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data <= reg;
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END beh;
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