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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more Cdetails.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
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GENERIC (
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Coef_sel_SZ : INTEGER;
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Cels_count : INTEGER := 5;
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ChanelsCount : INTEGER := 1);
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PORT (
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rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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sample_in_val : IN STD_LOGIC;
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sample_in_rot : OUT STD_LOGIC;
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sample_out_val : OUT STD_LOGIC;
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sample_out_rot : OUT STD_LOGIC;
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in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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ram_write : OUT STD_LOGIC;
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ram_read : OUT STD_LOGIC;
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raddr_rst : OUT STD_LOGIC;
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raddr_add1 : OUT STD_LOGIC;
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waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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alu_sel_input : OUT STD_LOGIC;
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alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
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alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
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);
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END IIR_CEL_CTRLR_v2_CONTROL;
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ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS
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TYPE fsmIIR_CEL_T IS (waiting,
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first_read,
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compute_b0,
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compute_b1,
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compute_b2,
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compute_a1,
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compute_a2,
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LAST_CEL,
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wait_valid_last_output,
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wait_valid_last_output_2);
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SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
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SIGNAL alu_selected_coeff : INTEGER RANGE 0 TO 2**Coef_sel_SZ-1;
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SIGNAL Chanel_ongoing : INTEGER;
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SIGNAL Cel_ongoing : INTEGER;
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BEGIN
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alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ));
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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--REG -------------------------------------------------------------------
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in_sel_src <= (OTHERS => '0'); --
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--RAM_WRitE -------------------------------------------------------------
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ram_sel_Wdata <= "00"; --
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ram_write <= '0'; --
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waddr_previous <= "00"; --
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--RAM_READ --------------------------------------------------------------
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ram_read <= '0'; --
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raddr_rst <= '0'; --
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raddr_add1 <= '0'; --
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--ALU -------------------------------------------------------------------
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alu_selected_coeff <= 0; --
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alu_sel_input <= '0'; --
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alu_ctrl <= ctrl_IDLE; --
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--OUT
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sample_out_val <= '0'; --
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sample_out_rot <= '0'; --
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Chanel_ongoing <= 0; --
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Cel_ongoing <= 0; --
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sample_in_rot <= '0';
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IIR_CEL_STATE <= waiting;
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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CASE IIR_CEL_STATE IS
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WHEN waiting =>
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sample_out_rot <= '0';
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sample_in_rot <= '0';
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sample_out_val <= '0';
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alu_ctrl <= ctrl_CLRMAC;
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alu_selected_coeff <= 0;
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in_sel_src <= "01";
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ram_read <= '0';
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ram_sel_Wdata <= "00";
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ram_write <= '0';
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waddr_previous <= "00";
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IF sample_in_val = '1' THEN
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raddr_rst <= '0';
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alu_sel_input <= '1';
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ram_read <= '1';
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raddr_add1 <= '1';
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IIR_CEL_STATE <= first_read;
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Chanel_ongoing <= Chanel_ongoing + 1;
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Cel_ongoing <= 1;
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ELSE
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raddr_add1 <= '0';
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raddr_rst <= '1';
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Chanel_ongoing <= 0;
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Cel_ongoing <= 0;
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END IF;
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WHEN first_read =>
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IIR_CEL_STATE <= compute_b2;
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ram_read <= '1';
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raddr_add1 <= '1';
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alu_ctrl <= ctrl_MULT;
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alu_sel_input <= '1';
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in_sel_src <= "01";
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WHEN compute_b2 =>
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sample_out_rot <= '0';
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sample_in_rot <= '0';
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sample_out_val <= '0';
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alu_sel_input <= '1';
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--
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ram_sel_Wdata <= "10";
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ram_write <= '1';
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waddr_previous <= "10";
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--
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ram_read <= '1';
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raddr_rst <= '0';
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raddr_add1 <= '0';
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IF Cel_ongoing = 1 THEN
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in_sel_src <= "00";
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ELSE
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in_sel_src <= "11";
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END IF;
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alu_selected_coeff <= alu_selected_coeff+1;
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alu_ctrl <= ctrl_MAC;
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IIR_CEL_STATE <= compute_b1;
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WHEN compute_b1 =>
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sample_in_rot <= '0';
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alu_sel_input <= '0';
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--
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ram_sel_Wdata <= "00";
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ram_write <= '1';
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waddr_previous <= "01";
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--
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ram_read <= '1';
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raddr_rst <= '0';
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raddr_add1 <= '1';
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sample_out_rot <= '0';
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IF Cel_ongoing = 1 THEN
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in_sel_src <= "10";
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sample_out_val <= '0';
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ELSE
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sample_out_val <= '0';
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in_sel_src <= "00";
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END IF;
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alu_selected_coeff <= alu_selected_coeff+1;
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alu_ctrl <= ctrl_MAC;
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IIR_CEL_STATE <= compute_b0;
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WHEN compute_b0 =>
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sample_out_rot <= '0';
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sample_out_val <= '0';
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sample_in_rot <= '0';
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alu_sel_input <= '1';
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ram_sel_Wdata <= "00";
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ram_write <= '0';
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waddr_previous <= "01";
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ram_read <= '1';
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raddr_rst <= '0';
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raddr_add1 <= '0';
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in_sel_src <= "10";
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alu_selected_coeff <= alu_selected_coeff+1;
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alu_ctrl <= ctrl_MAC;
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IIR_CEL_STATE <= compute_a2;
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IF Cel_ongoing = Cels_count THEN
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sample_in_rot <= '1';
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ELSE
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sample_in_rot <= '0';
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END IF;
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WHEN compute_a2 =>
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sample_out_val <= '0';
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sample_out_rot <= '0';
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alu_sel_input <= '1';
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ram_sel_Wdata <= "00";
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ram_write <= '0';
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waddr_previous <= "01";
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ram_read <= '1';
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raddr_rst <= '0';
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IF Cel_ongoing = Cels_count THEN
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raddr_add1 <= '1';
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ELSE
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raddr_add1 <= '0';
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END IF;
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in_sel_src <= "00";
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alu_selected_coeff <= alu_selected_coeff+1;
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alu_ctrl <= ctrl_MAC;
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IIR_CEL_STATE <= compute_a1;
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sample_in_rot <= '0';
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WHEN compute_a1 =>
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sample_out_val <= '0';
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sample_out_rot <= '0';
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alu_sel_input <= '0';
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ram_sel_Wdata <= "00";
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ram_write <= '0';
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waddr_previous <= "01";
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ram_read <= '1';
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raddr_rst <= '0';
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alu_ctrl <= ctrl_MULT;
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sample_in_rot <= '0';
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IF Cel_ongoing = Cels_count THEN
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alu_selected_coeff <= 0;
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ram_sel_Wdata <= "10";
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raddr_add1 <= '1';
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ram_write <= '1';
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waddr_previous <= "10";
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IF Chanel_ongoing = ChanelsCount THEN
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IIR_CEL_STATE <= wait_valid_last_output;
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ELSE
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Chanel_ongoing <= Chanel_ongoing + 1;
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Cel_ongoing <= 1;
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IIR_CEL_STATE <= LAST_CEL;
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in_sel_src <= "01";
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END IF;
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ELSE
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raddr_add1 <= '1';
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alu_selected_coeff <= alu_selected_coeff+1;
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Cel_ongoing <= Cel_ongoing+1;
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IIR_CEL_STATE <= compute_b2;
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END IF;
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WHEN LAST_CEL =>
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alu_sel_input <= '1';
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IIR_CEL_STATE <= compute_b2;
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raddr_add1 <= '1';
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ram_sel_Wdata <= "01";
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ram_write <= '1';
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waddr_previous <= "10";
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sample_out_rot <= '1';
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WHEN wait_valid_last_output =>
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IIR_CEL_STATE <= wait_valid_last_output_2;
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sample_in_rot <= '0';
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alu_ctrl <= ctrl_IDLE;
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alu_selected_coeff <= 0;
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in_sel_src <= "01";
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ram_read <= '0';
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raddr_rst <= '1';
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raddr_add1 <= '1';
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ram_sel_Wdata <= "01";
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ram_write <= '1';
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waddr_previous <= "10";
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Chanel_ongoing <= 0;
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Cel_ongoing <= 0;
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sample_out_val <= '0';
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sample_out_rot <= '1';
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WHEN wait_valid_last_output_2 =>
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IIR_CEL_STATE <= waiting;
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sample_in_rot <= '0';
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alu_ctrl <= ctrl_IDLE;
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alu_selected_coeff <= 0;
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in_sel_src <= "01";
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ram_read <= '0';
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raddr_rst <= '1';
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raddr_add1 <= '1';
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ram_sel_Wdata <= "10";
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ram_write <= '1';
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waddr_previous <= "10";
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Chanel_ongoing <= 0;
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Cel_ongoing <= 0;
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sample_out_val <= '1';
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sample_out_rot <= '0';
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END PROCESS;
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END ar_IIR_CEL_CTRLR_v2_CONTROL;
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