# HG changeset patch # User pellion # Date 2016-11-02 10:34:14 # Node ID 5ffe6bd0368c616a15c44a05eca9bcaa28d95215 # Parent 905b2664a7452390efda9ff74bc4a7b1485ba73c Added missing files (sdc/pdc/makefile) for LFR-EQM boards Improved Validation IIR LFR design Update LFR Filter, first implementation of filter RAM Init. diff --git a/.hgignore b/.hgignore --- a/.hgignore +++ b/.hgignore @@ -39,3 +39,4 @@ actar.vhd *.bak *.pdc.ce *.zip +*/.ipynb_checkpoints/* diff --git a/boards/LFR-EQM/LFR_EQM.pdc b/boards/LFR-EQM/LFR_EQM.pdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM.pdc @@ -0,0 +1,122 @@ +set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout +set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout +set_io reset -pinname N18 -fixed yes -DIRECTION Inout + +set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout +set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout +set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout +set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout +set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout +set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout +set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout +set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout +set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout +set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout +set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout +set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout +set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout +set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout +set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout +set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout +set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout +set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout +set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout +set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout + +set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout +set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout +set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout +set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout +set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout +set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout +set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout +set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout +set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout +set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout +set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout +set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout +set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout +set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout +set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout +set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout +set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout +set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout +set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout +set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout +set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout +set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout +set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout +set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout +set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout +set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout +set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout +set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout +set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout +set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout +set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout +set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout + +set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout +set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout +set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout +set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout +set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout +set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout +set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout + +set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout +set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout +set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout +set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout + +set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout +set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout +set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout +set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout + +set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout +set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout +set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout + +set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout +set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout +set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout +set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout +#set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout +#set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout +#set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout +set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout +#set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout + +set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout + +set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout + +set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout + +set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout +set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout +set_io {HK_SEL[0]} -pinname A2 -fixed yes -DIRECTION Inout +set_io {HK_SEL[1]} -pinname C3 -fixed yes -DIRECTION Inout + +set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout +set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout +set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout +set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout +set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout +set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout +set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout +set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout +set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout +set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout +set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout +set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout +set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout +set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/LFR_EQM_A3PE3000_NoADC.pdc b/boards/LFR-EQM/LFR_EQM_A3PE3000_NoADC.pdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM_A3PE3000_NoADC.pdc @@ -0,0 +1,124 @@ +set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout +set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout +set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On + +set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout +set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout +set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout +set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout +set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout +set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout +set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout +set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout +set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout +set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout +set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout +set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout +set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout +set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout +set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout +set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout +set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout +set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout +set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout + +set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout +set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout +set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout +set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout +set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout +set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout +set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout +set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout +set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout +set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout +set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout +set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout +set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout +set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout +set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout +set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout +set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout +set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout +set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout +set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout +set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout +set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout +set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout +set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout +set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout +set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout +set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout +set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout +set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout +set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout +set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout +set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout + +set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout +set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout +set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout +#set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout +set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout +set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout +set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout + +set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout +set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout +set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout +set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout +set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout + +set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout +set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout +set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout +set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout +set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout + +set_io {TAG[1]} -pinname J12 -fixed yes -DIRECTION Inout +set_io {TAG[2]} -pinname K12 -fixed yes -DIRECTION Inout +set_io {TAG[3]} -pinname K13 -fixed yes -DIRECTION Inout +set_io {TAG[4]} -pinname L16 -fixed yes -DIRECTION Inout +set_io {TAG[5]} -pinname L15 -fixed yes -DIRECTION Inout +set_io {TAG[6]} -pinname M16 -fixed yes -DIRECTION Inout +set_io {TAG[7]} -pinname J14 -fixed yes -DIRECTION Inout +set_io {TAG[8]} -pinname K15 -fixed yes -DIRECTION Inout +set_io {TAG[9]} -pinname J17 -fixed yes -DIRECTION Inout + +set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout + +set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout + +set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout + +set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout +set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout +set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout +set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout + +#set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout +#set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout +#set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout +#set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout +#set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout +#set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout +#set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout +#set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout +#set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout +#set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout +#set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout +#set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout +#set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout +#set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout + +set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout +set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout +set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout +set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/LFR_EQM_A3PE3000_no49.pdc b/boards/LFR-EQM/LFR_EQM_A3PE3000_no49.pdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM_A3PE3000_no49.pdc @@ -0,0 +1,123 @@ +set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout +set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On + +set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout +set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout +set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout +set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout +set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout +set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout +set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout +set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout +set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout +set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout +set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout +set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout +set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout +set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout +set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout +set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout +set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout +set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout +set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout + +set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout +set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout +set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout +set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout +set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout +set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout +set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout +set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout +set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout +set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout +set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout +set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout +set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout +set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout +set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout +set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout +set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout +set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout +set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout +set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout +set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout +set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout +set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout +set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout +set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout +set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout +set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout +set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout +set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout +set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout +set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout +set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout + +set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout +set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout +set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout +#set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout +set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout +set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout +set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout + +set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout +set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout +set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout +set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout +set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout + +set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout +set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout +set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout +set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout +set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout + +set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout +set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout +set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout +set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout +#set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout +#set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout +#set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout +set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout +#set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout + +set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout + +set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout + +set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout + +set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout +set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout +set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout +set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout + +set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout +set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout +set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout +set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout +set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout +set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout +set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout +set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout +set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout +set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout +set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout +set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout +set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout +set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout + +set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout +set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout +set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout +set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/LFR_EQM_RTAX_layout.sdc b/boards/LFR-EQM/LFR_EQM_RTAX_layout.sdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM_RTAX_layout.sdc @@ -0,0 +1,77 @@ +################################################################################ +# SDC WRITER VERSION "3.1"; +# DESIGN "LFR_EQM"; +# Timing constraints scenario: "Primary"; +# DATE "Fri Jul 24 14:50:40 2015"; +# VENDOR "Actel"; +# PROGRAM "Actel Designer Software Release v9.1 SP5"; +# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. +################################################################################ + + +set sdc_version 1.7 + + +######## Clock Constraints ######## + +create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } + +create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } + +create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_pad_25/U0:Y } + +create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } + +create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1:Y } + +create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1:Y } + + + +######## Generated Clock Constraints ######## + + + +######## Clock Source Latency Constraints ######### + + + +######## Input Delay Constraints ######## + + + +######## Output Delay Constraints ######## +set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address }] + +set_min_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 }] + + + +######## Delay Constraints ######## + + + +######## Delay Constraints ######## + + + +######## Multicycle Constraints ######## + + + +######## False Path Constraints ######## + + + +######## Output load Constraints ######## + + + +######## Disable Timing Constraints ######### + + + +######## Clock Uncertainty Constraints ######### + + + diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_19-5-2015.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_19-5-2015.sdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM_place_and_route_19-5-2015.sdc @@ -0,0 +1,151 @@ +################################################################################ +# SDC WRITER VERSION "3.1"; +# DESIGN "LFR_EQM"; +# Timing constraints scenario: "Primary"; +# DATE "Tue May 19 15:46:14 2015"; +# VENDOR "Actel"; +# PROGRAM "Actel Designer Software Release v9.1 SP5"; +# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. +################################################################################ + + +set sdc_version 1.7 + + +######## Clock Constraints ######## + +create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } + +create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } + +create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } + +create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } + +create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } + +create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } + + + +######## Generated Clock Constraints ######## + + + +######## Clock Source Latency Constraints ######### + + + +######## Input Delay Constraints ######## + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] + +set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }] +set_input_delay -min 15.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }] + + + +######## Output Delay Constraints ######## + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] +set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \ +ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \ +ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] +set_min_delay 8.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \ +ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \ +ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] + + + +######## Delay Constraints ######## + +set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] + +set_max_delay 12.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] + +set_max_delay 12.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] + +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] + +set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] + +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] + +set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ +[get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] + +set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ +[get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] + + + +######## Delay Constraints ######## + +set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] + +set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] + + + +######## Multicycle Constraints ######## + + + +######## False Path Constraints ######## + + + +######## Output load Constraints ######## + + + +######## Disable Timing Constraints ######### + + + +######## Clock Uncertainty Constraints ######### + + + diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_5-5-2015.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_5-5-2015.sdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM_place_and_route_5-5-2015.sdc @@ -0,0 +1,156 @@ +################################################################################ +# SDC WRITER VERSION "3.1"; +# DESIGN "LFR_EQM"; +# Timing constraints scenario: "Primary"; +# DATE "Tue May 05 13:46:34 2015"; +# VENDOR "Actel"; +# PROGRAM "Actel Designer Software Release v9.1 SP5"; +# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. +################################################################################ + + +set sdc_version 1.7 + + +######## Clock Constraints ######## + +create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } + +create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } + +create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } + +create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } + +create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } + +create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } + + + +######## Generated Clock Constraints ######## + + + +######## Clock Source Latency Constraints ######### + + + +######## Input Delay Constraints ######## + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] + +set_input_delay -max 20.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }] + + + +######## Output Delay Constraints ######## + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] +set_max_delay 35.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \ +ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \ +ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \ +ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \ +ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] + + + +######## Delay Constraints ######## + +set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] + +set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] + +set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] + +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] + +set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] + +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] + +set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ +[get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] + +set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ +[get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] + + + +######## Delay Constraints ######## + +set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] + +set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] + + + +######## Multicycle Constraints ######## + + + +######## False Path Constraints ######## + +set_false_path -from [get_pins { \ +USE_ADCDRIVER_true.top_ad_conv_RHF1401_withFilter_1/cnv_s_reg:CLK }] -to [get_pins { \ +USE_ADCDRIVER_true.top_ad_conv_RHF1401_withFilter_1/SYNC_FF_cnv/sync_loop.1.A_temp[1]:D \ +}] +# SYNC PATH of ADC_CNV signal from CLK_domain_24 to CLK_domain_25 + + + +######## Output load Constraints ######## + + + +######## Disable Timing Constraints ######### + + + +######## Clock Uncertainty Constraints ######### + + + diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_ALTRAN.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_ALTRAN.sdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM_place_and_route_ALTRAN.sdc @@ -0,0 +1,128 @@ +################################################################################ +# SDC WRITER VERSION "3.1"; +# DESIGN "LFR_EQM"; +# Timing constraints scenario: "Primary"; +# DATE "Fri Apr 24 16:02:16 2015"; +# VENDOR "Actel"; +# PROGRAM "Actel Designer Software Release v9.1 SP5"; +# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. +################################################################################ + + +set sdc_version 1.7 + + +######## Clock Constraints ######## + +create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } + +create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } + +create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } + +create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } + +create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } + +create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } + + + +######## Generated Clock Constraints ######## + + + +######## Clock Source Latency Constraints ######### + + + +######## Input Delay Constraints ######## + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] +set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] +set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] +set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] +set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] + + + +######## Output Delay Constraints ######## + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] +set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] +set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] + + + +######## Delay Constraints ######## + +set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \ +nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \ +{spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] + +set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \ +nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \ +{spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] + + + +######## Delay Constraints ######## + + + +######## Multicycle Constraints ######## + + + +######## False Path Constraints ######## + + + +######## Output load Constraints ######## + + + +######## Disable Timing Constraints ######### + + + +######## Clock Uncertainty Constraints ######### + + + diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_RTAX_ALTRAN.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_RTAX_ALTRAN.sdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM_place_and_route_RTAX_ALTRAN.sdc @@ -0,0 +1,129 @@ +################################################################################ +# SDC WRITER VERSION "3.1"; +# DESIGN "LFR_EQM"; +# Timing constraints scenario: "Primary"; +# DATE "Fri Apr 24 16:02:16 2015"; +# VENDOR "Actel"; +# PROGRAM "Actel Designer Software Release v9.1 SP5"; +# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. +################################################################################ + + +set sdc_version 1.7 + + +######## Clock Constraints ######## + +create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } + +create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } + +create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } + +create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } + + +create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } + +create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } + + + +######## Generated Clock Constraints ######## + + + +######## Clock Source Latency Constraints ######### + + + +######## Input Delay Constraints ######## + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] +set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] +set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] +set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] +set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] + + + +######## Output Delay Constraints ######## + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] +set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] +set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] + + + +######## Delay Constraints ######## + +set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \ +nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \ +{spw_inputloop.0.spw_phy0/rxclki_1_0:Y}] + +set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \ +nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \ +{spw_inputloop.1.spw_phy0/rxclki_1_0:YY}] + + + +######## Delay Constraints ######## + + + +######## Multicycle Constraints ######## + + + +######## False Path Constraints ######## + + + +######## Output load Constraints ######## + + + +######## Disable Timing Constraints ######### + + + +######## Clock Uncertainty Constraints ######### + + + diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_no49.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_no49.sdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM_place_and_route_no49.sdc @@ -0,0 +1,124 @@ +################################################################################ +# SDC WRITER VERSION "3.1"; +# DESIGN "LFR_EQM"; +# Timing constraints scenario: "Primary"; +# DATE "Fri Apr 24 16:02:16 2015"; +# VENDOR "Actel"; +# PROGRAM "Actel Designer Software Release v9.1 SP5"; +# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. +################################################################################ + + +set sdc_version 1.7 + + +######## Clock Constraints ######## + +create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } + +##create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } + +create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } + +##create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } + +create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } + +create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } + + + +######## Generated Clock Constraints ######## + + + +######## Clock Source Latency Constraints ######### + + + +######## Input Delay Constraints ######## + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] +set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] +set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] +set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] +set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] + + + +######## Output Delay Constraints ######## + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] +set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] +set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] + + + +######## Delay Constraints ######## + +set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] + +set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] + + + +######## Delay Constraints ######## + + + +######## Multicycle Constraints ######## + + + +######## False Path Constraints ######## + + + +######## Output load Constraints ######## + + + +######## Disable Timing Constraints ######### + + + +######## Clock Uncertainty Constraints ######### + + + diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_no49_GUI.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_no49_GUI.sdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM_place_and_route_no49_GUI.sdc @@ -0,0 +1,157 @@ +################################################################################ +# SDC WRITER VERSION "3.1"; +# DESIGN "LFR_EQM"; +# Timing constraints scenario: "Primary"; +# DATE "Wed May 13 13:09:37 2015"; +# VENDOR "Actel"; +# PROGRAM "Actel Designer Software Release v9.1 SP5"; +# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. +################################################################################ + + +set sdc_version 1.7 + + +######## Clock Constraints ######## + +create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } + +create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } + +create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } + +create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } + + + +######## Generated Clock Constraints ######## + + + +######## Clock Source Latency Constraints ######### + + + +######## Input Delay Constraints ######## + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] + +set_input_delay -max 0.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }] +set_input_delay -min 0.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }] + + + +######## Output Delay Constraints ######## + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] + + + +######## Delay Constraints ######## + +set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] + +set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] + +set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] + +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] + +set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] + +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] + +set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ +[get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] + +set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ +[get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] + +set_max_delay 30.000 -from [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] \ +ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] \ +ADC_data[7] ADC_data[8] ADC_data[9] }] -to [get_clocks {clk_25:Q}] + +set_max_delay 15.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \ +ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \ +ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] + + + +######## Delay Constraints ######## + +set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] + +set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] + +set_min_delay 0.000 -from [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] \ +ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] \ +ADC_data[7] ADC_data[8] ADC_data[9] }] -to [get_clocks {clk_25:Q}] + +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \ +ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \ +ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] + + + +######## Multicycle Constraints ######## + + + +######## False Path Constraints ######## + + + +######## Output load Constraints ######## + + + +######## Disable Timing Constraints ######### + + + +######## Clock Uncertainty Constraints ######### + + + diff --git a/boards/LFR-EQM/LFR_EQM_synthesis.sdc b/boards/LFR-EQM/LFR_EQM_synthesis.sdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/LFR_EQM_synthesis.sdc @@ -0,0 +1,61 @@ +# Synplicity, Inc. constraint file +# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc +# Written on Wed Aug 1 19:29:24 2007 +# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor + +# +# Collections +# + +# +# Clocks +# + +define_clock -name {clk50MHz} -freq 50 -clockgroup default_clkgroup_50 -route 5 +define_clock -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_49 -route 5 + +# +# Clock to Clock +# + +# +# Inputs/Outputs +# + + +# +# Registers +# + +# +# Multicycle Path +# + +# +# False Path +# + +set_false_path -from reset + +# +# Path Delay +# + +# +# Attributes +# + +define_global_attribute syn_useioff {1} +define_global_attribute -disable syn_netlist_hierarchy {0} + +# +# I/O standards +# + +# +# Compile Points +# + +# +# Other Constraints +# diff --git a/boards/LFR-EQM/Makefile_RTAX.inc b/boards/LFR-EQM/Makefile_RTAX.inc new file mode 100644 --- /dev/null +++ b/boards/LFR-EQM/Makefile_RTAX.inc @@ -0,0 +1,41 @@ +PACKAGE=CQFP352 +SPEED=Std +SYNFREQ=50 + +TECHNOLOGY=Axcelerator + +DESIGNER_PACKAGE=CQFP +DESIGNER_PINS=352 +DESIGNER_VOLTAGE=COM +DESIGNER_TEMP=COM + +#ifeq ("$(FPGA_RTAX4000)","S") +# LIBERO_DIE=70800rts +# PART=RTAX4000S +# LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r +#endif + +#ifeq ("$(FPGA_RTAX4000)","D") +LIBERO_DIE=70800d +PART=RTAX4000D +LIBERO_PACKAGE=cq$(DESIGNER_PINS) +#endif + +MANUFACTURER=Actel +MGCPART=$(PART) +MGCTECHNOLOGY=Axcelerator +MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} + +## RTAX4000S OPTIONS +#LIBERO_DIE=70800rts +#PART=RTAX4000S + +## RTAX4000D OPTIONS +#LIBERO_DIE=70800d +#PART=RTAX4000D + +# RTAX4000D +#LIBERO_PACKAGE=cq$(DESIGNER_PINS) + +# RTAX4000S +#LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r diff --git a/designs/EGSE_ICI/config.vhd.h b/designs/EGSE_ICI/config.vhd.h --- a/designs/EGSE_ICI/config.vhd.h +++ b/designs/EGSE_ICI/config.vhd.h @@ -1,208 +1,208 @@ --- Technology and synthesis options - constant CFG_FABTECH : integer := CONFIG_SYN_TECH; - constant CFG_MEMTECH : integer := CFG_RAM_TECH; - constant CFG_PADTECH : integer := CFG_PAD_TECH; - constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; - constant CFG_SCAN : integer := CONFIG_SYN_SCAN; - --- Clock generator - constant CFG_CLKTECH : integer := CFG_CLK_TECH; - constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; - constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; - constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; - constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; - constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; - constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; - --- LEON3 processor core - constant CFG_LEON3 : integer := CONFIG_LEON3; - constant CFG_NCPU : integer := CONFIG_PROC_NUM; - constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; - constant CFG_V8 : integer := CFG_IU_V8; - constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; - constant CFG_SVT : integer := CONFIG_IU_SVT; - constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; - constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; - constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; - constant CFG_PWD : integer := CONFIG_PWD*2; - constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST; - constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; - constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; - constant CFG_ISETS : integer := CFG_IU_ISETS; - constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; - constant CFG_ILINE : integer := CFG_ILINE_SZ; - constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; - constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; - constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; - constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; - constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; - constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; - constant CFG_DSETS : integer := CFG_IU_DSETS; - constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; - constant CFG_DLINE : integer := CFG_DLINE_SZ; - constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; - constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; - constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; - constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; - constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; - constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; - constant CFG_MMUEN : integer := CONFIG_MMUEN; - constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; - constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; - constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; - constant CFG_TLB_REP : integer := CONFIG_TLB_REP; - constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; - constant CFG_DSU : integer := CONFIG_DSU_ENABLE; - constant CFG_ITBSZ : integer := CFG_DSU_ITB; - constant CFG_ATBSZ : integer := CFG_DSU_ATB; - constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; - constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; - constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; - constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; - constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; - constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; - constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; - constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; - constant CFG_PCLOW : integer := CFG_DEBUG_PC32; - --- AMBA settings - constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; - constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; - constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; - constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; - constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; - constant CFG_AHB_MON : integer := CONFIG_AHB_MON; - constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; - constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; - --- DSU UART - constant CFG_AHB_UART : integer := CONFIG_DSU_UART; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG; - constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; - constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; - constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; - constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; - constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; - --- PROM/SRAM controller - constant CFG_SRCTRL : integer := CONFIG_SRCTRL; - constant CFG_SRCTRL_PROMWS : integer := CONFIG_SRCTRL_PROMWS; - constant CFG_SRCTRL_RAMWS : integer := CONFIG_SRCTRL_RAMWS; - constant CFG_SRCTRL_IOWS : integer := CONFIG_SRCTRL_IOWS; - constant CFG_SRCTRL_RMW : integer := CONFIG_SRCTRL_RMW; - constant CFG_SRCTRL_8BIT : integer := CONFIG_SRCTRL_8BIT; - - constant CFG_SRCTRL_SRBANKS : integer := CFG_SR_CTRL_SRBANKS; - constant CFG_SRCTRL_BANKSZ : integer := CFG_SR_CTRL_BANKSZ; - constant CFG_SRCTRL_ROMASEL : integer := CONFIG_SRCTRL_ROMASEL; --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; - constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; - constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; - constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; - constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; - constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; - constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; - constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; - constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; - --- SDRAM controller - constant CFG_SDCTRL : integer := CONFIG_SDCTRL; - constant CFG_SDCTRL_INVCLK : integer := CONFIG_SDCTRL_INVCLK; - constant CFG_SDCTRL_SD64 : integer := CONFIG_SDCTRL_BUS64; - constant CFG_SDCTRL_PAGE : integer := CONFIG_SDCTRL_PAGE + CONFIG_SDCTRL_PROGPAGE; - --- AHB ROM - constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; - constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; - constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; - constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; - constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; - constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; - constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; - constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; - constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; - --- CAN 2.0 interface - constant CFG_CAN : integer := CONFIG_CAN_ENABLE; - constant CFG_CANIO : integer := 16#CONFIG_CANIO#; - constant CFG_CANIRQ : integer := CONFIG_CANIRQ; - constant CFG_CANLOOP : integer := CONFIG_CANLOOP; - constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST; - constant CFG_CANFT : integer := CONFIG_CAN_FT; - --- PCI interface - constant CFG_PCI : integer := CFG_PCITYPE; - constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#; - constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#; - constant CFG_PCIDEPTH : integer := CFG_PCIFIFO; - constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO; - --- PCI arbiter - constant CFG_PCI_ARB : integer := CONFIG_PCI_ARBITER; - constant CFG_PCI_ARBAPB : integer := CONFIG_PCI_ARBITER_APB; - constant CFG_PCI_ARB_NGNT : integer := CONFIG_PCI_ARBITER_NREQ; - --- PCI trace buffer - constant CFG_PCITBUFEN: integer := CONFIG_PCI_TRACE; - constant CFG_PCITBUF : integer := CFG_PCI_TRACEBUF; - --- Spacewire interface - constant CFG_SPW_EN : integer := CONFIG_SPW_ENABLE; - constant CFG_SPW_NUM : integer := CONFIG_SPW_NUM; - constant CFG_SPW_AHBFIFO : integer := CONFIG_SPW_AHBFIFO; - constant CFG_SPW_RXFIFO : integer := CONFIG_SPW_RXFIFO; - constant CFG_SPW_RMAP : integer := CONFIG_SPW_RMAP; - constant CFG_SPW_RMAPBUF : integer := CONFIG_SPW_RMAPBUF; - constant CFG_SPW_RMAPCRC : integer := CONFIG_SPW_RMAPCRC; - constant CFG_SPW_NETLIST : integer := CONFIG_SPW_NETLIST; - constant CFG_SPW_FT : integer := CONFIG_SPW_FT; - constant CFG_SPW_GRSPW : integer := CONFIG_SPW_GRSPW; - constant CFG_SPW_RXUNAL : integer := CONFIG_SPW_RXUNAL; - constant CFG_SPW_DMACHAN : integer := CONFIG_SPW_DMACHAN; - constant CFG_SPW_PORTS : integer := CONFIG_SPW_PORTS; - constant CFG_SPW_INPUT : integer := CONFIG_SPW_INPUT; - constant CFG_SPW_OUTPUT : integer := CONFIG_SPW_OUTPUT; - constant CFG_SPW_RTSAME : integer := CONFIG_SPW_RTSAME; --- UART 1 - constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; - constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; - --- UART 2 - constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE; - constant CFG_UART2_FIFO : integer := CFG_UA2_FIFO; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; - constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; - --- Modular timer - constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; - constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; - constant CFG_GPT_SW : integer := CONFIG_GPT_SW; - constant CFG_GPT_TW : integer := CONFIG_GPT_TW; - constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; - constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; - constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; - constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; - constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; - constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; - --- GRLIB debugging - constant CFG_DUART : integer := CONFIG_DEBUG_UART; - +-- Technology and synthesis options + constant CFG_FABTECH : integer := CONFIG_SYN_TECH; + constant CFG_MEMTECH : integer := CFG_RAM_TECH; + constant CFG_PADTECH : integer := CFG_PAD_TECH; + constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; + constant CFG_SCAN : integer := CONFIG_SYN_SCAN; + +-- Clock generator + constant CFG_CLKTECH : integer := CFG_CLK_TECH; + constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; + constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; + constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; + constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; + constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; + constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; + +-- LEON3 processor core + constant CFG_LEON3 : integer := CONFIG_LEON3; + constant CFG_NCPU : integer := CONFIG_PROC_NUM; + constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; + constant CFG_V8 : integer := CFG_IU_V8; + constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; + constant CFG_SVT : integer := CONFIG_IU_SVT; + constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; + constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; + constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; + constant CFG_PWD : integer := CONFIG_PWD*2; + constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST; + constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; + constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; + constant CFG_ISETS : integer := CFG_IU_ISETS; + constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; + constant CFG_ILINE : integer := CFG_ILINE_SZ; + constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; + constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; + constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; + constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; + constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; + constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; + constant CFG_DSETS : integer := CFG_IU_DSETS; + constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; + constant CFG_DLINE : integer := CFG_DLINE_SZ; + constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; + constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; + constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; + constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; + constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; + constant CFG_MMUEN : integer := CONFIG_MMUEN; + constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; + constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; + constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; + constant CFG_TLB_REP : integer := CONFIG_TLB_REP; + constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; + constant CFG_DSU : integer := CONFIG_DSU_ENABLE; + constant CFG_ITBSZ : integer := CFG_DSU_ITB; + constant CFG_ATBSZ : integer := CFG_DSU_ATB; + constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; + constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; + constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; + constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; + constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; + constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; + constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; + constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; + constant CFG_PCLOW : integer := CFG_DEBUG_PC32; + +-- AMBA settings + constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; + constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; + constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; + constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; + constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; + constant CFG_AHB_MON : integer := CONFIG_AHB_MON; + constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; + constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; + +-- DSU UART + constant CFG_AHB_UART : integer := CONFIG_DSU_UART; + +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; + +-- Ethernet DSU + constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG; + constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; + constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; + constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; + constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; + constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; + +-- PROM/SRAM controller + constant CFG_SRCTRL : integer := CONFIG_SRCTRL; + constant CFG_SRCTRL_PROMWS : integer := CONFIG_SRCTRL_PROMWS; + constant CFG_SRCTRL_RAMWS : integer := CONFIG_SRCTRL_RAMWS; + constant CFG_SRCTRL_IOWS : integer := CONFIG_SRCTRL_IOWS; + constant CFG_SRCTRL_RMW : integer := CONFIG_SRCTRL_RMW; + constant CFG_SRCTRL_8BIT : integer := CONFIG_SRCTRL_8BIT; + + constant CFG_SRCTRL_SRBANKS : integer := CFG_SR_CTRL_SRBANKS; + constant CFG_SRCTRL_BANKSZ : integer := CFG_SR_CTRL_BANKSZ; + constant CFG_SRCTRL_ROMASEL : integer := CONFIG_SRCTRL_ROMASEL; +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; + constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; + constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; + constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; + constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; + constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; + constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; + constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; + constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; + +-- SDRAM controller + constant CFG_SDCTRL : integer := CONFIG_SDCTRL; + constant CFG_SDCTRL_INVCLK : integer := CONFIG_SDCTRL_INVCLK; + constant CFG_SDCTRL_SD64 : integer := CONFIG_SDCTRL_BUS64; + constant CFG_SDCTRL_PAGE : integer := CONFIG_SDCTRL_PAGE + CONFIG_SDCTRL_PROGPAGE; + +-- AHB ROM + constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; + constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; + constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; + constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; + constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; + +-- AHB RAM + constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; + constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; + constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; + +-- Gaisler Ethernet core + constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; + constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; + constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; + +-- CAN 2.0 interface + constant CFG_CAN : integer := CONFIG_CAN_ENABLE; + constant CFG_CANIO : integer := 16#CONFIG_CANIO#; + constant CFG_CANIRQ : integer := CONFIG_CANIRQ; + constant CFG_CANLOOP : integer := CONFIG_CANLOOP; + constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST; + constant CFG_CANFT : integer := CONFIG_CAN_FT; + +-- PCI interface + constant CFG_PCI : integer := CFG_PCITYPE; + constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#; + constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#; + constant CFG_PCIDEPTH : integer := CFG_PCIFIFO; + constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO; + +-- PCI arbiter + constant CFG_PCI_ARB : integer := CONFIG_PCI_ARBITER; + constant CFG_PCI_ARBAPB : integer := CONFIG_PCI_ARBITER_APB; + constant CFG_PCI_ARB_NGNT : integer := CONFIG_PCI_ARBITER_NREQ; + +-- PCI trace buffer + constant CFG_PCITBUFEN: integer := CONFIG_PCI_TRACE; + constant CFG_PCITBUF : integer := CFG_PCI_TRACEBUF; + +-- Spacewire interface + constant CFG_SPW_EN : integer := CONFIG_SPW_ENABLE; + constant CFG_SPW_NUM : integer := CONFIG_SPW_NUM; + constant CFG_SPW_AHBFIFO : integer := CONFIG_SPW_AHBFIFO; + constant CFG_SPW_RXFIFO : integer := CONFIG_SPW_RXFIFO; + constant CFG_SPW_RMAP : integer := CONFIG_SPW_RMAP; + constant CFG_SPW_RMAPBUF : integer := CONFIG_SPW_RMAPBUF; + constant CFG_SPW_RMAPCRC : integer := CONFIG_SPW_RMAPCRC; + constant CFG_SPW_NETLIST : integer := CONFIG_SPW_NETLIST; + constant CFG_SPW_FT : integer := CONFIG_SPW_FT; + constant CFG_SPW_GRSPW : integer := CONFIG_SPW_GRSPW; + constant CFG_SPW_RXUNAL : integer := CONFIG_SPW_RXUNAL; + constant CFG_SPW_DMACHAN : integer := CONFIG_SPW_DMACHAN; + constant CFG_SPW_PORTS : integer := CONFIG_SPW_PORTS; + constant CFG_SPW_INPUT : integer := CONFIG_SPW_INPUT; + constant CFG_SPW_OUTPUT : integer := CONFIG_SPW_OUTPUT; + constant CFG_SPW_RTSAME : integer := CONFIG_SPW_RTSAME; +-- UART 1 + constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; + constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; + +-- UART 2 + constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE; + constant CFG_UART2_FIFO : integer := CFG_UA2_FIFO; + +-- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; + constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; + +-- Modular timer + constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; + constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; + constant CFG_GPT_SW : integer := CONFIG_GPT_SW; + constant CFG_GPT_TW : integer := CONFIG_GPT_TW; + constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; + constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; + constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; + constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; + +-- GPIO port + constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; + constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; + constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; + +-- GRLIB debugging + constant CFG_DUART : integer := CONFIG_DEBUG_UART; + diff --git a/designs/EGSE_ICI/tkconfig.h b/designs/EGSE_ICI/tkconfig.h --- a/designs/EGSE_ICI/tkconfig.h +++ b/designs/EGSE_ICI/tkconfig.h @@ -1,1189 +1,1189 @@ -#if defined CONFIG_SYN_INFERRED -#define CONFIG_SYN_TECH inferred -#elif defined CONFIG_SYN_UMC -#define CONFIG_SYN_TECH umc -#elif defined CONFIG_SYN_RHUMC -#define CONFIG_SYN_TECH rhumc -#elif defined CONFIG_SYN_ATC18 -#define CONFIG_SYN_TECH atc18s -#elif defined CONFIG_SYN_ATC18RHA -#define CONFIG_SYN_TECH atc18rha -#elif defined CONFIG_SYN_AXCEL -#define CONFIG_SYN_TECH axcel -#elif defined CONFIG_SYN_PROASICPLUS -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_ALTERA -#define CONFIG_SYN_TECH altera -#elif defined CONFIG_SYN_STRATIX -#define CONFIG_SYN_TECH stratix1 -#elif defined CONFIG_SYN_STRATIXII -#define CONFIG_SYN_TECH stratix2 -#elif defined CONFIG_SYN_STRATIXIII -#define CONFIG_SYN_TECH stratix3 -#elif defined CONFIG_SYN_CYCLONEIII -#define CONFIG_SYN_TECH cyclone3 -#elif defined CONFIG_SYN_EASIC90 -#define CONFIG_SYN_TECH easic90 -#elif defined CONFIG_SYN_IHP25 -#define CONFIG_SYN_TECH ihp25 -#elif defined CONFIG_SYN_IHP25RH -#define CONFIG_SYN_TECH ihp25rh -#elif defined CONFIG_SYN_LATTICE -#define CONFIG_SYN_TECH lattice -#elif defined CONFIG_SYN_ECLIPSE -#define CONFIG_SYN_TECH eclipse -#elif defined CONFIG_SYN_PEREGRINE -#define CONFIG_SYN_TECH peregrine -#elif defined CONFIG_SYN_PROASIC -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_PROASIC3 -#define CONFIG_SYN_TECH apa3 -#elif defined CONFIG_SYN_SPARTAN2 -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEX -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEXE -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_SPARTAN3 -#define CONFIG_SYN_TECH spartan3 -#elif defined CONFIG_SYN_SPARTAN3E -#define CONFIG_SYN_TECH spartan3e -#elif defined CONFIG_SYN_VIRTEX2 -#define CONFIG_SYN_TECH virtex2 -#elif defined CONFIG_SYN_VIRTEX4 -#define CONFIG_SYN_TECH virtex4 -#elif defined CONFIG_SYN_VIRTEX5 -#define CONFIG_SYN_TECH virtex5 -#elif defined CONFIG_SYN_RH_LIB18T -#define CONFIG_SYN_TECH rhlib18t -#elif defined CONFIG_SYN_SMIC13 -#define CONFIG_SYN_TECH smic013 -#elif defined CONFIG_SYN_UT025CRH -#define CONFIG_SYN_TECH ut25 -#elif defined CONFIG_SYN_TSMC90 -#define CONFIG_SYN_TECH tsmc90 -#elif defined CONFIG_SYN_CUSTOM1 -#define CONFIG_SYN_TECH custom1 -#else -#error "unknown target technology" -#endif - -#if defined CONFIG_SYN_INFER_RAM -#define CFG_RAM_TECH inferred -#elif defined CONFIG_MEM_UMC -#define CFG_RAM_TECH umc -#elif defined CONFIG_MEM_RHUMC -#define CFG_RAM_TECH rhumc -#elif defined CONFIG_MEM_VIRAGE -#define CFG_RAM_TECH memvirage -#elif defined CONFIG_MEM_ARTISAN -#define CFG_RAM_TECH memartisan -#elif defined CONFIG_MEM_CUSTOM1 -#define CFG_RAM_TECH custom1 -#elif defined CONFIG_MEM_VIRAGE90 -#define CFG_RAM_TECH memvirage90 -#elif defined CONFIG_MEM_INFERRED -#define CFG_RAM_TECH inferred -#else -#define CFG_RAM_TECH CONFIG_SYN_TECH -#endif - -#if defined CONFIG_SYN_INFER_PADS -#define CFG_PAD_TECH inferred -#else -#define CFG_PAD_TECH CONFIG_SYN_TECH -#endif - -#ifndef CONFIG_SYN_NO_ASYNC -#define CONFIG_SYN_NO_ASYNC 0 -#endif - -#ifndef CONFIG_SYN_SCAN -#define CONFIG_SYN_SCAN 0 -#endif - - -#if defined CONFIG_CLK_ALTDLL -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_HCLKBUF -#define CFG_CLK_TECH axcel -#elif defined CONFIG_CLK_LATDLL -#define CFG_CLK_TECH lattice -#elif defined CONFIG_CLK_PRO3PLL -#define CFG_CLK_TECH apa3 -#elif defined CONFIG_CLK_CLKDLL -#define CFG_CLK_TECH virtex -#elif defined CONFIG_CLK_DCM -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_LIB18T -#define CFG_CLK_TECH rhlib18t -#elif defined CONFIG_CLK_RHUMC -#define CFG_CLK_TECH rhumc -#else -#define CFG_CLK_TECH inferred -#endif - -#ifndef CONFIG_CLK_MUL -#define CONFIG_CLK_MUL 2 -#endif - -#ifndef CONFIG_CLK_DIV -#define CONFIG_CLK_DIV 2 -#endif - -#ifndef CONFIG_OCLK_DIV -#define CONFIG_OCLK_DIV 2 -#endif - -#ifndef CONFIG_PCI_CLKDLL -#define CONFIG_PCI_CLKDLL 0 -#endif - -#ifndef CONFIG_PCI_SYSCLK -#define CONFIG_PCI_SYSCLK 0 -#endif - -#ifndef CONFIG_CLK_NOFB -#define CONFIG_CLK_NOFB 0 -#endif -#ifndef CONFIG_LEON3 -#define CONFIG_LEON3 0 -#endif - -#ifndef CONFIG_PROC_NUM -#define CONFIG_PROC_NUM 1 -#endif - -#ifndef CONFIG_IU_NWINDOWS -#define CONFIG_IU_NWINDOWS 8 -#endif - -#ifndef CONFIG_IU_RSTADDR -#define CONFIG_IU_RSTADDR 8 -#endif - -#ifndef CONFIG_IU_LDELAY -#define CONFIG_IU_LDELAY 1 -#endif - -#ifndef CONFIG_IU_WATCHPOINTS -#define CONFIG_IU_WATCHPOINTS 0 -#endif - -#ifdef CONFIG_IU_V8MULDIV -#ifdef CONFIG_IU_MUL_LATENCY_4 -#define CFG_IU_V8 1 -#elif defined CONFIG_IU_MUL_LATENCY_5 -#define CFG_IU_V8 2 -#elif defined CONFIG_IU_MUL_LATENCY_2 -#define CFG_IU_V8 16#32# -#endif -#else -#define CFG_IU_V8 0 -#endif - -#ifndef CONFIG_PWD -#define CONFIG_PWD 0 -#endif - -#ifndef CONFIG_IU_MUL_MAC -#define CONFIG_IU_MUL_MAC 0 -#endif - -#ifndef CONFIG_IU_SVT -#define CONFIG_IU_SVT 0 -#endif - -#if defined CONFIG_FPU_GRFPC1 -#define CONFIG_FPU_GRFPC 1 -#elif defined CONFIG_FPU_GRFPC2 -#define CONFIG_FPU_GRFPC 2 -#else -#define CONFIG_FPU_GRFPC 0 -#endif - -#if defined CONFIG_FPU_GRFPU_INFMUL -#define CONFIG_FPU_GRFPU_MUL 0 -#elif defined CONFIG_FPU_GRFPU_DWMUL -#define CONFIG_FPU_GRFPU_MUL 1 -#elif defined CONFIG_FPU_GRFPU_MODGEN -#define CONFIG_FPU_GRFPU_MUL 2 -#else -#define CONFIG_FPU_GRFPU_MUL 0 -#endif - -#if defined CONFIG_FPU_GRFPU_SH -#define CONFIG_FPU_GRFPU_SHARED 1 -#else -#define CONFIG_FPU_GRFPU_SHARED 0 -#endif - -#if defined CONFIG_FPU_GRFPU -#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) -#elif defined CONFIG_FPU_MEIKO -#define CONFIG_FPU 15 -#elif defined CONFIG_FPU_GRFPULITE -#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) -#else -#define CONFIG_FPU 0 -#endif - -#ifndef CONFIG_FPU_NETLIST -#define CONFIG_FPU_NETLIST 0 -#endif - -#ifndef CONFIG_ICACHE_ENABLE -#define CONFIG_ICACHE_ENABLE 0 -#endif - -#if defined CONFIG_ICACHE_ASSO1 -#define CFG_IU_ISETS 1 -#elif defined CONFIG_ICACHE_ASSO2 -#define CFG_IU_ISETS 2 -#elif defined CONFIG_ICACHE_ASSO3 -#define CFG_IU_ISETS 3 -#elif defined CONFIG_ICACHE_ASSO4 -#define CFG_IU_ISETS 4 -#else -#define CFG_IU_ISETS 1 -#endif - -#if defined CONFIG_ICACHE_SZ1 -#define CFG_ICACHE_SZ 1 -#elif defined CONFIG_ICACHE_SZ2 -#define CFG_ICACHE_SZ 2 -#elif defined CONFIG_ICACHE_SZ4 -#define CFG_ICACHE_SZ 4 -#elif defined CONFIG_ICACHE_SZ8 -#define CFG_ICACHE_SZ 8 -#elif defined CONFIG_ICACHE_SZ16 -#define CFG_ICACHE_SZ 16 -#elif defined CONFIG_ICACHE_SZ32 -#define CFG_ICACHE_SZ 32 -#elif defined CONFIG_ICACHE_SZ64 -#define CFG_ICACHE_SZ 64 -#elif defined CONFIG_ICACHE_SZ128 -#define CFG_ICACHE_SZ 128 -#elif defined CONFIG_ICACHE_SZ256 -#define CFG_ICACHE_SZ 256 -#else -#define CFG_ICACHE_SZ 1 -#endif - -#ifdef CONFIG_ICACHE_LZ16 -#define CFG_ILINE_SZ 4 -#else -#define CFG_ILINE_SZ 8 -#endif - -#if defined CONFIG_ICACHE_ALGORND -#define CFG_ICACHE_ALGORND 2 -#elif defined CONFIG_ICACHE_ALGOLRR -#define CFG_ICACHE_ALGORND 1 -#else -#define CFG_ICACHE_ALGORND 0 -#endif - -#ifndef CONFIG_ICACHE_LOCK -#define CONFIG_ICACHE_LOCK 0 -#endif - -#ifndef CONFIG_ICACHE_LRAM -#define CONFIG_ICACHE_LRAM 0 -#endif - -#ifndef CONFIG_ICACHE_LRSTART -#define CONFIG_ICACHE_LRSTART 8E -#endif - -#if defined CONFIG_ICACHE_LRAM_SZ2 -#define CFG_ILRAM_SIZE 2 -#elif defined CONFIG_ICACHE_LRAM_SZ4 -#define CFG_ILRAM_SIZE 4 -#elif defined CONFIG_ICACHE_LRAM_SZ8 -#define CFG_ILRAM_SIZE 8 -#elif defined CONFIG_ICACHE_LRAM_SZ16 -#define CFG_ILRAM_SIZE 16 -#elif defined CONFIG_ICACHE_LRAM_SZ32 -#define CFG_ILRAM_SIZE 32 -#elif defined CONFIG_ICACHE_LRAM_SZ64 -#define CFG_ILRAM_SIZE 64 -#elif defined CONFIG_ICACHE_LRAM_SZ128 -#define CFG_ILRAM_SIZE 128 -#elif defined CONFIG_ICACHE_LRAM_SZ256 -#define CFG_ILRAM_SIZE 256 -#else -#define CFG_ILRAM_SIZE 1 -#endif - - -#ifndef CONFIG_DCACHE_ENABLE -#define CONFIG_DCACHE_ENABLE 0 -#endif - -#if defined CONFIG_DCACHE_ASSO1 -#define CFG_IU_DSETS 1 -#elif defined CONFIG_DCACHE_ASSO2 -#define CFG_IU_DSETS 2 -#elif defined CONFIG_DCACHE_ASSO3 -#define CFG_IU_DSETS 3 -#elif defined CONFIG_DCACHE_ASSO4 -#define CFG_IU_DSETS 4 -#else -#define CFG_IU_DSETS 1 -#endif - -#if defined CONFIG_DCACHE_SZ1 -#define CFG_DCACHE_SZ 1 -#elif defined CONFIG_DCACHE_SZ2 -#define CFG_DCACHE_SZ 2 -#elif defined CONFIG_DCACHE_SZ4 -#define CFG_DCACHE_SZ 4 -#elif defined CONFIG_DCACHE_SZ8 -#define CFG_DCACHE_SZ 8 -#elif defined CONFIG_DCACHE_SZ16 -#define CFG_DCACHE_SZ 16 -#elif defined CONFIG_DCACHE_SZ32 -#define CFG_DCACHE_SZ 32 -#elif defined CONFIG_DCACHE_SZ64 -#define CFG_DCACHE_SZ 64 -#elif defined CONFIG_DCACHE_SZ128 -#define CFG_DCACHE_SZ 128 -#elif defined CONFIG_DCACHE_SZ256 -#define CFG_DCACHE_SZ 256 -#else -#define CFG_DCACHE_SZ 1 -#endif - -#ifdef CONFIG_DCACHE_LZ16 -#define CFG_DLINE_SZ 4 -#else -#define CFG_DLINE_SZ 8 -#endif - -#if defined CONFIG_DCACHE_ALGORND -#define CFG_DCACHE_ALGORND 2 -#elif defined CONFIG_DCACHE_ALGOLRR -#define CFG_DCACHE_ALGORND 1 -#else -#define CFG_DCACHE_ALGORND 0 -#endif - -#ifndef CONFIG_DCACHE_LOCK -#define CONFIG_DCACHE_LOCK 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP -#define CONFIG_DCACHE_SNOOP 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_SEPTAG -#define CONFIG_DCACHE_SNOOP_SEPTAG 0 -#endif - -#ifndef CONFIG_CACHE_FIXED -#define CONFIG_CACHE_FIXED 0 -#endif - -#ifndef CONFIG_DCACHE_LRAM -#define CONFIG_DCACHE_LRAM 0 -#endif - -#ifndef CONFIG_DCACHE_LRSTART -#define CONFIG_DCACHE_LRSTART 8F -#endif - -#if defined CONFIG_DCACHE_LRAM_SZ2 -#define CFG_DLRAM_SIZE 2 -#elif defined CONFIG_DCACHE_LRAM_SZ4 -#define CFG_DLRAM_SIZE 4 -#elif defined CONFIG_DCACHE_LRAM_SZ8 -#define CFG_DLRAM_SIZE 8 -#elif defined CONFIG_DCACHE_LRAM_SZ16 -#define CFG_DLRAM_SIZE 16 -#elif defined CONFIG_DCACHE_LRAM_SZ32 -#define CFG_DLRAM_SIZE 32 -#elif defined CONFIG_DCACHE_LRAM_SZ64 -#define CFG_DLRAM_SIZE 64 -#elif defined CONFIG_DCACHE_LRAM_SZ128 -#define CFG_DLRAM_SIZE 128 -#elif defined CONFIG_DCACHE_LRAM_SZ256 -#define CFG_DLRAM_SIZE 256 -#else -#define CFG_DLRAM_SIZE 1 -#endif - -#if defined CONFIG_MMU_PAGE_4K -#define CONFIG_MMU_PAGE 0 -#elif defined CONFIG_MMU_PAGE_8K -#define CONFIG_MMU_PAGE 1 -#elif defined CONFIG_MMU_PAGE_16K -#define CONFIG_MMU_PAGE 2 -#elif defined CONFIG_MMU_PAGE_32K -#define CONFIG_MMU_PAGE 3 -#elif defined CONFIG_MMU_PAGE_PROG -#define CONFIG_MMU_PAGE 4 -#else -#define CONFIG_MMU_PAGE 0 -#endif - -#ifdef CONFIG_MMU_ENABLE -#define CONFIG_MMUEN 1 - -#ifdef CONFIG_MMU_SPLIT -#define CONFIG_TLB_TYPE 0 -#endif -#ifdef CONFIG_MMU_COMBINED -#define CONFIG_TLB_TYPE 1 -#endif - -#ifdef CONFIG_MMU_REPARRAY -#define CONFIG_TLB_REP 0 -#endif -#ifdef CONFIG_MMU_REPINCREMENT -#define CONFIG_TLB_REP 1 -#endif - -#ifdef CONFIG_MMU_I2 -#define CONFIG_ITLBNUM 2 -#endif -#ifdef CONFIG_MMU_I4 -#define CONFIG_ITLBNUM 4 -#endif -#ifdef CONFIG_MMU_I8 -#define CONFIG_ITLBNUM 8 -#endif -#ifdef CONFIG_MMU_I16 -#define CONFIG_ITLBNUM 16 -#endif -#ifdef CONFIG_MMU_I32 -#define CONFIG_ITLBNUM 32 -#endif - -#define CONFIG_DTLBNUM 2 -#ifdef CONFIG_MMU_D2 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 2 -#endif -#ifdef CONFIG_MMU_D4 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 4 -#endif -#ifdef CONFIG_MMU_D8 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 8 -#endif -#ifdef CONFIG_MMU_D16 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 16 -#endif -#ifdef CONFIG_MMU_D32 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 32 -#endif -#ifdef CONFIG_MMU_FASTWB -#define CFG_MMU_FASTWB 1 -#else -#define CFG_MMU_FASTWB 0 -#endif - -#else -#define CONFIG_MMUEN 0 -#define CONFIG_ITLBNUM 2 -#define CONFIG_DTLBNUM 2 -#define CONFIG_TLB_TYPE 1 -#define CONFIG_TLB_REP 1 -#define CFG_MMU_FASTWB 0 -#endif - -#ifndef CONFIG_DSU_ENABLE -#define CONFIG_DSU_ENABLE 0 -#endif - -#if defined CONFIG_DSU_ITRACESZ1 -#define CFG_DSU_ITB 1 -#elif CONFIG_DSU_ITRACESZ2 -#define CFG_DSU_ITB 2 -#elif CONFIG_DSU_ITRACESZ4 -#define CFG_DSU_ITB 4 -#elif CONFIG_DSU_ITRACESZ8 -#define CFG_DSU_ITB 8 -#elif CONFIG_DSU_ITRACESZ16 -#define CFG_DSU_ITB 16 -#else -#define CFG_DSU_ITB 0 -#endif - -#if defined CONFIG_DSU_ATRACESZ1 -#define CFG_DSU_ATB 1 -#elif CONFIG_DSU_ATRACESZ2 -#define CFG_DSU_ATB 2 -#elif CONFIG_DSU_ATRACESZ4 -#define CFG_DSU_ATB 4 -#elif CONFIG_DSU_ATRACESZ8 -#define CFG_DSU_ATB 8 -#elif CONFIG_DSU_ATRACESZ16 -#define CFG_DSU_ATB 16 -#else -#define CFG_DSU_ATB 0 -#endif - -#ifndef CONFIG_LEON3FT_EN -#define CONFIG_LEON3FT_EN 0 -#endif - -#if defined CONFIG_IUFT_PAR -#define CONFIG_IUFT_EN 1 -#elif defined CONFIG_IUFT_DMR -#define CONFIG_IUFT_EN 2 -#elif defined CONFIG_IUFT_BCH -#define CONFIG_IUFT_EN 3 -#elif defined CONFIG_IUFT_TMR -#define CONFIG_IUFT_EN 4 -#else -#define CONFIG_IUFT_EN 0 -#endif -#ifndef CONFIG_RF_ERRINJ -#define CONFIG_RF_ERRINJ 0 -#endif - -#ifndef CONFIG_FPUFT_EN -#define CONFIG_FPUFT 0 -#else -#ifdef CONFIG_FPU_GRFPU -#define CONFIG_FPUFT 2 -#else -#define CONFIG_FPUFT 1 -#endif -#endif - -#ifndef CONFIG_CACHE_FT_EN -#define CONFIG_CACHE_FT_EN 0 -#endif -#ifndef CONFIG_CACHE_ERRINJ -#define CONFIG_CACHE_ERRINJ 0 -#endif - -#ifndef CONFIG_LEON3_NETLIST -#define CONFIG_LEON3_NETLIST 0 -#endif - -#ifdef CONFIG_DEBUG_PC32 -#define CFG_DEBUG_PC32 0 -#else -#define CFG_DEBUG_PC32 2 -#endif -#ifndef CONFIG_IU_DISAS -#define CONFIG_IU_DISAS 0 -#endif -#ifndef CONFIG_IU_DISAS_NET -#define CONFIG_IU_DISAS_NET 0 -#endif - - -#ifndef CONFIG_AHB_SPLIT -#define CONFIG_AHB_SPLIT 0 -#endif - -#ifndef CONFIG_AHB_RROBIN -#define CONFIG_AHB_RROBIN 0 -#endif - -#ifndef CONFIG_AHB_IOADDR -#define CONFIG_AHB_IOADDR FFF -#endif - -#ifndef CONFIG_APB_HADDR -#define CONFIG_APB_HADDR 800 -#endif - -#ifndef CONFIG_AHB_MON -#define CONFIG_AHB_MON 0 -#endif - -#ifndef CONFIG_AHB_MONERR -#define CONFIG_AHB_MONERR 0 -#endif - -#ifndef CONFIG_AHB_MONWAR -#define CONFIG_AHB_MONWAR 0 -#endif - -#ifndef CONFIG_DSU_UART -#define CONFIG_DSU_UART 0 -#endif - - -#ifndef CONFIG_DSU_JTAG -#define CONFIG_DSU_JTAG 0 -#endif - -#ifndef CONFIG_DSU_ETH -#define CONFIG_DSU_ETH 0 -#endif - -#ifndef CONFIG_DSU_IPMSB -#define CONFIG_DSU_IPMSB C0A8 -#endif - -#ifndef CONFIG_DSU_IPLSB -#define CONFIG_DSU_IPLSB 0033 -#endif - -#ifndef CONFIG_DSU_ETHMSB -#define CONFIG_DSU_ETHMSB 020000 -#endif - -#ifndef CONFIG_DSU_ETHLSB -#define CONFIG_DSU_ETHLSB 000009 -#endif - -#if defined CONFIG_DSU_ETHSZ1 -#define CFG_DSU_ETHB 1 -#elif CONFIG_DSU_ETHSZ2 -#define CFG_DSU_ETHB 2 -#elif CONFIG_DSU_ETHSZ4 -#define CFG_DSU_ETHB 4 -#elif CONFIG_DSU_ETHSZ8 -#define CFG_DSU_ETHB 8 -#elif CONFIG_DSU_ETHSZ16 -#define CFG_DSU_ETHB 16 -#elif CONFIG_DSU_ETHSZ32 -#define CFG_DSU_ETHB 32 -#else -#define CFG_DSU_ETHB 1 -#endif - -#ifndef CONFIG_DSU_ETH_PROG -#define CONFIG_DSU_ETH_PROG 0 -#endif - - -#ifndef CONFIG_SRCTRL -#define CONFIG_SRCTRL 0 -#endif - -#ifndef CONFIG_SRCTRL_PROMWS -#define CONFIG_SRCTRL_PROMWS 0 -#endif - -#ifndef CONFIG_SRCTRL_RAMWS -#define CONFIG_SRCTRL_RAMWS 0 -#endif - -#ifndef CONFIG_SRCTRL_IOWS -#define CONFIG_SRCTRL_IOWS 0 -#endif - -#ifndef CONFIG_SRCTRL_RMW -#define CONFIG_SRCTRL_RMW 0 -#endif - -#ifndef CONFIG_SRCTRL_8BIT -#define CONFIG_SRCTRL_8BIT 0 -#endif - - -#ifndef CONFIG_SRCTRL_ROMASEL -#define CONFIG_SRCTRL_ROMASEL 0 -#endif - -#if defined CONFIG_SRCTRL_SRBANKS1 -#define CFG_SR_CTRL_SRBANKS 1 -#elif defined CONFIG_SRCTRL_SRBANKS2 -#define CFG_SR_CTRL_SRBANKS 2 -#elif defined CONFIG_SRCTRL_SRBANKS3 -#define CFG_SR_CTRL_SRBANKS 3 -#elif defined CONFIG_SRCTRL_SRBANKS4 -#define CFG_SR_CTRL_SRBANKS 4 -#elif defined CONFIG_SRCTRL_SRBANKS5 -#define CFG_SR_CTRL_SRBANKS 5 -#else -#define CFG_SR_CTRL_SRBANKS 1 -#endif - -#if defined CONFIG_SRCTRL_BANKSZ0 -#define CFG_SR_CTRL_BANKSZ 0 -#elif defined CONFIG_SRCTRL_BANKSZ1 -#define CFG_SR_CTRL_BANKSZ 1 -#elif defined CONFIG_SRCTRL_BANKSZ2 -#define CFG_SR_CTRL_BANKSZ 2 -#elif defined CONFIG_SRCTRL_BANKSZ3 -#define CFG_SR_CTRL_BANKSZ 3 -#elif defined CONFIG_SRCTRL_BANKSZ4 -#define CFG_SR_CTRL_BANKSZ 4 -#elif defined CONFIG_SRCTRL_BANKSZ5 -#define CFG_SR_CTRL_BANKSZ 5 -#elif defined CONFIG_SRCTRL_BANKSZ6 -#define CFG_SR_CTRL_BANKSZ 6 -#elif defined CONFIG_SRCTRL_BANKSZ7 -#define CFG_SR_CTRL_BANKSZ 7 -#elif defined CONFIG_SRCTRL_BANKSZ8 -#define CFG_SR_CTRL_BANKSZ 8 -#elif defined CONFIG_SRCTRL_BANKSZ9 -#define CFG_SR_CTRL_BANKSZ 9 -#elif defined CONFIG_SRCTRL_BANKSZ10 -#define CFG_SR_CTRL_BANKSZ 10 -#elif defined CONFIG_SRCTRL_BANKSZ11 -#define CFG_SR_CTRL_BANKSZ 11 -#elif defined CONFIG_SRCTRL_BANKSZ12 -#define CFG_SR_CTRL_BANKSZ 12 -#elif defined CONFIG_SRCTRL_BANKSZ13 -#define CFG_SR_CTRL_BANKSZ 13 -#else -#define CFG_SR_CTRL_BANKSZ 0 -#endif -#ifndef CONFIG_MCTRL_LEON2 -#define CONFIG_MCTRL_LEON2 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM -#define CONFIG_MCTRL_SDRAM 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_SEPBUS -#define CONFIG_MCTRL_SDRAM_SEPBUS 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_INVCLK -#define CONFIG_MCTRL_SDRAM_INVCLK 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_BUS64 -#define CONFIG_MCTRL_SDRAM_BUS64 0 -#endif - -#ifndef CONFIG_MCTRL_8BIT -#define CONFIG_MCTRL_8BIT 0 -#endif - -#ifndef CONFIG_MCTRL_16BIT -#define CONFIG_MCTRL_16BIT 0 -#endif - -#ifndef CONFIG_MCTRL_5CS -#define CONFIG_MCTRL_5CS 0 -#endif - -#ifndef CONFIG_MCTRL_EDAC -#define CONFIG_MCTRL_EDAC 0 -#endif - -#ifndef CONFIG_MCTRL_PAGE -#define CONFIG_MCTRL_PAGE 0 -#endif - -#ifndef CONFIG_MCTRL_PROGPAGE -#define CONFIG_MCTRL_PROGPAGE 0 -#endif - -#ifndef CONFIG_SDCTRL -#define CONFIG_SDCTRL 0 -#endif - -#ifndef CONFIG_SDCTRL_SEPBUS -#define CONFIG_SDCTRL_SEPBUS 0 -#endif - -#ifndef CONFIG_SDCTRL_INVCLK -#define CONFIG_SDCTRL_INVCLK 0 -#endif - -#ifndef CONFIG_SDCTRL_BUS64 -#define CONFIG_SDCTRL_BUS64 0 -#endif - -#ifndef CONFIG_SDCTRL_PAGE -#define CONFIG_SDCTRL_PAGE 0 -#endif - -#ifndef CONFIG_SDCTRL_PROGPAGE -#define CONFIG_SDCTRL_PROGPAGE 0 -#endif - -#ifndef CONFIG_AHBROM_ENABLE -#define CONFIG_AHBROM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBROM_START -#define CONFIG_AHBROM_START 000 -#endif - -#ifndef CONFIG_AHBROM_PIPE -#define CONFIG_AHBROM_PIPE 0 -#endif - -#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) -#define CONFIG_ROM_START 100 -#else -#define CONFIG_ROM_START 000 -#endif - - -#ifndef CONFIG_AHBRAM_ENABLE -#define CONFIG_AHBRAM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBRAM_START -#define CONFIG_AHBRAM_START A00 -#endif - -#if defined CONFIG_AHBRAM_SZ1 -#define CFG_AHBRAMSZ 1 -#elif CONFIG_AHBRAM_SZ2 -#define CFG_AHBRAMSZ 2 -#elif CONFIG_AHBRAM_SZ4 -#define CFG_AHBRAMSZ 4 -#elif CONFIG_AHBRAM_SZ8 -#define CFG_AHBRAMSZ 8 -#elif CONFIG_AHBRAM_SZ16 -#define CFG_AHBRAMSZ 16 -#elif CONFIG_AHBRAM_SZ32 -#define CFG_AHBRAMSZ 32 -#elif CONFIG_AHBRAM_SZ64 -#define CFG_AHBRAMSZ 64 -#else -#define CFG_AHBRAMSZ 1 -#endif - -#ifndef CONFIG_GRETH_ENABLE -#define CONFIG_GRETH_ENABLE 0 -#endif - -#ifndef CONFIG_GRETH_GIGA -#define CONFIG_GRETH_GIGA 0 -#endif - -#if defined CONFIG_GRETH_FIFO4 -#define CFG_GRETH_FIFO 4 -#elif defined CONFIG_GRETH_FIFO8 -#define CFG_GRETH_FIFO 8 -#elif defined CONFIG_GRETH_FIFO16 -#define CFG_GRETH_FIFO 16 -#elif defined CONFIG_GRETH_FIFO32 -#define CFG_GRETH_FIFO 32 -#elif defined CONFIG_GRETH_FIFO64 -#define CFG_GRETH_FIFO 64 -#else -#define CFG_GRETH_FIFO 8 -#endif - -#ifndef CONFIG_CAN_ENABLE -#define CONFIG_CAN_ENABLE 0 -#endif - -#ifndef CONFIG_CANIO -#define CONFIG_CANIO 0 -#endif - -#ifndef CONFIG_CANIRQ -#define CONFIG_CANIRQ 0 -#endif - -#ifndef CONFIG_CANLOOP -#define CONFIG_CANLOOP 0 -#endif - -#ifndef CONFIG_CAN_SYNCRST -#define CONFIG_CAN_SYNCRST 0 -#endif - - -#ifndef CONFIG_CAN_FT -#define CONFIG_CAN_FT 0 -#endif -#if defined CONFIG_PCI_SIMPLE_TARGET -#define CFG_PCITYPE 1 -#elif defined CONFIG_PCI_MASTER_TARGET_DMA -#define CFG_PCITYPE 3 -#elif defined CONFIG_PCI_MASTER_TARGET -#define CFG_PCITYPE 2 -#else -#define CFG_PCITYPE 0 -#endif - -#ifndef CONFIG_PCI_VENDORID -#define CONFIG_PCI_VENDORID 0 -#endif - -#ifndef CONFIG_PCI_DEVICEID -#define CONFIG_PCI_DEVICEID 0 -#endif - -#ifndef CONFIG_PCI_REVID -#define CONFIG_PCI_REVID 0 -#endif - -#if defined CONFIG_PCI_FIFO0 -#define CFG_PCIFIFO 8 -#define CFG_PCI_ENFIFO 0 -#elif defined CONFIG_PCI_FIFO16 -#define CFG_PCIFIFO 16 -#elif defined CONFIG_PCI_FIFO32 -#define CFG_PCIFIFO 32 -#elif defined CONFIG_PCI_FIFO64 -#define CFG_PCIFIFO 64 -#elif defined CONFIG_PCI_FIFO128 -#define CFG_PCIFIFO 128 -#elif defined CONFIG_PCI_FIFO256 -#define CFG_PCIFIFO 256 -#else -#define CFG_PCIFIFO 8 -#endif - -#ifndef CFG_PCI_ENFIFO -#define CFG_PCI_ENFIFO 1 -#endif - - -#ifndef CONFIG_PCI_ARBITER_APB -#define CONFIG_PCI_ARBITER_APB 0 -#endif - -#ifndef CONFIG_PCI_ARBITER -#define CONFIG_PCI_ARBITER 0 -#endif - -#ifndef CONFIG_PCI_ARBITER_NREQ -#define CONFIG_PCI_ARBITER_NREQ 4 -#endif - -#ifndef CONFIG_PCI_TRACE -#define CONFIG_PCI_TRACE 0 -#endif - -#if defined CONFIG_PCI_TRACE512 -#define CFG_PCI_TRACEBUF 512 -#elif defined CONFIG_PCI_TRACE1024 -#define CFG_PCI_TRACEBUF 1024 -#elif defined CONFIG_PCI_TRACE2048 -#define CFG_PCI_TRACEBUF 2048 -#elif defined CONFIG_PCI_TRACE4096 -#define CFG_PCI_TRACEBUF 4096 -#else -#define CFG_PCI_TRACEBUF 256 -#endif - - -#ifndef CONFIG_SPW_ENABLE -#define CONFIG_SPW_ENABLE 0 -#endif - -#ifndef CONFIG_SPW_NUM -#define CONFIG_SPW_NUM 1 -#endif - -#if defined CONFIG_SPW_AHBFIFO4 -#define CONFIG_SPW_AHBFIFO 4 -#elif defined CONFIG_SPW_AHBFIFO8 -#define CONFIG_SPW_AHBFIFO 8 -#elif defined CONFIG_SPW_AHBFIFO16 -#define CONFIG_SPW_AHBFIFO 16 -#elif defined CONFIG_SPW_AHBFIFO32 -#define CONFIG_SPW_AHBFIFO 32 -#elif defined CONFIG_SPW_AHBFIFO64 -#define CONFIG_SPW_AHBFIFO 64 -#else -#define CONFIG_SPW_AHBFIFO 4 -#endif - -#if defined CONFIG_SPW_RXFIFO16 -#define CONFIG_SPW_RXFIFO 16 -#elif defined CONFIG_SPW_RXFIFO32 -#define CONFIG_SPW_RXFIFO 32 -#elif defined CONFIG_SPW_RXFIFO64 -#define CONFIG_SPW_RXFIFO 64 -#else -#define CONFIG_SPW_RXFIFO 16 -#endif - -#ifndef CONFIG_SPW_RMAP -#define CONFIG_SPW_RMAP 0 -#endif - -#if defined CONFIG_SPW_RMAPBUF2 -#define CONFIG_SPW_RMAPBUF 2 -#elif defined CONFIG_SPW_RMAPBUF4 -#define CONFIG_SPW_RMAPBUF 4 -#elif defined CONFIG_SPW_RMAPBUF6 -#define CONFIG_SPW_RMAPBUF 6 -#elif defined CONFIG_SPW_RMAPBUF8 -#define CONFIG_SPW_RMAPBUF 8 -#else -#define CONFIG_SPW_RMAPBUF 4 -#endif - -#ifndef CONFIG_SPW_RMAPCRC -#define CONFIG_SPW_RMAPCRC 0 -#endif - -#ifndef CONFIG_SPW_RXUNAL -#define CONFIG_SPW_RXUNAL 0 -#endif - -#ifndef CONFIG_SPW_NETLIST -#define CONFIG_SPW_NETLIST 0 -#endif - -#ifndef CONFIG_SPW_FT -#define CONFIG_SPW_FT 0 -#endif - -#if defined CONFIG_SPW_GRSPW1 -#define CONFIG_SPW_GRSPW 1 -#else -#define CONFIG_SPW_GRSPW 2 -#endif - -#ifndef CONFIG_SPW_DMACHAN -#define CONFIG_SPW_DMACHAN 1 -#endif - -#ifndef CONFIG_SPW_PORTS -#define CONFIG_SPW_PORTS 1 -#endif - -#if defined CONFIG_SPW_RX_SDR -#define CONFIG_SPW_INPUT 2 -#elif defined CONFIG_SPW_RX_DDR -#define CONFIG_SPW_INPUT 3 -#elif defined CONFIG_SPW_RX_XOR -#define CONFIG_SPW_INPUT 0 -#elif defined CONFIG_SPW_RX_AFLEX -#define CONFIG_SPW_INPUT 1 -#else -#define CONFIG_SPW_INPUT 2 -#endif - -#if defined CONFIG_SPW_TX_SDR -#define CONFIG_SPW_OUTPUT 0 -#elif defined CONFIG_SPW_TX_DDR -#define CONFIG_SPW_OUTPUT 1 -#elif defined CONFIG_SPW_TX_AFLEX -#define CONFIG_SPW_OUTPUT 2 -#else -#define CONFIG_SPW_OUTPUT 0 -#endif - -#ifndef CONFIG_SPW_RTSAME -#define CONFIG_SPW_RTSAME 0 -#endif -#ifndef CONFIG_UART1_ENABLE -#define CONFIG_UART1_ENABLE 0 -#endif - -#if defined CONFIG_UA1_FIFO1 -#define CFG_UA1_FIFO 1 -#elif defined CONFIG_UA1_FIFO2 -#define CFG_UA1_FIFO 2 -#elif defined CONFIG_UA1_FIFO4 -#define CFG_UA1_FIFO 4 -#elif defined CONFIG_UA1_FIFO8 -#define CFG_UA1_FIFO 8 -#elif defined CONFIG_UA1_FIFO16 -#define CFG_UA1_FIFO 16 -#elif defined CONFIG_UA1_FIFO32 -#define CFG_UA1_FIFO 32 -#else -#define CFG_UA1_FIFO 1 -#endif - -#ifndef CONFIG_UART2_ENABLE -#define CONFIG_UART2_ENABLE 0 -#endif - -#if defined CONFIG_UA2_FIFO1 -#define CFG_UA2_FIFO 1 -#elif defined CONFIG_UA2_FIFO2 -#define CFG_UA2_FIFO 2 -#elif defined CONFIG_UA2_FIFO4 -#define CFG_UA2_FIFO 4 -#elif defined CONFIG_UA2_FIFO8 -#define CFG_UA2_FIFO 8 -#elif defined CONFIG_UA2_FIFO16 -#define CFG_UA2_FIFO 16 -#elif defined CONFIG_UA2_FIFO32 -#define CFG_UA2_FIFO 32 -#else -#define CFG_UA2_FIFO 1 -#endif - -#ifndef CONFIG_IRQ3_ENABLE -#define CONFIG_IRQ3_ENABLE 0 -#endif -#ifndef CONFIG_IRQ3_NSEC -#define CONFIG_IRQ3_NSEC 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif - -#ifndef CONFIG_GPT_WDOGEN -#define CONFIG_GPT_WDOGEN 0 -#endif - -#ifndef CONFIG_GPT_WDOG -#define CONFIG_GPT_WDOG 0 -#endif - -#ifndef CONFIG_GRGPIO_ENABLE -#define CONFIG_GRGPIO_ENABLE 0 -#endif -#ifndef CONFIG_GRGPIO_IMASK -#define CONFIG_GRGPIO_IMASK 0000 -#endif -#ifndef CONFIG_GRGPIO_WIDTH -#define CONFIG_GRGPIO_WIDTH 1 -#endif - - -#ifndef CONFIG_DEBUG_UART -#define CONFIG_DEBUG_UART 0 -#endif +#if defined CONFIG_SYN_INFERRED +#define CONFIG_SYN_TECH inferred +#elif defined CONFIG_SYN_UMC +#define CONFIG_SYN_TECH umc +#elif defined CONFIG_SYN_RHUMC +#define CONFIG_SYN_TECH rhumc +#elif defined CONFIG_SYN_ATC18 +#define CONFIG_SYN_TECH atc18s +#elif defined CONFIG_SYN_ATC18RHA +#define CONFIG_SYN_TECH atc18rha +#elif defined CONFIG_SYN_AXCEL +#define CONFIG_SYN_TECH axcel +#elif defined CONFIG_SYN_PROASICPLUS +#define CONFIG_SYN_TECH proasic +#elif defined CONFIG_SYN_ALTERA +#define CONFIG_SYN_TECH altera +#elif defined CONFIG_SYN_STRATIX +#define CONFIG_SYN_TECH stratix1 +#elif defined CONFIG_SYN_STRATIXII +#define CONFIG_SYN_TECH stratix2 +#elif defined CONFIG_SYN_STRATIXIII +#define CONFIG_SYN_TECH stratix3 +#elif defined CONFIG_SYN_CYCLONEIII +#define CONFIG_SYN_TECH cyclone3 +#elif defined CONFIG_SYN_EASIC90 +#define CONFIG_SYN_TECH easic90 +#elif defined CONFIG_SYN_IHP25 +#define CONFIG_SYN_TECH ihp25 +#elif defined CONFIG_SYN_IHP25RH +#define CONFIG_SYN_TECH ihp25rh +#elif defined CONFIG_SYN_LATTICE +#define CONFIG_SYN_TECH lattice +#elif defined CONFIG_SYN_ECLIPSE +#define CONFIG_SYN_TECH eclipse +#elif defined CONFIG_SYN_PEREGRINE +#define CONFIG_SYN_TECH peregrine +#elif defined CONFIG_SYN_PROASIC +#define CONFIG_SYN_TECH proasic +#elif defined CONFIG_SYN_PROASIC3 +#define CONFIG_SYN_TECH apa3 +#elif defined CONFIG_SYN_SPARTAN2 +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_VIRTEX +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_VIRTEXE +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_SPARTAN3 +#define CONFIG_SYN_TECH spartan3 +#elif defined CONFIG_SYN_SPARTAN3E +#define CONFIG_SYN_TECH spartan3e +#elif defined CONFIG_SYN_VIRTEX2 +#define CONFIG_SYN_TECH virtex2 +#elif defined CONFIG_SYN_VIRTEX4 +#define CONFIG_SYN_TECH virtex4 +#elif defined CONFIG_SYN_VIRTEX5 +#define CONFIG_SYN_TECH virtex5 +#elif defined CONFIG_SYN_RH_LIB18T +#define CONFIG_SYN_TECH rhlib18t +#elif defined CONFIG_SYN_SMIC13 +#define CONFIG_SYN_TECH smic013 +#elif defined CONFIG_SYN_UT025CRH +#define CONFIG_SYN_TECH ut25 +#elif defined CONFIG_SYN_TSMC90 +#define CONFIG_SYN_TECH tsmc90 +#elif defined CONFIG_SYN_CUSTOM1 +#define CONFIG_SYN_TECH custom1 +#else +#error "unknown target technology" +#endif + +#if defined CONFIG_SYN_INFER_RAM +#define CFG_RAM_TECH inferred +#elif defined CONFIG_MEM_UMC +#define CFG_RAM_TECH umc +#elif defined CONFIG_MEM_RHUMC +#define CFG_RAM_TECH rhumc +#elif defined CONFIG_MEM_VIRAGE +#define CFG_RAM_TECH memvirage +#elif defined CONFIG_MEM_ARTISAN +#define CFG_RAM_TECH memartisan +#elif defined CONFIG_MEM_CUSTOM1 +#define CFG_RAM_TECH custom1 +#elif defined CONFIG_MEM_VIRAGE90 +#define CFG_RAM_TECH memvirage90 +#elif defined CONFIG_MEM_INFERRED +#define CFG_RAM_TECH inferred +#else +#define CFG_RAM_TECH CONFIG_SYN_TECH +#endif + +#if defined CONFIG_SYN_INFER_PADS +#define CFG_PAD_TECH inferred +#else +#define CFG_PAD_TECH CONFIG_SYN_TECH +#endif + +#ifndef CONFIG_SYN_NO_ASYNC +#define CONFIG_SYN_NO_ASYNC 0 +#endif + +#ifndef CONFIG_SYN_SCAN +#define CONFIG_SYN_SCAN 0 +#endif + + +#if defined CONFIG_CLK_ALTDLL +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_HCLKBUF +#define CFG_CLK_TECH axcel +#elif defined CONFIG_CLK_LATDLL +#define CFG_CLK_TECH lattice +#elif defined CONFIG_CLK_PRO3PLL +#define CFG_CLK_TECH apa3 +#elif defined CONFIG_CLK_CLKDLL +#define CFG_CLK_TECH virtex +#elif defined CONFIG_CLK_DCM +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_LIB18T +#define CFG_CLK_TECH rhlib18t +#elif defined CONFIG_CLK_RHUMC +#define CFG_CLK_TECH rhumc +#else +#define CFG_CLK_TECH inferred +#endif + +#ifndef CONFIG_CLK_MUL +#define CONFIG_CLK_MUL 2 +#endif + +#ifndef CONFIG_CLK_DIV +#define CONFIG_CLK_DIV 2 +#endif + +#ifndef CONFIG_OCLK_DIV +#define CONFIG_OCLK_DIV 2 +#endif + +#ifndef CONFIG_PCI_CLKDLL +#define CONFIG_PCI_CLKDLL 0 +#endif + +#ifndef CONFIG_PCI_SYSCLK +#define CONFIG_PCI_SYSCLK 0 +#endif + +#ifndef CONFIG_CLK_NOFB +#define CONFIG_CLK_NOFB 0 +#endif +#ifndef CONFIG_LEON3 +#define CONFIG_LEON3 0 +#endif + +#ifndef CONFIG_PROC_NUM +#define CONFIG_PROC_NUM 1 +#endif + +#ifndef CONFIG_IU_NWINDOWS +#define CONFIG_IU_NWINDOWS 8 +#endif + +#ifndef CONFIG_IU_RSTADDR +#define CONFIG_IU_RSTADDR 8 +#endif + +#ifndef CONFIG_IU_LDELAY +#define CONFIG_IU_LDELAY 1 +#endif + +#ifndef CONFIG_IU_WATCHPOINTS +#define CONFIG_IU_WATCHPOINTS 0 +#endif + +#ifdef CONFIG_IU_V8MULDIV +#ifdef CONFIG_IU_MUL_LATENCY_4 +#define CFG_IU_V8 1 +#elif defined CONFIG_IU_MUL_LATENCY_5 +#define CFG_IU_V8 2 +#elif defined CONFIG_IU_MUL_LATENCY_2 +#define CFG_IU_V8 16#32# +#endif +#else +#define CFG_IU_V8 0 +#endif + +#ifndef CONFIG_PWD +#define CONFIG_PWD 0 +#endif + +#ifndef CONFIG_IU_MUL_MAC +#define CONFIG_IU_MUL_MAC 0 +#endif + +#ifndef CONFIG_IU_SVT +#define CONFIG_IU_SVT 0 +#endif + +#if defined CONFIG_FPU_GRFPC1 +#define CONFIG_FPU_GRFPC 1 +#elif defined CONFIG_FPU_GRFPC2 +#define CONFIG_FPU_GRFPC 2 +#else +#define CONFIG_FPU_GRFPC 0 +#endif + +#if defined CONFIG_FPU_GRFPU_INFMUL +#define CONFIG_FPU_GRFPU_MUL 0 +#elif defined CONFIG_FPU_GRFPU_DWMUL +#define CONFIG_FPU_GRFPU_MUL 1 +#elif defined CONFIG_FPU_GRFPU_MODGEN +#define CONFIG_FPU_GRFPU_MUL 2 +#else +#define CONFIG_FPU_GRFPU_MUL 0 +#endif + +#if defined CONFIG_FPU_GRFPU_SH +#define CONFIG_FPU_GRFPU_SHARED 1 +#else +#define CONFIG_FPU_GRFPU_SHARED 0 +#endif + +#if defined CONFIG_FPU_GRFPU +#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) +#elif defined CONFIG_FPU_MEIKO +#define CONFIG_FPU 15 +#elif defined CONFIG_FPU_GRFPULITE +#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) +#else +#define CONFIG_FPU 0 +#endif + +#ifndef CONFIG_FPU_NETLIST +#define CONFIG_FPU_NETLIST 0 +#endif + +#ifndef CONFIG_ICACHE_ENABLE +#define CONFIG_ICACHE_ENABLE 0 +#endif + +#if defined CONFIG_ICACHE_ASSO1 +#define CFG_IU_ISETS 1 +#elif defined CONFIG_ICACHE_ASSO2 +#define CFG_IU_ISETS 2 +#elif defined CONFIG_ICACHE_ASSO3 +#define CFG_IU_ISETS 3 +#elif defined CONFIG_ICACHE_ASSO4 +#define CFG_IU_ISETS 4 +#else +#define CFG_IU_ISETS 1 +#endif + +#if defined CONFIG_ICACHE_SZ1 +#define CFG_ICACHE_SZ 1 +#elif defined CONFIG_ICACHE_SZ2 +#define CFG_ICACHE_SZ 2 +#elif defined CONFIG_ICACHE_SZ4 +#define CFG_ICACHE_SZ 4 +#elif defined CONFIG_ICACHE_SZ8 +#define CFG_ICACHE_SZ 8 +#elif defined CONFIG_ICACHE_SZ16 +#define CFG_ICACHE_SZ 16 +#elif defined CONFIG_ICACHE_SZ32 +#define CFG_ICACHE_SZ 32 +#elif defined CONFIG_ICACHE_SZ64 +#define CFG_ICACHE_SZ 64 +#elif defined CONFIG_ICACHE_SZ128 +#define CFG_ICACHE_SZ 128 +#elif defined CONFIG_ICACHE_SZ256 +#define CFG_ICACHE_SZ 256 +#else +#define CFG_ICACHE_SZ 1 +#endif + +#ifdef CONFIG_ICACHE_LZ16 +#define CFG_ILINE_SZ 4 +#else +#define CFG_ILINE_SZ 8 +#endif + +#if defined CONFIG_ICACHE_ALGORND +#define CFG_ICACHE_ALGORND 2 +#elif defined CONFIG_ICACHE_ALGOLRR +#define CFG_ICACHE_ALGORND 1 +#else +#define CFG_ICACHE_ALGORND 0 +#endif + +#ifndef CONFIG_ICACHE_LOCK +#define CONFIG_ICACHE_LOCK 0 +#endif + +#ifndef CONFIG_ICACHE_LRAM +#define CONFIG_ICACHE_LRAM 0 +#endif + +#ifndef CONFIG_ICACHE_LRSTART +#define CONFIG_ICACHE_LRSTART 8E +#endif + +#if defined CONFIG_ICACHE_LRAM_SZ2 +#define CFG_ILRAM_SIZE 2 +#elif defined CONFIG_ICACHE_LRAM_SZ4 +#define CFG_ILRAM_SIZE 4 +#elif defined CONFIG_ICACHE_LRAM_SZ8 +#define CFG_ILRAM_SIZE 8 +#elif defined CONFIG_ICACHE_LRAM_SZ16 +#define CFG_ILRAM_SIZE 16 +#elif defined CONFIG_ICACHE_LRAM_SZ32 +#define CFG_ILRAM_SIZE 32 +#elif defined CONFIG_ICACHE_LRAM_SZ64 +#define CFG_ILRAM_SIZE 64 +#elif defined CONFIG_ICACHE_LRAM_SZ128 +#define CFG_ILRAM_SIZE 128 +#elif defined CONFIG_ICACHE_LRAM_SZ256 +#define CFG_ILRAM_SIZE 256 +#else +#define CFG_ILRAM_SIZE 1 +#endif + + +#ifndef CONFIG_DCACHE_ENABLE +#define CONFIG_DCACHE_ENABLE 0 +#endif + +#if defined CONFIG_DCACHE_ASSO1 +#define CFG_IU_DSETS 1 +#elif defined CONFIG_DCACHE_ASSO2 +#define CFG_IU_DSETS 2 +#elif defined CONFIG_DCACHE_ASSO3 +#define CFG_IU_DSETS 3 +#elif defined CONFIG_DCACHE_ASSO4 +#define CFG_IU_DSETS 4 +#else +#define CFG_IU_DSETS 1 +#endif + +#if defined CONFIG_DCACHE_SZ1 +#define CFG_DCACHE_SZ 1 +#elif defined CONFIG_DCACHE_SZ2 +#define CFG_DCACHE_SZ 2 +#elif defined CONFIG_DCACHE_SZ4 +#define CFG_DCACHE_SZ 4 +#elif defined CONFIG_DCACHE_SZ8 +#define CFG_DCACHE_SZ 8 +#elif defined CONFIG_DCACHE_SZ16 +#define CFG_DCACHE_SZ 16 +#elif defined CONFIG_DCACHE_SZ32 +#define CFG_DCACHE_SZ 32 +#elif defined CONFIG_DCACHE_SZ64 +#define CFG_DCACHE_SZ 64 +#elif defined CONFIG_DCACHE_SZ128 +#define CFG_DCACHE_SZ 128 +#elif defined CONFIG_DCACHE_SZ256 +#define CFG_DCACHE_SZ 256 +#else +#define CFG_DCACHE_SZ 1 +#endif + +#ifdef CONFIG_DCACHE_LZ16 +#define CFG_DLINE_SZ 4 +#else +#define CFG_DLINE_SZ 8 +#endif + +#if defined CONFIG_DCACHE_ALGORND +#define CFG_DCACHE_ALGORND 2 +#elif defined CONFIG_DCACHE_ALGOLRR +#define CFG_DCACHE_ALGORND 1 +#else +#define CFG_DCACHE_ALGORND 0 +#endif + +#ifndef CONFIG_DCACHE_LOCK +#define CONFIG_DCACHE_LOCK 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP +#define CONFIG_DCACHE_SNOOP 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP_FAST +#define CONFIG_DCACHE_SNOOP_FAST 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP_SEPTAG +#define CONFIG_DCACHE_SNOOP_SEPTAG 0 +#endif + +#ifndef CONFIG_CACHE_FIXED +#define CONFIG_CACHE_FIXED 0 +#endif + +#ifndef CONFIG_DCACHE_LRAM +#define CONFIG_DCACHE_LRAM 0 +#endif + +#ifndef CONFIG_DCACHE_LRSTART +#define CONFIG_DCACHE_LRSTART 8F +#endif + +#if defined CONFIG_DCACHE_LRAM_SZ2 +#define CFG_DLRAM_SIZE 2 +#elif defined CONFIG_DCACHE_LRAM_SZ4 +#define CFG_DLRAM_SIZE 4 +#elif defined CONFIG_DCACHE_LRAM_SZ8 +#define CFG_DLRAM_SIZE 8 +#elif defined CONFIG_DCACHE_LRAM_SZ16 +#define CFG_DLRAM_SIZE 16 +#elif defined CONFIG_DCACHE_LRAM_SZ32 +#define CFG_DLRAM_SIZE 32 +#elif defined CONFIG_DCACHE_LRAM_SZ64 +#define CFG_DLRAM_SIZE 64 +#elif defined CONFIG_DCACHE_LRAM_SZ128 +#define CFG_DLRAM_SIZE 128 +#elif defined CONFIG_DCACHE_LRAM_SZ256 +#define CFG_DLRAM_SIZE 256 +#else +#define CFG_DLRAM_SIZE 1 +#endif + +#if defined CONFIG_MMU_PAGE_4K +#define CONFIG_MMU_PAGE 0 +#elif defined CONFIG_MMU_PAGE_8K +#define CONFIG_MMU_PAGE 1 +#elif defined CONFIG_MMU_PAGE_16K +#define CONFIG_MMU_PAGE 2 +#elif defined CONFIG_MMU_PAGE_32K +#define CONFIG_MMU_PAGE 3 +#elif defined CONFIG_MMU_PAGE_PROG +#define CONFIG_MMU_PAGE 4 +#else +#define CONFIG_MMU_PAGE 0 +#endif + +#ifdef CONFIG_MMU_ENABLE +#define CONFIG_MMUEN 1 + +#ifdef CONFIG_MMU_SPLIT +#define CONFIG_TLB_TYPE 0 +#endif +#ifdef CONFIG_MMU_COMBINED +#define CONFIG_TLB_TYPE 1 +#endif + +#ifdef CONFIG_MMU_REPARRAY +#define CONFIG_TLB_REP 0 +#endif +#ifdef CONFIG_MMU_REPINCREMENT +#define CONFIG_TLB_REP 1 +#endif + +#ifdef CONFIG_MMU_I2 +#define CONFIG_ITLBNUM 2 +#endif +#ifdef CONFIG_MMU_I4 +#define CONFIG_ITLBNUM 4 +#endif +#ifdef CONFIG_MMU_I8 +#define CONFIG_ITLBNUM 8 +#endif +#ifdef CONFIG_MMU_I16 +#define CONFIG_ITLBNUM 16 +#endif +#ifdef CONFIG_MMU_I32 +#define CONFIG_ITLBNUM 32 +#endif + +#define CONFIG_DTLBNUM 2 +#ifdef CONFIG_MMU_D2 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 2 +#endif +#ifdef CONFIG_MMU_D4 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 4 +#endif +#ifdef CONFIG_MMU_D8 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 8 +#endif +#ifdef CONFIG_MMU_D16 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 16 +#endif +#ifdef CONFIG_MMU_D32 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 32 +#endif +#ifdef CONFIG_MMU_FASTWB +#define CFG_MMU_FASTWB 1 +#else +#define CFG_MMU_FASTWB 0 +#endif + +#else +#define CONFIG_MMUEN 0 +#define CONFIG_ITLBNUM 2 +#define CONFIG_DTLBNUM 2 +#define CONFIG_TLB_TYPE 1 +#define CONFIG_TLB_REP 1 +#define CFG_MMU_FASTWB 0 +#endif + +#ifndef CONFIG_DSU_ENABLE +#define CONFIG_DSU_ENABLE 0 +#endif + +#if defined CONFIG_DSU_ITRACESZ1 +#define CFG_DSU_ITB 1 +#elif CONFIG_DSU_ITRACESZ2 +#define CFG_DSU_ITB 2 +#elif CONFIG_DSU_ITRACESZ4 +#define CFG_DSU_ITB 4 +#elif CONFIG_DSU_ITRACESZ8 +#define CFG_DSU_ITB 8 +#elif CONFIG_DSU_ITRACESZ16 +#define CFG_DSU_ITB 16 +#else +#define CFG_DSU_ITB 0 +#endif + +#if defined CONFIG_DSU_ATRACESZ1 +#define CFG_DSU_ATB 1 +#elif CONFIG_DSU_ATRACESZ2 +#define CFG_DSU_ATB 2 +#elif CONFIG_DSU_ATRACESZ4 +#define CFG_DSU_ATB 4 +#elif CONFIG_DSU_ATRACESZ8 +#define CFG_DSU_ATB 8 +#elif CONFIG_DSU_ATRACESZ16 +#define CFG_DSU_ATB 16 +#else +#define CFG_DSU_ATB 0 +#endif + +#ifndef CONFIG_LEON3FT_EN +#define CONFIG_LEON3FT_EN 0 +#endif + +#if defined CONFIG_IUFT_PAR +#define CONFIG_IUFT_EN 1 +#elif defined CONFIG_IUFT_DMR +#define CONFIG_IUFT_EN 2 +#elif defined CONFIG_IUFT_BCH +#define CONFIG_IUFT_EN 3 +#elif defined CONFIG_IUFT_TMR +#define CONFIG_IUFT_EN 4 +#else +#define CONFIG_IUFT_EN 0 +#endif +#ifndef CONFIG_RF_ERRINJ +#define CONFIG_RF_ERRINJ 0 +#endif + +#ifndef CONFIG_FPUFT_EN +#define CONFIG_FPUFT 0 +#else +#ifdef CONFIG_FPU_GRFPU +#define CONFIG_FPUFT 2 +#else +#define CONFIG_FPUFT 1 +#endif +#endif + +#ifndef CONFIG_CACHE_FT_EN +#define CONFIG_CACHE_FT_EN 0 +#endif +#ifndef CONFIG_CACHE_ERRINJ +#define CONFIG_CACHE_ERRINJ 0 +#endif + +#ifndef CONFIG_LEON3_NETLIST +#define CONFIG_LEON3_NETLIST 0 +#endif + +#ifdef CONFIG_DEBUG_PC32 +#define CFG_DEBUG_PC32 0 +#else +#define CFG_DEBUG_PC32 2 +#endif +#ifndef CONFIG_IU_DISAS +#define CONFIG_IU_DISAS 0 +#endif +#ifndef CONFIG_IU_DISAS_NET +#define CONFIG_IU_DISAS_NET 0 +#endif + + +#ifndef CONFIG_AHB_SPLIT +#define CONFIG_AHB_SPLIT 0 +#endif + +#ifndef CONFIG_AHB_RROBIN +#define CONFIG_AHB_RROBIN 0 +#endif + +#ifndef CONFIG_AHB_IOADDR +#define CONFIG_AHB_IOADDR FFF +#endif + +#ifndef CONFIG_APB_HADDR +#define CONFIG_APB_HADDR 800 +#endif + +#ifndef CONFIG_AHB_MON +#define CONFIG_AHB_MON 0 +#endif + +#ifndef CONFIG_AHB_MONERR +#define CONFIG_AHB_MONERR 0 +#endif + +#ifndef CONFIG_AHB_MONWAR +#define CONFIG_AHB_MONWAR 0 +#endif + +#ifndef CONFIG_DSU_UART +#define CONFIG_DSU_UART 0 +#endif + + +#ifndef CONFIG_DSU_JTAG +#define CONFIG_DSU_JTAG 0 +#endif + +#ifndef CONFIG_DSU_ETH +#define CONFIG_DSU_ETH 0 +#endif + +#ifndef CONFIG_DSU_IPMSB +#define CONFIG_DSU_IPMSB C0A8 +#endif + +#ifndef CONFIG_DSU_IPLSB +#define CONFIG_DSU_IPLSB 0033 +#endif + +#ifndef CONFIG_DSU_ETHMSB +#define CONFIG_DSU_ETHMSB 020000 +#endif + +#ifndef CONFIG_DSU_ETHLSB +#define CONFIG_DSU_ETHLSB 000009 +#endif + +#if defined CONFIG_DSU_ETHSZ1 +#define CFG_DSU_ETHB 1 +#elif CONFIG_DSU_ETHSZ2 +#define CFG_DSU_ETHB 2 +#elif CONFIG_DSU_ETHSZ4 +#define CFG_DSU_ETHB 4 +#elif CONFIG_DSU_ETHSZ8 +#define CFG_DSU_ETHB 8 +#elif CONFIG_DSU_ETHSZ16 +#define CFG_DSU_ETHB 16 +#elif CONFIG_DSU_ETHSZ32 +#define CFG_DSU_ETHB 32 +#else +#define CFG_DSU_ETHB 1 +#endif + +#ifndef CONFIG_DSU_ETH_PROG +#define CONFIG_DSU_ETH_PROG 0 +#endif + + +#ifndef CONFIG_SRCTRL +#define CONFIG_SRCTRL 0 +#endif + +#ifndef CONFIG_SRCTRL_PROMWS +#define CONFIG_SRCTRL_PROMWS 0 +#endif + +#ifndef CONFIG_SRCTRL_RAMWS +#define CONFIG_SRCTRL_RAMWS 0 +#endif + +#ifndef CONFIG_SRCTRL_IOWS +#define CONFIG_SRCTRL_IOWS 0 +#endif + +#ifndef CONFIG_SRCTRL_RMW +#define CONFIG_SRCTRL_RMW 0 +#endif + +#ifndef CONFIG_SRCTRL_8BIT +#define CONFIG_SRCTRL_8BIT 0 +#endif + + +#ifndef CONFIG_SRCTRL_ROMASEL +#define CONFIG_SRCTRL_ROMASEL 0 +#endif + +#if defined CONFIG_SRCTRL_SRBANKS1 +#define CFG_SR_CTRL_SRBANKS 1 +#elif defined CONFIG_SRCTRL_SRBANKS2 +#define CFG_SR_CTRL_SRBANKS 2 +#elif defined CONFIG_SRCTRL_SRBANKS3 +#define CFG_SR_CTRL_SRBANKS 3 +#elif defined CONFIG_SRCTRL_SRBANKS4 +#define CFG_SR_CTRL_SRBANKS 4 +#elif defined CONFIG_SRCTRL_SRBANKS5 +#define CFG_SR_CTRL_SRBANKS 5 +#else +#define CFG_SR_CTRL_SRBANKS 1 +#endif + +#if defined CONFIG_SRCTRL_BANKSZ0 +#define CFG_SR_CTRL_BANKSZ 0 +#elif defined CONFIG_SRCTRL_BANKSZ1 +#define CFG_SR_CTRL_BANKSZ 1 +#elif defined CONFIG_SRCTRL_BANKSZ2 +#define CFG_SR_CTRL_BANKSZ 2 +#elif defined CONFIG_SRCTRL_BANKSZ3 +#define CFG_SR_CTRL_BANKSZ 3 +#elif defined CONFIG_SRCTRL_BANKSZ4 +#define CFG_SR_CTRL_BANKSZ 4 +#elif defined CONFIG_SRCTRL_BANKSZ5 +#define CFG_SR_CTRL_BANKSZ 5 +#elif defined CONFIG_SRCTRL_BANKSZ6 +#define CFG_SR_CTRL_BANKSZ 6 +#elif defined CONFIG_SRCTRL_BANKSZ7 +#define CFG_SR_CTRL_BANKSZ 7 +#elif defined CONFIG_SRCTRL_BANKSZ8 +#define CFG_SR_CTRL_BANKSZ 8 +#elif defined CONFIG_SRCTRL_BANKSZ9 +#define CFG_SR_CTRL_BANKSZ 9 +#elif defined CONFIG_SRCTRL_BANKSZ10 +#define CFG_SR_CTRL_BANKSZ 10 +#elif defined CONFIG_SRCTRL_BANKSZ11 +#define CFG_SR_CTRL_BANKSZ 11 +#elif defined CONFIG_SRCTRL_BANKSZ12 +#define CFG_SR_CTRL_BANKSZ 12 +#elif defined CONFIG_SRCTRL_BANKSZ13 +#define CFG_SR_CTRL_BANKSZ 13 +#else +#define CFG_SR_CTRL_BANKSZ 0 +#endif +#ifndef CONFIG_MCTRL_LEON2 +#define CONFIG_MCTRL_LEON2 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM +#define CONFIG_MCTRL_SDRAM 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_SEPBUS +#define CONFIG_MCTRL_SDRAM_SEPBUS 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_INVCLK +#define CONFIG_MCTRL_SDRAM_INVCLK 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_BUS64 +#define CONFIG_MCTRL_SDRAM_BUS64 0 +#endif + +#ifndef CONFIG_MCTRL_8BIT +#define CONFIG_MCTRL_8BIT 0 +#endif + +#ifndef CONFIG_MCTRL_16BIT +#define CONFIG_MCTRL_16BIT 0 +#endif + +#ifndef CONFIG_MCTRL_5CS +#define CONFIG_MCTRL_5CS 0 +#endif + +#ifndef CONFIG_MCTRL_EDAC +#define CONFIG_MCTRL_EDAC 0 +#endif + +#ifndef CONFIG_MCTRL_PAGE +#define CONFIG_MCTRL_PAGE 0 +#endif + +#ifndef CONFIG_MCTRL_PROGPAGE +#define CONFIG_MCTRL_PROGPAGE 0 +#endif + +#ifndef CONFIG_SDCTRL +#define CONFIG_SDCTRL 0 +#endif + +#ifndef CONFIG_SDCTRL_SEPBUS +#define CONFIG_SDCTRL_SEPBUS 0 +#endif + +#ifndef CONFIG_SDCTRL_INVCLK +#define CONFIG_SDCTRL_INVCLK 0 +#endif + +#ifndef CONFIG_SDCTRL_BUS64 +#define CONFIG_SDCTRL_BUS64 0 +#endif + +#ifndef CONFIG_SDCTRL_PAGE +#define CONFIG_SDCTRL_PAGE 0 +#endif + +#ifndef CONFIG_SDCTRL_PROGPAGE +#define CONFIG_SDCTRL_PROGPAGE 0 +#endif + +#ifndef CONFIG_AHBROM_ENABLE +#define CONFIG_AHBROM_ENABLE 0 +#endif + +#ifndef CONFIG_AHBROM_START +#define CONFIG_AHBROM_START 000 +#endif + +#ifndef CONFIG_AHBROM_PIPE +#define CONFIG_AHBROM_PIPE 0 +#endif + +#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) +#define CONFIG_ROM_START 100 +#else +#define CONFIG_ROM_START 000 +#endif + + +#ifndef CONFIG_AHBRAM_ENABLE +#define CONFIG_AHBRAM_ENABLE 0 +#endif + +#ifndef CONFIG_AHBRAM_START +#define CONFIG_AHBRAM_START A00 +#endif + +#if defined CONFIG_AHBRAM_SZ1 +#define CFG_AHBRAMSZ 1 +#elif CONFIG_AHBRAM_SZ2 +#define CFG_AHBRAMSZ 2 +#elif CONFIG_AHBRAM_SZ4 +#define CFG_AHBRAMSZ 4 +#elif CONFIG_AHBRAM_SZ8 +#define CFG_AHBRAMSZ 8 +#elif CONFIG_AHBRAM_SZ16 +#define CFG_AHBRAMSZ 16 +#elif CONFIG_AHBRAM_SZ32 +#define CFG_AHBRAMSZ 32 +#elif CONFIG_AHBRAM_SZ64 +#define CFG_AHBRAMSZ 64 +#else +#define CFG_AHBRAMSZ 1 +#endif + +#ifndef CONFIG_GRETH_ENABLE +#define CONFIG_GRETH_ENABLE 0 +#endif + +#ifndef CONFIG_GRETH_GIGA +#define CONFIG_GRETH_GIGA 0 +#endif + +#if defined CONFIG_GRETH_FIFO4 +#define CFG_GRETH_FIFO 4 +#elif defined CONFIG_GRETH_FIFO8 +#define CFG_GRETH_FIFO 8 +#elif defined CONFIG_GRETH_FIFO16 +#define CFG_GRETH_FIFO 16 +#elif defined CONFIG_GRETH_FIFO32 +#define CFG_GRETH_FIFO 32 +#elif defined CONFIG_GRETH_FIFO64 +#define CFG_GRETH_FIFO 64 +#else +#define CFG_GRETH_FIFO 8 +#endif + +#ifndef CONFIG_CAN_ENABLE +#define CONFIG_CAN_ENABLE 0 +#endif + +#ifndef CONFIG_CANIO +#define CONFIG_CANIO 0 +#endif + +#ifndef CONFIG_CANIRQ +#define CONFIG_CANIRQ 0 +#endif + +#ifndef CONFIG_CANLOOP +#define CONFIG_CANLOOP 0 +#endif + +#ifndef CONFIG_CAN_SYNCRST +#define CONFIG_CAN_SYNCRST 0 +#endif + + +#ifndef CONFIG_CAN_FT +#define CONFIG_CAN_FT 0 +#endif +#if defined CONFIG_PCI_SIMPLE_TARGET +#define CFG_PCITYPE 1 +#elif defined CONFIG_PCI_MASTER_TARGET_DMA +#define CFG_PCITYPE 3 +#elif defined CONFIG_PCI_MASTER_TARGET +#define CFG_PCITYPE 2 +#else +#define CFG_PCITYPE 0 +#endif + +#ifndef CONFIG_PCI_VENDORID +#define CONFIG_PCI_VENDORID 0 +#endif + +#ifndef CONFIG_PCI_DEVICEID +#define CONFIG_PCI_DEVICEID 0 +#endif + +#ifndef CONFIG_PCI_REVID +#define CONFIG_PCI_REVID 0 +#endif + +#if defined CONFIG_PCI_FIFO0 +#define CFG_PCIFIFO 8 +#define CFG_PCI_ENFIFO 0 +#elif defined CONFIG_PCI_FIFO16 +#define CFG_PCIFIFO 16 +#elif defined CONFIG_PCI_FIFO32 +#define CFG_PCIFIFO 32 +#elif defined CONFIG_PCI_FIFO64 +#define CFG_PCIFIFO 64 +#elif defined CONFIG_PCI_FIFO128 +#define CFG_PCIFIFO 128 +#elif defined CONFIG_PCI_FIFO256 +#define CFG_PCIFIFO 256 +#else +#define CFG_PCIFIFO 8 +#endif + +#ifndef CFG_PCI_ENFIFO +#define CFG_PCI_ENFIFO 1 +#endif + + +#ifndef CONFIG_PCI_ARBITER_APB +#define CONFIG_PCI_ARBITER_APB 0 +#endif + +#ifndef CONFIG_PCI_ARBITER +#define CONFIG_PCI_ARBITER 0 +#endif + +#ifndef CONFIG_PCI_ARBITER_NREQ +#define CONFIG_PCI_ARBITER_NREQ 4 +#endif + +#ifndef CONFIG_PCI_TRACE +#define CONFIG_PCI_TRACE 0 +#endif + +#if defined CONFIG_PCI_TRACE512 +#define CFG_PCI_TRACEBUF 512 +#elif defined CONFIG_PCI_TRACE1024 +#define CFG_PCI_TRACEBUF 1024 +#elif defined CONFIG_PCI_TRACE2048 +#define CFG_PCI_TRACEBUF 2048 +#elif defined CONFIG_PCI_TRACE4096 +#define CFG_PCI_TRACEBUF 4096 +#else +#define CFG_PCI_TRACEBUF 256 +#endif + + +#ifndef CONFIG_SPW_ENABLE +#define CONFIG_SPW_ENABLE 0 +#endif + +#ifndef CONFIG_SPW_NUM +#define CONFIG_SPW_NUM 1 +#endif + +#if defined CONFIG_SPW_AHBFIFO4 +#define CONFIG_SPW_AHBFIFO 4 +#elif defined CONFIG_SPW_AHBFIFO8 +#define CONFIG_SPW_AHBFIFO 8 +#elif defined CONFIG_SPW_AHBFIFO16 +#define CONFIG_SPW_AHBFIFO 16 +#elif defined CONFIG_SPW_AHBFIFO32 +#define CONFIG_SPW_AHBFIFO 32 +#elif defined CONFIG_SPW_AHBFIFO64 +#define CONFIG_SPW_AHBFIFO 64 +#else +#define CONFIG_SPW_AHBFIFO 4 +#endif + +#if defined CONFIG_SPW_RXFIFO16 +#define CONFIG_SPW_RXFIFO 16 +#elif defined CONFIG_SPW_RXFIFO32 +#define CONFIG_SPW_RXFIFO 32 +#elif defined CONFIG_SPW_RXFIFO64 +#define CONFIG_SPW_RXFIFO 64 +#else +#define CONFIG_SPW_RXFIFO 16 +#endif + +#ifndef CONFIG_SPW_RMAP +#define CONFIG_SPW_RMAP 0 +#endif + +#if defined CONFIG_SPW_RMAPBUF2 +#define CONFIG_SPW_RMAPBUF 2 +#elif defined CONFIG_SPW_RMAPBUF4 +#define CONFIG_SPW_RMAPBUF 4 +#elif defined CONFIG_SPW_RMAPBUF6 +#define CONFIG_SPW_RMAPBUF 6 +#elif defined CONFIG_SPW_RMAPBUF8 +#define CONFIG_SPW_RMAPBUF 8 +#else +#define CONFIG_SPW_RMAPBUF 4 +#endif + +#ifndef CONFIG_SPW_RMAPCRC +#define CONFIG_SPW_RMAPCRC 0 +#endif + +#ifndef CONFIG_SPW_RXUNAL +#define CONFIG_SPW_RXUNAL 0 +#endif + +#ifndef CONFIG_SPW_NETLIST +#define CONFIG_SPW_NETLIST 0 +#endif + +#ifndef CONFIG_SPW_FT +#define CONFIG_SPW_FT 0 +#endif + +#if defined CONFIG_SPW_GRSPW1 +#define CONFIG_SPW_GRSPW 1 +#else +#define CONFIG_SPW_GRSPW 2 +#endif + +#ifndef CONFIG_SPW_DMACHAN +#define CONFIG_SPW_DMACHAN 1 +#endif + +#ifndef CONFIG_SPW_PORTS +#define CONFIG_SPW_PORTS 1 +#endif + +#if defined CONFIG_SPW_RX_SDR +#define CONFIG_SPW_INPUT 2 +#elif defined CONFIG_SPW_RX_DDR +#define CONFIG_SPW_INPUT 3 +#elif defined CONFIG_SPW_RX_XOR +#define CONFIG_SPW_INPUT 0 +#elif defined CONFIG_SPW_RX_AFLEX +#define CONFIG_SPW_INPUT 1 +#else +#define CONFIG_SPW_INPUT 2 +#endif + +#if defined CONFIG_SPW_TX_SDR +#define CONFIG_SPW_OUTPUT 0 +#elif defined CONFIG_SPW_TX_DDR +#define CONFIG_SPW_OUTPUT 1 +#elif defined CONFIG_SPW_TX_AFLEX +#define CONFIG_SPW_OUTPUT 2 +#else +#define CONFIG_SPW_OUTPUT 0 +#endif + +#ifndef CONFIG_SPW_RTSAME +#define CONFIG_SPW_RTSAME 0 +#endif +#ifndef CONFIG_UART1_ENABLE +#define CONFIG_UART1_ENABLE 0 +#endif + +#if defined CONFIG_UA1_FIFO1 +#define CFG_UA1_FIFO 1 +#elif defined CONFIG_UA1_FIFO2 +#define CFG_UA1_FIFO 2 +#elif defined CONFIG_UA1_FIFO4 +#define CFG_UA1_FIFO 4 +#elif defined CONFIG_UA1_FIFO8 +#define CFG_UA1_FIFO 8 +#elif defined CONFIG_UA1_FIFO16 +#define CFG_UA1_FIFO 16 +#elif defined CONFIG_UA1_FIFO32 +#define CFG_UA1_FIFO 32 +#else +#define CFG_UA1_FIFO 1 +#endif + +#ifndef CONFIG_UART2_ENABLE +#define CONFIG_UART2_ENABLE 0 +#endif + +#if defined CONFIG_UA2_FIFO1 +#define CFG_UA2_FIFO 1 +#elif defined CONFIG_UA2_FIFO2 +#define CFG_UA2_FIFO 2 +#elif defined CONFIG_UA2_FIFO4 +#define CFG_UA2_FIFO 4 +#elif defined CONFIG_UA2_FIFO8 +#define CFG_UA2_FIFO 8 +#elif defined CONFIG_UA2_FIFO16 +#define CFG_UA2_FIFO 16 +#elif defined CONFIG_UA2_FIFO32 +#define CFG_UA2_FIFO 32 +#else +#define CFG_UA2_FIFO 1 +#endif + +#ifndef CONFIG_IRQ3_ENABLE +#define CONFIG_IRQ3_ENABLE 0 +#endif +#ifndef CONFIG_IRQ3_NSEC +#define CONFIG_IRQ3_NSEC 0 +#endif +#ifndef CONFIG_GPT_ENABLE +#define CONFIG_GPT_ENABLE 0 +#endif + +#ifndef CONFIG_GPT_NTIM +#define CONFIG_GPT_NTIM 1 +#endif + +#ifndef CONFIG_GPT_SW +#define CONFIG_GPT_SW 8 +#endif + +#ifndef CONFIG_GPT_TW +#define CONFIG_GPT_TW 8 +#endif + +#ifndef CONFIG_GPT_IRQ +#define CONFIG_GPT_IRQ 8 +#endif + +#ifndef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 0 +#endif +#ifndef CONFIG_GPT_ENABLE +#define CONFIG_GPT_ENABLE 0 +#endif + +#ifndef CONFIG_GPT_NTIM +#define CONFIG_GPT_NTIM 1 +#endif + +#ifndef CONFIG_GPT_SW +#define CONFIG_GPT_SW 8 +#endif + +#ifndef CONFIG_GPT_TW +#define CONFIG_GPT_TW 8 +#endif + +#ifndef CONFIG_GPT_IRQ +#define CONFIG_GPT_IRQ 8 +#endif + +#ifndef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 0 +#endif + +#ifndef CONFIG_GPT_WDOGEN +#define CONFIG_GPT_WDOGEN 0 +#endif + +#ifndef CONFIG_GPT_WDOG +#define CONFIG_GPT_WDOG 0 +#endif + +#ifndef CONFIG_GRGPIO_ENABLE +#define CONFIG_GRGPIO_ENABLE 0 +#endif +#ifndef CONFIG_GRGPIO_IMASK +#define CONFIG_GRGPIO_IMASK 0000 +#endif +#ifndef CONFIG_GRGPIO_WIDTH +#define CONFIG_GRGPIO_WIDTH 1 +#endif + + +#ifndef CONFIG_DEBUG_UART +#define CONFIG_DEBUG_UART 0 +#endif diff --git a/designs/ICI4-3DCAM-Integ1/README.txt b/designs/ICI4-3DCAM-Integ1/README.txt --- a/designs/ICI4-3DCAM-Integ1/README.txt +++ b/designs/ICI4-3DCAM-Integ1/README.txt @@ -1,209 +1,209 @@ -This leon3 design is tailored to the Xilinx SP605 Spartan6 board - -Simulation and synthesis ------------------------- - -The design uses the Xilinx MIG memory interface with an AHB-2.0 -interface. The MIG source code cannot be distributed due to the -prohibitive Xilinx license, so the MIG must be re-generated with -coregen before simulation and synthesis can be done. - -To generate the MIG and install tne Xilinx unisim simulation -library, do as follows: - - make mig - make install-secureip - -This will ONLY work with ISE-13.2 installed, and the XILINX variable -properly set in the shell. To synthesize the design, do - - make ise - -and then - - make ise-prog-fpga - -to program the FPGA. - -Design specifics ----------------- - -* System reset is mapped to the CPU RESET button - -* The AHB and processor is clocked by a 60 MHz clock, generated - from the 33 MHz SYSACE clock using a DCM. You can change the frequency - generation in the clocks menu of xconfig. The DDR3 (MIG) controller - runs at 667 MHz. - -* The GRETH core is enabled and runs without problems at 100 Mbit. - Ethernet debug link is enabled and has IP 192.168.0.51. - 1 Gbit operation is also possible (requires grlib com release), - uncomment related timing constraints in the leon3mp.ucf first. - -* 16-bit flash prom can be read at address 0. It can be programmed - with GRMON version 1.1.16 or later. - -* DDR3 is working with the provided Xilinx MIG DDR3 controller. - If you want to simulate this design, first install the secure - IP models with: - - make install-secureip - - Then rebuild the scripts and simulation model: - - make distclean vsim - - Modelsim v6.6e or newer is required to build the secure IP models. - Note that the regular leon3 test bench cannot be run in simulation - as the DDR3 model lacks data pre-load. - -* The application UART1 is connected to the USB/UART connector - -* The SVGA frame buffer uses a separate port on the DDR3 controller, - and therefore does not noticeably affect the performance of the processor. - Default output is analog VGA, to switch to DVI mode execute this - command in grmon: - - i2c dvi init_l4itx_vga - -* The JTAG DSU interface is enabled and accesible via the USB/JTAG port. - Start grmon with -xilusb to connect. - -* Output from GRMON is: - -$ grmon -xilusb -u - - GRMON LEON debug monitor v1.1.51 professional version (debug) - - Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved. - For latest updates, go to http://www.gaisler.com/ - Comments or bug-reports to support@gaisler.com - - Xilinx cable: Cable type/rev : 0x3 - JTAG chain: xc6slx45t xccace - - GRLIB build version: 4111 - - initialising ............... - detected frequency: 50 MHz - SRAM waitstates: 1 - - Component Vendor - LEON3 SPARC V8 Processor Gaisler Research - AHB Debug JTAG TAP Gaisler Research - GR Ethernet MAC Gaisler Research - LEON2 Memory Controller European Space Agency - AHB/APB Bridge Gaisler Research - LEON3 Debug Support Unit Gaisler Research - Xilinx MIG DDR2 controller Gaisler Research - AHB/APB Bridge Gaisler Research - Generic APB UART Gaisler Research - Multi-processor Interrupt Ctrl Gaisler Research - Modular Timer Unit Gaisler Research - SVGA Controller Gaisler Research - AMBA Wrapper for OC I2C-master Gaisler Research - General purpose I/O port Gaisler Research - AHB status register Gaisler Research - - Use command 'info sys' to print a detailed report of attached cores - -grlib> inf sys -00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0) - ahb master 0 -01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1) - ahb master 1 -02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0) - ahb master 2, irq 12 - apb: 80000e00 - 80000f00 - Device index: dev0 - edcl ip 192.168.1.51, buffer 2 kbyte -00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1) - ahb: 00000000 - 20000000 - apb: 80000000 - 80000100 - 16-bit prom @ 0x00000000 -01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) - ahb: 80000000 - 80100000 -02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1) - ahb: 90000000 - a0000000 - AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0 - CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1 - icache 2 * 8 kbyte, 32 byte/line rnd - dcache 2 * 4 kbyte, 16 byte/line rnd -04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0) - ahb: 40000000 - 48000000 - apb: 80100000 - 80100100 - DDR2: 128 Mbyte -0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) - ahb: 80100000 - 80200000 -01.01:00c Gaisler Research Generic APB UART (ver 0x1) - irq 2 - apb: 80000100 - 80000200 - baud rate 38343, DSU mode (FIFO debug) -02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3) - apb: 80000200 - 80000300 -03.01:011 Gaisler Research Modular Timer Unit (ver 0x0) - irq 8 - apb: 80000300 - 80000400 - 8-bit scaler, 2 * 32-bit timers, divisor 50 -06.01:063 Gaisler Research SVGA Controller (ver 0x0) - apb: 80000600 - 80000700 - clk0: 50.00 MHz -09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3) - irq 14 - apb: 80000900 - 80000a00 -0a.01:01a Gaisler Research General purpose I/O port (ver 0x1) - apb: 80000a00 - 80000b00 -0f.01:052 Gaisler Research AHB status register (ver 0x0) - irq 7 - apb: 80000f00 - 80001000 -grlib> fla - - Intel-style 16-bit flash on D[31:16] - - Manuf. Intel - Device Strataflash P30 - - Device ID 02e44603e127ffff - User ID ffffffffffffffff - - - 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000 - - - CFI info - flash family : 1 - flash size : 256 Mbit - erase regions : 2 - erase blocks : 259 - write buffer : 1024 bytes - lock-down : yes - region 0 : 255 blocks of 128 Kbytes - region 1 : 4 blocks of 32 Kbytes - -grlib> lo ~/ibm/src/bench/leonbench/coremark.exe -section: .text at 0x40000000, size 102544 bytes -section: .data at 0x40019090, size 2788 bytes -total size: 105332 bytes (1.2 Mbit/s) -read 272 symbols -entry point: 0x40000000 -grlib> run -2K performance run parameters for coremark. -CoreMark Size : 666 -Total ticks : 19945918 -Total time (secs): 19.945918 -Iterations/Sec : 100.271143 -Iterations : 2000 -Compiler version : GCC4.4.2 -Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float -Memory location : STACK -seedcrc : 0xe9f5 -[0]crclist : 0xe714 -[0]crcmatrix : 0x1fd7 -[0]crcstate : 0x8e3a -[0]crcfinal : 0x4983 -Correct operation validated. See readme.txt for run and reporting rules. -CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack - -Program exited normally. -grlib> - +This leon3 design is tailored to the Xilinx SP605 Spartan6 board + +Simulation and synthesis +------------------------ + +The design uses the Xilinx MIG memory interface with an AHB-2.0 +interface. The MIG source code cannot be distributed due to the +prohibitive Xilinx license, so the MIG must be re-generated with +coregen before simulation and synthesis can be done. + +To generate the MIG and install tne Xilinx unisim simulation +library, do as follows: + + make mig + make install-secureip + +This will ONLY work with ISE-13.2 installed, and the XILINX variable +properly set in the shell. To synthesize the design, do + + make ise + +and then + + make ise-prog-fpga + +to program the FPGA. + +Design specifics +---------------- + +* System reset is mapped to the CPU RESET button + +* The AHB and processor is clocked by a 60 MHz clock, generated + from the 33 MHz SYSACE clock using a DCM. You can change the frequency + generation in the clocks menu of xconfig. The DDR3 (MIG) controller + runs at 667 MHz. + +* The GRETH core is enabled and runs without problems at 100 Mbit. + Ethernet debug link is enabled and has IP 192.168.0.51. + 1 Gbit operation is also possible (requires grlib com release), + uncomment related timing constraints in the leon3mp.ucf first. + +* 16-bit flash prom can be read at address 0. It can be programmed + with GRMON version 1.1.16 or later. + +* DDR3 is working with the provided Xilinx MIG DDR3 controller. + If you want to simulate this design, first install the secure + IP models with: + + make install-secureip + + Then rebuild the scripts and simulation model: + + make distclean vsim + + Modelsim v6.6e or newer is required to build the secure IP models. + Note that the regular leon3 test bench cannot be run in simulation + as the DDR3 model lacks data pre-load. + +* The application UART1 is connected to the USB/UART connector + +* The SVGA frame buffer uses a separate port on the DDR3 controller, + and therefore does not noticeably affect the performance of the processor. + Default output is analog VGA, to switch to DVI mode execute this + command in grmon: + + i2c dvi init_l4itx_vga + +* The JTAG DSU interface is enabled and accesible via the USB/JTAG port. + Start grmon with -xilusb to connect. + +* Output from GRMON is: + +$ grmon -xilusb -u + + GRMON LEON debug monitor v1.1.51 professional version (debug) + + Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved. + For latest updates, go to http://www.gaisler.com/ + Comments or bug-reports to support@gaisler.com + + Xilinx cable: Cable type/rev : 0x3 + JTAG chain: xc6slx45t xccace + + GRLIB build version: 4111 + + initialising ............... + detected frequency: 50 MHz + SRAM waitstates: 1 + + Component Vendor + LEON3 SPARC V8 Processor Gaisler Research + AHB Debug JTAG TAP Gaisler Research + GR Ethernet MAC Gaisler Research + LEON2 Memory Controller European Space Agency + AHB/APB Bridge Gaisler Research + LEON3 Debug Support Unit Gaisler Research + Xilinx MIG DDR2 controller Gaisler Research + AHB/APB Bridge Gaisler Research + Generic APB UART Gaisler Research + Multi-processor Interrupt Ctrl Gaisler Research + Modular Timer Unit Gaisler Research + SVGA Controller Gaisler Research + AMBA Wrapper for OC I2C-master Gaisler Research + General purpose I/O port Gaisler Research + AHB status register Gaisler Research + + Use command 'info sys' to print a detailed report of attached cores + +grlib> inf sys +00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0) + ahb master 0 +01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1) + ahb master 1 +02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0) + ahb master 2, irq 12 + apb: 80000e00 - 80000f00 + Device index: dev0 + edcl ip 192.168.1.51, buffer 2 kbyte +00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1) + ahb: 00000000 - 20000000 + apb: 80000000 - 80000100 + 16-bit prom @ 0x00000000 +01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) + ahb: 80000000 - 80100000 +02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1) + ahb: 90000000 - a0000000 + AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0 + CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1 + icache 2 * 8 kbyte, 32 byte/line rnd + dcache 2 * 4 kbyte, 16 byte/line rnd +04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0) + ahb: 40000000 - 48000000 + apb: 80100000 - 80100100 + DDR2: 128 Mbyte +0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) + ahb: 80100000 - 80200000 +01.01:00c Gaisler Research Generic APB UART (ver 0x1) + irq 2 + apb: 80000100 - 80000200 + baud rate 38343, DSU mode (FIFO debug) +02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3) + apb: 80000200 - 80000300 +03.01:011 Gaisler Research Modular Timer Unit (ver 0x0) + irq 8 + apb: 80000300 - 80000400 + 8-bit scaler, 2 * 32-bit timers, divisor 50 +06.01:063 Gaisler Research SVGA Controller (ver 0x0) + apb: 80000600 - 80000700 + clk0: 50.00 MHz +09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3) + irq 14 + apb: 80000900 - 80000a00 +0a.01:01a Gaisler Research General purpose I/O port (ver 0x1) + apb: 80000a00 - 80000b00 +0f.01:052 Gaisler Research AHB status register (ver 0x0) + irq 7 + apb: 80000f00 - 80001000 +grlib> fla + + Intel-style 16-bit flash on D[31:16] + + Manuf. Intel + Device Strataflash P30 + + Device ID 02e44603e127ffff + User ID ffffffffffffffff + + + 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000 + + + CFI info + flash family : 1 + flash size : 256 Mbit + erase regions : 2 + erase blocks : 259 + write buffer : 1024 bytes + lock-down : yes + region 0 : 255 blocks of 128 Kbytes + region 1 : 4 blocks of 32 Kbytes + +grlib> lo ~/ibm/src/bench/leonbench/coremark.exe +section: .text at 0x40000000, size 102544 bytes +section: .data at 0x40019090, size 2788 bytes +total size: 105332 bytes (1.2 Mbit/s) +read 272 symbols +entry point: 0x40000000 +grlib> run +2K performance run parameters for coremark. +CoreMark Size : 666 +Total ticks : 19945918 +Total time (secs): 19.945918 +Iterations/Sec : 100.271143 +Iterations : 2000 +Compiler version : GCC4.4.2 +Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float +Memory location : STACK +seedcrc : 0xe9f5 +[0]crclist : 0xe714 +[0]crcmatrix : 0x1fd7 +[0]crcstate : 0x8e3a +[0]crcfinal : 0x4983 +Correct operation validated. See readme.txt for run and reporting rules. +CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack + +Program exited normally. +grlib> + diff --git a/designs/ICI4-3DCAM-Integ1/config.vhd.h b/designs/ICI4-3DCAM-Integ1/config.vhd.h --- a/designs/ICI4-3DCAM-Integ1/config.vhd.h +++ b/designs/ICI4-3DCAM-Integ1/config.vhd.h @@ -1,190 +1,190 @@ --- Technology and synthesis options - constant CFG_FABTECH : integer := CONFIG_SYN_TECH; - constant CFG_MEMTECH : integer := CFG_RAM_TECH; - constant CFG_PADTECH : integer := CFG_PAD_TECH; - constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; - constant CFG_SCAN : integer := CONFIG_SYN_SCAN; - --- Clock generator - constant CFG_CLKTECH : integer := CFG_CLK_TECH; - constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; - constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; - constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; - constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV; - constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV; - constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; - constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; - constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; - --- LEON3 processor core - constant CFG_LEON3 : integer := CONFIG_LEON3; - constant CFG_NCPU : integer := CONFIG_PROC_NUM; - constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; - constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT; - constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; - constant CFG_BP : integer := CONFIG_IU_BP; - constant CFG_SVT : integer := CONFIG_IU_SVT; - constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; - constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; - constant CFG_NOTAG : integer := CONFIG_NOTAG; - constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; - constant CFG_PWD : integer := CONFIG_PWD*2; - constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED; - constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; - constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; - constant CFG_ISETS : integer := CFG_IU_ISETS; - constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; - constant CFG_ILINE : integer := CFG_ILINE_SZ; - constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; - constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; - constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; - constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; - constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; - constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; - constant CFG_DSETS : integer := CFG_IU_DSETS; - constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; - constant CFG_DLINE : integer := CFG_DLINE_SZ; - constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; - constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; - constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; - constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; - constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; - constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; - constant CFG_MMUEN : integer := CONFIG_MMUEN; - constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; - constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; - constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; - constant CFG_TLB_REP : integer := CONFIG_TLB_REP; - constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; - constant CFG_DSU : integer := CONFIG_DSU_ENABLE; - constant CFG_ITBSZ : integer := CFG_DSU_ITB; - constant CFG_ATBSZ : integer := CFG_DSU_ATB; - constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; - constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; - constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; - constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; - constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; - constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; - constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; - constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; - constant CFG_PCLOW : integer := CFG_DEBUG_PC32; - --- AMBA settings - constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; - constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; - constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; - constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; - constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; - constant CFG_AHB_MON : integer := CONFIG_AHB_MON; - constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; - constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; - constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS; - constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; - constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; - constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; - constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; - constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; - constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; - constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; - constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; - constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; - constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; - constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; - constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; - constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; - --- Xilinx MIG - constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2; - constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS; - constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS; - constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS; - constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS; - constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#; - - --- AHB status register - constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE; - constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV; - --- AHB ROM - constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; - constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; - constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; - constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; - constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; - constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; - constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; - constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; - constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; - --- UART 1 - constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; - constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; - constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; - --- Modular timer - constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; - constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; - constant CFG_GPT_SW : integer := CONFIG_GPT_SW; - constant CFG_GPT_TW : integer := CONFIG_GPT_TW; - constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; - constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; - constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; - constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; - constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; - constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; - --- VGA and PS2/ interface - constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE; - constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE; - constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE; - --- SPI memory controller - constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL; - constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD; - constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#; - constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE; - constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT; - constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER; - constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER; - constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT; - --- SPI controller - constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE; - constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM; - constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS; - constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO; - constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG; - constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE; - constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM; - constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL; - constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN; - constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN; - constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM; - constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT; - --- GRLIB debugging - constant CFG_DUART : integer := CONFIG_DEBUG_UART; - +-- Technology and synthesis options + constant CFG_FABTECH : integer := CONFIG_SYN_TECH; + constant CFG_MEMTECH : integer := CFG_RAM_TECH; + constant CFG_PADTECH : integer := CFG_PAD_TECH; + constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; + constant CFG_SCAN : integer := CONFIG_SYN_SCAN; + +-- Clock generator + constant CFG_CLKTECH : integer := CFG_CLK_TECH; + constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; + constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; + constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; + constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV; + constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV; + constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; + constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; + constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; + +-- LEON3 processor core + constant CFG_LEON3 : integer := CONFIG_LEON3; + constant CFG_NCPU : integer := CONFIG_PROC_NUM; + constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; + constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT; + constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; + constant CFG_BP : integer := CONFIG_IU_BP; + constant CFG_SVT : integer := CONFIG_IU_SVT; + constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; + constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; + constant CFG_NOTAG : integer := CONFIG_NOTAG; + constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; + constant CFG_PWD : integer := CONFIG_PWD*2; + constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED; + constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; + constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; + constant CFG_ISETS : integer := CFG_IU_ISETS; + constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; + constant CFG_ILINE : integer := CFG_ILINE_SZ; + constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; + constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; + constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; + constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; + constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; + constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; + constant CFG_DSETS : integer := CFG_IU_DSETS; + constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; + constant CFG_DLINE : integer := CFG_DLINE_SZ; + constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; + constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; + constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; + constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; + constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; + constant CFG_MMUEN : integer := CONFIG_MMUEN; + constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; + constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; + constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; + constant CFG_TLB_REP : integer := CONFIG_TLB_REP; + constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; + constant CFG_DSU : integer := CONFIG_DSU_ENABLE; + constant CFG_ITBSZ : integer := CFG_DSU_ITB; + constant CFG_ATBSZ : integer := CFG_DSU_ATB; + constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; + constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; + constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; + constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; + constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; + constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; + constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; + constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; + constant CFG_PCLOW : integer := CFG_DEBUG_PC32; + +-- AMBA settings + constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; + constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; + constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; + constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; + constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; + constant CFG_AHB_MON : integer := CONFIG_AHB_MON; + constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; + constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; + constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE; + +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; + +-- Ethernet DSU + constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS; + constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; + constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; + constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; + constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; + constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; + +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; + constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; + constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; + constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; + constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; + constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; + constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; + constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; + constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; + +-- Xilinx MIG + constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2; + constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS; + constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS; + constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS; + constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS; + constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#; + + +-- AHB status register + constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE; + constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV; + +-- AHB ROM + constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; + constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; + constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; + constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; + constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; + +-- AHB RAM + constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; + constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; + constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; + +-- Gaisler Ethernet core + constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; + constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; + constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; + +-- UART 1 + constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; + constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; + +-- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; + constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; + +-- Modular timer + constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; + constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; + constant CFG_GPT_SW : integer := CONFIG_GPT_SW; + constant CFG_GPT_TW : integer := CONFIG_GPT_TW; + constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; + constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; + constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; + constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; + +-- GPIO port + constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; + constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; + constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; + +-- VGA and PS2/ interface + constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE; + constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE; + constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE; + +-- SPI memory controller + constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL; + constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD; + constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#; + constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE; + constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT; + constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER; + constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER; + constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT; + +-- SPI controller + constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE; + constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM; + constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS; + constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO; + constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG; + constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE; + constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM; + constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL; + constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN; + constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN; + constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM; + constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT; + +-- GRLIB debugging + constant CFG_DUART : integer := CONFIG_DEBUG_UART; + diff --git a/designs/ICI4-3DCAM-Integ1/systest.c b/designs/ICI4-3DCAM-Integ1/systest.c --- a/designs/ICI4-3DCAM-Integ1/systest.c +++ b/designs/ICI4-3DCAM-Integ1/systest.c @@ -1,18 +1,18 @@ - -main() - -{ - report_start(); - - -// svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); - base_test(); -/* - greth_test(0x80000e00); - spw_test(0x80100A00); - spw_test(0x80100B00); - spw_test(0x80100C00); - svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); -*/ - report_end(); -} + +main() + +{ + report_start(); + + +// svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); + base_test(); +/* + greth_test(0x80000e00); + spw_test(0x80100A00); + spw_test(0x80100B00); + spw_test(0x80100C00); + svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); +*/ + report_end(); +} diff --git a/designs/ICI4-3DCAM-Integ1/tkconfig.h b/designs/ICI4-3DCAM-Integ1/tkconfig.h --- a/designs/ICI4-3DCAM-Integ1/tkconfig.h +++ b/designs/ICI4-3DCAM-Integ1/tkconfig.h @@ -1,1051 +1,1051 @@ -#if defined CONFIG_SYN_INFERRED -#define CONFIG_SYN_TECH inferred -#elif defined CONFIG_SYN_UMC -#define CONFIG_SYN_TECH umc -#elif defined CONFIG_SYN_RHUMC -#define CONFIG_SYN_TECH rhumc -#elif defined CONFIG_SYN_ATC18 -#define CONFIG_SYN_TECH atc18s -#elif defined CONFIG_SYN_ATC18RHA -#define CONFIG_SYN_TECH atc18rha -#elif defined CONFIG_SYN_AXCEL -#define CONFIG_SYN_TECH axcel -#elif defined CONFIG_SYN_AXDSP -#define CONFIG_SYN_TECH axdsp -#elif defined CONFIG_SYN_PROASICPLUS -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_ALTERA -#define CONFIG_SYN_TECH altera -#elif defined CONFIG_SYN_STRATIX -#define CONFIG_SYN_TECH stratix1 -#elif defined CONFIG_SYN_STRATIXII -#define CONFIG_SYN_TECH stratix2 -#elif defined CONFIG_SYN_STRATIXIII -#define CONFIG_SYN_TECH stratix3 -#elif defined CONFIG_SYN_CYCLONEIII -#define CONFIG_SYN_TECH cyclone3 -#elif defined CONFIG_SYN_EASIC45 -#define CONFIG_SYN_TECH easic45 -#elif defined CONFIG_SYN_EASIC90 -#define CONFIG_SYN_TECH easic90 -#elif defined CONFIG_SYN_IHP25 -#define CONFIG_SYN_TECH ihp25 -#elif defined CONFIG_SYN_IHP25RH -#define CONFIG_SYN_TECH ihp25rh -#elif defined CONFIG_SYN_CMOS9SF -#define CONFIG_SYN_TECH cmos9sf -#elif defined CONFIG_SYN_LATTICE -#define CONFIG_SYN_TECH lattice -#elif defined CONFIG_SYN_ECLIPSE -#define CONFIG_SYN_TECH eclipse -#elif defined CONFIG_SYN_PEREGRINE -#define CONFIG_SYN_TECH peregrine -#elif defined CONFIG_SYN_PROASIC -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_PROASIC3 -#define CONFIG_SYN_TECH apa3 -#elif defined CONFIG_SYN_PROASIC3E -#define CONFIG_SYN_TECH apa3e -#elif defined CONFIG_SYN_PROASIC3L -#define CONFIG_SYN_TECH apa3l -#elif defined CONFIG_SYN_IGLOO -#define CONFIG_SYN_TECH apa3 -#elif defined CONFIG_SYN_FUSION -#define CONFIG_SYN_TECH actfus -#elif defined CONFIG_SYN_SPARTAN2 -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEX -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEXE -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_SPARTAN3 -#define CONFIG_SYN_TECH spartan3 -#elif defined CONFIG_SYN_SPARTAN3E -#define CONFIG_SYN_TECH spartan3e -#elif defined CONFIG_SYN_SPARTAN6 -#define CONFIG_SYN_TECH spartan6 -#elif defined CONFIG_SYN_VIRTEX2 -#define CONFIG_SYN_TECH virtex2 -#elif defined CONFIG_SYN_VIRTEX4 -#define CONFIG_SYN_TECH virtex4 -#elif defined CONFIG_SYN_VIRTEX5 -#define CONFIG_SYN_TECH virtex5 -#elif defined CONFIG_SYN_VIRTEX6 -#define CONFIG_SYN_TECH virtex6 -#elif defined CONFIG_SYN_RH_LIB18T -#define CONFIG_SYN_TECH rhlib18t -#elif defined CONFIG_SYN_SMIC13 -#define CONFIG_SYN_TECH smic013 -#elif defined CONFIG_SYN_UT025CRH -#define CONFIG_SYN_TECH ut25 -#elif defined CONFIG_SYN_UT130HBD -#define CONFIG_SYN_TECH ut130 -#elif defined CONFIG_SYN_UT90NHBD -#define CONFIG_SYN_TECH ut90 -#elif defined CONFIG_SYN_TSMC90 -#define CONFIG_SYN_TECH tsmc90 -#elif defined CONFIG_SYN_TM65GPLUS -#define CONFIG_SYN_TECH tm65gpl -#elif defined CONFIG_SYN_CUSTOM1 -#define CONFIG_SYN_TECH custom1 -#else -#error "unknown target technology" -#endif - -#if defined CONFIG_SYN_INFER_RAM -#define CFG_RAM_TECH inferred -#elif defined CONFIG_MEM_UMC -#define CFG_RAM_TECH umc -#elif defined CONFIG_MEM_RHUMC -#define CFG_RAM_TECH rhumc -#elif defined CONFIG_MEM_VIRAGE -#define CFG_RAM_TECH memvirage -#elif defined CONFIG_MEM_ARTISAN -#define CFG_RAM_TECH memartisan -#elif defined CONFIG_MEM_CUSTOM1 -#define CFG_RAM_TECH custom1 -#elif defined CONFIG_MEM_VIRAGE90 -#define CFG_RAM_TECH memvirage90 -#elif defined CONFIG_MEM_INFERRED -#define CFG_RAM_TECH inferred -#else -#define CFG_RAM_TECH CONFIG_SYN_TECH -#endif - -#if defined CONFIG_SYN_INFER_PADS -#define CFG_PAD_TECH inferred -#else -#define CFG_PAD_TECH CONFIG_SYN_TECH -#endif - -#ifndef CONFIG_SYN_NO_ASYNC -#define CONFIG_SYN_NO_ASYNC 0 -#endif - -#ifndef CONFIG_SYN_SCAN -#define CONFIG_SYN_SCAN 0 -#endif - - -#if defined CONFIG_CLK_ALTDLL -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_HCLKBUF -#define CFG_CLK_TECH axcel -#elif defined CONFIG_CLK_LATDLL -#define CFG_CLK_TECH lattice -#elif defined CONFIG_CLK_PRO3PLL -#define CFG_CLK_TECH apa3 -#elif defined CONFIG_CLK_PRO3EPLL -#define CFG_CLK_TECH apa3e -#elif defined CONFIG_CLK_PRO3LPLL -#define CFG_CLK_TECH apa3l -#elif defined CONFIG_CLK_FUSPLL -#define CFG_CLK_TECH actfus -#elif defined CONFIG_CLK_CLKDLL -#define CFG_CLK_TECH virtex -#elif defined CONFIG_CLK_DCM -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_LIB18T -#define CFG_CLK_TECH rhlib18t -#elif defined CONFIG_CLK_RHUMC -#define CFG_CLK_TECH rhumc -#elif defined CONFIG_CLK_UT130HBD -#define CFG_CLK_TECH ut130 -#else -#define CFG_CLK_TECH inferred -#endif - -#ifndef CONFIG_CLK_MUL -#define CONFIG_CLK_MUL 2 -#endif - -#ifndef CONFIG_CLK_DIV -#define CONFIG_CLK_DIV 2 -#endif - -#ifndef CONFIG_OCLK_DIV -#define CONFIG_OCLK_DIV 1 -#endif - -#ifndef CONFIG_OCLKB_DIV -#define CONFIG_OCLKB_DIV 0 -#endif - -#ifndef CONFIG_OCLKC_DIV -#define CONFIG_OCLKC_DIV 0 -#endif - -#ifndef CONFIG_PCI_CLKDLL -#define CONFIG_PCI_CLKDLL 0 -#endif - -#ifndef CONFIG_PCI_SYSCLK -#define CONFIG_PCI_SYSCLK 0 -#endif - -#ifndef CONFIG_CLK_NOFB -#define CONFIG_CLK_NOFB 0 -#endif -#ifndef CONFIG_LEON3 -#define CONFIG_LEON3 0 -#endif - -#ifndef CONFIG_PROC_NUM -#define CONFIG_PROC_NUM 1 -#endif - -#ifndef CONFIG_IU_NWINDOWS -#define CONFIG_IU_NWINDOWS 8 -#endif - -#ifndef CONFIG_IU_RSTADDR -#define CONFIG_IU_RSTADDR 8 -#endif - -#ifndef CONFIG_IU_LDELAY -#define CONFIG_IU_LDELAY 1 -#endif - -#ifndef CONFIG_IU_WATCHPOINTS -#define CONFIG_IU_WATCHPOINTS 0 -#endif - -#ifdef CONFIG_IU_V8MULDIV -#ifdef CONFIG_IU_MUL_LATENCY_4 -#define CFG_IU_V8 1 -#elif defined CONFIG_IU_MUL_LATENCY_5 -#define CFG_IU_V8 2 -#elif defined CONFIG_IU_MUL_LATENCY_2 -#define CFG_IU_V8 16#32# -#endif -#else -#define CFG_IU_V8 0 -#endif - -#ifdef CONFIG_IU_MUL_MODGEN -#define CFG_IU_MUL_STRUCT 1 -#elif defined CONFIG_IU_MUL_TECHSPEC -#define CFG_IU_MUL_STRUCT 2 -#elif defined CONFIG_IU_MUL_DW -#define CFG_IU_MUL_STRUCT 3 -#else -#define CFG_IU_MUL_STRUCT 0 -#endif - -#ifndef CONFIG_PWD -#define CONFIG_PWD 0 -#endif - -#ifndef CONFIG_IU_MUL_MAC -#define CONFIG_IU_MUL_MAC 0 -#endif - -#ifndef CONFIG_IU_BP -#define CONFIG_IU_BP 0 -#endif - -#ifndef CONFIG_NOTAG -#define CONFIG_NOTAG 0 -#endif - -#ifndef CONFIG_IU_SVT -#define CONFIG_IU_SVT 0 -#endif - -#if defined CONFIG_FPU_GRFPC1 -#define CONFIG_FPU_GRFPC 1 -#elif defined CONFIG_FPU_GRFPC2 -#define CONFIG_FPU_GRFPC 2 -#else -#define CONFIG_FPU_GRFPC 0 -#endif - -#if defined CONFIG_FPU_GRFPU_INFMUL -#define CONFIG_FPU_GRFPU_MUL 0 -#elif defined CONFIG_FPU_GRFPU_DWMUL -#define CONFIG_FPU_GRFPU_MUL 1 -#elif defined CONFIG_FPU_GRFPU_MODGEN -#define CONFIG_FPU_GRFPU_MUL 2 -#elif defined CONFIG_FPU_GRFPU_TECHSPEC -#define CONFIG_FPU_GRFPU_MUL 3 -#else -#define CONFIG_FPU_GRFPU_MUL 0 -#endif - -#if defined CONFIG_FPU_GRFPU_SH -#define CONFIG_FPU_GRFPU_SHARED 1 -#else -#define CONFIG_FPU_GRFPU_SHARED 0 -#endif - -#if defined CONFIG_FPU_GRFPU -#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) -#elif defined CONFIG_FPU_MEIKO -#define CONFIG_FPU 15 -#elif defined CONFIG_FPU_GRFPULITE -#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) -#else -#define CONFIG_FPU 0 -#endif - -#ifndef CONFIG_FPU_NETLIST -#define CONFIG_FPU_NETLIST 0 -#endif - -#ifndef CONFIG_ICACHE_ENABLE -#define CONFIG_ICACHE_ENABLE 0 -#endif - -#if defined CONFIG_ICACHE_ASSO1 -#define CFG_IU_ISETS 1 -#elif defined CONFIG_ICACHE_ASSO2 -#define CFG_IU_ISETS 2 -#elif defined CONFIG_ICACHE_ASSO3 -#define CFG_IU_ISETS 3 -#elif defined CONFIG_ICACHE_ASSO4 -#define CFG_IU_ISETS 4 -#else -#define CFG_IU_ISETS 1 -#endif - -#if defined CONFIG_ICACHE_SZ1 -#define CFG_ICACHE_SZ 1 -#elif defined CONFIG_ICACHE_SZ2 -#define CFG_ICACHE_SZ 2 -#elif defined CONFIG_ICACHE_SZ4 -#define CFG_ICACHE_SZ 4 -#elif defined CONFIG_ICACHE_SZ8 -#define CFG_ICACHE_SZ 8 -#elif defined CONFIG_ICACHE_SZ16 -#define CFG_ICACHE_SZ 16 -#elif defined CONFIG_ICACHE_SZ32 -#define CFG_ICACHE_SZ 32 -#elif defined CONFIG_ICACHE_SZ64 -#define CFG_ICACHE_SZ 64 -#elif defined CONFIG_ICACHE_SZ128 -#define CFG_ICACHE_SZ 128 -#elif defined CONFIG_ICACHE_SZ256 -#define CFG_ICACHE_SZ 256 -#else -#define CFG_ICACHE_SZ 1 -#endif - -#ifdef CONFIG_ICACHE_LZ16 -#define CFG_ILINE_SZ 4 -#else -#define CFG_ILINE_SZ 8 -#endif - -#if defined CONFIG_ICACHE_ALGODIR -#define CFG_ICACHE_ALGORND 3 -#elif defined CONFIG_ICACHE_ALGORND -#define CFG_ICACHE_ALGORND 2 -#elif defined CONFIG_ICACHE_ALGOLRR -#define CFG_ICACHE_ALGORND 1 -#else -#define CFG_ICACHE_ALGORND 0 -#endif - -#ifndef CONFIG_ICACHE_LOCK -#define CONFIG_ICACHE_LOCK 0 -#endif - -#ifndef CONFIG_ICACHE_LRAM -#define CONFIG_ICACHE_LRAM 0 -#endif - -#ifndef CONFIG_ICACHE_LRSTART -#define CONFIG_ICACHE_LRSTART 8E -#endif - -#if defined CONFIG_ICACHE_LRAM_SZ2 -#define CFG_ILRAM_SIZE 2 -#elif defined CONFIG_ICACHE_LRAM_SZ4 -#define CFG_ILRAM_SIZE 4 -#elif defined CONFIG_ICACHE_LRAM_SZ8 -#define CFG_ILRAM_SIZE 8 -#elif defined CONFIG_ICACHE_LRAM_SZ16 -#define CFG_ILRAM_SIZE 16 -#elif defined CONFIG_ICACHE_LRAM_SZ32 -#define CFG_ILRAM_SIZE 32 -#elif defined CONFIG_ICACHE_LRAM_SZ64 -#define CFG_ILRAM_SIZE 64 -#elif defined CONFIG_ICACHE_LRAM_SZ128 -#define CFG_ILRAM_SIZE 128 -#elif defined CONFIG_ICACHE_LRAM_SZ256 -#define CFG_ILRAM_SIZE 256 -#else -#define CFG_ILRAM_SIZE 1 -#endif - - -#ifndef CONFIG_DCACHE_ENABLE -#define CONFIG_DCACHE_ENABLE 0 -#endif - -#if defined CONFIG_DCACHE_ASSO1 -#define CFG_IU_DSETS 1 -#elif defined CONFIG_DCACHE_ASSO2 -#define CFG_IU_DSETS 2 -#elif defined CONFIG_DCACHE_ASSO3 -#define CFG_IU_DSETS 3 -#elif defined CONFIG_DCACHE_ASSO4 -#define CFG_IU_DSETS 4 -#else -#define CFG_IU_DSETS 1 -#endif - -#if defined CONFIG_DCACHE_SZ1 -#define CFG_DCACHE_SZ 1 -#elif defined CONFIG_DCACHE_SZ2 -#define CFG_DCACHE_SZ 2 -#elif defined CONFIG_DCACHE_SZ4 -#define CFG_DCACHE_SZ 4 -#elif defined CONFIG_DCACHE_SZ8 -#define CFG_DCACHE_SZ 8 -#elif defined CONFIG_DCACHE_SZ16 -#define CFG_DCACHE_SZ 16 -#elif defined CONFIG_DCACHE_SZ32 -#define CFG_DCACHE_SZ 32 -#elif defined CONFIG_DCACHE_SZ64 -#define CFG_DCACHE_SZ 64 -#elif defined CONFIG_DCACHE_SZ128 -#define CFG_DCACHE_SZ 128 -#elif defined CONFIG_DCACHE_SZ256 -#define CFG_DCACHE_SZ 256 -#else -#define CFG_DCACHE_SZ 1 -#endif - -#ifdef CONFIG_DCACHE_LZ16 -#define CFG_DLINE_SZ 4 -#else -#define CFG_DLINE_SZ 8 -#endif - -#if defined CONFIG_DCACHE_ALGODIR -#define CFG_DCACHE_ALGORND 3 -#elif defined CONFIG_DCACHE_ALGORND -#define CFG_DCACHE_ALGORND 2 -#elif defined CONFIG_DCACHE_ALGOLRR -#define CFG_DCACHE_ALGORND 1 -#else -#define CFG_DCACHE_ALGORND 0 -#endif - -#ifndef CONFIG_DCACHE_LOCK -#define CONFIG_DCACHE_LOCK 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP -#define CONFIG_DCACHE_SNOOP 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_SEPTAG -#define CONFIG_DCACHE_SNOOP_SEPTAG 0 -#endif - -#ifndef CONFIG_CACHE_FIXED -#define CONFIG_CACHE_FIXED 0 -#endif - -#ifndef CONFIG_DCACHE_LRAM -#define CONFIG_DCACHE_LRAM 0 -#endif - -#ifndef CONFIG_DCACHE_LRSTART -#define CONFIG_DCACHE_LRSTART 8F -#endif - -#if defined CONFIG_DCACHE_LRAM_SZ2 -#define CFG_DLRAM_SIZE 2 -#elif defined CONFIG_DCACHE_LRAM_SZ4 -#define CFG_DLRAM_SIZE 4 -#elif defined CONFIG_DCACHE_LRAM_SZ8 -#define CFG_DLRAM_SIZE 8 -#elif defined CONFIG_DCACHE_LRAM_SZ16 -#define CFG_DLRAM_SIZE 16 -#elif defined CONFIG_DCACHE_LRAM_SZ32 -#define CFG_DLRAM_SIZE 32 -#elif defined CONFIG_DCACHE_LRAM_SZ64 -#define CFG_DLRAM_SIZE 64 -#elif defined CONFIG_DCACHE_LRAM_SZ128 -#define CFG_DLRAM_SIZE 128 -#elif defined CONFIG_DCACHE_LRAM_SZ256 -#define CFG_DLRAM_SIZE 256 -#else -#define CFG_DLRAM_SIZE 1 -#endif - -#if defined CONFIG_MMU_PAGE_4K -#define CONFIG_MMU_PAGE 0 -#elif defined CONFIG_MMU_PAGE_8K -#define CONFIG_MMU_PAGE 1 -#elif defined CONFIG_MMU_PAGE_16K -#define CONFIG_MMU_PAGE 2 -#elif defined CONFIG_MMU_PAGE_32K -#define CONFIG_MMU_PAGE 3 -#elif defined CONFIG_MMU_PAGE_PROG -#define CONFIG_MMU_PAGE 4 -#else -#define CONFIG_MMU_PAGE 0 -#endif - -#ifdef CONFIG_MMU_ENABLE -#define CONFIG_MMUEN 1 - -#ifdef CONFIG_MMU_SPLIT -#define CONFIG_TLB_TYPE 0 -#endif -#ifdef CONFIG_MMU_COMBINED -#define CONFIG_TLB_TYPE 1 -#endif - -#ifdef CONFIG_MMU_REPARRAY -#define CONFIG_TLB_REP 0 -#endif -#ifdef CONFIG_MMU_REPINCREMENT -#define CONFIG_TLB_REP 1 -#endif - -#ifdef CONFIG_MMU_I2 -#define CONFIG_ITLBNUM 2 -#endif -#ifdef CONFIG_MMU_I4 -#define CONFIG_ITLBNUM 4 -#endif -#ifdef CONFIG_MMU_I8 -#define CONFIG_ITLBNUM 8 -#endif -#ifdef CONFIG_MMU_I16 -#define CONFIG_ITLBNUM 16 -#endif -#ifdef CONFIG_MMU_I32 -#define CONFIG_ITLBNUM 32 -#endif - -#define CONFIG_DTLBNUM 2 -#ifdef CONFIG_MMU_D2 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 2 -#endif -#ifdef CONFIG_MMU_D4 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 4 -#endif -#ifdef CONFIG_MMU_D8 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 8 -#endif -#ifdef CONFIG_MMU_D16 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 16 -#endif -#ifdef CONFIG_MMU_D32 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 32 -#endif -#ifdef CONFIG_MMU_FASTWB -#define CFG_MMU_FASTWB 1 -#else -#define CFG_MMU_FASTWB 0 -#endif - -#else -#define CONFIG_MMUEN 0 -#define CONFIG_ITLBNUM 2 -#define CONFIG_DTLBNUM 2 -#define CONFIG_TLB_TYPE 1 -#define CONFIG_TLB_REP 1 -#define CFG_MMU_FASTWB 0 -#endif - -#ifndef CONFIG_DSU_ENABLE -#define CONFIG_DSU_ENABLE 0 -#endif - -#if defined CONFIG_DSU_ITRACESZ1 -#define CFG_DSU_ITB 1 -#elif CONFIG_DSU_ITRACESZ2 -#define CFG_DSU_ITB 2 -#elif CONFIG_DSU_ITRACESZ4 -#define CFG_DSU_ITB 4 -#elif CONFIG_DSU_ITRACESZ8 -#define CFG_DSU_ITB 8 -#elif CONFIG_DSU_ITRACESZ16 -#define CFG_DSU_ITB 16 -#else -#define CFG_DSU_ITB 0 -#endif - -#if defined CONFIG_DSU_ATRACESZ1 -#define CFG_DSU_ATB 1 -#elif CONFIG_DSU_ATRACESZ2 -#define CFG_DSU_ATB 2 -#elif CONFIG_DSU_ATRACESZ4 -#define CFG_DSU_ATB 4 -#elif CONFIG_DSU_ATRACESZ8 -#define CFG_DSU_ATB 8 -#elif CONFIG_DSU_ATRACESZ16 -#define CFG_DSU_ATB 16 -#else -#define CFG_DSU_ATB 0 -#endif - -#ifndef CONFIG_LEON3FT_EN -#define CONFIG_LEON3FT_EN 0 -#endif - -#if defined CONFIG_IUFT_PAR -#define CONFIG_IUFT_EN 1 -#elif defined CONFIG_IUFT_DMR -#define CONFIG_IUFT_EN 2 -#elif defined CONFIG_IUFT_BCH -#define CONFIG_IUFT_EN 3 -#elif defined CONFIG_IUFT_TMR -#define CONFIG_IUFT_EN 4 -#else -#define CONFIG_IUFT_EN 0 -#endif -#ifndef CONFIG_RF_ERRINJ -#define CONFIG_RF_ERRINJ 0 -#endif - -#ifndef CONFIG_FPUFT_EN -#define CONFIG_FPUFT 0 -#else -#ifdef CONFIG_FPU_GRFPU -#define CONFIG_FPUFT 2 -#else -#define CONFIG_FPUFT 1 -#endif -#endif - -#ifndef CONFIG_CACHE_FT_EN -#define CONFIG_CACHE_FT_EN 0 -#endif -#ifndef CONFIG_CACHE_ERRINJ -#define CONFIG_CACHE_ERRINJ 0 -#endif - -#ifndef CONFIG_LEON3_NETLIST -#define CONFIG_LEON3_NETLIST 0 -#endif - -#ifdef CONFIG_DEBUG_PC32 -#define CFG_DEBUG_PC32 0 -#else -#define CFG_DEBUG_PC32 2 -#endif -#ifndef CONFIG_IU_DISAS -#define CONFIG_IU_DISAS 0 -#endif -#ifndef CONFIG_IU_DISAS_NET -#define CONFIG_IU_DISAS_NET 0 -#endif - - -#ifndef CONFIG_AHB_SPLIT -#define CONFIG_AHB_SPLIT 0 -#endif - -#ifndef CONFIG_AHB_RROBIN -#define CONFIG_AHB_RROBIN 0 -#endif - -#ifndef CONFIG_AHB_IOADDR -#define CONFIG_AHB_IOADDR FFF -#endif - -#ifndef CONFIG_APB_HADDR -#define CONFIG_APB_HADDR 800 -#endif - -#ifndef CONFIG_AHB_MON -#define CONFIG_AHB_MON 0 -#endif - -#ifndef CONFIG_AHB_MONERR -#define CONFIG_AHB_MONERR 0 -#endif - -#ifndef CONFIG_AHB_MONWAR -#define CONFIG_AHB_MONWAR 0 -#endif - -#ifndef CONFIG_AHB_DTRACE -#define CONFIG_AHB_DTRACE 0 -#endif - -#ifndef CONFIG_DSU_JTAG -#define CONFIG_DSU_JTAG 0 -#endif - -#ifndef CONFIG_DSU_ETH -#define CONFIG_DSU_ETH 0 -#endif - -#ifndef CONFIG_DSU_IPMSB -#define CONFIG_DSU_IPMSB C0A8 -#endif - -#ifndef CONFIG_DSU_IPLSB -#define CONFIG_DSU_IPLSB 0033 -#endif - -#ifndef CONFIG_DSU_ETHMSB -#define CONFIG_DSU_ETHMSB 020000 -#endif - -#ifndef CONFIG_DSU_ETHLSB -#define CONFIG_DSU_ETHLSB 000009 -#endif - -#if defined CONFIG_DSU_ETHSZ1 -#define CFG_DSU_ETHB 1 -#elif CONFIG_DSU_ETHSZ2 -#define CFG_DSU_ETHB 2 -#elif CONFIG_DSU_ETHSZ4 -#define CFG_DSU_ETHB 4 -#elif CONFIG_DSU_ETHSZ8 -#define CFG_DSU_ETHB 8 -#elif CONFIG_DSU_ETHSZ16 -#define CFG_DSU_ETHB 16 -#elif CONFIG_DSU_ETHSZ32 -#define CFG_DSU_ETHB 32 -#else -#define CFG_DSU_ETHB 1 -#endif - -#ifndef CONFIG_DSU_ETH_PROG -#define CONFIG_DSU_ETH_PROG 0 -#endif - -#ifndef CONFIG_DSU_ETH_DIS -#define CONFIG_DSU_ETH_DIS 0 -#endif - -#ifndef CONFIG_MCTRL_LEON2 -#define CONFIG_MCTRL_LEON2 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM -#define CONFIG_MCTRL_SDRAM 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_SEPBUS -#define CONFIG_MCTRL_SDRAM_SEPBUS 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_INVCLK -#define CONFIG_MCTRL_SDRAM_INVCLK 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_BUS64 -#define CONFIG_MCTRL_SDRAM_BUS64 0 -#endif - -#ifndef CONFIG_MCTRL_8BIT -#define CONFIG_MCTRL_8BIT 0 -#endif - -#ifndef CONFIG_MCTRL_16BIT -#define CONFIG_MCTRL_16BIT 0 -#endif - -#ifndef CONFIG_MCTRL_5CS -#define CONFIG_MCTRL_5CS 0 -#endif - -#ifndef CONFIG_MCTRL_EDAC -#define CONFIG_MCTRL_EDAC 0 -#endif - -#ifndef CONFIG_MCTRL_PAGE -#define CONFIG_MCTRL_PAGE 0 -#endif - -#ifndef CONFIG_MCTRL_PROGPAGE -#define CONFIG_MCTRL_PROGPAGE 0 -#endif - - -#ifndef CONFIG_MIG_DDR2 -#define CONFIG_MIG_DDR2 0 -#endif - -#ifndef CONFIG_MIG_RANKS -#define CONFIG_MIG_RANKS 1 -#endif - -#ifndef CONFIG_MIG_COLBITS -#define CONFIG_MIG_COLBITS 10 -#endif - -#ifndef CONFIG_MIG_ROWBITS -#define CONFIG_MIG_ROWBITS 13 -#endif - -#ifndef CONFIG_MIG_BANKBITS -#define CONFIG_MIG_BANKBITS 2 -#endif - -#ifndef CONFIG_MIG_HMASK -#define CONFIG_MIG_HMASK F00 -#endif -#ifndef CONFIG_AHBSTAT_ENABLE -#define CONFIG_AHBSTAT_ENABLE 0 -#endif - -#ifndef CONFIG_AHBSTAT_NFTSLV -#define CONFIG_AHBSTAT_NFTSLV 1 -#endif - -#ifndef CONFIG_AHBROM_ENABLE -#define CONFIG_AHBROM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBROM_START -#define CONFIG_AHBROM_START 000 -#endif - -#ifndef CONFIG_AHBROM_PIPE -#define CONFIG_AHBROM_PIPE 0 -#endif - -#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) -#define CONFIG_ROM_START 100 -#else -#define CONFIG_ROM_START 000 -#endif - - -#ifndef CONFIG_AHBRAM_ENABLE -#define CONFIG_AHBRAM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBRAM_START -#define CONFIG_AHBRAM_START A00 -#endif - -#if defined CONFIG_AHBRAM_SZ1 -#define CFG_AHBRAMSZ 1 -#elif CONFIG_AHBRAM_SZ2 -#define CFG_AHBRAMSZ 2 -#elif CONFIG_AHBRAM_SZ4 -#define CFG_AHBRAMSZ 4 -#elif CONFIG_AHBRAM_SZ8 -#define CFG_AHBRAMSZ 8 -#elif CONFIG_AHBRAM_SZ16 -#define CFG_AHBRAMSZ 16 -#elif CONFIG_AHBRAM_SZ32 -#define CFG_AHBRAMSZ 32 -#elif CONFIG_AHBRAM_SZ64 -#define CFG_AHBRAMSZ 64 -#else -#define CFG_AHBRAMSZ 1 -#endif - -#ifndef CONFIG_GRETH_ENABLE -#define CONFIG_GRETH_ENABLE 0 -#endif - -#ifndef CONFIG_GRETH_GIGA -#define CONFIG_GRETH_GIGA 0 -#endif - -#if defined CONFIG_GRETH_FIFO4 -#define CFG_GRETH_FIFO 4 -#elif defined CONFIG_GRETH_FIFO8 -#define CFG_GRETH_FIFO 8 -#elif defined CONFIG_GRETH_FIFO16 -#define CFG_GRETH_FIFO 16 -#elif defined CONFIG_GRETH_FIFO32 -#define CFG_GRETH_FIFO 32 -#elif defined CONFIG_GRETH_FIFO64 -#define CFG_GRETH_FIFO 64 -#else -#define CFG_GRETH_FIFO 8 -#endif - -#ifndef CONFIG_UART1_ENABLE -#define CONFIG_UART1_ENABLE 0 -#endif - -#if defined CONFIG_UA1_FIFO1 -#define CFG_UA1_FIFO 1 -#elif defined CONFIG_UA1_FIFO2 -#define CFG_UA1_FIFO 2 -#elif defined CONFIG_UA1_FIFO4 -#define CFG_UA1_FIFO 4 -#elif defined CONFIG_UA1_FIFO8 -#define CFG_UA1_FIFO 8 -#elif defined CONFIG_UA1_FIFO16 -#define CFG_UA1_FIFO 16 -#elif defined CONFIG_UA1_FIFO32 -#define CFG_UA1_FIFO 32 -#else -#define CFG_UA1_FIFO 1 -#endif - -#ifndef CONFIG_IRQ3_ENABLE -#define CONFIG_IRQ3_ENABLE 0 -#endif -#ifndef CONFIG_IRQ3_NSEC -#define CONFIG_IRQ3_NSEC 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif - -#ifndef CONFIG_GPT_WDOGEN -#define CONFIG_GPT_WDOGEN 0 -#endif - -#ifndef CONFIG_GPT_WDOG -#define CONFIG_GPT_WDOG 0 -#endif - -#ifndef CONFIG_GRGPIO_ENABLE -#define CONFIG_GRGPIO_ENABLE 0 -#endif -#ifndef CONFIG_GRGPIO_IMASK -#define CONFIG_GRGPIO_IMASK 0000 -#endif -#ifndef CONFIG_GRGPIO_WIDTH -#define CONFIG_GRGPIO_WIDTH 1 -#endif - -#ifndef CONFIG_VGA_ENABLE -#define CONFIG_VGA_ENABLE 0 -#endif -#ifndef CONFIG_SVGA_ENABLE -#define CONFIG_SVGA_ENABLE 0 -#endif -#ifndef CONFIG_KBD_ENABLE -#define CONFIG_KBD_ENABLE 0 -#endif - - -#ifndef CONFIG_SPIMCTRL -#define CONFIG_SPIMCTRL 0 -#endif - -#ifndef CONFIG_SPIMCTRL_SDCARD -#define CONFIG_SPIMCTRL_SDCARD 0 -#endif - -#ifndef CONFIG_SPIMCTRL_READCMD -#define CONFIG_SPIMCTRL_READCMD 0 -#endif - -#ifndef CONFIG_SPIMCTRL_DUMMYBYTE -#define CONFIG_SPIMCTRL_DUMMYBYTE 0 -#endif - -#ifndef CONFIG_SPIMCTRL_DUALOUTPUT -#define CONFIG_SPIMCTRL_DUALOUTPUT 0 -#endif - -#ifndef CONFIG_SPIMCTRL_SCALER -#define CONFIG_SPIMCTRL_SCALER 1 -#endif - -#ifndef CONFIG_SPIMCTRL_ASCALER -#define CONFIG_SPIMCTRL_ASCALER 1 -#endif - -#ifndef CONFIG_SPIMCTRL_PWRUPCNT -#define CONFIG_SPIMCTRL_PWRUPCNT 0 -#endif -#ifndef CONFIG_SPICTRL_ENABLE -#define CONFIG_SPICTRL_ENABLE 0 -#endif -#ifndef CONFIG_SPICTRL_NUM -#define CONFIG_SPICTRL_NUM 1 -#endif -#ifndef CONFIG_SPICTRL_SLVS -#define CONFIG_SPICTRL_SLVS 1 -#endif -#ifndef CONFIG_SPICTRL_FIFO -#define CONFIG_SPICTRL_FIFO 1 -#endif -#ifndef CONFIG_SPICTRL_SLVREG -#define CONFIG_SPICTRL_SLVREG 0 -#endif -#ifndef CONFIG_SPICTRL_ODMODE -#define CONFIG_SPICTRL_ODMODE 0 -#endif -#ifndef CONFIG_SPICTRL_AM -#define CONFIG_SPICTRL_AM 0 -#endif -#ifndef CONFIG_SPICTRL_ASEL -#define CONFIG_SPICTRL_ASEL 0 -#endif -#ifndef CONFIG_SPICTRL_TWEN -#define CONFIG_SPICTRL_TWEN 0 -#endif -#ifndef CONFIG_SPICTRL_MAXWLEN -#define CONFIG_SPICTRL_MAXWLEN 0 -#endif -#ifndef CONFIG_SPICTRL_SYNCRAM -#define CONFIG_SPICTRL_SYNCRAM 0 -#endif -#if defined(CONFIG_SPICTRL_DMRFT) -#define CONFIG_SPICTRL_FT 1 -#elif defined(CONFIG_SPICTRL_TMRFT) -#define CONFIG_SPICTRL_FT 2 -#else -#define CONFIG_SPICTRL_FT 0 -#endif - -#ifndef CONFIG_DEBUG_UART -#define CONFIG_DEBUG_UART 0 -#endif +#if defined CONFIG_SYN_INFERRED +#define CONFIG_SYN_TECH inferred +#elif defined CONFIG_SYN_UMC +#define CONFIG_SYN_TECH umc +#elif defined CONFIG_SYN_RHUMC +#define CONFIG_SYN_TECH rhumc +#elif defined CONFIG_SYN_ATC18 +#define CONFIG_SYN_TECH atc18s +#elif defined CONFIG_SYN_ATC18RHA +#define CONFIG_SYN_TECH atc18rha +#elif defined CONFIG_SYN_AXCEL +#define CONFIG_SYN_TECH axcel +#elif defined CONFIG_SYN_AXDSP +#define CONFIG_SYN_TECH axdsp +#elif defined CONFIG_SYN_PROASICPLUS +#define CONFIG_SYN_TECH proasic +#elif defined CONFIG_SYN_ALTERA +#define CONFIG_SYN_TECH altera +#elif defined CONFIG_SYN_STRATIX +#define CONFIG_SYN_TECH stratix1 +#elif defined CONFIG_SYN_STRATIXII +#define CONFIG_SYN_TECH stratix2 +#elif defined CONFIG_SYN_STRATIXIII +#define CONFIG_SYN_TECH stratix3 +#elif defined CONFIG_SYN_CYCLONEIII +#define CONFIG_SYN_TECH cyclone3 +#elif defined CONFIG_SYN_EASIC45 +#define CONFIG_SYN_TECH easic45 +#elif defined CONFIG_SYN_EASIC90 +#define CONFIG_SYN_TECH easic90 +#elif defined CONFIG_SYN_IHP25 +#define CONFIG_SYN_TECH ihp25 +#elif defined CONFIG_SYN_IHP25RH +#define CONFIG_SYN_TECH ihp25rh +#elif defined CONFIG_SYN_CMOS9SF +#define CONFIG_SYN_TECH cmos9sf +#elif defined CONFIG_SYN_LATTICE +#define CONFIG_SYN_TECH lattice +#elif defined CONFIG_SYN_ECLIPSE +#define CONFIG_SYN_TECH eclipse +#elif defined CONFIG_SYN_PEREGRINE +#define CONFIG_SYN_TECH peregrine +#elif defined CONFIG_SYN_PROASIC +#define CONFIG_SYN_TECH proasic +#elif defined CONFIG_SYN_PROASIC3 +#define CONFIG_SYN_TECH apa3 +#elif defined CONFIG_SYN_PROASIC3E +#define CONFIG_SYN_TECH apa3e +#elif defined CONFIG_SYN_PROASIC3L +#define CONFIG_SYN_TECH apa3l +#elif defined CONFIG_SYN_IGLOO +#define CONFIG_SYN_TECH apa3 +#elif defined CONFIG_SYN_FUSION +#define CONFIG_SYN_TECH actfus +#elif defined CONFIG_SYN_SPARTAN2 +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_VIRTEX +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_VIRTEXE +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_SPARTAN3 +#define CONFIG_SYN_TECH spartan3 +#elif defined CONFIG_SYN_SPARTAN3E +#define CONFIG_SYN_TECH spartan3e +#elif defined CONFIG_SYN_SPARTAN6 +#define CONFIG_SYN_TECH spartan6 +#elif defined CONFIG_SYN_VIRTEX2 +#define CONFIG_SYN_TECH virtex2 +#elif defined CONFIG_SYN_VIRTEX4 +#define CONFIG_SYN_TECH virtex4 +#elif defined CONFIG_SYN_VIRTEX5 +#define CONFIG_SYN_TECH virtex5 +#elif defined CONFIG_SYN_VIRTEX6 +#define CONFIG_SYN_TECH virtex6 +#elif defined CONFIG_SYN_RH_LIB18T +#define CONFIG_SYN_TECH rhlib18t +#elif defined CONFIG_SYN_SMIC13 +#define CONFIG_SYN_TECH smic013 +#elif defined CONFIG_SYN_UT025CRH +#define CONFIG_SYN_TECH ut25 +#elif defined CONFIG_SYN_UT130HBD +#define CONFIG_SYN_TECH ut130 +#elif defined CONFIG_SYN_UT90NHBD +#define CONFIG_SYN_TECH ut90 +#elif defined CONFIG_SYN_TSMC90 +#define CONFIG_SYN_TECH tsmc90 +#elif defined CONFIG_SYN_TM65GPLUS +#define CONFIG_SYN_TECH tm65gpl +#elif defined CONFIG_SYN_CUSTOM1 +#define CONFIG_SYN_TECH custom1 +#else +#error "unknown target technology" +#endif + +#if defined CONFIG_SYN_INFER_RAM +#define CFG_RAM_TECH inferred +#elif defined CONFIG_MEM_UMC +#define CFG_RAM_TECH umc +#elif defined CONFIG_MEM_RHUMC +#define CFG_RAM_TECH rhumc +#elif defined CONFIG_MEM_VIRAGE +#define CFG_RAM_TECH memvirage +#elif defined CONFIG_MEM_ARTISAN +#define CFG_RAM_TECH memartisan +#elif defined CONFIG_MEM_CUSTOM1 +#define CFG_RAM_TECH custom1 +#elif defined CONFIG_MEM_VIRAGE90 +#define CFG_RAM_TECH memvirage90 +#elif defined CONFIG_MEM_INFERRED +#define CFG_RAM_TECH inferred +#else +#define CFG_RAM_TECH CONFIG_SYN_TECH +#endif + +#if defined CONFIG_SYN_INFER_PADS +#define CFG_PAD_TECH inferred +#else +#define CFG_PAD_TECH CONFIG_SYN_TECH +#endif + +#ifndef CONFIG_SYN_NO_ASYNC +#define CONFIG_SYN_NO_ASYNC 0 +#endif + +#ifndef CONFIG_SYN_SCAN +#define CONFIG_SYN_SCAN 0 +#endif + + +#if defined CONFIG_CLK_ALTDLL +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_HCLKBUF +#define CFG_CLK_TECH axcel +#elif defined CONFIG_CLK_LATDLL +#define CFG_CLK_TECH lattice +#elif defined CONFIG_CLK_PRO3PLL +#define CFG_CLK_TECH apa3 +#elif defined CONFIG_CLK_PRO3EPLL +#define CFG_CLK_TECH apa3e +#elif defined CONFIG_CLK_PRO3LPLL +#define CFG_CLK_TECH apa3l +#elif defined CONFIG_CLK_FUSPLL +#define CFG_CLK_TECH actfus +#elif defined CONFIG_CLK_CLKDLL +#define CFG_CLK_TECH virtex +#elif defined CONFIG_CLK_DCM +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_LIB18T +#define CFG_CLK_TECH rhlib18t +#elif defined CONFIG_CLK_RHUMC +#define CFG_CLK_TECH rhumc +#elif defined CONFIG_CLK_UT130HBD +#define CFG_CLK_TECH ut130 +#else +#define CFG_CLK_TECH inferred +#endif + +#ifndef CONFIG_CLK_MUL +#define CONFIG_CLK_MUL 2 +#endif + +#ifndef CONFIG_CLK_DIV +#define CONFIG_CLK_DIV 2 +#endif + +#ifndef CONFIG_OCLK_DIV +#define CONFIG_OCLK_DIV 1 +#endif + +#ifndef CONFIG_OCLKB_DIV +#define CONFIG_OCLKB_DIV 0 +#endif + +#ifndef CONFIG_OCLKC_DIV +#define CONFIG_OCLKC_DIV 0 +#endif + +#ifndef CONFIG_PCI_CLKDLL +#define CONFIG_PCI_CLKDLL 0 +#endif + +#ifndef CONFIG_PCI_SYSCLK +#define CONFIG_PCI_SYSCLK 0 +#endif + +#ifndef CONFIG_CLK_NOFB +#define CONFIG_CLK_NOFB 0 +#endif +#ifndef CONFIG_LEON3 +#define CONFIG_LEON3 0 +#endif + +#ifndef CONFIG_PROC_NUM +#define CONFIG_PROC_NUM 1 +#endif + +#ifndef CONFIG_IU_NWINDOWS +#define CONFIG_IU_NWINDOWS 8 +#endif + +#ifndef CONFIG_IU_RSTADDR +#define CONFIG_IU_RSTADDR 8 +#endif + +#ifndef CONFIG_IU_LDELAY +#define CONFIG_IU_LDELAY 1 +#endif + +#ifndef CONFIG_IU_WATCHPOINTS +#define CONFIG_IU_WATCHPOINTS 0 +#endif + +#ifdef CONFIG_IU_V8MULDIV +#ifdef CONFIG_IU_MUL_LATENCY_4 +#define CFG_IU_V8 1 +#elif defined CONFIG_IU_MUL_LATENCY_5 +#define CFG_IU_V8 2 +#elif defined CONFIG_IU_MUL_LATENCY_2 +#define CFG_IU_V8 16#32# +#endif +#else +#define CFG_IU_V8 0 +#endif + +#ifdef CONFIG_IU_MUL_MODGEN +#define CFG_IU_MUL_STRUCT 1 +#elif defined CONFIG_IU_MUL_TECHSPEC +#define CFG_IU_MUL_STRUCT 2 +#elif defined CONFIG_IU_MUL_DW +#define CFG_IU_MUL_STRUCT 3 +#else +#define CFG_IU_MUL_STRUCT 0 +#endif + +#ifndef CONFIG_PWD +#define CONFIG_PWD 0 +#endif + +#ifndef CONFIG_IU_MUL_MAC +#define CONFIG_IU_MUL_MAC 0 +#endif + +#ifndef CONFIG_IU_BP +#define CONFIG_IU_BP 0 +#endif + +#ifndef CONFIG_NOTAG +#define CONFIG_NOTAG 0 +#endif + +#ifndef CONFIG_IU_SVT +#define CONFIG_IU_SVT 0 +#endif + +#if defined CONFIG_FPU_GRFPC1 +#define CONFIG_FPU_GRFPC 1 +#elif defined CONFIG_FPU_GRFPC2 +#define CONFIG_FPU_GRFPC 2 +#else +#define CONFIG_FPU_GRFPC 0 +#endif + +#if defined CONFIG_FPU_GRFPU_INFMUL +#define CONFIG_FPU_GRFPU_MUL 0 +#elif defined CONFIG_FPU_GRFPU_DWMUL +#define CONFIG_FPU_GRFPU_MUL 1 +#elif defined CONFIG_FPU_GRFPU_MODGEN +#define CONFIG_FPU_GRFPU_MUL 2 +#elif defined CONFIG_FPU_GRFPU_TECHSPEC +#define CONFIG_FPU_GRFPU_MUL 3 +#else +#define CONFIG_FPU_GRFPU_MUL 0 +#endif + +#if defined CONFIG_FPU_GRFPU_SH +#define CONFIG_FPU_GRFPU_SHARED 1 +#else +#define CONFIG_FPU_GRFPU_SHARED 0 +#endif + +#if defined CONFIG_FPU_GRFPU +#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) +#elif defined CONFIG_FPU_MEIKO +#define CONFIG_FPU 15 +#elif defined CONFIG_FPU_GRFPULITE +#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) +#else +#define CONFIG_FPU 0 +#endif + +#ifndef CONFIG_FPU_NETLIST +#define CONFIG_FPU_NETLIST 0 +#endif + +#ifndef CONFIG_ICACHE_ENABLE +#define CONFIG_ICACHE_ENABLE 0 +#endif + +#if defined CONFIG_ICACHE_ASSO1 +#define CFG_IU_ISETS 1 +#elif defined CONFIG_ICACHE_ASSO2 +#define CFG_IU_ISETS 2 +#elif defined CONFIG_ICACHE_ASSO3 +#define CFG_IU_ISETS 3 +#elif defined CONFIG_ICACHE_ASSO4 +#define CFG_IU_ISETS 4 +#else +#define CFG_IU_ISETS 1 +#endif + +#if defined CONFIG_ICACHE_SZ1 +#define CFG_ICACHE_SZ 1 +#elif defined CONFIG_ICACHE_SZ2 +#define CFG_ICACHE_SZ 2 +#elif defined CONFIG_ICACHE_SZ4 +#define CFG_ICACHE_SZ 4 +#elif defined CONFIG_ICACHE_SZ8 +#define CFG_ICACHE_SZ 8 +#elif defined CONFIG_ICACHE_SZ16 +#define CFG_ICACHE_SZ 16 +#elif defined CONFIG_ICACHE_SZ32 +#define CFG_ICACHE_SZ 32 +#elif defined CONFIG_ICACHE_SZ64 +#define CFG_ICACHE_SZ 64 +#elif defined CONFIG_ICACHE_SZ128 +#define CFG_ICACHE_SZ 128 +#elif defined CONFIG_ICACHE_SZ256 +#define CFG_ICACHE_SZ 256 +#else +#define CFG_ICACHE_SZ 1 +#endif + +#ifdef CONFIG_ICACHE_LZ16 +#define CFG_ILINE_SZ 4 +#else +#define CFG_ILINE_SZ 8 +#endif + +#if defined CONFIG_ICACHE_ALGODIR +#define CFG_ICACHE_ALGORND 3 +#elif defined CONFIG_ICACHE_ALGORND +#define CFG_ICACHE_ALGORND 2 +#elif defined CONFIG_ICACHE_ALGOLRR +#define CFG_ICACHE_ALGORND 1 +#else +#define CFG_ICACHE_ALGORND 0 +#endif + +#ifndef CONFIG_ICACHE_LOCK +#define CONFIG_ICACHE_LOCK 0 +#endif + +#ifndef CONFIG_ICACHE_LRAM +#define CONFIG_ICACHE_LRAM 0 +#endif + +#ifndef CONFIG_ICACHE_LRSTART +#define CONFIG_ICACHE_LRSTART 8E +#endif + +#if defined CONFIG_ICACHE_LRAM_SZ2 +#define CFG_ILRAM_SIZE 2 +#elif defined CONFIG_ICACHE_LRAM_SZ4 +#define CFG_ILRAM_SIZE 4 +#elif defined CONFIG_ICACHE_LRAM_SZ8 +#define CFG_ILRAM_SIZE 8 +#elif defined CONFIG_ICACHE_LRAM_SZ16 +#define CFG_ILRAM_SIZE 16 +#elif defined CONFIG_ICACHE_LRAM_SZ32 +#define CFG_ILRAM_SIZE 32 +#elif defined CONFIG_ICACHE_LRAM_SZ64 +#define CFG_ILRAM_SIZE 64 +#elif defined CONFIG_ICACHE_LRAM_SZ128 +#define CFG_ILRAM_SIZE 128 +#elif defined CONFIG_ICACHE_LRAM_SZ256 +#define CFG_ILRAM_SIZE 256 +#else +#define CFG_ILRAM_SIZE 1 +#endif + + +#ifndef CONFIG_DCACHE_ENABLE +#define CONFIG_DCACHE_ENABLE 0 +#endif + +#if defined CONFIG_DCACHE_ASSO1 +#define CFG_IU_DSETS 1 +#elif defined CONFIG_DCACHE_ASSO2 +#define CFG_IU_DSETS 2 +#elif defined CONFIG_DCACHE_ASSO3 +#define CFG_IU_DSETS 3 +#elif defined CONFIG_DCACHE_ASSO4 +#define CFG_IU_DSETS 4 +#else +#define CFG_IU_DSETS 1 +#endif + +#if defined CONFIG_DCACHE_SZ1 +#define CFG_DCACHE_SZ 1 +#elif defined CONFIG_DCACHE_SZ2 +#define CFG_DCACHE_SZ 2 +#elif defined CONFIG_DCACHE_SZ4 +#define CFG_DCACHE_SZ 4 +#elif defined CONFIG_DCACHE_SZ8 +#define CFG_DCACHE_SZ 8 +#elif defined CONFIG_DCACHE_SZ16 +#define CFG_DCACHE_SZ 16 +#elif defined CONFIG_DCACHE_SZ32 +#define CFG_DCACHE_SZ 32 +#elif defined CONFIG_DCACHE_SZ64 +#define CFG_DCACHE_SZ 64 +#elif defined CONFIG_DCACHE_SZ128 +#define CFG_DCACHE_SZ 128 +#elif defined CONFIG_DCACHE_SZ256 +#define CFG_DCACHE_SZ 256 +#else +#define CFG_DCACHE_SZ 1 +#endif + +#ifdef CONFIG_DCACHE_LZ16 +#define CFG_DLINE_SZ 4 +#else +#define CFG_DLINE_SZ 8 +#endif + +#if defined CONFIG_DCACHE_ALGODIR +#define CFG_DCACHE_ALGORND 3 +#elif defined CONFIG_DCACHE_ALGORND +#define CFG_DCACHE_ALGORND 2 +#elif defined CONFIG_DCACHE_ALGOLRR +#define CFG_DCACHE_ALGORND 1 +#else +#define CFG_DCACHE_ALGORND 0 +#endif + +#ifndef CONFIG_DCACHE_LOCK +#define CONFIG_DCACHE_LOCK 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP +#define CONFIG_DCACHE_SNOOP 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP_FAST +#define CONFIG_DCACHE_SNOOP_FAST 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP_SEPTAG +#define CONFIG_DCACHE_SNOOP_SEPTAG 0 +#endif + +#ifndef CONFIG_CACHE_FIXED +#define CONFIG_CACHE_FIXED 0 +#endif + +#ifndef CONFIG_DCACHE_LRAM +#define CONFIG_DCACHE_LRAM 0 +#endif + +#ifndef CONFIG_DCACHE_LRSTART +#define CONFIG_DCACHE_LRSTART 8F +#endif + +#if defined CONFIG_DCACHE_LRAM_SZ2 +#define CFG_DLRAM_SIZE 2 +#elif defined CONFIG_DCACHE_LRAM_SZ4 +#define CFG_DLRAM_SIZE 4 +#elif defined CONFIG_DCACHE_LRAM_SZ8 +#define CFG_DLRAM_SIZE 8 +#elif defined CONFIG_DCACHE_LRAM_SZ16 +#define CFG_DLRAM_SIZE 16 +#elif defined CONFIG_DCACHE_LRAM_SZ32 +#define CFG_DLRAM_SIZE 32 +#elif defined CONFIG_DCACHE_LRAM_SZ64 +#define CFG_DLRAM_SIZE 64 +#elif defined CONFIG_DCACHE_LRAM_SZ128 +#define CFG_DLRAM_SIZE 128 +#elif defined CONFIG_DCACHE_LRAM_SZ256 +#define CFG_DLRAM_SIZE 256 +#else +#define CFG_DLRAM_SIZE 1 +#endif + +#if defined CONFIG_MMU_PAGE_4K +#define CONFIG_MMU_PAGE 0 +#elif defined CONFIG_MMU_PAGE_8K +#define CONFIG_MMU_PAGE 1 +#elif defined CONFIG_MMU_PAGE_16K +#define CONFIG_MMU_PAGE 2 +#elif defined CONFIG_MMU_PAGE_32K +#define CONFIG_MMU_PAGE 3 +#elif defined CONFIG_MMU_PAGE_PROG +#define CONFIG_MMU_PAGE 4 +#else +#define CONFIG_MMU_PAGE 0 +#endif + +#ifdef CONFIG_MMU_ENABLE +#define CONFIG_MMUEN 1 + +#ifdef CONFIG_MMU_SPLIT +#define CONFIG_TLB_TYPE 0 +#endif +#ifdef CONFIG_MMU_COMBINED +#define CONFIG_TLB_TYPE 1 +#endif + +#ifdef CONFIG_MMU_REPARRAY +#define CONFIG_TLB_REP 0 +#endif +#ifdef CONFIG_MMU_REPINCREMENT +#define CONFIG_TLB_REP 1 +#endif + +#ifdef CONFIG_MMU_I2 +#define CONFIG_ITLBNUM 2 +#endif +#ifdef CONFIG_MMU_I4 +#define CONFIG_ITLBNUM 4 +#endif +#ifdef CONFIG_MMU_I8 +#define CONFIG_ITLBNUM 8 +#endif +#ifdef CONFIG_MMU_I16 +#define CONFIG_ITLBNUM 16 +#endif +#ifdef CONFIG_MMU_I32 +#define CONFIG_ITLBNUM 32 +#endif + +#define CONFIG_DTLBNUM 2 +#ifdef CONFIG_MMU_D2 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 2 +#endif +#ifdef CONFIG_MMU_D4 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 4 +#endif +#ifdef CONFIG_MMU_D8 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 8 +#endif +#ifdef CONFIG_MMU_D16 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 16 +#endif +#ifdef CONFIG_MMU_D32 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 32 +#endif +#ifdef CONFIG_MMU_FASTWB +#define CFG_MMU_FASTWB 1 +#else +#define CFG_MMU_FASTWB 0 +#endif + +#else +#define CONFIG_MMUEN 0 +#define CONFIG_ITLBNUM 2 +#define CONFIG_DTLBNUM 2 +#define CONFIG_TLB_TYPE 1 +#define CONFIG_TLB_REP 1 +#define CFG_MMU_FASTWB 0 +#endif + +#ifndef CONFIG_DSU_ENABLE +#define CONFIG_DSU_ENABLE 0 +#endif + +#if defined CONFIG_DSU_ITRACESZ1 +#define CFG_DSU_ITB 1 +#elif CONFIG_DSU_ITRACESZ2 +#define CFG_DSU_ITB 2 +#elif CONFIG_DSU_ITRACESZ4 +#define CFG_DSU_ITB 4 +#elif CONFIG_DSU_ITRACESZ8 +#define CFG_DSU_ITB 8 +#elif CONFIG_DSU_ITRACESZ16 +#define CFG_DSU_ITB 16 +#else +#define CFG_DSU_ITB 0 +#endif + +#if defined CONFIG_DSU_ATRACESZ1 +#define CFG_DSU_ATB 1 +#elif CONFIG_DSU_ATRACESZ2 +#define CFG_DSU_ATB 2 +#elif CONFIG_DSU_ATRACESZ4 +#define CFG_DSU_ATB 4 +#elif CONFIG_DSU_ATRACESZ8 +#define CFG_DSU_ATB 8 +#elif CONFIG_DSU_ATRACESZ16 +#define CFG_DSU_ATB 16 +#else +#define CFG_DSU_ATB 0 +#endif + +#ifndef CONFIG_LEON3FT_EN +#define CONFIG_LEON3FT_EN 0 +#endif + +#if defined CONFIG_IUFT_PAR +#define CONFIG_IUFT_EN 1 +#elif defined CONFIG_IUFT_DMR +#define CONFIG_IUFT_EN 2 +#elif defined CONFIG_IUFT_BCH +#define CONFIG_IUFT_EN 3 +#elif defined CONFIG_IUFT_TMR +#define CONFIG_IUFT_EN 4 +#else +#define CONFIG_IUFT_EN 0 +#endif +#ifndef CONFIG_RF_ERRINJ +#define CONFIG_RF_ERRINJ 0 +#endif + +#ifndef CONFIG_FPUFT_EN +#define CONFIG_FPUFT 0 +#else +#ifdef CONFIG_FPU_GRFPU +#define CONFIG_FPUFT 2 +#else +#define CONFIG_FPUFT 1 +#endif +#endif + +#ifndef CONFIG_CACHE_FT_EN +#define CONFIG_CACHE_FT_EN 0 +#endif +#ifndef CONFIG_CACHE_ERRINJ +#define CONFIG_CACHE_ERRINJ 0 +#endif + +#ifndef CONFIG_LEON3_NETLIST +#define CONFIG_LEON3_NETLIST 0 +#endif + +#ifdef CONFIG_DEBUG_PC32 +#define CFG_DEBUG_PC32 0 +#else +#define CFG_DEBUG_PC32 2 +#endif +#ifndef CONFIG_IU_DISAS +#define CONFIG_IU_DISAS 0 +#endif +#ifndef CONFIG_IU_DISAS_NET +#define CONFIG_IU_DISAS_NET 0 +#endif + + +#ifndef CONFIG_AHB_SPLIT +#define CONFIG_AHB_SPLIT 0 +#endif + +#ifndef CONFIG_AHB_RROBIN +#define CONFIG_AHB_RROBIN 0 +#endif + +#ifndef CONFIG_AHB_IOADDR +#define CONFIG_AHB_IOADDR FFF +#endif + +#ifndef CONFIG_APB_HADDR +#define CONFIG_APB_HADDR 800 +#endif + +#ifndef CONFIG_AHB_MON +#define CONFIG_AHB_MON 0 +#endif + +#ifndef CONFIG_AHB_MONERR +#define CONFIG_AHB_MONERR 0 +#endif + +#ifndef CONFIG_AHB_MONWAR +#define CONFIG_AHB_MONWAR 0 +#endif + +#ifndef CONFIG_AHB_DTRACE +#define CONFIG_AHB_DTRACE 0 +#endif + +#ifndef CONFIG_DSU_JTAG +#define CONFIG_DSU_JTAG 0 +#endif + +#ifndef CONFIG_DSU_ETH +#define CONFIG_DSU_ETH 0 +#endif + +#ifndef CONFIG_DSU_IPMSB +#define CONFIG_DSU_IPMSB C0A8 +#endif + +#ifndef CONFIG_DSU_IPLSB +#define CONFIG_DSU_IPLSB 0033 +#endif + +#ifndef CONFIG_DSU_ETHMSB +#define CONFIG_DSU_ETHMSB 020000 +#endif + +#ifndef CONFIG_DSU_ETHLSB +#define CONFIG_DSU_ETHLSB 000009 +#endif + +#if defined CONFIG_DSU_ETHSZ1 +#define CFG_DSU_ETHB 1 +#elif CONFIG_DSU_ETHSZ2 +#define CFG_DSU_ETHB 2 +#elif CONFIG_DSU_ETHSZ4 +#define CFG_DSU_ETHB 4 +#elif CONFIG_DSU_ETHSZ8 +#define CFG_DSU_ETHB 8 +#elif CONFIG_DSU_ETHSZ16 +#define CFG_DSU_ETHB 16 +#elif CONFIG_DSU_ETHSZ32 +#define CFG_DSU_ETHB 32 +#else +#define CFG_DSU_ETHB 1 +#endif + +#ifndef CONFIG_DSU_ETH_PROG +#define CONFIG_DSU_ETH_PROG 0 +#endif + +#ifndef CONFIG_DSU_ETH_DIS +#define CONFIG_DSU_ETH_DIS 0 +#endif + +#ifndef CONFIG_MCTRL_LEON2 +#define CONFIG_MCTRL_LEON2 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM +#define CONFIG_MCTRL_SDRAM 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_SEPBUS +#define CONFIG_MCTRL_SDRAM_SEPBUS 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_INVCLK +#define CONFIG_MCTRL_SDRAM_INVCLK 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_BUS64 +#define CONFIG_MCTRL_SDRAM_BUS64 0 +#endif + +#ifndef CONFIG_MCTRL_8BIT +#define CONFIG_MCTRL_8BIT 0 +#endif + +#ifndef CONFIG_MCTRL_16BIT +#define CONFIG_MCTRL_16BIT 0 +#endif + +#ifndef CONFIG_MCTRL_5CS +#define CONFIG_MCTRL_5CS 0 +#endif + +#ifndef CONFIG_MCTRL_EDAC +#define CONFIG_MCTRL_EDAC 0 +#endif + +#ifndef CONFIG_MCTRL_PAGE +#define CONFIG_MCTRL_PAGE 0 +#endif + +#ifndef CONFIG_MCTRL_PROGPAGE +#define CONFIG_MCTRL_PROGPAGE 0 +#endif + + +#ifndef CONFIG_MIG_DDR2 +#define CONFIG_MIG_DDR2 0 +#endif + +#ifndef CONFIG_MIG_RANKS +#define CONFIG_MIG_RANKS 1 +#endif + +#ifndef CONFIG_MIG_COLBITS +#define CONFIG_MIG_COLBITS 10 +#endif + +#ifndef CONFIG_MIG_ROWBITS +#define CONFIG_MIG_ROWBITS 13 +#endif + +#ifndef CONFIG_MIG_BANKBITS +#define CONFIG_MIG_BANKBITS 2 +#endif + +#ifndef CONFIG_MIG_HMASK +#define CONFIG_MIG_HMASK F00 +#endif +#ifndef CONFIG_AHBSTAT_ENABLE +#define CONFIG_AHBSTAT_ENABLE 0 +#endif + +#ifndef CONFIG_AHBSTAT_NFTSLV +#define CONFIG_AHBSTAT_NFTSLV 1 +#endif + +#ifndef CONFIG_AHBROM_ENABLE +#define CONFIG_AHBROM_ENABLE 0 +#endif + +#ifndef CONFIG_AHBROM_START +#define CONFIG_AHBROM_START 000 +#endif + +#ifndef CONFIG_AHBROM_PIPE +#define CONFIG_AHBROM_PIPE 0 +#endif + +#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) +#define CONFIG_ROM_START 100 +#else +#define CONFIG_ROM_START 000 +#endif + + +#ifndef CONFIG_AHBRAM_ENABLE +#define CONFIG_AHBRAM_ENABLE 0 +#endif + +#ifndef CONFIG_AHBRAM_START +#define CONFIG_AHBRAM_START A00 +#endif + +#if defined CONFIG_AHBRAM_SZ1 +#define CFG_AHBRAMSZ 1 +#elif CONFIG_AHBRAM_SZ2 +#define CFG_AHBRAMSZ 2 +#elif CONFIG_AHBRAM_SZ4 +#define CFG_AHBRAMSZ 4 +#elif CONFIG_AHBRAM_SZ8 +#define CFG_AHBRAMSZ 8 +#elif CONFIG_AHBRAM_SZ16 +#define CFG_AHBRAMSZ 16 +#elif CONFIG_AHBRAM_SZ32 +#define CFG_AHBRAMSZ 32 +#elif CONFIG_AHBRAM_SZ64 +#define CFG_AHBRAMSZ 64 +#else +#define CFG_AHBRAMSZ 1 +#endif + +#ifndef CONFIG_GRETH_ENABLE +#define CONFIG_GRETH_ENABLE 0 +#endif + +#ifndef CONFIG_GRETH_GIGA +#define CONFIG_GRETH_GIGA 0 +#endif + +#if defined CONFIG_GRETH_FIFO4 +#define CFG_GRETH_FIFO 4 +#elif defined CONFIG_GRETH_FIFO8 +#define CFG_GRETH_FIFO 8 +#elif defined CONFIG_GRETH_FIFO16 +#define CFG_GRETH_FIFO 16 +#elif defined CONFIG_GRETH_FIFO32 +#define CFG_GRETH_FIFO 32 +#elif defined CONFIG_GRETH_FIFO64 +#define CFG_GRETH_FIFO 64 +#else +#define CFG_GRETH_FIFO 8 +#endif + +#ifndef CONFIG_UART1_ENABLE +#define CONFIG_UART1_ENABLE 0 +#endif + +#if defined CONFIG_UA1_FIFO1 +#define CFG_UA1_FIFO 1 +#elif defined CONFIG_UA1_FIFO2 +#define CFG_UA1_FIFO 2 +#elif defined CONFIG_UA1_FIFO4 +#define CFG_UA1_FIFO 4 +#elif defined CONFIG_UA1_FIFO8 +#define CFG_UA1_FIFO 8 +#elif defined CONFIG_UA1_FIFO16 +#define CFG_UA1_FIFO 16 +#elif defined CONFIG_UA1_FIFO32 +#define CFG_UA1_FIFO 32 +#else +#define CFG_UA1_FIFO 1 +#endif + +#ifndef CONFIG_IRQ3_ENABLE +#define CONFIG_IRQ3_ENABLE 0 +#endif +#ifndef CONFIG_IRQ3_NSEC +#define CONFIG_IRQ3_NSEC 0 +#endif +#ifndef CONFIG_GPT_ENABLE +#define CONFIG_GPT_ENABLE 0 +#endif + +#ifndef CONFIG_GPT_NTIM +#define CONFIG_GPT_NTIM 1 +#endif + +#ifndef CONFIG_GPT_SW +#define CONFIG_GPT_SW 8 +#endif + +#ifndef CONFIG_GPT_TW +#define CONFIG_GPT_TW 8 +#endif + +#ifndef CONFIG_GPT_IRQ +#define CONFIG_GPT_IRQ 8 +#endif + +#ifndef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 0 +#endif +#ifndef CONFIG_GPT_ENABLE +#define CONFIG_GPT_ENABLE 0 +#endif + +#ifndef CONFIG_GPT_NTIM +#define CONFIG_GPT_NTIM 1 +#endif + +#ifndef CONFIG_GPT_SW +#define CONFIG_GPT_SW 8 +#endif + +#ifndef CONFIG_GPT_TW +#define CONFIG_GPT_TW 8 +#endif + +#ifndef CONFIG_GPT_IRQ +#define CONFIG_GPT_IRQ 8 +#endif + +#ifndef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 0 +#endif + +#ifndef CONFIG_GPT_WDOGEN +#define CONFIG_GPT_WDOGEN 0 +#endif + +#ifndef CONFIG_GPT_WDOG +#define CONFIG_GPT_WDOG 0 +#endif + +#ifndef CONFIG_GRGPIO_ENABLE +#define CONFIG_GRGPIO_ENABLE 0 +#endif +#ifndef CONFIG_GRGPIO_IMASK +#define CONFIG_GRGPIO_IMASK 0000 +#endif +#ifndef CONFIG_GRGPIO_WIDTH +#define CONFIG_GRGPIO_WIDTH 1 +#endif + +#ifndef CONFIG_VGA_ENABLE +#define CONFIG_VGA_ENABLE 0 +#endif +#ifndef CONFIG_SVGA_ENABLE +#define CONFIG_SVGA_ENABLE 0 +#endif +#ifndef CONFIG_KBD_ENABLE +#define CONFIG_KBD_ENABLE 0 +#endif + + +#ifndef CONFIG_SPIMCTRL +#define CONFIG_SPIMCTRL 0 +#endif + +#ifndef CONFIG_SPIMCTRL_SDCARD +#define CONFIG_SPIMCTRL_SDCARD 0 +#endif + +#ifndef CONFIG_SPIMCTRL_READCMD +#define CONFIG_SPIMCTRL_READCMD 0 +#endif + +#ifndef CONFIG_SPIMCTRL_DUMMYBYTE +#define CONFIG_SPIMCTRL_DUMMYBYTE 0 +#endif + +#ifndef CONFIG_SPIMCTRL_DUALOUTPUT +#define CONFIG_SPIMCTRL_DUALOUTPUT 0 +#endif + +#ifndef CONFIG_SPIMCTRL_SCALER +#define CONFIG_SPIMCTRL_SCALER 1 +#endif + +#ifndef CONFIG_SPIMCTRL_ASCALER +#define CONFIG_SPIMCTRL_ASCALER 1 +#endif + +#ifndef CONFIG_SPIMCTRL_PWRUPCNT +#define CONFIG_SPIMCTRL_PWRUPCNT 0 +#endif +#ifndef CONFIG_SPICTRL_ENABLE +#define CONFIG_SPICTRL_ENABLE 0 +#endif +#ifndef CONFIG_SPICTRL_NUM +#define CONFIG_SPICTRL_NUM 1 +#endif +#ifndef CONFIG_SPICTRL_SLVS +#define CONFIG_SPICTRL_SLVS 1 +#endif +#ifndef CONFIG_SPICTRL_FIFO +#define CONFIG_SPICTRL_FIFO 1 +#endif +#ifndef CONFIG_SPICTRL_SLVREG +#define CONFIG_SPICTRL_SLVREG 0 +#endif +#ifndef CONFIG_SPICTRL_ODMODE +#define CONFIG_SPICTRL_ODMODE 0 +#endif +#ifndef CONFIG_SPICTRL_AM +#define CONFIG_SPICTRL_AM 0 +#endif +#ifndef CONFIG_SPICTRL_ASEL +#define CONFIG_SPICTRL_ASEL 0 +#endif +#ifndef CONFIG_SPICTRL_TWEN +#define CONFIG_SPICTRL_TWEN 0 +#endif +#ifndef CONFIG_SPICTRL_MAXWLEN +#define CONFIG_SPICTRL_MAXWLEN 0 +#endif +#ifndef CONFIG_SPICTRL_SYNCRAM +#define CONFIG_SPICTRL_SYNCRAM 0 +#endif +#if defined(CONFIG_SPICTRL_DMRFT) +#define CONFIG_SPICTRL_FT 1 +#elif defined(CONFIG_SPICTRL_TMRFT) +#define CONFIG_SPICTRL_FT 2 +#else +#define CONFIG_SPICTRL_FT 0 +#endif + +#ifndef CONFIG_DEBUG_UART +#define CONFIG_DEBUG_UART 0 +#endif diff --git a/designs/ICI4-Integ1/README.txt b/designs/ICI4-Integ1/README.txt --- a/designs/ICI4-Integ1/README.txt +++ b/designs/ICI4-Integ1/README.txt @@ -1,209 +1,209 @@ -This leon3 design is tailored to the Xilinx SP605 Spartan6 board - -Simulation and synthesis ------------------------- - -The design uses the Xilinx MIG memory interface with an AHB-2.0 -interface. The MIG source code cannot be distributed due to the -prohibitive Xilinx license, so the MIG must be re-generated with -coregen before simulation and synthesis can be done. - -To generate the MIG and install tne Xilinx unisim simulation -library, do as follows: - - make mig - make install-secureip - -This will ONLY work with ISE-13.2 installed, and the XILINX variable -properly set in the shell. To synthesize the design, do - - make ise - -and then - - make ise-prog-fpga - -to program the FPGA. - -Design specifics ----------------- - -* System reset is mapped to the CPU RESET button - -* The AHB and processor is clocked by a 60 MHz clock, generated - from the 33 MHz SYSACE clock using a DCM. You can change the frequency - generation in the clocks menu of xconfig. The DDR3 (MIG) controller - runs at 667 MHz. - -* The GRETH core is enabled and runs without problems at 100 Mbit. - Ethernet debug link is enabled and has IP 192.168.0.51. - 1 Gbit operation is also possible (requires grlib com release), - uncomment related timing constraints in the leon3mp.ucf first. - -* 16-bit flash prom can be read at address 0. It can be programmed - with GRMON version 1.1.16 or later. - -* DDR3 is working with the provided Xilinx MIG DDR3 controller. - If you want to simulate this design, first install the secure - IP models with: - - make install-secureip - - Then rebuild the scripts and simulation model: - - make distclean vsim - - Modelsim v6.6e or newer is required to build the secure IP models. - Note that the regular leon3 test bench cannot be run in simulation - as the DDR3 model lacks data pre-load. - -* The application UART1 is connected to the USB/UART connector - -* The SVGA frame buffer uses a separate port on the DDR3 controller, - and therefore does not noticeably affect the performance of the processor. - Default output is analog VGA, to switch to DVI mode execute this - command in grmon: - - i2c dvi init_l4itx_vga - -* The JTAG DSU interface is enabled and accesible via the USB/JTAG port. - Start grmon with -xilusb to connect. - -* Output from GRMON is: - -$ grmon -xilusb -u - - GRMON LEON debug monitor v1.1.51 professional version (debug) - - Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved. - For latest updates, go to http://www.gaisler.com/ - Comments or bug-reports to support@gaisler.com - - Xilinx cable: Cable type/rev : 0x3 - JTAG chain: xc6slx45t xccace - - GRLIB build version: 4111 - - initialising ............... - detected frequency: 50 MHz - SRAM waitstates: 1 - - Component Vendor - LEON3 SPARC V8 Processor Gaisler Research - AHB Debug JTAG TAP Gaisler Research - GR Ethernet MAC Gaisler Research - LEON2 Memory Controller European Space Agency - AHB/APB Bridge Gaisler Research - LEON3 Debug Support Unit Gaisler Research - Xilinx MIG DDR2 controller Gaisler Research - AHB/APB Bridge Gaisler Research - Generic APB UART Gaisler Research - Multi-processor Interrupt Ctrl Gaisler Research - Modular Timer Unit Gaisler Research - SVGA Controller Gaisler Research - AMBA Wrapper for OC I2C-master Gaisler Research - General purpose I/O port Gaisler Research - AHB status register Gaisler Research - - Use command 'info sys' to print a detailed report of attached cores - -grlib> inf sys -00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0) - ahb master 0 -01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1) - ahb master 1 -02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0) - ahb master 2, irq 12 - apb: 80000e00 - 80000f00 - Device index: dev0 - edcl ip 192.168.1.51, buffer 2 kbyte -00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1) - ahb: 00000000 - 20000000 - apb: 80000000 - 80000100 - 16-bit prom @ 0x00000000 -01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) - ahb: 80000000 - 80100000 -02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1) - ahb: 90000000 - a0000000 - AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0 - CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1 - icache 2 * 8 kbyte, 32 byte/line rnd - dcache 2 * 4 kbyte, 16 byte/line rnd -04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0) - ahb: 40000000 - 48000000 - apb: 80100000 - 80100100 - DDR2: 128 Mbyte -0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) - ahb: 80100000 - 80200000 -01.01:00c Gaisler Research Generic APB UART (ver 0x1) - irq 2 - apb: 80000100 - 80000200 - baud rate 38343, DSU mode (FIFO debug) -02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3) - apb: 80000200 - 80000300 -03.01:011 Gaisler Research Modular Timer Unit (ver 0x0) - irq 8 - apb: 80000300 - 80000400 - 8-bit scaler, 2 * 32-bit timers, divisor 50 -06.01:063 Gaisler Research SVGA Controller (ver 0x0) - apb: 80000600 - 80000700 - clk0: 50.00 MHz -09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3) - irq 14 - apb: 80000900 - 80000a00 -0a.01:01a Gaisler Research General purpose I/O port (ver 0x1) - apb: 80000a00 - 80000b00 -0f.01:052 Gaisler Research AHB status register (ver 0x0) - irq 7 - apb: 80000f00 - 80001000 -grlib> fla - - Intel-style 16-bit flash on D[31:16] - - Manuf. Intel - Device Strataflash P30 - - Device ID 02e44603e127ffff - User ID ffffffffffffffff - - - 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000 - - - CFI info - flash family : 1 - flash size : 256 Mbit - erase regions : 2 - erase blocks : 259 - write buffer : 1024 bytes - lock-down : yes - region 0 : 255 blocks of 128 Kbytes - region 1 : 4 blocks of 32 Kbytes - -grlib> lo ~/ibm/src/bench/leonbench/coremark.exe -section: .text at 0x40000000, size 102544 bytes -section: .data at 0x40019090, size 2788 bytes -total size: 105332 bytes (1.2 Mbit/s) -read 272 symbols -entry point: 0x40000000 -grlib> run -2K performance run parameters for coremark. -CoreMark Size : 666 -Total ticks : 19945918 -Total time (secs): 19.945918 -Iterations/Sec : 100.271143 -Iterations : 2000 -Compiler version : GCC4.4.2 -Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float -Memory location : STACK -seedcrc : 0xe9f5 -[0]crclist : 0xe714 -[0]crcmatrix : 0x1fd7 -[0]crcstate : 0x8e3a -[0]crcfinal : 0x4983 -Correct operation validated. See readme.txt for run and reporting rules. -CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack - -Program exited normally. -grlib> - +This leon3 design is tailored to the Xilinx SP605 Spartan6 board + +Simulation and synthesis +------------------------ + +The design uses the Xilinx MIG memory interface with an AHB-2.0 +interface. The MIG source code cannot be distributed due to the +prohibitive Xilinx license, so the MIG must be re-generated with +coregen before simulation and synthesis can be done. + +To generate the MIG and install tne Xilinx unisim simulation +library, do as follows: + + make mig + make install-secureip + +This will ONLY work with ISE-13.2 installed, and the XILINX variable +properly set in the shell. To synthesize the design, do + + make ise + +and then + + make ise-prog-fpga + +to program the FPGA. + +Design specifics +---------------- + +* System reset is mapped to the CPU RESET button + +* The AHB and processor is clocked by a 60 MHz clock, generated + from the 33 MHz SYSACE clock using a DCM. You can change the frequency + generation in the clocks menu of xconfig. The DDR3 (MIG) controller + runs at 667 MHz. + +* The GRETH core is enabled and runs without problems at 100 Mbit. + Ethernet debug link is enabled and has IP 192.168.0.51. + 1 Gbit operation is also possible (requires grlib com release), + uncomment related timing constraints in the leon3mp.ucf first. + +* 16-bit flash prom can be read at address 0. It can be programmed + with GRMON version 1.1.16 or later. + +* DDR3 is working with the provided Xilinx MIG DDR3 controller. + If you want to simulate this design, first install the secure + IP models with: + + make install-secureip + + Then rebuild the scripts and simulation model: + + make distclean vsim + + Modelsim v6.6e or newer is required to build the secure IP models. + Note that the regular leon3 test bench cannot be run in simulation + as the DDR3 model lacks data pre-load. + +* The application UART1 is connected to the USB/UART connector + +* The SVGA frame buffer uses a separate port on the DDR3 controller, + and therefore does not noticeably affect the performance of the processor. + Default output is analog VGA, to switch to DVI mode execute this + command in grmon: + + i2c dvi init_l4itx_vga + +* The JTAG DSU interface is enabled and accesible via the USB/JTAG port. + Start grmon with -xilusb to connect. + +* Output from GRMON is: + +$ grmon -xilusb -u + + GRMON LEON debug monitor v1.1.51 professional version (debug) + + Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved. + For latest updates, go to http://www.gaisler.com/ + Comments or bug-reports to support@gaisler.com + + Xilinx cable: Cable type/rev : 0x3 + JTAG chain: xc6slx45t xccace + + GRLIB build version: 4111 + + initialising ............... + detected frequency: 50 MHz + SRAM waitstates: 1 + + Component Vendor + LEON3 SPARC V8 Processor Gaisler Research + AHB Debug JTAG TAP Gaisler Research + GR Ethernet MAC Gaisler Research + LEON2 Memory Controller European Space Agency + AHB/APB Bridge Gaisler Research + LEON3 Debug Support Unit Gaisler Research + Xilinx MIG DDR2 controller Gaisler Research + AHB/APB Bridge Gaisler Research + Generic APB UART Gaisler Research + Multi-processor Interrupt Ctrl Gaisler Research + Modular Timer Unit Gaisler Research + SVGA Controller Gaisler Research + AMBA Wrapper for OC I2C-master Gaisler Research + General purpose I/O port Gaisler Research + AHB status register Gaisler Research + + Use command 'info sys' to print a detailed report of attached cores + +grlib> inf sys +00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0) + ahb master 0 +01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1) + ahb master 1 +02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0) + ahb master 2, irq 12 + apb: 80000e00 - 80000f00 + Device index: dev0 + edcl ip 192.168.1.51, buffer 2 kbyte +00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1) + ahb: 00000000 - 20000000 + apb: 80000000 - 80000100 + 16-bit prom @ 0x00000000 +01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) + ahb: 80000000 - 80100000 +02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1) + ahb: 90000000 - a0000000 + AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0 + CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1 + icache 2 * 8 kbyte, 32 byte/line rnd + dcache 2 * 4 kbyte, 16 byte/line rnd +04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0) + ahb: 40000000 - 48000000 + apb: 80100000 - 80100100 + DDR2: 128 Mbyte +0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) + ahb: 80100000 - 80200000 +01.01:00c Gaisler Research Generic APB UART (ver 0x1) + irq 2 + apb: 80000100 - 80000200 + baud rate 38343, DSU mode (FIFO debug) +02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3) + apb: 80000200 - 80000300 +03.01:011 Gaisler Research Modular Timer Unit (ver 0x0) + irq 8 + apb: 80000300 - 80000400 + 8-bit scaler, 2 * 32-bit timers, divisor 50 +06.01:063 Gaisler Research SVGA Controller (ver 0x0) + apb: 80000600 - 80000700 + clk0: 50.00 MHz +09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3) + irq 14 + apb: 80000900 - 80000a00 +0a.01:01a Gaisler Research General purpose I/O port (ver 0x1) + apb: 80000a00 - 80000b00 +0f.01:052 Gaisler Research AHB status register (ver 0x0) + irq 7 + apb: 80000f00 - 80001000 +grlib> fla + + Intel-style 16-bit flash on D[31:16] + + Manuf. Intel + Device Strataflash P30 + + Device ID 02e44603e127ffff + User ID ffffffffffffffff + + + 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000 + + + CFI info + flash family : 1 + flash size : 256 Mbit + erase regions : 2 + erase blocks : 259 + write buffer : 1024 bytes + lock-down : yes + region 0 : 255 blocks of 128 Kbytes + region 1 : 4 blocks of 32 Kbytes + +grlib> lo ~/ibm/src/bench/leonbench/coremark.exe +section: .text at 0x40000000, size 102544 bytes +section: .data at 0x40019090, size 2788 bytes +total size: 105332 bytes (1.2 Mbit/s) +read 272 symbols +entry point: 0x40000000 +grlib> run +2K performance run parameters for coremark. +CoreMark Size : 666 +Total ticks : 19945918 +Total time (secs): 19.945918 +Iterations/Sec : 100.271143 +Iterations : 2000 +Compiler version : GCC4.4.2 +Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float +Memory location : STACK +seedcrc : 0xe9f5 +[0]crclist : 0xe714 +[0]crcmatrix : 0x1fd7 +[0]crcstate : 0x8e3a +[0]crcfinal : 0x4983 +Correct operation validated. See readme.txt for run and reporting rules. +CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack + +Program exited normally. +grlib> + diff --git a/designs/ICI4-Integ1/config.vhd.h b/designs/ICI4-Integ1/config.vhd.h --- a/designs/ICI4-Integ1/config.vhd.h +++ b/designs/ICI4-Integ1/config.vhd.h @@ -1,190 +1,190 @@ --- Technology and synthesis options - constant CFG_FABTECH : integer := CONFIG_SYN_TECH; - constant CFG_MEMTECH : integer := CFG_RAM_TECH; - constant CFG_PADTECH : integer := CFG_PAD_TECH; - constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; - constant CFG_SCAN : integer := CONFIG_SYN_SCAN; - --- Clock generator - constant CFG_CLKTECH : integer := CFG_CLK_TECH; - constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; - constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; - constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; - constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV; - constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV; - constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; - constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; - constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; - --- LEON3 processor core - constant CFG_LEON3 : integer := CONFIG_LEON3; - constant CFG_NCPU : integer := CONFIG_PROC_NUM; - constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; - constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT; - constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; - constant CFG_BP : integer := CONFIG_IU_BP; - constant CFG_SVT : integer := CONFIG_IU_SVT; - constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; - constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; - constant CFG_NOTAG : integer := CONFIG_NOTAG; - constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; - constant CFG_PWD : integer := CONFIG_PWD*2; - constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED; - constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; - constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; - constant CFG_ISETS : integer := CFG_IU_ISETS; - constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; - constant CFG_ILINE : integer := CFG_ILINE_SZ; - constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; - constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; - constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; - constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; - constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; - constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; - constant CFG_DSETS : integer := CFG_IU_DSETS; - constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; - constant CFG_DLINE : integer := CFG_DLINE_SZ; - constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; - constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; - constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; - constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; - constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; - constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; - constant CFG_MMUEN : integer := CONFIG_MMUEN; - constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; - constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; - constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; - constant CFG_TLB_REP : integer := CONFIG_TLB_REP; - constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; - constant CFG_DSU : integer := CONFIG_DSU_ENABLE; - constant CFG_ITBSZ : integer := CFG_DSU_ITB; - constant CFG_ATBSZ : integer := CFG_DSU_ATB; - constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; - constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; - constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; - constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; - constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; - constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; - constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; - constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; - constant CFG_PCLOW : integer := CFG_DEBUG_PC32; - --- AMBA settings - constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; - constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; - constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; - constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; - constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; - constant CFG_AHB_MON : integer := CONFIG_AHB_MON; - constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; - constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; - constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS; - constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; - constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; - constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; - constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; - constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; - constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; - constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; - constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; - constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; - constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; - constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; - constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; - constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; - --- Xilinx MIG - constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2; - constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS; - constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS; - constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS; - constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS; - constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#; - - --- AHB status register - constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE; - constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV; - --- AHB ROM - constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; - constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; - constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; - constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; - constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; - constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; - constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; - constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; - constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; - --- UART 1 - constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; - constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; - constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; - --- Modular timer - constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; - constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; - constant CFG_GPT_SW : integer := CONFIG_GPT_SW; - constant CFG_GPT_TW : integer := CONFIG_GPT_TW; - constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; - constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; - constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; - constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; - constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; - constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; - --- VGA and PS2/ interface - constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE; - constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE; - constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE; - --- SPI memory controller - constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL; - constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD; - constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#; - constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE; - constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT; - constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER; - constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER; - constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT; - --- SPI controller - constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE; - constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM; - constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS; - constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO; - constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG; - constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE; - constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM; - constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL; - constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN; - constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN; - constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM; - constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT; - --- GRLIB debugging - constant CFG_DUART : integer := CONFIG_DEBUG_UART; - +-- Technology and synthesis options + constant CFG_FABTECH : integer := CONFIG_SYN_TECH; + constant CFG_MEMTECH : integer := CFG_RAM_TECH; + constant CFG_PADTECH : integer := CFG_PAD_TECH; + constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; + constant CFG_SCAN : integer := CONFIG_SYN_SCAN; + +-- Clock generator + constant CFG_CLKTECH : integer := CFG_CLK_TECH; + constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; + constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; + constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; + constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV; + constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV; + constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; + constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; + constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; + +-- LEON3 processor core + constant CFG_LEON3 : integer := CONFIG_LEON3; + constant CFG_NCPU : integer := CONFIG_PROC_NUM; + constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; + constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT; + constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; + constant CFG_BP : integer := CONFIG_IU_BP; + constant CFG_SVT : integer := CONFIG_IU_SVT; + constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; + constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; + constant CFG_NOTAG : integer := CONFIG_NOTAG; + constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; + constant CFG_PWD : integer := CONFIG_PWD*2; + constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED; + constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; + constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; + constant CFG_ISETS : integer := CFG_IU_ISETS; + constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; + constant CFG_ILINE : integer := CFG_ILINE_SZ; + constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; + constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; + constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; + constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; + constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; + constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; + constant CFG_DSETS : integer := CFG_IU_DSETS; + constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; + constant CFG_DLINE : integer := CFG_DLINE_SZ; + constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; + constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; + constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; + constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; + constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; + constant CFG_MMUEN : integer := CONFIG_MMUEN; + constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; + constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; + constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; + constant CFG_TLB_REP : integer := CONFIG_TLB_REP; + constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; + constant CFG_DSU : integer := CONFIG_DSU_ENABLE; + constant CFG_ITBSZ : integer := CFG_DSU_ITB; + constant CFG_ATBSZ : integer := CFG_DSU_ATB; + constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; + constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; + constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; + constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; + constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; + constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; + constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; + constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; + constant CFG_PCLOW : integer := CFG_DEBUG_PC32; + +-- AMBA settings + constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; + constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; + constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; + constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; + constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; + constant CFG_AHB_MON : integer := CONFIG_AHB_MON; + constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; + constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; + constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE; + +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; + +-- Ethernet DSU + constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS; + constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; + constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; + constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; + constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; + constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; + +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; + constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; + constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; + constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; + constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; + constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; + constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; + constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; + constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; + +-- Xilinx MIG + constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2; + constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS; + constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS; + constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS; + constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS; + constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#; + + +-- AHB status register + constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE; + constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV; + +-- AHB ROM + constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; + constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; + constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; + constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; + constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; + +-- AHB RAM + constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; + constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; + constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; + +-- Gaisler Ethernet core + constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; + constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; + constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; + +-- UART 1 + constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; + constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; + +-- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; + constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; + +-- Modular timer + constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; + constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; + constant CFG_GPT_SW : integer := CONFIG_GPT_SW; + constant CFG_GPT_TW : integer := CONFIG_GPT_TW; + constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; + constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; + constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; + constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; + +-- GPIO port + constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; + constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; + constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; + +-- VGA and PS2/ interface + constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE; + constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE; + constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE; + +-- SPI memory controller + constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL; + constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD; + constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#; + constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE; + constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT; + constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER; + constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER; + constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT; + +-- SPI controller + constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE; + constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM; + constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS; + constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO; + constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG; + constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE; + constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM; + constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL; + constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN; + constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN; + constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM; + constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT; + +-- GRLIB debugging + constant CFG_DUART : integer := CONFIG_DEBUG_UART; + diff --git a/designs/ICI4-Integ1/res.txt b/designs/ICI4-Integ1/res.txt --- a/designs/ICI4-Integ1/res.txt +++ b/designs/ICI4-Integ1/res.txt @@ -1,13 +1,13 @@ - -SPARTAN6 50 MHz, MIG DDR2, 2x8 + 2x4 cache, GRFPU - - LEON3 LEON3FTV2 -Dhrystone 78.4 78.4 -Whetstone DP 27.7 27.7 -gzip 43.98 s 41.38 s -bzip2 248.22 s 200.10 s -176.gcc 208.62 s 180.48 s -coremark 100.12 i/s 100.12 i/s -aocs_v8 12388.7 i/s 12388.7 i/s -basicmath_large 13245.0 i/s 13245.0 i/s -linpack_unroll_dp_v8 3265 KFLOPS 3563 KFLOPS + +SPARTAN6 50 MHz, MIG DDR2, 2x8 + 2x4 cache, GRFPU + + LEON3 LEON3FTV2 +Dhrystone 78.4 78.4 +Whetstone DP 27.7 27.7 +gzip 43.98 s 41.38 s +bzip2 248.22 s 200.10 s +176.gcc 208.62 s 180.48 s +coremark 100.12 i/s 100.12 i/s +aocs_v8 12388.7 i/s 12388.7 i/s +basicmath_large 13245.0 i/s 13245.0 i/s +linpack_unroll_dp_v8 3265 KFLOPS 3563 KFLOPS diff --git a/designs/ICI4-Integ1/systest.c b/designs/ICI4-Integ1/systest.c --- a/designs/ICI4-Integ1/systest.c +++ b/designs/ICI4-Integ1/systest.c @@ -1,18 +1,18 @@ - -main() - -{ - report_start(); - - -// svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); - base_test(); -/* - greth_test(0x80000e00); - spw_test(0x80100A00); - spw_test(0x80100B00); - spw_test(0x80100C00); - svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); -*/ - report_end(); -} + +main() + +{ + report_start(); + + +// svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); + base_test(); +/* + greth_test(0x80000e00); + spw_test(0x80100A00); + spw_test(0x80100B00); + spw_test(0x80100C00); + svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); +*/ + report_end(); +} diff --git a/designs/ICI4-Integ1/tkconfig.h b/designs/ICI4-Integ1/tkconfig.h --- a/designs/ICI4-Integ1/tkconfig.h +++ b/designs/ICI4-Integ1/tkconfig.h @@ -1,1051 +1,1051 @@ -#if defined CONFIG_SYN_INFERRED -#define CONFIG_SYN_TECH inferred -#elif defined CONFIG_SYN_UMC -#define CONFIG_SYN_TECH umc -#elif defined CONFIG_SYN_RHUMC -#define CONFIG_SYN_TECH rhumc -#elif defined CONFIG_SYN_ATC18 -#define CONFIG_SYN_TECH atc18s -#elif defined CONFIG_SYN_ATC18RHA -#define CONFIG_SYN_TECH atc18rha -#elif defined CONFIG_SYN_AXCEL -#define CONFIG_SYN_TECH axcel -#elif defined CONFIG_SYN_AXDSP -#define CONFIG_SYN_TECH axdsp -#elif defined CONFIG_SYN_PROASICPLUS -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_ALTERA -#define CONFIG_SYN_TECH altera -#elif defined CONFIG_SYN_STRATIX -#define CONFIG_SYN_TECH stratix1 -#elif defined CONFIG_SYN_STRATIXII -#define CONFIG_SYN_TECH stratix2 -#elif defined CONFIG_SYN_STRATIXIII -#define CONFIG_SYN_TECH stratix3 -#elif defined CONFIG_SYN_CYCLONEIII -#define CONFIG_SYN_TECH cyclone3 -#elif defined CONFIG_SYN_EASIC45 -#define CONFIG_SYN_TECH easic45 -#elif defined CONFIG_SYN_EASIC90 -#define CONFIG_SYN_TECH easic90 -#elif defined CONFIG_SYN_IHP25 -#define CONFIG_SYN_TECH ihp25 -#elif defined CONFIG_SYN_IHP25RH -#define CONFIG_SYN_TECH ihp25rh -#elif defined CONFIG_SYN_CMOS9SF -#define CONFIG_SYN_TECH cmos9sf -#elif defined CONFIG_SYN_LATTICE -#define CONFIG_SYN_TECH lattice -#elif defined CONFIG_SYN_ECLIPSE -#define CONFIG_SYN_TECH eclipse -#elif defined CONFIG_SYN_PEREGRINE -#define CONFIG_SYN_TECH peregrine -#elif defined CONFIG_SYN_PROASIC -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_PROASIC3 -#define CONFIG_SYN_TECH apa3 -#elif defined CONFIG_SYN_PROASIC3E -#define CONFIG_SYN_TECH apa3e -#elif defined CONFIG_SYN_PROASIC3L -#define CONFIG_SYN_TECH apa3l -#elif defined CONFIG_SYN_IGLOO -#define CONFIG_SYN_TECH apa3 -#elif defined CONFIG_SYN_FUSION -#define CONFIG_SYN_TECH actfus -#elif defined CONFIG_SYN_SPARTAN2 -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEX -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEXE -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_SPARTAN3 -#define CONFIG_SYN_TECH spartan3 -#elif defined CONFIG_SYN_SPARTAN3E -#define CONFIG_SYN_TECH spartan3e -#elif defined CONFIG_SYN_SPARTAN6 -#define CONFIG_SYN_TECH spartan6 -#elif defined CONFIG_SYN_VIRTEX2 -#define CONFIG_SYN_TECH virtex2 -#elif defined CONFIG_SYN_VIRTEX4 -#define CONFIG_SYN_TECH virtex4 -#elif defined CONFIG_SYN_VIRTEX5 -#define CONFIG_SYN_TECH virtex5 -#elif defined CONFIG_SYN_VIRTEX6 -#define CONFIG_SYN_TECH virtex6 -#elif defined CONFIG_SYN_RH_LIB18T -#define CONFIG_SYN_TECH rhlib18t -#elif defined CONFIG_SYN_SMIC13 -#define CONFIG_SYN_TECH smic013 -#elif defined CONFIG_SYN_UT025CRH -#define CONFIG_SYN_TECH ut25 -#elif defined CONFIG_SYN_UT130HBD -#define CONFIG_SYN_TECH ut130 -#elif defined CONFIG_SYN_UT90NHBD -#define CONFIG_SYN_TECH ut90 -#elif defined CONFIG_SYN_TSMC90 -#define CONFIG_SYN_TECH tsmc90 -#elif defined CONFIG_SYN_TM65GPLUS -#define CONFIG_SYN_TECH tm65gpl -#elif defined CONFIG_SYN_CUSTOM1 -#define CONFIG_SYN_TECH custom1 -#else -#error "unknown target technology" -#endif - -#if defined CONFIG_SYN_INFER_RAM -#define CFG_RAM_TECH inferred -#elif defined CONFIG_MEM_UMC -#define CFG_RAM_TECH umc -#elif defined CONFIG_MEM_RHUMC -#define CFG_RAM_TECH rhumc -#elif defined CONFIG_MEM_VIRAGE -#define CFG_RAM_TECH memvirage -#elif defined CONFIG_MEM_ARTISAN -#define CFG_RAM_TECH memartisan -#elif defined CONFIG_MEM_CUSTOM1 -#define CFG_RAM_TECH custom1 -#elif defined CONFIG_MEM_VIRAGE90 -#define CFG_RAM_TECH memvirage90 -#elif defined CONFIG_MEM_INFERRED -#define CFG_RAM_TECH inferred -#else -#define CFG_RAM_TECH CONFIG_SYN_TECH -#endif - -#if defined CONFIG_SYN_INFER_PADS -#define CFG_PAD_TECH inferred -#else -#define CFG_PAD_TECH CONFIG_SYN_TECH -#endif - -#ifndef CONFIG_SYN_NO_ASYNC -#define CONFIG_SYN_NO_ASYNC 0 -#endif - -#ifndef CONFIG_SYN_SCAN -#define CONFIG_SYN_SCAN 0 -#endif - - -#if defined CONFIG_CLK_ALTDLL -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_HCLKBUF -#define CFG_CLK_TECH axcel -#elif defined CONFIG_CLK_LATDLL -#define CFG_CLK_TECH lattice -#elif defined CONFIG_CLK_PRO3PLL -#define CFG_CLK_TECH apa3 -#elif defined CONFIG_CLK_PRO3EPLL -#define CFG_CLK_TECH apa3e -#elif defined CONFIG_CLK_PRO3LPLL -#define CFG_CLK_TECH apa3l -#elif defined CONFIG_CLK_FUSPLL -#define CFG_CLK_TECH actfus -#elif defined CONFIG_CLK_CLKDLL -#define CFG_CLK_TECH virtex -#elif defined CONFIG_CLK_DCM -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_LIB18T -#define CFG_CLK_TECH rhlib18t -#elif defined CONFIG_CLK_RHUMC -#define CFG_CLK_TECH rhumc -#elif defined CONFIG_CLK_UT130HBD -#define CFG_CLK_TECH ut130 -#else -#define CFG_CLK_TECH inferred -#endif - -#ifndef CONFIG_CLK_MUL -#define CONFIG_CLK_MUL 2 -#endif - -#ifndef CONFIG_CLK_DIV -#define CONFIG_CLK_DIV 2 -#endif - -#ifndef CONFIG_OCLK_DIV -#define CONFIG_OCLK_DIV 1 -#endif - -#ifndef CONFIG_OCLKB_DIV -#define CONFIG_OCLKB_DIV 0 -#endif - -#ifndef CONFIG_OCLKC_DIV -#define CONFIG_OCLKC_DIV 0 -#endif - -#ifndef CONFIG_PCI_CLKDLL -#define CONFIG_PCI_CLKDLL 0 -#endif - -#ifndef CONFIG_PCI_SYSCLK -#define CONFIG_PCI_SYSCLK 0 -#endif - -#ifndef CONFIG_CLK_NOFB -#define CONFIG_CLK_NOFB 0 -#endif -#ifndef CONFIG_LEON3 -#define CONFIG_LEON3 0 -#endif - -#ifndef CONFIG_PROC_NUM -#define CONFIG_PROC_NUM 1 -#endif - -#ifndef CONFIG_IU_NWINDOWS -#define CONFIG_IU_NWINDOWS 8 -#endif - -#ifndef CONFIG_IU_RSTADDR -#define CONFIG_IU_RSTADDR 8 -#endif - -#ifndef CONFIG_IU_LDELAY -#define CONFIG_IU_LDELAY 1 -#endif - -#ifndef CONFIG_IU_WATCHPOINTS -#define CONFIG_IU_WATCHPOINTS 0 -#endif - -#ifdef CONFIG_IU_V8MULDIV -#ifdef CONFIG_IU_MUL_LATENCY_4 -#define CFG_IU_V8 1 -#elif defined CONFIG_IU_MUL_LATENCY_5 -#define CFG_IU_V8 2 -#elif defined CONFIG_IU_MUL_LATENCY_2 -#define CFG_IU_V8 16#32# -#endif -#else -#define CFG_IU_V8 0 -#endif - -#ifdef CONFIG_IU_MUL_MODGEN -#define CFG_IU_MUL_STRUCT 1 -#elif defined CONFIG_IU_MUL_TECHSPEC -#define CFG_IU_MUL_STRUCT 2 -#elif defined CONFIG_IU_MUL_DW -#define CFG_IU_MUL_STRUCT 3 -#else -#define CFG_IU_MUL_STRUCT 0 -#endif - -#ifndef CONFIG_PWD -#define CONFIG_PWD 0 -#endif - -#ifndef CONFIG_IU_MUL_MAC -#define CONFIG_IU_MUL_MAC 0 -#endif - -#ifndef CONFIG_IU_BP -#define CONFIG_IU_BP 0 -#endif - -#ifndef CONFIG_NOTAG -#define CONFIG_NOTAG 0 -#endif - -#ifndef CONFIG_IU_SVT -#define CONFIG_IU_SVT 0 -#endif - -#if defined CONFIG_FPU_GRFPC1 -#define CONFIG_FPU_GRFPC 1 -#elif defined CONFIG_FPU_GRFPC2 -#define CONFIG_FPU_GRFPC 2 -#else -#define CONFIG_FPU_GRFPC 0 -#endif - -#if defined CONFIG_FPU_GRFPU_INFMUL -#define CONFIG_FPU_GRFPU_MUL 0 -#elif defined CONFIG_FPU_GRFPU_DWMUL -#define CONFIG_FPU_GRFPU_MUL 1 -#elif defined CONFIG_FPU_GRFPU_MODGEN -#define CONFIG_FPU_GRFPU_MUL 2 -#elif defined CONFIG_FPU_GRFPU_TECHSPEC -#define CONFIG_FPU_GRFPU_MUL 3 -#else -#define CONFIG_FPU_GRFPU_MUL 0 -#endif - -#if defined CONFIG_FPU_GRFPU_SH -#define CONFIG_FPU_GRFPU_SHARED 1 -#else -#define CONFIG_FPU_GRFPU_SHARED 0 -#endif - -#if defined CONFIG_FPU_GRFPU -#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) -#elif defined CONFIG_FPU_MEIKO -#define CONFIG_FPU 15 -#elif defined CONFIG_FPU_GRFPULITE -#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) -#else -#define CONFIG_FPU 0 -#endif - -#ifndef CONFIG_FPU_NETLIST -#define CONFIG_FPU_NETLIST 0 -#endif - -#ifndef CONFIG_ICACHE_ENABLE -#define CONFIG_ICACHE_ENABLE 0 -#endif - -#if defined CONFIG_ICACHE_ASSO1 -#define CFG_IU_ISETS 1 -#elif defined CONFIG_ICACHE_ASSO2 -#define CFG_IU_ISETS 2 -#elif defined CONFIG_ICACHE_ASSO3 -#define CFG_IU_ISETS 3 -#elif defined CONFIG_ICACHE_ASSO4 -#define CFG_IU_ISETS 4 -#else -#define CFG_IU_ISETS 1 -#endif - -#if defined CONFIG_ICACHE_SZ1 -#define CFG_ICACHE_SZ 1 -#elif defined CONFIG_ICACHE_SZ2 -#define CFG_ICACHE_SZ 2 -#elif defined CONFIG_ICACHE_SZ4 -#define CFG_ICACHE_SZ 4 -#elif defined CONFIG_ICACHE_SZ8 -#define CFG_ICACHE_SZ 8 -#elif defined CONFIG_ICACHE_SZ16 -#define CFG_ICACHE_SZ 16 -#elif defined CONFIG_ICACHE_SZ32 -#define CFG_ICACHE_SZ 32 -#elif defined CONFIG_ICACHE_SZ64 -#define CFG_ICACHE_SZ 64 -#elif defined CONFIG_ICACHE_SZ128 -#define CFG_ICACHE_SZ 128 -#elif defined CONFIG_ICACHE_SZ256 -#define CFG_ICACHE_SZ 256 -#else -#define CFG_ICACHE_SZ 1 -#endif - -#ifdef CONFIG_ICACHE_LZ16 -#define CFG_ILINE_SZ 4 -#else -#define CFG_ILINE_SZ 8 -#endif - -#if defined CONFIG_ICACHE_ALGODIR -#define CFG_ICACHE_ALGORND 3 -#elif defined CONFIG_ICACHE_ALGORND -#define CFG_ICACHE_ALGORND 2 -#elif defined CONFIG_ICACHE_ALGOLRR -#define CFG_ICACHE_ALGORND 1 -#else -#define CFG_ICACHE_ALGORND 0 -#endif - -#ifndef CONFIG_ICACHE_LOCK -#define CONFIG_ICACHE_LOCK 0 -#endif - -#ifndef CONFIG_ICACHE_LRAM -#define CONFIG_ICACHE_LRAM 0 -#endif - -#ifndef CONFIG_ICACHE_LRSTART -#define CONFIG_ICACHE_LRSTART 8E -#endif - -#if defined CONFIG_ICACHE_LRAM_SZ2 -#define CFG_ILRAM_SIZE 2 -#elif defined CONFIG_ICACHE_LRAM_SZ4 -#define CFG_ILRAM_SIZE 4 -#elif defined CONFIG_ICACHE_LRAM_SZ8 -#define CFG_ILRAM_SIZE 8 -#elif defined CONFIG_ICACHE_LRAM_SZ16 -#define CFG_ILRAM_SIZE 16 -#elif defined CONFIG_ICACHE_LRAM_SZ32 -#define CFG_ILRAM_SIZE 32 -#elif defined CONFIG_ICACHE_LRAM_SZ64 -#define CFG_ILRAM_SIZE 64 -#elif defined CONFIG_ICACHE_LRAM_SZ128 -#define CFG_ILRAM_SIZE 128 -#elif defined CONFIG_ICACHE_LRAM_SZ256 -#define CFG_ILRAM_SIZE 256 -#else -#define CFG_ILRAM_SIZE 1 -#endif - - -#ifndef CONFIG_DCACHE_ENABLE -#define CONFIG_DCACHE_ENABLE 0 -#endif - -#if defined CONFIG_DCACHE_ASSO1 -#define CFG_IU_DSETS 1 -#elif defined CONFIG_DCACHE_ASSO2 -#define CFG_IU_DSETS 2 -#elif defined CONFIG_DCACHE_ASSO3 -#define CFG_IU_DSETS 3 -#elif defined CONFIG_DCACHE_ASSO4 -#define CFG_IU_DSETS 4 -#else -#define CFG_IU_DSETS 1 -#endif - -#if defined CONFIG_DCACHE_SZ1 -#define CFG_DCACHE_SZ 1 -#elif defined CONFIG_DCACHE_SZ2 -#define CFG_DCACHE_SZ 2 -#elif defined CONFIG_DCACHE_SZ4 -#define CFG_DCACHE_SZ 4 -#elif defined CONFIG_DCACHE_SZ8 -#define CFG_DCACHE_SZ 8 -#elif defined CONFIG_DCACHE_SZ16 -#define CFG_DCACHE_SZ 16 -#elif defined CONFIG_DCACHE_SZ32 -#define CFG_DCACHE_SZ 32 -#elif defined CONFIG_DCACHE_SZ64 -#define CFG_DCACHE_SZ 64 -#elif defined CONFIG_DCACHE_SZ128 -#define CFG_DCACHE_SZ 128 -#elif defined CONFIG_DCACHE_SZ256 -#define CFG_DCACHE_SZ 256 -#else -#define CFG_DCACHE_SZ 1 -#endif - -#ifdef CONFIG_DCACHE_LZ16 -#define CFG_DLINE_SZ 4 -#else -#define CFG_DLINE_SZ 8 -#endif - -#if defined CONFIG_DCACHE_ALGODIR -#define CFG_DCACHE_ALGORND 3 -#elif defined CONFIG_DCACHE_ALGORND -#define CFG_DCACHE_ALGORND 2 -#elif defined CONFIG_DCACHE_ALGOLRR -#define CFG_DCACHE_ALGORND 1 -#else -#define CFG_DCACHE_ALGORND 0 -#endif - -#ifndef CONFIG_DCACHE_LOCK -#define CONFIG_DCACHE_LOCK 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP -#define CONFIG_DCACHE_SNOOP 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_SEPTAG -#define CONFIG_DCACHE_SNOOP_SEPTAG 0 -#endif - -#ifndef CONFIG_CACHE_FIXED -#define CONFIG_CACHE_FIXED 0 -#endif - -#ifndef CONFIG_DCACHE_LRAM -#define CONFIG_DCACHE_LRAM 0 -#endif - -#ifndef CONFIG_DCACHE_LRSTART -#define CONFIG_DCACHE_LRSTART 8F -#endif - -#if defined CONFIG_DCACHE_LRAM_SZ2 -#define CFG_DLRAM_SIZE 2 -#elif defined CONFIG_DCACHE_LRAM_SZ4 -#define CFG_DLRAM_SIZE 4 -#elif defined CONFIG_DCACHE_LRAM_SZ8 -#define CFG_DLRAM_SIZE 8 -#elif defined CONFIG_DCACHE_LRAM_SZ16 -#define CFG_DLRAM_SIZE 16 -#elif defined CONFIG_DCACHE_LRAM_SZ32 -#define CFG_DLRAM_SIZE 32 -#elif defined CONFIG_DCACHE_LRAM_SZ64 -#define CFG_DLRAM_SIZE 64 -#elif defined CONFIG_DCACHE_LRAM_SZ128 -#define CFG_DLRAM_SIZE 128 -#elif defined CONFIG_DCACHE_LRAM_SZ256 -#define CFG_DLRAM_SIZE 256 -#else -#define CFG_DLRAM_SIZE 1 -#endif - -#if defined CONFIG_MMU_PAGE_4K -#define CONFIG_MMU_PAGE 0 -#elif defined CONFIG_MMU_PAGE_8K -#define CONFIG_MMU_PAGE 1 -#elif defined CONFIG_MMU_PAGE_16K -#define CONFIG_MMU_PAGE 2 -#elif defined CONFIG_MMU_PAGE_32K -#define CONFIG_MMU_PAGE 3 -#elif defined CONFIG_MMU_PAGE_PROG -#define CONFIG_MMU_PAGE 4 -#else -#define CONFIG_MMU_PAGE 0 -#endif - -#ifdef CONFIG_MMU_ENABLE -#define CONFIG_MMUEN 1 - -#ifdef CONFIG_MMU_SPLIT -#define CONFIG_TLB_TYPE 0 -#endif -#ifdef CONFIG_MMU_COMBINED -#define CONFIG_TLB_TYPE 1 -#endif - -#ifdef CONFIG_MMU_REPARRAY -#define CONFIG_TLB_REP 0 -#endif -#ifdef CONFIG_MMU_REPINCREMENT -#define CONFIG_TLB_REP 1 -#endif - -#ifdef CONFIG_MMU_I2 -#define CONFIG_ITLBNUM 2 -#endif -#ifdef CONFIG_MMU_I4 -#define CONFIG_ITLBNUM 4 -#endif -#ifdef CONFIG_MMU_I8 -#define CONFIG_ITLBNUM 8 -#endif -#ifdef CONFIG_MMU_I16 -#define CONFIG_ITLBNUM 16 -#endif -#ifdef CONFIG_MMU_I32 -#define CONFIG_ITLBNUM 32 -#endif - -#define CONFIG_DTLBNUM 2 -#ifdef CONFIG_MMU_D2 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 2 -#endif -#ifdef CONFIG_MMU_D4 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 4 -#endif -#ifdef CONFIG_MMU_D8 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 8 -#endif -#ifdef CONFIG_MMU_D16 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 16 -#endif -#ifdef CONFIG_MMU_D32 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 32 -#endif -#ifdef CONFIG_MMU_FASTWB -#define CFG_MMU_FASTWB 1 -#else -#define CFG_MMU_FASTWB 0 -#endif - -#else -#define CONFIG_MMUEN 0 -#define CONFIG_ITLBNUM 2 -#define CONFIG_DTLBNUM 2 -#define CONFIG_TLB_TYPE 1 -#define CONFIG_TLB_REP 1 -#define CFG_MMU_FASTWB 0 -#endif - -#ifndef CONFIG_DSU_ENABLE -#define CONFIG_DSU_ENABLE 0 -#endif - -#if defined CONFIG_DSU_ITRACESZ1 -#define CFG_DSU_ITB 1 -#elif CONFIG_DSU_ITRACESZ2 -#define CFG_DSU_ITB 2 -#elif CONFIG_DSU_ITRACESZ4 -#define CFG_DSU_ITB 4 -#elif CONFIG_DSU_ITRACESZ8 -#define CFG_DSU_ITB 8 -#elif CONFIG_DSU_ITRACESZ16 -#define CFG_DSU_ITB 16 -#else -#define CFG_DSU_ITB 0 -#endif - -#if defined CONFIG_DSU_ATRACESZ1 -#define CFG_DSU_ATB 1 -#elif CONFIG_DSU_ATRACESZ2 -#define CFG_DSU_ATB 2 -#elif CONFIG_DSU_ATRACESZ4 -#define CFG_DSU_ATB 4 -#elif CONFIG_DSU_ATRACESZ8 -#define CFG_DSU_ATB 8 -#elif CONFIG_DSU_ATRACESZ16 -#define CFG_DSU_ATB 16 -#else -#define CFG_DSU_ATB 0 -#endif - -#ifndef CONFIG_LEON3FT_EN -#define CONFIG_LEON3FT_EN 0 -#endif - -#if defined CONFIG_IUFT_PAR -#define CONFIG_IUFT_EN 1 -#elif defined CONFIG_IUFT_DMR -#define CONFIG_IUFT_EN 2 -#elif defined CONFIG_IUFT_BCH -#define CONFIG_IUFT_EN 3 -#elif defined CONFIG_IUFT_TMR -#define CONFIG_IUFT_EN 4 -#else -#define CONFIG_IUFT_EN 0 -#endif -#ifndef CONFIG_RF_ERRINJ -#define CONFIG_RF_ERRINJ 0 -#endif - -#ifndef CONFIG_FPUFT_EN -#define CONFIG_FPUFT 0 -#else -#ifdef CONFIG_FPU_GRFPU -#define CONFIG_FPUFT 2 -#else -#define CONFIG_FPUFT 1 -#endif -#endif - -#ifndef CONFIG_CACHE_FT_EN -#define CONFIG_CACHE_FT_EN 0 -#endif -#ifndef CONFIG_CACHE_ERRINJ -#define CONFIG_CACHE_ERRINJ 0 -#endif - -#ifndef CONFIG_LEON3_NETLIST -#define CONFIG_LEON3_NETLIST 0 -#endif - -#ifdef CONFIG_DEBUG_PC32 -#define CFG_DEBUG_PC32 0 -#else -#define CFG_DEBUG_PC32 2 -#endif -#ifndef CONFIG_IU_DISAS -#define CONFIG_IU_DISAS 0 -#endif -#ifndef CONFIG_IU_DISAS_NET -#define CONFIG_IU_DISAS_NET 0 -#endif - - -#ifndef CONFIG_AHB_SPLIT -#define CONFIG_AHB_SPLIT 0 -#endif - -#ifndef CONFIG_AHB_RROBIN -#define CONFIG_AHB_RROBIN 0 -#endif - -#ifndef CONFIG_AHB_IOADDR -#define CONFIG_AHB_IOADDR FFF -#endif - -#ifndef CONFIG_APB_HADDR -#define CONFIG_APB_HADDR 800 -#endif - -#ifndef CONFIG_AHB_MON -#define CONFIG_AHB_MON 0 -#endif - -#ifndef CONFIG_AHB_MONERR -#define CONFIG_AHB_MONERR 0 -#endif - -#ifndef CONFIG_AHB_MONWAR -#define CONFIG_AHB_MONWAR 0 -#endif - -#ifndef CONFIG_AHB_DTRACE -#define CONFIG_AHB_DTRACE 0 -#endif - -#ifndef CONFIG_DSU_JTAG -#define CONFIG_DSU_JTAG 0 -#endif - -#ifndef CONFIG_DSU_ETH -#define CONFIG_DSU_ETH 0 -#endif - -#ifndef CONFIG_DSU_IPMSB -#define CONFIG_DSU_IPMSB C0A8 -#endif - -#ifndef CONFIG_DSU_IPLSB -#define CONFIG_DSU_IPLSB 0033 -#endif - -#ifndef CONFIG_DSU_ETHMSB -#define CONFIG_DSU_ETHMSB 020000 -#endif - -#ifndef CONFIG_DSU_ETHLSB -#define CONFIG_DSU_ETHLSB 000009 -#endif - -#if defined CONFIG_DSU_ETHSZ1 -#define CFG_DSU_ETHB 1 -#elif CONFIG_DSU_ETHSZ2 -#define CFG_DSU_ETHB 2 -#elif CONFIG_DSU_ETHSZ4 -#define CFG_DSU_ETHB 4 -#elif CONFIG_DSU_ETHSZ8 -#define CFG_DSU_ETHB 8 -#elif CONFIG_DSU_ETHSZ16 -#define CFG_DSU_ETHB 16 -#elif CONFIG_DSU_ETHSZ32 -#define CFG_DSU_ETHB 32 -#else -#define CFG_DSU_ETHB 1 -#endif - -#ifndef CONFIG_DSU_ETH_PROG -#define CONFIG_DSU_ETH_PROG 0 -#endif - -#ifndef CONFIG_DSU_ETH_DIS -#define CONFIG_DSU_ETH_DIS 0 -#endif - -#ifndef CONFIG_MCTRL_LEON2 -#define CONFIG_MCTRL_LEON2 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM -#define CONFIG_MCTRL_SDRAM 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_SEPBUS -#define CONFIG_MCTRL_SDRAM_SEPBUS 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_INVCLK -#define CONFIG_MCTRL_SDRAM_INVCLK 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_BUS64 -#define CONFIG_MCTRL_SDRAM_BUS64 0 -#endif - -#ifndef CONFIG_MCTRL_8BIT -#define CONFIG_MCTRL_8BIT 0 -#endif - -#ifndef CONFIG_MCTRL_16BIT -#define CONFIG_MCTRL_16BIT 0 -#endif - -#ifndef CONFIG_MCTRL_5CS -#define CONFIG_MCTRL_5CS 0 -#endif - -#ifndef CONFIG_MCTRL_EDAC -#define CONFIG_MCTRL_EDAC 0 -#endif - -#ifndef CONFIG_MCTRL_PAGE -#define CONFIG_MCTRL_PAGE 0 -#endif - -#ifndef CONFIG_MCTRL_PROGPAGE -#define CONFIG_MCTRL_PROGPAGE 0 -#endif - - -#ifndef CONFIG_MIG_DDR2 -#define CONFIG_MIG_DDR2 0 -#endif - -#ifndef CONFIG_MIG_RANKS -#define CONFIG_MIG_RANKS 1 -#endif - -#ifndef CONFIG_MIG_COLBITS -#define CONFIG_MIG_COLBITS 10 -#endif - -#ifndef CONFIG_MIG_ROWBITS -#define CONFIG_MIG_ROWBITS 13 -#endif - -#ifndef CONFIG_MIG_BANKBITS -#define CONFIG_MIG_BANKBITS 2 -#endif - -#ifndef CONFIG_MIG_HMASK -#define CONFIG_MIG_HMASK F00 -#endif -#ifndef CONFIG_AHBSTAT_ENABLE -#define CONFIG_AHBSTAT_ENABLE 0 -#endif - -#ifndef CONFIG_AHBSTAT_NFTSLV -#define CONFIG_AHBSTAT_NFTSLV 1 -#endif - -#ifndef CONFIG_AHBROM_ENABLE -#define CONFIG_AHBROM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBROM_START -#define CONFIG_AHBROM_START 000 -#endif - -#ifndef CONFIG_AHBROM_PIPE -#define CONFIG_AHBROM_PIPE 0 -#endif - -#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) -#define CONFIG_ROM_START 100 -#else -#define CONFIG_ROM_START 000 -#endif - - -#ifndef CONFIG_AHBRAM_ENABLE -#define CONFIG_AHBRAM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBRAM_START -#define CONFIG_AHBRAM_START A00 -#endif - -#if defined CONFIG_AHBRAM_SZ1 -#define CFG_AHBRAMSZ 1 -#elif CONFIG_AHBRAM_SZ2 -#define CFG_AHBRAMSZ 2 -#elif CONFIG_AHBRAM_SZ4 -#define CFG_AHBRAMSZ 4 -#elif CONFIG_AHBRAM_SZ8 -#define CFG_AHBRAMSZ 8 -#elif CONFIG_AHBRAM_SZ16 -#define CFG_AHBRAMSZ 16 -#elif CONFIG_AHBRAM_SZ32 -#define CFG_AHBRAMSZ 32 -#elif CONFIG_AHBRAM_SZ64 -#define CFG_AHBRAMSZ 64 -#else -#define CFG_AHBRAMSZ 1 -#endif - -#ifndef CONFIG_GRETH_ENABLE -#define CONFIG_GRETH_ENABLE 0 -#endif - -#ifndef CONFIG_GRETH_GIGA -#define CONFIG_GRETH_GIGA 0 -#endif - -#if defined CONFIG_GRETH_FIFO4 -#define CFG_GRETH_FIFO 4 -#elif defined CONFIG_GRETH_FIFO8 -#define CFG_GRETH_FIFO 8 -#elif defined CONFIG_GRETH_FIFO16 -#define CFG_GRETH_FIFO 16 -#elif defined CONFIG_GRETH_FIFO32 -#define CFG_GRETH_FIFO 32 -#elif defined CONFIG_GRETH_FIFO64 -#define CFG_GRETH_FIFO 64 -#else -#define CFG_GRETH_FIFO 8 -#endif - -#ifndef CONFIG_UART1_ENABLE -#define CONFIG_UART1_ENABLE 0 -#endif - -#if defined CONFIG_UA1_FIFO1 -#define CFG_UA1_FIFO 1 -#elif defined CONFIG_UA1_FIFO2 -#define CFG_UA1_FIFO 2 -#elif defined CONFIG_UA1_FIFO4 -#define CFG_UA1_FIFO 4 -#elif defined CONFIG_UA1_FIFO8 -#define CFG_UA1_FIFO 8 -#elif defined CONFIG_UA1_FIFO16 -#define CFG_UA1_FIFO 16 -#elif defined CONFIG_UA1_FIFO32 -#define CFG_UA1_FIFO 32 -#else -#define CFG_UA1_FIFO 1 -#endif - -#ifndef CONFIG_IRQ3_ENABLE -#define CONFIG_IRQ3_ENABLE 0 -#endif -#ifndef CONFIG_IRQ3_NSEC -#define CONFIG_IRQ3_NSEC 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif - -#ifndef CONFIG_GPT_WDOGEN -#define CONFIG_GPT_WDOGEN 0 -#endif - -#ifndef CONFIG_GPT_WDOG -#define CONFIG_GPT_WDOG 0 -#endif - -#ifndef CONFIG_GRGPIO_ENABLE -#define CONFIG_GRGPIO_ENABLE 0 -#endif -#ifndef CONFIG_GRGPIO_IMASK -#define CONFIG_GRGPIO_IMASK 0000 -#endif -#ifndef CONFIG_GRGPIO_WIDTH -#define CONFIG_GRGPIO_WIDTH 1 -#endif - -#ifndef CONFIG_VGA_ENABLE -#define CONFIG_VGA_ENABLE 0 -#endif -#ifndef CONFIG_SVGA_ENABLE -#define CONFIG_SVGA_ENABLE 0 -#endif -#ifndef CONFIG_KBD_ENABLE -#define CONFIG_KBD_ENABLE 0 -#endif - - -#ifndef CONFIG_SPIMCTRL -#define CONFIG_SPIMCTRL 0 -#endif - -#ifndef CONFIG_SPIMCTRL_SDCARD -#define CONFIG_SPIMCTRL_SDCARD 0 -#endif - -#ifndef CONFIG_SPIMCTRL_READCMD -#define CONFIG_SPIMCTRL_READCMD 0 -#endif - -#ifndef CONFIG_SPIMCTRL_DUMMYBYTE -#define CONFIG_SPIMCTRL_DUMMYBYTE 0 -#endif - -#ifndef CONFIG_SPIMCTRL_DUALOUTPUT -#define CONFIG_SPIMCTRL_DUALOUTPUT 0 -#endif - -#ifndef CONFIG_SPIMCTRL_SCALER -#define CONFIG_SPIMCTRL_SCALER 1 -#endif - -#ifndef CONFIG_SPIMCTRL_ASCALER -#define CONFIG_SPIMCTRL_ASCALER 1 -#endif - -#ifndef CONFIG_SPIMCTRL_PWRUPCNT -#define CONFIG_SPIMCTRL_PWRUPCNT 0 -#endif -#ifndef CONFIG_SPICTRL_ENABLE -#define CONFIG_SPICTRL_ENABLE 0 -#endif -#ifndef CONFIG_SPICTRL_NUM -#define CONFIG_SPICTRL_NUM 1 -#endif -#ifndef CONFIG_SPICTRL_SLVS -#define CONFIG_SPICTRL_SLVS 1 -#endif -#ifndef CONFIG_SPICTRL_FIFO -#define CONFIG_SPICTRL_FIFO 1 -#endif -#ifndef CONFIG_SPICTRL_SLVREG -#define CONFIG_SPICTRL_SLVREG 0 -#endif -#ifndef CONFIG_SPICTRL_ODMODE -#define CONFIG_SPICTRL_ODMODE 0 -#endif -#ifndef CONFIG_SPICTRL_AM -#define CONFIG_SPICTRL_AM 0 -#endif -#ifndef CONFIG_SPICTRL_ASEL -#define CONFIG_SPICTRL_ASEL 0 -#endif -#ifndef CONFIG_SPICTRL_TWEN -#define CONFIG_SPICTRL_TWEN 0 -#endif -#ifndef CONFIG_SPICTRL_MAXWLEN -#define CONFIG_SPICTRL_MAXWLEN 0 -#endif -#ifndef CONFIG_SPICTRL_SYNCRAM -#define CONFIG_SPICTRL_SYNCRAM 0 -#endif -#if defined(CONFIG_SPICTRL_DMRFT) -#define CONFIG_SPICTRL_FT 1 -#elif defined(CONFIG_SPICTRL_TMRFT) -#define CONFIG_SPICTRL_FT 2 -#else -#define CONFIG_SPICTRL_FT 0 -#endif - -#ifndef CONFIG_DEBUG_UART -#define CONFIG_DEBUG_UART 0 -#endif +#if defined CONFIG_SYN_INFERRED +#define CONFIG_SYN_TECH inferred +#elif defined CONFIG_SYN_UMC +#define CONFIG_SYN_TECH umc +#elif defined CONFIG_SYN_RHUMC +#define CONFIG_SYN_TECH rhumc +#elif defined CONFIG_SYN_ATC18 +#define CONFIG_SYN_TECH atc18s +#elif defined CONFIG_SYN_ATC18RHA +#define CONFIG_SYN_TECH atc18rha +#elif defined CONFIG_SYN_AXCEL +#define CONFIG_SYN_TECH axcel +#elif defined CONFIG_SYN_AXDSP +#define CONFIG_SYN_TECH axdsp +#elif defined CONFIG_SYN_PROASICPLUS +#define CONFIG_SYN_TECH proasic +#elif defined CONFIG_SYN_ALTERA +#define CONFIG_SYN_TECH altera +#elif defined CONFIG_SYN_STRATIX +#define CONFIG_SYN_TECH stratix1 +#elif defined CONFIG_SYN_STRATIXII +#define CONFIG_SYN_TECH stratix2 +#elif defined CONFIG_SYN_STRATIXIII +#define CONFIG_SYN_TECH stratix3 +#elif defined CONFIG_SYN_CYCLONEIII +#define CONFIG_SYN_TECH cyclone3 +#elif defined CONFIG_SYN_EASIC45 +#define CONFIG_SYN_TECH easic45 +#elif defined CONFIG_SYN_EASIC90 +#define CONFIG_SYN_TECH easic90 +#elif defined CONFIG_SYN_IHP25 +#define CONFIG_SYN_TECH ihp25 +#elif defined CONFIG_SYN_IHP25RH +#define CONFIG_SYN_TECH ihp25rh +#elif defined CONFIG_SYN_CMOS9SF +#define CONFIG_SYN_TECH cmos9sf +#elif defined CONFIG_SYN_LATTICE +#define CONFIG_SYN_TECH lattice +#elif defined CONFIG_SYN_ECLIPSE +#define CONFIG_SYN_TECH eclipse +#elif defined CONFIG_SYN_PEREGRINE +#define CONFIG_SYN_TECH peregrine +#elif defined CONFIG_SYN_PROASIC +#define CONFIG_SYN_TECH proasic +#elif defined CONFIG_SYN_PROASIC3 +#define CONFIG_SYN_TECH apa3 +#elif defined CONFIG_SYN_PROASIC3E +#define CONFIG_SYN_TECH apa3e +#elif defined CONFIG_SYN_PROASIC3L +#define CONFIG_SYN_TECH apa3l +#elif defined CONFIG_SYN_IGLOO +#define CONFIG_SYN_TECH apa3 +#elif defined CONFIG_SYN_FUSION +#define CONFIG_SYN_TECH actfus +#elif defined CONFIG_SYN_SPARTAN2 +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_VIRTEX +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_VIRTEXE +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_SPARTAN3 +#define CONFIG_SYN_TECH spartan3 +#elif defined CONFIG_SYN_SPARTAN3E +#define CONFIG_SYN_TECH spartan3e +#elif defined CONFIG_SYN_SPARTAN6 +#define CONFIG_SYN_TECH spartan6 +#elif defined CONFIG_SYN_VIRTEX2 +#define CONFIG_SYN_TECH virtex2 +#elif defined CONFIG_SYN_VIRTEX4 +#define CONFIG_SYN_TECH virtex4 +#elif defined CONFIG_SYN_VIRTEX5 +#define CONFIG_SYN_TECH virtex5 +#elif defined CONFIG_SYN_VIRTEX6 +#define CONFIG_SYN_TECH virtex6 +#elif defined CONFIG_SYN_RH_LIB18T +#define CONFIG_SYN_TECH rhlib18t +#elif defined CONFIG_SYN_SMIC13 +#define CONFIG_SYN_TECH smic013 +#elif defined CONFIG_SYN_UT025CRH +#define CONFIG_SYN_TECH ut25 +#elif defined CONFIG_SYN_UT130HBD +#define CONFIG_SYN_TECH ut130 +#elif defined CONFIG_SYN_UT90NHBD +#define CONFIG_SYN_TECH ut90 +#elif defined CONFIG_SYN_TSMC90 +#define CONFIG_SYN_TECH tsmc90 +#elif defined CONFIG_SYN_TM65GPLUS +#define CONFIG_SYN_TECH tm65gpl +#elif defined CONFIG_SYN_CUSTOM1 +#define CONFIG_SYN_TECH custom1 +#else +#error "unknown target technology" +#endif + +#if defined CONFIG_SYN_INFER_RAM +#define CFG_RAM_TECH inferred +#elif defined CONFIG_MEM_UMC +#define CFG_RAM_TECH umc +#elif defined CONFIG_MEM_RHUMC +#define CFG_RAM_TECH rhumc +#elif defined CONFIG_MEM_VIRAGE +#define CFG_RAM_TECH memvirage +#elif defined CONFIG_MEM_ARTISAN +#define CFG_RAM_TECH memartisan +#elif defined CONFIG_MEM_CUSTOM1 +#define CFG_RAM_TECH custom1 +#elif defined CONFIG_MEM_VIRAGE90 +#define CFG_RAM_TECH memvirage90 +#elif defined CONFIG_MEM_INFERRED +#define CFG_RAM_TECH inferred +#else +#define CFG_RAM_TECH CONFIG_SYN_TECH +#endif + +#if defined CONFIG_SYN_INFER_PADS +#define CFG_PAD_TECH inferred +#else +#define CFG_PAD_TECH CONFIG_SYN_TECH +#endif + +#ifndef CONFIG_SYN_NO_ASYNC +#define CONFIG_SYN_NO_ASYNC 0 +#endif + +#ifndef CONFIG_SYN_SCAN +#define CONFIG_SYN_SCAN 0 +#endif + + +#if defined CONFIG_CLK_ALTDLL +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_HCLKBUF +#define CFG_CLK_TECH axcel +#elif defined CONFIG_CLK_LATDLL +#define CFG_CLK_TECH lattice +#elif defined CONFIG_CLK_PRO3PLL +#define CFG_CLK_TECH apa3 +#elif defined CONFIG_CLK_PRO3EPLL +#define CFG_CLK_TECH apa3e +#elif defined CONFIG_CLK_PRO3LPLL +#define CFG_CLK_TECH apa3l +#elif defined CONFIG_CLK_FUSPLL +#define CFG_CLK_TECH actfus +#elif defined CONFIG_CLK_CLKDLL +#define CFG_CLK_TECH virtex +#elif defined CONFIG_CLK_DCM +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_LIB18T +#define CFG_CLK_TECH rhlib18t +#elif defined CONFIG_CLK_RHUMC +#define CFG_CLK_TECH rhumc +#elif defined CONFIG_CLK_UT130HBD +#define CFG_CLK_TECH ut130 +#else +#define CFG_CLK_TECH inferred +#endif + +#ifndef CONFIG_CLK_MUL +#define CONFIG_CLK_MUL 2 +#endif + +#ifndef CONFIG_CLK_DIV +#define CONFIG_CLK_DIV 2 +#endif + +#ifndef CONFIG_OCLK_DIV +#define CONFIG_OCLK_DIV 1 +#endif + +#ifndef CONFIG_OCLKB_DIV +#define CONFIG_OCLKB_DIV 0 +#endif + +#ifndef CONFIG_OCLKC_DIV +#define CONFIG_OCLKC_DIV 0 +#endif + +#ifndef CONFIG_PCI_CLKDLL +#define CONFIG_PCI_CLKDLL 0 +#endif + +#ifndef CONFIG_PCI_SYSCLK +#define CONFIG_PCI_SYSCLK 0 +#endif + +#ifndef CONFIG_CLK_NOFB +#define CONFIG_CLK_NOFB 0 +#endif +#ifndef CONFIG_LEON3 +#define CONFIG_LEON3 0 +#endif + +#ifndef CONFIG_PROC_NUM +#define CONFIG_PROC_NUM 1 +#endif + +#ifndef CONFIG_IU_NWINDOWS +#define CONFIG_IU_NWINDOWS 8 +#endif + +#ifndef CONFIG_IU_RSTADDR +#define CONFIG_IU_RSTADDR 8 +#endif + +#ifndef CONFIG_IU_LDELAY +#define CONFIG_IU_LDELAY 1 +#endif + +#ifndef CONFIG_IU_WATCHPOINTS +#define CONFIG_IU_WATCHPOINTS 0 +#endif + +#ifdef CONFIG_IU_V8MULDIV +#ifdef CONFIG_IU_MUL_LATENCY_4 +#define CFG_IU_V8 1 +#elif defined CONFIG_IU_MUL_LATENCY_5 +#define CFG_IU_V8 2 +#elif defined CONFIG_IU_MUL_LATENCY_2 +#define CFG_IU_V8 16#32# +#endif +#else +#define CFG_IU_V8 0 +#endif + +#ifdef CONFIG_IU_MUL_MODGEN +#define CFG_IU_MUL_STRUCT 1 +#elif defined CONFIG_IU_MUL_TECHSPEC +#define CFG_IU_MUL_STRUCT 2 +#elif defined CONFIG_IU_MUL_DW +#define CFG_IU_MUL_STRUCT 3 +#else +#define CFG_IU_MUL_STRUCT 0 +#endif + +#ifndef CONFIG_PWD +#define CONFIG_PWD 0 +#endif + +#ifndef CONFIG_IU_MUL_MAC +#define CONFIG_IU_MUL_MAC 0 +#endif + +#ifndef CONFIG_IU_BP +#define CONFIG_IU_BP 0 +#endif + +#ifndef CONFIG_NOTAG +#define CONFIG_NOTAG 0 +#endif + +#ifndef CONFIG_IU_SVT +#define CONFIG_IU_SVT 0 +#endif + +#if defined CONFIG_FPU_GRFPC1 +#define CONFIG_FPU_GRFPC 1 +#elif defined CONFIG_FPU_GRFPC2 +#define CONFIG_FPU_GRFPC 2 +#else +#define CONFIG_FPU_GRFPC 0 +#endif + +#if defined CONFIG_FPU_GRFPU_INFMUL +#define CONFIG_FPU_GRFPU_MUL 0 +#elif defined CONFIG_FPU_GRFPU_DWMUL +#define CONFIG_FPU_GRFPU_MUL 1 +#elif defined CONFIG_FPU_GRFPU_MODGEN +#define CONFIG_FPU_GRFPU_MUL 2 +#elif defined CONFIG_FPU_GRFPU_TECHSPEC +#define CONFIG_FPU_GRFPU_MUL 3 +#else +#define CONFIG_FPU_GRFPU_MUL 0 +#endif + +#if defined CONFIG_FPU_GRFPU_SH +#define CONFIG_FPU_GRFPU_SHARED 1 +#else +#define CONFIG_FPU_GRFPU_SHARED 0 +#endif + +#if defined CONFIG_FPU_GRFPU +#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) +#elif defined CONFIG_FPU_MEIKO +#define CONFIG_FPU 15 +#elif defined CONFIG_FPU_GRFPULITE +#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) +#else +#define CONFIG_FPU 0 +#endif + +#ifndef CONFIG_FPU_NETLIST +#define CONFIG_FPU_NETLIST 0 +#endif + +#ifndef CONFIG_ICACHE_ENABLE +#define CONFIG_ICACHE_ENABLE 0 +#endif + +#if defined CONFIG_ICACHE_ASSO1 +#define CFG_IU_ISETS 1 +#elif defined CONFIG_ICACHE_ASSO2 +#define CFG_IU_ISETS 2 +#elif defined CONFIG_ICACHE_ASSO3 +#define CFG_IU_ISETS 3 +#elif defined CONFIG_ICACHE_ASSO4 +#define CFG_IU_ISETS 4 +#else +#define CFG_IU_ISETS 1 +#endif + +#if defined CONFIG_ICACHE_SZ1 +#define CFG_ICACHE_SZ 1 +#elif defined CONFIG_ICACHE_SZ2 +#define CFG_ICACHE_SZ 2 +#elif defined CONFIG_ICACHE_SZ4 +#define CFG_ICACHE_SZ 4 +#elif defined CONFIG_ICACHE_SZ8 +#define CFG_ICACHE_SZ 8 +#elif defined CONFIG_ICACHE_SZ16 +#define CFG_ICACHE_SZ 16 +#elif defined CONFIG_ICACHE_SZ32 +#define CFG_ICACHE_SZ 32 +#elif defined CONFIG_ICACHE_SZ64 +#define CFG_ICACHE_SZ 64 +#elif defined CONFIG_ICACHE_SZ128 +#define CFG_ICACHE_SZ 128 +#elif defined CONFIG_ICACHE_SZ256 +#define CFG_ICACHE_SZ 256 +#else +#define CFG_ICACHE_SZ 1 +#endif + +#ifdef CONFIG_ICACHE_LZ16 +#define CFG_ILINE_SZ 4 +#else +#define CFG_ILINE_SZ 8 +#endif + +#if defined CONFIG_ICACHE_ALGODIR +#define CFG_ICACHE_ALGORND 3 +#elif defined CONFIG_ICACHE_ALGORND +#define CFG_ICACHE_ALGORND 2 +#elif defined CONFIG_ICACHE_ALGOLRR +#define CFG_ICACHE_ALGORND 1 +#else +#define CFG_ICACHE_ALGORND 0 +#endif + +#ifndef CONFIG_ICACHE_LOCK +#define CONFIG_ICACHE_LOCK 0 +#endif + +#ifndef CONFIG_ICACHE_LRAM +#define CONFIG_ICACHE_LRAM 0 +#endif + +#ifndef CONFIG_ICACHE_LRSTART +#define CONFIG_ICACHE_LRSTART 8E +#endif + +#if defined CONFIG_ICACHE_LRAM_SZ2 +#define CFG_ILRAM_SIZE 2 +#elif defined CONFIG_ICACHE_LRAM_SZ4 +#define CFG_ILRAM_SIZE 4 +#elif defined CONFIG_ICACHE_LRAM_SZ8 +#define CFG_ILRAM_SIZE 8 +#elif defined CONFIG_ICACHE_LRAM_SZ16 +#define CFG_ILRAM_SIZE 16 +#elif defined CONFIG_ICACHE_LRAM_SZ32 +#define CFG_ILRAM_SIZE 32 +#elif defined CONFIG_ICACHE_LRAM_SZ64 +#define CFG_ILRAM_SIZE 64 +#elif defined CONFIG_ICACHE_LRAM_SZ128 +#define CFG_ILRAM_SIZE 128 +#elif defined CONFIG_ICACHE_LRAM_SZ256 +#define CFG_ILRAM_SIZE 256 +#else +#define CFG_ILRAM_SIZE 1 +#endif + + +#ifndef CONFIG_DCACHE_ENABLE +#define CONFIG_DCACHE_ENABLE 0 +#endif + +#if defined CONFIG_DCACHE_ASSO1 +#define CFG_IU_DSETS 1 +#elif defined CONFIG_DCACHE_ASSO2 +#define CFG_IU_DSETS 2 +#elif defined CONFIG_DCACHE_ASSO3 +#define CFG_IU_DSETS 3 +#elif defined CONFIG_DCACHE_ASSO4 +#define CFG_IU_DSETS 4 +#else +#define CFG_IU_DSETS 1 +#endif + +#if defined CONFIG_DCACHE_SZ1 +#define CFG_DCACHE_SZ 1 +#elif defined CONFIG_DCACHE_SZ2 +#define CFG_DCACHE_SZ 2 +#elif defined CONFIG_DCACHE_SZ4 +#define CFG_DCACHE_SZ 4 +#elif defined CONFIG_DCACHE_SZ8 +#define CFG_DCACHE_SZ 8 +#elif defined CONFIG_DCACHE_SZ16 +#define CFG_DCACHE_SZ 16 +#elif defined CONFIG_DCACHE_SZ32 +#define CFG_DCACHE_SZ 32 +#elif defined CONFIG_DCACHE_SZ64 +#define CFG_DCACHE_SZ 64 +#elif defined CONFIG_DCACHE_SZ128 +#define CFG_DCACHE_SZ 128 +#elif defined CONFIG_DCACHE_SZ256 +#define CFG_DCACHE_SZ 256 +#else +#define CFG_DCACHE_SZ 1 +#endif + +#ifdef CONFIG_DCACHE_LZ16 +#define CFG_DLINE_SZ 4 +#else +#define CFG_DLINE_SZ 8 +#endif + +#if defined CONFIG_DCACHE_ALGODIR +#define CFG_DCACHE_ALGORND 3 +#elif defined CONFIG_DCACHE_ALGORND +#define CFG_DCACHE_ALGORND 2 +#elif defined CONFIG_DCACHE_ALGOLRR +#define CFG_DCACHE_ALGORND 1 +#else +#define CFG_DCACHE_ALGORND 0 +#endif + +#ifndef CONFIG_DCACHE_LOCK +#define CONFIG_DCACHE_LOCK 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP +#define CONFIG_DCACHE_SNOOP 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP_FAST +#define CONFIG_DCACHE_SNOOP_FAST 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP_SEPTAG +#define CONFIG_DCACHE_SNOOP_SEPTAG 0 +#endif + +#ifndef CONFIG_CACHE_FIXED +#define CONFIG_CACHE_FIXED 0 +#endif + +#ifndef CONFIG_DCACHE_LRAM +#define CONFIG_DCACHE_LRAM 0 +#endif + +#ifndef CONFIG_DCACHE_LRSTART +#define CONFIG_DCACHE_LRSTART 8F +#endif + +#if defined CONFIG_DCACHE_LRAM_SZ2 +#define CFG_DLRAM_SIZE 2 +#elif defined CONFIG_DCACHE_LRAM_SZ4 +#define CFG_DLRAM_SIZE 4 +#elif defined CONFIG_DCACHE_LRAM_SZ8 +#define CFG_DLRAM_SIZE 8 +#elif defined CONFIG_DCACHE_LRAM_SZ16 +#define CFG_DLRAM_SIZE 16 +#elif defined CONFIG_DCACHE_LRAM_SZ32 +#define CFG_DLRAM_SIZE 32 +#elif defined CONFIG_DCACHE_LRAM_SZ64 +#define CFG_DLRAM_SIZE 64 +#elif defined CONFIG_DCACHE_LRAM_SZ128 +#define CFG_DLRAM_SIZE 128 +#elif defined CONFIG_DCACHE_LRAM_SZ256 +#define CFG_DLRAM_SIZE 256 +#else +#define CFG_DLRAM_SIZE 1 +#endif + +#if defined CONFIG_MMU_PAGE_4K +#define CONFIG_MMU_PAGE 0 +#elif defined CONFIG_MMU_PAGE_8K +#define CONFIG_MMU_PAGE 1 +#elif defined CONFIG_MMU_PAGE_16K +#define CONFIG_MMU_PAGE 2 +#elif defined CONFIG_MMU_PAGE_32K +#define CONFIG_MMU_PAGE 3 +#elif defined CONFIG_MMU_PAGE_PROG +#define CONFIG_MMU_PAGE 4 +#else +#define CONFIG_MMU_PAGE 0 +#endif + +#ifdef CONFIG_MMU_ENABLE +#define CONFIG_MMUEN 1 + +#ifdef CONFIG_MMU_SPLIT +#define CONFIG_TLB_TYPE 0 +#endif +#ifdef CONFIG_MMU_COMBINED +#define CONFIG_TLB_TYPE 1 +#endif + +#ifdef CONFIG_MMU_REPARRAY +#define CONFIG_TLB_REP 0 +#endif +#ifdef CONFIG_MMU_REPINCREMENT +#define CONFIG_TLB_REP 1 +#endif + +#ifdef CONFIG_MMU_I2 +#define CONFIG_ITLBNUM 2 +#endif +#ifdef CONFIG_MMU_I4 +#define CONFIG_ITLBNUM 4 +#endif +#ifdef CONFIG_MMU_I8 +#define CONFIG_ITLBNUM 8 +#endif +#ifdef CONFIG_MMU_I16 +#define CONFIG_ITLBNUM 16 +#endif +#ifdef CONFIG_MMU_I32 +#define CONFIG_ITLBNUM 32 +#endif + +#define CONFIG_DTLBNUM 2 +#ifdef CONFIG_MMU_D2 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 2 +#endif +#ifdef CONFIG_MMU_D4 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 4 +#endif +#ifdef CONFIG_MMU_D8 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 8 +#endif +#ifdef CONFIG_MMU_D16 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 16 +#endif +#ifdef CONFIG_MMU_D32 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 32 +#endif +#ifdef CONFIG_MMU_FASTWB +#define CFG_MMU_FASTWB 1 +#else +#define CFG_MMU_FASTWB 0 +#endif + +#else +#define CONFIG_MMUEN 0 +#define CONFIG_ITLBNUM 2 +#define CONFIG_DTLBNUM 2 +#define CONFIG_TLB_TYPE 1 +#define CONFIG_TLB_REP 1 +#define CFG_MMU_FASTWB 0 +#endif + +#ifndef CONFIG_DSU_ENABLE +#define CONFIG_DSU_ENABLE 0 +#endif + +#if defined CONFIG_DSU_ITRACESZ1 +#define CFG_DSU_ITB 1 +#elif CONFIG_DSU_ITRACESZ2 +#define CFG_DSU_ITB 2 +#elif CONFIG_DSU_ITRACESZ4 +#define CFG_DSU_ITB 4 +#elif CONFIG_DSU_ITRACESZ8 +#define CFG_DSU_ITB 8 +#elif CONFIG_DSU_ITRACESZ16 +#define CFG_DSU_ITB 16 +#else +#define CFG_DSU_ITB 0 +#endif + +#if defined CONFIG_DSU_ATRACESZ1 +#define CFG_DSU_ATB 1 +#elif CONFIG_DSU_ATRACESZ2 +#define CFG_DSU_ATB 2 +#elif CONFIG_DSU_ATRACESZ4 +#define CFG_DSU_ATB 4 +#elif CONFIG_DSU_ATRACESZ8 +#define CFG_DSU_ATB 8 +#elif CONFIG_DSU_ATRACESZ16 +#define CFG_DSU_ATB 16 +#else +#define CFG_DSU_ATB 0 +#endif + +#ifndef CONFIG_LEON3FT_EN +#define CONFIG_LEON3FT_EN 0 +#endif + +#if defined CONFIG_IUFT_PAR +#define CONFIG_IUFT_EN 1 +#elif defined CONFIG_IUFT_DMR +#define CONFIG_IUFT_EN 2 +#elif defined CONFIG_IUFT_BCH +#define CONFIG_IUFT_EN 3 +#elif defined CONFIG_IUFT_TMR +#define CONFIG_IUFT_EN 4 +#else +#define CONFIG_IUFT_EN 0 +#endif +#ifndef CONFIG_RF_ERRINJ +#define CONFIG_RF_ERRINJ 0 +#endif + +#ifndef CONFIG_FPUFT_EN +#define CONFIG_FPUFT 0 +#else +#ifdef CONFIG_FPU_GRFPU +#define CONFIG_FPUFT 2 +#else +#define CONFIG_FPUFT 1 +#endif +#endif + +#ifndef CONFIG_CACHE_FT_EN +#define CONFIG_CACHE_FT_EN 0 +#endif +#ifndef CONFIG_CACHE_ERRINJ +#define CONFIG_CACHE_ERRINJ 0 +#endif + +#ifndef CONFIG_LEON3_NETLIST +#define CONFIG_LEON3_NETLIST 0 +#endif + +#ifdef CONFIG_DEBUG_PC32 +#define CFG_DEBUG_PC32 0 +#else +#define CFG_DEBUG_PC32 2 +#endif +#ifndef CONFIG_IU_DISAS +#define CONFIG_IU_DISAS 0 +#endif +#ifndef CONFIG_IU_DISAS_NET +#define CONFIG_IU_DISAS_NET 0 +#endif + + +#ifndef CONFIG_AHB_SPLIT +#define CONFIG_AHB_SPLIT 0 +#endif + +#ifndef CONFIG_AHB_RROBIN +#define CONFIG_AHB_RROBIN 0 +#endif + +#ifndef CONFIG_AHB_IOADDR +#define CONFIG_AHB_IOADDR FFF +#endif + +#ifndef CONFIG_APB_HADDR +#define CONFIG_APB_HADDR 800 +#endif + +#ifndef CONFIG_AHB_MON +#define CONFIG_AHB_MON 0 +#endif + +#ifndef CONFIG_AHB_MONERR +#define CONFIG_AHB_MONERR 0 +#endif + +#ifndef CONFIG_AHB_MONWAR +#define CONFIG_AHB_MONWAR 0 +#endif + +#ifndef CONFIG_AHB_DTRACE +#define CONFIG_AHB_DTRACE 0 +#endif + +#ifndef CONFIG_DSU_JTAG +#define CONFIG_DSU_JTAG 0 +#endif + +#ifndef CONFIG_DSU_ETH +#define CONFIG_DSU_ETH 0 +#endif + +#ifndef CONFIG_DSU_IPMSB +#define CONFIG_DSU_IPMSB C0A8 +#endif + +#ifndef CONFIG_DSU_IPLSB +#define CONFIG_DSU_IPLSB 0033 +#endif + +#ifndef CONFIG_DSU_ETHMSB +#define CONFIG_DSU_ETHMSB 020000 +#endif + +#ifndef CONFIG_DSU_ETHLSB +#define CONFIG_DSU_ETHLSB 000009 +#endif + +#if defined CONFIG_DSU_ETHSZ1 +#define CFG_DSU_ETHB 1 +#elif CONFIG_DSU_ETHSZ2 +#define CFG_DSU_ETHB 2 +#elif CONFIG_DSU_ETHSZ4 +#define CFG_DSU_ETHB 4 +#elif CONFIG_DSU_ETHSZ8 +#define CFG_DSU_ETHB 8 +#elif CONFIG_DSU_ETHSZ16 +#define CFG_DSU_ETHB 16 +#elif CONFIG_DSU_ETHSZ32 +#define CFG_DSU_ETHB 32 +#else +#define CFG_DSU_ETHB 1 +#endif + +#ifndef CONFIG_DSU_ETH_PROG +#define CONFIG_DSU_ETH_PROG 0 +#endif + +#ifndef CONFIG_DSU_ETH_DIS +#define CONFIG_DSU_ETH_DIS 0 +#endif + +#ifndef CONFIG_MCTRL_LEON2 +#define CONFIG_MCTRL_LEON2 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM +#define CONFIG_MCTRL_SDRAM 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_SEPBUS +#define CONFIG_MCTRL_SDRAM_SEPBUS 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_INVCLK +#define CONFIG_MCTRL_SDRAM_INVCLK 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_BUS64 +#define CONFIG_MCTRL_SDRAM_BUS64 0 +#endif + +#ifndef CONFIG_MCTRL_8BIT +#define CONFIG_MCTRL_8BIT 0 +#endif + +#ifndef CONFIG_MCTRL_16BIT +#define CONFIG_MCTRL_16BIT 0 +#endif + +#ifndef CONFIG_MCTRL_5CS +#define CONFIG_MCTRL_5CS 0 +#endif + +#ifndef CONFIG_MCTRL_EDAC +#define CONFIG_MCTRL_EDAC 0 +#endif + +#ifndef CONFIG_MCTRL_PAGE +#define CONFIG_MCTRL_PAGE 0 +#endif + +#ifndef CONFIG_MCTRL_PROGPAGE +#define CONFIG_MCTRL_PROGPAGE 0 +#endif + + +#ifndef CONFIG_MIG_DDR2 +#define CONFIG_MIG_DDR2 0 +#endif + +#ifndef CONFIG_MIG_RANKS +#define CONFIG_MIG_RANKS 1 +#endif + +#ifndef CONFIG_MIG_COLBITS +#define CONFIG_MIG_COLBITS 10 +#endif + +#ifndef CONFIG_MIG_ROWBITS +#define CONFIG_MIG_ROWBITS 13 +#endif + +#ifndef CONFIG_MIG_BANKBITS +#define CONFIG_MIG_BANKBITS 2 +#endif + +#ifndef CONFIG_MIG_HMASK +#define CONFIG_MIG_HMASK F00 +#endif +#ifndef CONFIG_AHBSTAT_ENABLE +#define CONFIG_AHBSTAT_ENABLE 0 +#endif + +#ifndef CONFIG_AHBSTAT_NFTSLV +#define CONFIG_AHBSTAT_NFTSLV 1 +#endif + +#ifndef CONFIG_AHBROM_ENABLE +#define CONFIG_AHBROM_ENABLE 0 +#endif + +#ifndef CONFIG_AHBROM_START +#define CONFIG_AHBROM_START 000 +#endif + +#ifndef CONFIG_AHBROM_PIPE +#define CONFIG_AHBROM_PIPE 0 +#endif + +#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) +#define CONFIG_ROM_START 100 +#else +#define CONFIG_ROM_START 000 +#endif + + +#ifndef CONFIG_AHBRAM_ENABLE +#define CONFIG_AHBRAM_ENABLE 0 +#endif + +#ifndef CONFIG_AHBRAM_START +#define CONFIG_AHBRAM_START A00 +#endif + +#if defined CONFIG_AHBRAM_SZ1 +#define CFG_AHBRAMSZ 1 +#elif CONFIG_AHBRAM_SZ2 +#define CFG_AHBRAMSZ 2 +#elif CONFIG_AHBRAM_SZ4 +#define CFG_AHBRAMSZ 4 +#elif CONFIG_AHBRAM_SZ8 +#define CFG_AHBRAMSZ 8 +#elif CONFIG_AHBRAM_SZ16 +#define CFG_AHBRAMSZ 16 +#elif CONFIG_AHBRAM_SZ32 +#define CFG_AHBRAMSZ 32 +#elif CONFIG_AHBRAM_SZ64 +#define CFG_AHBRAMSZ 64 +#else +#define CFG_AHBRAMSZ 1 +#endif + +#ifndef CONFIG_GRETH_ENABLE +#define CONFIG_GRETH_ENABLE 0 +#endif + +#ifndef CONFIG_GRETH_GIGA +#define CONFIG_GRETH_GIGA 0 +#endif + +#if defined CONFIG_GRETH_FIFO4 +#define CFG_GRETH_FIFO 4 +#elif defined CONFIG_GRETH_FIFO8 +#define CFG_GRETH_FIFO 8 +#elif defined CONFIG_GRETH_FIFO16 +#define CFG_GRETH_FIFO 16 +#elif defined CONFIG_GRETH_FIFO32 +#define CFG_GRETH_FIFO 32 +#elif defined CONFIG_GRETH_FIFO64 +#define CFG_GRETH_FIFO 64 +#else +#define CFG_GRETH_FIFO 8 +#endif + +#ifndef CONFIG_UART1_ENABLE +#define CONFIG_UART1_ENABLE 0 +#endif + +#if defined CONFIG_UA1_FIFO1 +#define CFG_UA1_FIFO 1 +#elif defined CONFIG_UA1_FIFO2 +#define CFG_UA1_FIFO 2 +#elif defined CONFIG_UA1_FIFO4 +#define CFG_UA1_FIFO 4 +#elif defined CONFIG_UA1_FIFO8 +#define CFG_UA1_FIFO 8 +#elif defined CONFIG_UA1_FIFO16 +#define CFG_UA1_FIFO 16 +#elif defined CONFIG_UA1_FIFO32 +#define CFG_UA1_FIFO 32 +#else +#define CFG_UA1_FIFO 1 +#endif + +#ifndef CONFIG_IRQ3_ENABLE +#define CONFIG_IRQ3_ENABLE 0 +#endif +#ifndef CONFIG_IRQ3_NSEC +#define CONFIG_IRQ3_NSEC 0 +#endif +#ifndef CONFIG_GPT_ENABLE +#define CONFIG_GPT_ENABLE 0 +#endif + +#ifndef CONFIG_GPT_NTIM +#define CONFIG_GPT_NTIM 1 +#endif + +#ifndef CONFIG_GPT_SW +#define CONFIG_GPT_SW 8 +#endif + +#ifndef CONFIG_GPT_TW +#define CONFIG_GPT_TW 8 +#endif + +#ifndef CONFIG_GPT_IRQ +#define CONFIG_GPT_IRQ 8 +#endif + +#ifndef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 0 +#endif +#ifndef CONFIG_GPT_ENABLE +#define CONFIG_GPT_ENABLE 0 +#endif + +#ifndef CONFIG_GPT_NTIM +#define CONFIG_GPT_NTIM 1 +#endif + +#ifndef CONFIG_GPT_SW +#define CONFIG_GPT_SW 8 +#endif + +#ifndef CONFIG_GPT_TW +#define CONFIG_GPT_TW 8 +#endif + +#ifndef CONFIG_GPT_IRQ +#define CONFIG_GPT_IRQ 8 +#endif + +#ifndef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 0 +#endif + +#ifndef CONFIG_GPT_WDOGEN +#define CONFIG_GPT_WDOGEN 0 +#endif + +#ifndef CONFIG_GPT_WDOG +#define CONFIG_GPT_WDOG 0 +#endif + +#ifndef CONFIG_GRGPIO_ENABLE +#define CONFIG_GRGPIO_ENABLE 0 +#endif +#ifndef CONFIG_GRGPIO_IMASK +#define CONFIG_GRGPIO_IMASK 0000 +#endif +#ifndef CONFIG_GRGPIO_WIDTH +#define CONFIG_GRGPIO_WIDTH 1 +#endif + +#ifndef CONFIG_VGA_ENABLE +#define CONFIG_VGA_ENABLE 0 +#endif +#ifndef CONFIG_SVGA_ENABLE +#define CONFIG_SVGA_ENABLE 0 +#endif +#ifndef CONFIG_KBD_ENABLE +#define CONFIG_KBD_ENABLE 0 +#endif + + +#ifndef CONFIG_SPIMCTRL +#define CONFIG_SPIMCTRL 0 +#endif + +#ifndef CONFIG_SPIMCTRL_SDCARD +#define CONFIG_SPIMCTRL_SDCARD 0 +#endif + +#ifndef CONFIG_SPIMCTRL_READCMD +#define CONFIG_SPIMCTRL_READCMD 0 +#endif + +#ifndef CONFIG_SPIMCTRL_DUMMYBYTE +#define CONFIG_SPIMCTRL_DUMMYBYTE 0 +#endif + +#ifndef CONFIG_SPIMCTRL_DUALOUTPUT +#define CONFIG_SPIMCTRL_DUALOUTPUT 0 +#endif + +#ifndef CONFIG_SPIMCTRL_SCALER +#define CONFIG_SPIMCTRL_SCALER 1 +#endif + +#ifndef CONFIG_SPIMCTRL_ASCALER +#define CONFIG_SPIMCTRL_ASCALER 1 +#endif + +#ifndef CONFIG_SPIMCTRL_PWRUPCNT +#define CONFIG_SPIMCTRL_PWRUPCNT 0 +#endif +#ifndef CONFIG_SPICTRL_ENABLE +#define CONFIG_SPICTRL_ENABLE 0 +#endif +#ifndef CONFIG_SPICTRL_NUM +#define CONFIG_SPICTRL_NUM 1 +#endif +#ifndef CONFIG_SPICTRL_SLVS +#define CONFIG_SPICTRL_SLVS 1 +#endif +#ifndef CONFIG_SPICTRL_FIFO +#define CONFIG_SPICTRL_FIFO 1 +#endif +#ifndef CONFIG_SPICTRL_SLVREG +#define CONFIG_SPICTRL_SLVREG 0 +#endif +#ifndef CONFIG_SPICTRL_ODMODE +#define CONFIG_SPICTRL_ODMODE 0 +#endif +#ifndef CONFIG_SPICTRL_AM +#define CONFIG_SPICTRL_AM 0 +#endif +#ifndef CONFIG_SPICTRL_ASEL +#define CONFIG_SPICTRL_ASEL 0 +#endif +#ifndef CONFIG_SPICTRL_TWEN +#define CONFIG_SPICTRL_TWEN 0 +#endif +#ifndef CONFIG_SPICTRL_MAXWLEN +#define CONFIG_SPICTRL_MAXWLEN 0 +#endif +#ifndef CONFIG_SPICTRL_SYNCRAM +#define CONFIG_SPICTRL_SYNCRAM 0 +#endif +#if defined(CONFIG_SPICTRL_DMRFT) +#define CONFIG_SPICTRL_FT 1 +#elif defined(CONFIG_SPICTRL_TMRFT) +#define CONFIG_SPICTRL_FT 2 +#else +#define CONFIG_SPICTRL_FT 0 +#endif + +#ifndef CONFIG_DEBUG_UART +#define CONFIG_DEBUG_UART 0 +#endif diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/readme.txt b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/readme.txt --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/readme.txt +++ b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/readme.txt @@ -1,13 +1,13 @@ -leon3_soc : - ENABLE_AHB_UART = 0 (disabled) - ENABLE_APB_UART = 0 (disabled) - FPU_NETLIST = 1 (enabled) - -apb_lfr_management : - lfr_cal_driver (enabled) - -top : - LFR_rstn <= LFR_soft_rstn AND rstn_25; - -GRSPW : - ft = 1 (enabled) +leon3_soc : + ENABLE_AHB_UART = 0 (disabled) + ENABLE_APB_UART = 0 (disabled) + FPU_NETLIST = 1 (enabled) + +apb_lfr_management : + lfr_cal_driver (enabled) + +top : + LFR_rstn <= LFR_soft_rstn AND rstn_25; + +GRSPW : + ft = 1 (enabled) diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/readme.txt b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/readme.txt --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/readme.txt +++ b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/readme.txt @@ -1,13 +1,13 @@ -leon3_soc : - ENABLE_AHB_UART = 0 (disabled) - ENABLE_APB_UART = 0 (disabled) - FPU_NETLIST = 0 (enabled) - -apb_lfr_management : - lfr_cal_driver (enabled) - -top : - LFR_rstn <= LFR_soft_rstn AND rstn_25; - -GRSPW : - ft = 1 (enabled) +leon3_soc : + ENABLE_AHB_UART = 0 (disabled) + ENABLE_APB_UART = 0 (disabled) + FPU_NETLIST = 0 (enabled) + +apb_lfr_management : + lfr_cal_driver (enabled) + +top : + LFR_rstn <= LFR_soft_rstn AND rstn_25; + +GRSPW : + ft = 1 (enabled) diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/readme.txt b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/readme.txt --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/readme.txt +++ b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/readme.txt @@ -1,16 +1,16 @@ -leon3_soc : - ENABLE_AHB_UART = 0 (disabled) - ENABLE_APB_UART = 0 (disabled) - FPU_NETLIST = 0 (enabled) - -apb_lfr_management : - lfr_cal_driver (enabled) - -top : - LFR_rstn <= LFR_soft_rstn AND rstn_25; - -GRSPW : - ft = 1 (enabled) - -Constraint file : - LFR_EQM_altran_syn_fanout.sdc +leon3_soc : + ENABLE_AHB_UART = 0 (disabled) + ENABLE_APB_UART = 0 (disabled) + FPU_NETLIST = 0 (enabled) + +apb_lfr_management : + lfr_cal_driver (enabled) + +top : + LFR_rstn <= LFR_soft_rstn AND rstn_25; + +GRSPW : + ft = 1 (enabled) + +Constraint file : + LFR_EQM_altran_syn_fanout.sdc diff --git a/designs/Validation_IIR_LFR/Makefile b/designs/Validation_IIR_LFR/Makefile --- a/designs/Validation_IIR_LFR/Makefile +++ b/designs/Validation_IIR_LFR/Makefile @@ -2,9 +2,9 @@ VHDLIB=../.. SCRIPTSDIR=$(VHDLIB)/scripts/ GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=leon3mp -BOARD=em-LeonLPP-A3PE3kL-v3-core1 -include $(GRLIB)/boards/$(BOARD)/Makefile.inc +TOP=testbench +BOARD=LFR-EQM +include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc DEVICE=$(PART)-$(PACKAGE)$(SPEED) UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf @@ -12,31 +12,34 @@ EFFORT=high XSTOPT= SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -VHDLSYNFILES= -VHDLSIMFILES= tb.vhd +VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd +VHDLSIMFILES= tb.vhd SIMTOP=testbench #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc -#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc -PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc +SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut CLEAN=soft-clean -TECHLIBS = proasic3e +TECHLIBS = axcelerator LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc + tmtc openchip hynix ihp gleichmann micron usbhc opencores DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \ ./amba_lcd_16x2_ctrlr \ ./general_purpose/lpp_AMR \ ./general_purpose/lpp_balise \ ./general_purpose/lpp_delay \ ./lpp_bootloader \ + ./lfr_management \ + ./lpp_sim \ + ./lpp_sim/CY7C1061DV33 \ ./lpp_cna \ ./lpp_uart \ ./lpp_usb \ - ./dsp/lpp_fft_rtax \ + ./dsp/lpp_fft \ FILESKIP = i2cmst.vhd \ APB_MULTI_DIODE.vhd \ diff --git a/designs/Validation_IIR_LFR/PlotResults.ipynb b/designs/Validation_IIR_LFR/PlotResults.ipynb new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/PlotResults.ipynb @@ -0,0 +1,83 @@ +{ + "cells": [ + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false + }, + "outputs": [], + "source": [ + "#%matplotlib qt\n", + "%matplotlib inline\n", + "import matplotlib.pyplot as plt\n", + "plt.rcParams[\"figure.figsize\"] = [12,12]\n", + "import numpy as np\n", + "import pandas as pds" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false + }, + "outputs": [], + "source": [ + "def try_plot(df,ax,left,right):\n", + " try:\n", + " df[(df.index >= left) & (df.index <= right)].plot(ax=ax,subplots=True,legend=False)\n", + " except:\n", + " pass\n", + " \n", + "def make_plots(path=\"./simulation\",left=50e-3,right=100e-3):\n", + " inputSig = pds.read_csv(path+\"/log_input.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS2\",\"BIAS3\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n", + " fXSig=[]\n", + " G=[0.89,0.87,0.89]\n", + " [fXSig.append(pds.read_csv(\n", + " path+\"./log_output_f{0}.txt\".format(F),index_col=0,delim_whitespace=True,header=None,\n", + " names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])) for F in range(3) ]\n", + " inputSig.index*=5e-9\n", + " for F in range(3):\n", + " if len(fXSig[F].index):\n", + " fXSig[F].index*=5e-9\n", + " fXSig[F]/=G[F]\n", + " axes=inputSig[(inputSig.index >= left) & (inputSig.index <= right)].filter([\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"]).plot(subplots=True,layout=(3,2)) \n", + " [ try_plot(df,axes,left,right) for df in fXSig ]\n", + " " + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false + }, + "outputs": [], + "source": [ + "make_plots()" + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.5.2" + } + }, + "nbformat": 4, + "nbformat_minor": 1 +} diff --git a/designs/Validation_IIR_LFR/SimuManager.ipynb b/designs/Validation_IIR_LFR/SimuManager.ipynb new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/SimuManager.ipynb @@ -0,0 +1,223 @@ +{ + "cells": [ + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false + }, + "outputs": [], + "source": [ + "import random\n", + "import time\n", + "#%matplotlib inline\n", + "import matplotlib.pyplot as plt\n", + "import numpy as np\n", + "import pandas as pds\n", + "import datetime as dt" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], + "source": [ + "DOFILE=\"run.do.in\"\n", + "RAM1={\n", + "\"instance\":\"testbench/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n", + "\"abits\":8,\n", + "\"dbits\":12,\n", + "\"name\":\"RAM1.txt\"\n", + "}\n", + "RAM2={\n", + "\"instance\":\"testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n", + "\"abits\":8,\n", + "\"dbits\":12,\n", + "\"name\":\"RAM2.txt\"\n", + "}\n", + "RAM3={\n", + "\"instance\":\"testbench/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n", + "\"abits\":9,\n", + "\"dbits\":10,\n", + "\"name\":\"RAM3.txt\"\n", + "}\n", + "RAM4={\n", + "\"instance\":\"testbench/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/axc/x0/a8to12/agen(1)/u0/u0/MEMORYFILE\",\n", + "\"abits\":9,\n", + "\"dbits\":10,\n", + "\"name\":\"RAM4.txt\"\n", + "}\n", + "RAM5={\n", + "\"instance\":\"testbench/lpp_lfr_filter_1/YES_IIR_FILTER_f2_f3/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n", + "\"abits\":8,\n", + "\"dbits\":12,\n", + "\"name\":\"RAM5.txt\"\n", + "}\n", + "RAM6={\n", + "\"instance\":\"testbench/lpp_lfr_filter_1/YES_IIR_FILTER_f2_f3/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/axc/x0/a8to12/agen(0)/u0/u0/MEMORYFILE\",\n", + "\"abits\":8,\n", + "\"dbits\":12,\n", + "\"name\":\"RAM6.txt\"\n", + "}\n", + "\n", + "RAMS=[RAM1,RAM2,RAM3,RAM4,RAM5,RAM6]" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false + }, + "outputs": [], + "source": [ + "def mkram(length,width,gentype='rand',**kwargs):\n", + " return toBinStr(gen(length,width,gentype,**kwargs),width)\n", + "\n", + "def toBinStr(data,width):\n", + " return [format(val, 'b').zfill(width) for val in data]\n", + "\n", + "def gen(length,width,gentype='rand',**kwargs):\n", + " LUT={\n", + " \"rand\":gen_rand,\n", + " \"const\":gen_const\n", + " }\n", + " return LUT[gentype](length,width,**kwargs)\n", + "\n", + "def gen_rand(length,width,**kwargs):\n", + " random.seed(time.time())\n", + " mask=(2**width)-1\n", + " data=[]\n", + " for line in range(length):\n", + " data.append(int(2**32*random.random())&mask)\n", + " return data\n", + "\n", + "def gen_const(length,width, value):\n", + " mask=(2**width)-1\n", + " return [value&mask for i in range(length)]\n", + "\n", + "def save(data,file):\n", + " f = open(file,\"w\")\n", + " [f.write(line+'\\n') for line in data]\n", + " f.close()\n", + " \n", + "def start_Vsim(gentype='rand',**kwargs):\n", + " args=\"\"\n", + " for RAM in RAMS:\n", + " save(mkram(2**RAM[\"abits\"],RAM[\"dbits\"],gentype=gentype,**kwargs),\"simulation/\"+RAM[\"name\"])\n", + " args = args + \" -g\" + RAM[\"instance\"] + \"=\\\"\" + RAM[\"name\"] + \"\\\"\"\n", + " with open(\"run.do.in\",\"r\") as inFile, open(\"simulation/run.do\",\"w\") as outFile:\n", + " input = inFile.read()\n", + " outFile.write(input.replace(\"#VSIM_ARGS#\",args))\n", + " $(cd simulation)\n", + " vsim -do run.do > sim.log\n", + " folder=dt.datetime.today().strftime(\"%Y-%m-%d_%H-%M\")\n", + " mkdir @(folder)\n", + " for RAM in RAMS:\n", + " cp @(RAM[\"name\"]) @(folder+\"/\"+RAM[\"name\"])\n", + " cp log*.txt run.do sim.log @(folder) \n", + " $(cd ..)\n", + " \n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false + }, + "outputs": [], + "source": [] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false + }, + "outputs": [], + "source": [ + "df = pds.read_csv(\"./simulation/log_input.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS2\",\"BIAS3\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n", + "df2 = pds.read_csv(\"./simulation/log_output_f0.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n", + "df3 = pds.read_csv(\"./simulation/log_output_f1.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n", + "df4 = pds.read_csv(\"./simulation/log_output_f2.txt\",index_col=0,delim_whitespace=True,header=None,names=[\"TSTAMP\",\"BIAS1\",\"BIAS4\",\"BIAS5\",\"B1\",\"B2\",\"B3\"])\n", + "\n", + "df.index*=5e-9\n", + "if len(df2.index):\n", + " df2.index*=5e-9\n", + " df2/=0.89\n", + "if len(df3.index):\n", + " df3.index*=5e-9\n", + " df3/=0.87\n", + "if len(df4.index):\n", + " df4.index*=5e-9\n", + " df4/=0.89\n", + "\n", + "print(len(df))\n", + "df.filter([\"B1\"]).plot()\n", + "#plt.plot(df2)\n", + "plt.plot(df3.filter([\"B1\"]))\n", + "#plt.plot(df4)\n", + "plt.show()" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false + }, + "outputs": [], + "source": [ + "cd .." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false + }, + "outputs": [], + "source": [ + "mkram(2,32)\n", + "\n", + "mkram(20,32,gentype='const',value=55)\n", + "\n", + "save(mkram(10,32),\"RAM_FILE.txt\")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": false, + "scrolled": false + }, + "outputs": [], + "source": [ + "for i in range(2):\n", + " start_Vsim(gentype='rand',value=0)" + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Xonsh", + "language": "xonsh", + "name": "xonsh" + }, + "language_info": { + "codemirror_mode": "shell", + "file_extension": ".xsh", + "mimetype": "text/x-sh", + "name": "xonsh", + "pygments_lexer": "xonsh" + } + }, + "nbformat": 4, + "nbformat_minor": 1 +} diff --git a/designs/Validation_IIR_LFR/generator.vhd b/designs/Validation_IIR_LFR/generator.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/generator.vhd @@ -0,0 +1,74 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +use ieee.numeric_std.all; +USE IEEE.std_logic_signed.ALL; +USE IEEE.MATH_real.ALL; + +ENTITY generator IS + + GENERIC ( + AMPLITUDE : INTEGER := 100; + NB_BITS : INTEGER := 16); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + + data_ack : IN STD_LOGIC; + offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0); + data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0) + ); + +END generator; + +ARCHITECTURE beh OF generator IS + + SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0); +BEGIN -- beh + + + PROCESS (clk, rstn) + variable seed1, seed2: positive; -- seed values for random generator + variable rand: real; -- random real-number value in range 0 to 1.0 + BEGIN -- PROCESS + uniform(seed1, seed2, rand);--more entropy by skipping values + IF rstn = '0' THEN -- asynchronous reset (active low) + reg <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF run = '0' THEN + reg <= (OTHERS => '0'); + ELSE + IF data_ack = '1' THEN + reg <= std_logic_vector(to_signed(INTEGER( (REAL(AMPLITUDE) * rand) + REAL(to_integer(SIGNED(offset))) ),NB_BITS)); + END IF; + END IF; + END IF; + END PROCESS; + + data <= reg; + +END beh; diff --git a/designs/Validation_IIR_LFR/run.do.in b/designs/Validation_IIR_LFR/run.do.in new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/run.do.in @@ -0,0 +1,516 @@ +quietly set ACTELLIBNAME Axcelerator +quietly set PROJECT_DIR "C:/opt/VHDLIB/designs/Validation_IIR_LFR" + +if {[file exists presynth/_info]} { + echo "INFO: Simulation library presynth already exists" +} else { + vlib presynth +} +vmap presynth presynth +vmap Axcelerator "C:/Microsemi/Libero_v9.2/Designer/lib/modelsim/precompiled/vhdl/Axcelerator" +if {[file exists grlib/_info]} { + echo "INFO: Simulation library grlib already exists" +} else { + vlib grlib +} +vmap grlib "grlib" +if {[file exists synplify/_info]} { + echo "INFO: Simulation library synplify already exists" +} else { + vlib synplify +} +vmap synplify "synplify" +if {[file exists techmap/_info]} { + echo "INFO: Simulation library techmap already exists" +} else { + vlib techmap +} +vmap techmap "techmap" +if {[file exists spw/_info]} { + echo "INFO: Simulation library spw already exists" +} else { + vlib spw +} +vmap spw "spw" +if {[file exists eth/_info]} { + echo "INFO: Simulation library eth already exists" +} else { + vlib eth +} +vmap eth "eth" +if {[file exists gaisler/_info]} { + echo "INFO: Simulation library gaisler already exists" +} else { + vlib gaisler +} +vmap gaisler "gaisler" +if {[file exists esa/_info]} { + echo "INFO: Simulation library esa already exists" +} else { + vlib esa +} +vmap esa "esa" +if {[file exists fmf/_info]} { + echo "INFO: Simulation library fmf already exists" +} else { + vlib fmf +} +vmap fmf "fmf" +if {[file exists spansion/_info]} { + echo "INFO: Simulation library spansion already exists" +} else { + vlib spansion +} +vmap spansion "spansion" +if {[file exists gsi/_info]} { + echo "INFO: Simulation library gsi already exists" +} else { + vlib gsi +} +vmap gsi "gsi" +if {[file exists iap/_info]} { + echo "INFO: Simulation library iap already exists" +} else { + vlib iap +} +vmap iap "iap" +if {[file exists lpp/_info]} { + echo "INFO: Simulation library lpp already exists" +} else { + vlib lpp +} +vmap lpp "lpp" +if {[file exists cypress/_info]} { + echo "INFO: Simulation library cypress already exists" +} else { + vlib cypress +} +vmap cypress "cypress" + +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/version.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/config_types.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/config.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/stdlib.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/stdio.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/stdlib/testlib.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/ftlib/mtie_ftlib.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/util/util.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/sparc/sparc.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/sparc/sparc_disas.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/sparc/cpu_disas.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/modgen/multlib.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/modgen/leaves.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/amba.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/devices.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/defmst.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/apbctrl.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ahbctrl.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/dma2ahb_pkg.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/dma2ahb.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ahbmst.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ahbmon.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/apbmon.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/ambamon.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/dma2ahb_tp.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/amba/amba_tp.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_pkg.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_mst_pkg.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_slv_pkg.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_util.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_mst.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_slv.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahbs.vhd" +vcom -93 -explicit -work grlib "${PROJECT_DIR}/../../../GRLIB/lib/grlib/atf/at_ahb_ctrl.vhd" +vcom -93 -explicit -work synplify "${PROJECT_DIR}/../../../GRLIB/lib/synplify/sim/synplify.vhd" +vcom -93 -explicit -work synplify "${PROJECT_DIR}/../../../GRLIB/lib/synplify/sim/synattr.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/gencomp/gencomp.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/gencomp/netcomp.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/memory_inferred.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/tap_inferred.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/ddr_inferred.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/mul_inferred.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/ddr_phy_inferred.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/ddrphy_datapath.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/sim_pll.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/inferred/lpddr2_phy_inferred.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/axcomp.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/memory_axcelerator.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/buffer_axcelerator.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/pads_axcelerator.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/clkgen_axcelerator.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/ddr_axcelerator.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/mul_axcelerator.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/axcelerator/grpci2_phy_rtax_bypass.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allclkgen.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allddr.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allmem.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allmul.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/allpads.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/alltap.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkgen.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkmux.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkinv.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkand.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ddr_ireg.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ddr_oreg.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ddrphy.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram64.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram_2p.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram_dp.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncfifo_2p.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/regfile_3p.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/tap.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/techbuf.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/nandtree.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkpad.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/clkpad_ds.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/inpad.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/inpad_ds.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iodpad.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iopad.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iopad_ds.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/lvds_combo.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/odpad.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/outpad.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/outpad_ds.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/toutpad.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/skew_outpad.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/mul_61x61.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/cpu_disas_net.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/ringosc.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/grpci2_phy_net.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/system_monitor.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/grgates.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/inpad_ddr.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/outpad_ddr.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/iopad_ddr.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram128bw.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram256bw.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram128.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram156bw.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/techmult.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/spictrl_net.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncrambw.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncram_2pbw.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/sdram_phy.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/from.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/syncreg.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/serdes.vhd" +vcom -93 -explicit -work techmap "${PROJECT_DIR}/../../../GRLIB/lib/techmap/maps/mtie_maps.vhd" +vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/comp/spwcomp.vhd" +vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/core/mtie_core.vhd" +vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/wrapper/grspw_gen.vhd" +vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/wrapper/grspw2_gen.vhd" +vcom -93 -explicit -work spw "${PROJECT_DIR}/../../../GRLIB/lib/spw/wrapper/grspw_codec_gen.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/comp/ethcomp.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_pkg.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_rstgen.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_edcl_ahb_mst.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_ahb_mst_gbit.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/eth_ahb_mst.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbit_rx.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbit_tx.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbit_gtx.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_tx.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_rx.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/greth_gbitc.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/core/grethc.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/wrapper/greth_gen.vhd" +vcom -93 -explicit -work eth "${PROJECT_DIR}/../../../GRLIB/lib/eth/wrapper/greth_gbit_gen.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/arith/arith.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/arith/mul32.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/arith/div32.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/memctrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/sdctrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/sdctrl64.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/sdmctrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/srctrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ssrctrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsrctrlc.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsrctrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsdctrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsrctrl8.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsdmctrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftmctrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/memctrl/ftsdctrl64.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/grlfpu/mtie_grlfpu.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/grlfpc/mtie_grlfpc.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmuconfig.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmuiface.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/libmmu.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmutlbcam.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmulrue.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmulru.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmutlb.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmutw.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/srmmu/mmu.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/leon3/leon3.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/leon3/grfpushwx.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/leon3v3/mtie_leon3v3.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqmp.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqmp2x.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqamp.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/irqmp/irqamp2x.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/l2cache/v2-pkg/l2cache.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/misc.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/rstgen.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/gptimer.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbram.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbdpram.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbtrace_mmb.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbtrace_mb.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbtrace.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grgpio.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ftahbram.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ftahbram2.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbstat.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/logan.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/apbps2.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/charrom_package.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/charrom.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/apbvga.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahb2ahb.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbbridge.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/svgactrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grfifo.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/gradcdac.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grsysmon.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/gracectrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grgpreg.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/memscrub.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahb_mst_iface.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grgprbank.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grclkgate.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grclkgate2x.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grtimer.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grpulse.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/grversion.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/misc/ahbfrom.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/ambatest/ahbtbp.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/ambatest/ahbtbm.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/net/net.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/uart.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/libdcom.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/apbuart.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/dcom.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/dcom_uart.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/uart/ahbuart.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sim.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sram.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sramft.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/sram16.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/phy.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ahbrep.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/delay_wire.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/pwm_check.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ramback.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/zbtssram.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/slavecheck.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/spwtrace.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/spwtracev.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ddrram.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ddr2ram.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/sim/ddr3ram.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtag.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/libjtagcom.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtagcom.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/ahbjtag.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/ahbjtag_bsd.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/bscanctrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/bscanregs.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/bscanregsbd.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtagcom2.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/jtag/jtagtst.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/spacewire.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw2.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspwm.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw2_phy.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw_codec_clockgate.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/spacewire/grspw_phy.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/gr1553b/gr1553b_pkg.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/gr1553b/gr1553b_pads.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/gr1553b/simtrans1553.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/nand/nandpkg.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/nand/nandfctrlx.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/nand/nandfctrl.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/clk2x/clk2x.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/clk2x/qmod.vhd" +vcom -93 -explicit -work gaisler "${PROJECT_DIR}/../../../GRLIB/lib/gaisler/clk2x/qmod_prect.vhd" +vcom -93 -explicit -work esa "${PROJECT_DIR}/../../../GRLIB/lib/esa/memoryctrl/memoryctrl.vhd" +vcom -93 -explicit -work esa "${PROJECT_DIR}/../../../GRLIB/lib/esa/memoryctrl/mctrl.vhd" +vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/utilities/conversions.vhd" +vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/utilities/gen_utils.vhd" +vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/flash/flash.vhd" +vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/flash/s25fl064a.vhd" +vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/flash/m25p80.vhd" +vcom -93 -explicit -work fmf "${PROJECT_DIR}/../../../GRLIB/lib/fmf/fifo/idt7202.vhd" +vcom -93 -explicit -work gsi "${PROJECT_DIR}/../../../GRLIB/lib/gsi/ssram/functions.vhd" +vcom -93 -explicit -work gsi "${PROJECT_DIR}/../../../GRLIB/lib/gsi/ssram/core_burst.vhd" +vcom -93 -explicit -work gsi "${PROJECT_DIR}/../../../GRLIB/lib/gsi/ssram/g880e18bt.vhd" +vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./apb_devices/apb_devices_list.vhd" +vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./apb_devices/apb_devices.vhd" +vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./memctrlr/memctrlr.vhd" +vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./memctrlr/srctrle-0ws.vhd" +vcom -93 -explicit -work iap "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB_NONFREE/lib/iap/./memctrlr/srctrle-1ws.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/data_type_pkg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/general_purpose.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/ADDRcntr.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/ALU.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Adder.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Clk_Divider2.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Clk_divider.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_CONTROLER.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_MUX.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_MUX2.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MAC_REG.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MUX2.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/MUXN.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Multiplier.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/REG.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/SYNC_FF.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Shifter.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/TwoComplementer.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/Clock_Divider.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/lpp_front_to_level.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/lpp_front_detection.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/RR_Arbiter_4.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/general_counter.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./general_purpose/ramp_generator.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_amba/apb_devices_list.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_amba/lpp_amba.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/chirp/chirp_pkg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/chirp/chirp.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/iir_filter.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/RAM.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_pkg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_integrator.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_downsampler.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_comb.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_control.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_add_sub.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_address_gen.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_r2.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/cic/cic_lfr_control_r2.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/fft_components.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/lpp_fft.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/actar.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/actram.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/fftDp.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/fftSm.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/primitives.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/twiddle.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/Driver_FFT.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/FFT.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/lpp_fft_rtax/Linker_FFT.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/window_function_pkg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/window_function.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/WF_processing.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./dsp/window_function/WF_rom.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_memory.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_control.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_memory/lppFIFOxN.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/RHF1401.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_ad_Conv/lpp_lfr_hk.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/MS_control.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_demux/DEMUX.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_demux/lpp_demux.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_Header/lpp_Header.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_Header/HeaderBuilder.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/lpp_matrix.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/ALU_Driver.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/Dispatch.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/DriveInputs.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/GetResult.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/Matrix.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/SpectralMatrix.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/fifo_latency_correction.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_ip.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_reg_head.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd" +vcom -93 -explicit -work lpp "${PROJECT_DIR}/../../../GRLIB/lib/../../VHDLIB/lib/lpp/./lpp_file/reader_pkg.vhd" +vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/components.vhd" +vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/package_utility.vhd" +vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/cy7c1354b.vhd" +vcom -93 -explicit -work cypress "${PROJECT_DIR}/../../../GRLIB/lib/cypress/ssram/cy7c1380d.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../../../GRLIB/lib/work/debug/debug.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../../../GRLIB/lib/work/debug/grtestmod.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/../../../GRLIB/lib/work/debug/cpu_disas.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/IIR_CEL_TEST.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/tb.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/IIR_CEL_TEST_v3.vhd" +vcom -93 -explicit -work presynth "${PROJECT_DIR}/generator.vhd" + +vsim #VSIM_ARGS# -L Axcelerator -L presynth -L grlib -L synplify -L techmap -L spw -L eth -L gaisler -L esa -L fmf -L spansion -L gsi -L iap -L lpp -L cypress -t 1ps presynth.testbench +# The following lines are commented because no testbench is associated with the project +# do "wave.do" +run 2000ms diff --git a/designs/Validation_IIR_LFR/tb.vhd b/designs/Validation_IIR_LFR/tb.vhd --- a/designs/Validation_IIR_LFR/tb.vhd +++ b/designs/Validation_IIR_LFR/tb.vhd @@ -1,11 +1,15 @@ -LIBRARY ieee; +LIBRARY ieee; USE ieee.std_logic_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; +use ieee.numeric_std.all; +USE IEEE.std_logic_signed.ALL; +USE IEEE.MATH_real.ALL; LIBRARY techmap; -USE techmap.gencomp.ALL; +USE techmap.gencomp.ALL; + +library std; +use std.textio.all; LIBRARY lpp; USE lpp.iir_filter.ALL; @@ -14,7 +18,6 @@ USE lpp.FILTERcfg.ALL; USE lpp.lpp_lfr_filter_coeff.ALL; USE lpp.general_purpose.ALL; USE lpp.data_type_pkg.ALL; -USE lpp.chirp_pkg.ALL; USE lpp.lpp_lfr_pkg.ALL; USE lpp.general_purpose.ALL; @@ -22,61 +25,64 @@ ENTITY testbench IS END; ARCHITECTURE behav OF testbench IS - - COMPONENT IIR_CEL_TEST - PORT ( - rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - sample_in_val : IN STD_LOGIC; - sample_in : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); - sample_out_val : OUT STD_LOGIC; - sample_out : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0)); - END COMPONENT; - - COMPONENT IIR_CEL_TEST_v3 - PORT ( - rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - sample_in1_val : IN STD_LOGIC; - sample_in1 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); - sample_in2_val : IN STD_LOGIC; - sample_in2 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); - sample_out1_val : OUT STD_LOGIC; - sample_out1 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0); - sample_out2_val : OUT STD_LOGIC; - sample_out2 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0)); - END COMPONENT; - + + SIGNAL TSTAMP : INTEGER:=0; SIGNAL clk : STD_LOGIC := '0'; SIGNAL clk_24k : STD_LOGIC := '0'; SIGNAL clk_24k_r : STD_LOGIC := '0'; SIGNAL rstn : STD_LOGIC; + SIGNAL signal_gen : Samples(7 DOWNTO 0); + SIGNAL offset_gen : Samples(7 DOWNTO 0); + SIGNAL sample : Samples(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; - SIGNAL sample_val_2 : STD_LOGIC; - SIGNAL data_chirp : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL data_chirp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f3_val : STD_LOGIC; - SIGNAL sample_s : samplT(7 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_out_s : samplT(7 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_out_s2 : samplT(7 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_out_val : STD_LOGIC; + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + SIGNAL sample_f0 : Samples(5 DOWNTO 0); + SIGNAL sample_f1 : Samples(5 DOWNTO 0); + SIGNAL sample_f2 : Samples(5 DOWNTO 0); + SIGNAL sample_f3 : Samples(5 DOWNTO 0); - SIGNAL sample_out1_val : STD_LOGIC; - SIGNAL sample_out2_val : STD_LOGIC; - SIGNAL sample_out1 : samplT(7 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_out2 : samplT(7 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_out1_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_out2_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0); - - SIGNAL sample_s_v3 : samplT(7 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_val_v3 : STD_LOGIC; - SIGNAL sample_val_v3_2 : STD_LOGIC; SIGNAL temp : STD_LOGIC; + + + COMPONENT generator IS + GENERIC ( + AMPLITUDE : INTEGER := 100; + NB_BITS : INTEGER := 16); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + + data_ack : IN STD_LOGIC; + offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0); + data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0) + ); + END COMPONENT; + + + file log_input : TEXT open write_mode is "log_input.txt"; + file log_output_f0 : TEXT open write_mode is "log_output_f0.txt"; + file log_output_f1 : TEXT open write_mode is "log_output_f1.txt"; + file log_output_f2 : TEXT open write_mode is "log_output_f2.txt"; + file log_output_f3 : TEXT open write_mode is "log_output_f3.txt"; + + BEGIN ----------------------------------------------------------------------------- @@ -91,23 +97,41 @@ BEGIN WAIT UNTIL clk = '1'; WAIT UNTIL clk = '1'; rstn <= '1'; - WAIT FOR 30 ms; + WAIT FOR 2000 ms; REPORT "*** END simulation ***" SEVERITY failure; WAIT; END PROCESS; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- - + -- COMMON TIMESTAMPS + ----------------------------------------------------------------------------- + + PROCESS(clk) + BEGIN + IF clk'event and clk ='1' THEN + TSTAMP <= TSTAMP+1; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- -- LPP_LFR_FILTER ----------------------------------------------------------------------------- lpp_lfr_filter_1: lpp_lfr_filter - GENERIC MAP ( - Mem_use => use_CEL) + GENERIC MAP ( + --tech => 0, + --Mem_use => use_CEL, + tech => axcel, + Mem_use => use_RAM, + RTL_DESIGN_LIGHT =>0 + ) PORT MAP ( sample => sample, sample_val => sample_val, - + sample_time => (others=>'0'), clk => clk, rstn => rstn, @@ -117,14 +141,16 @@ BEGIN data_shaping_R1 => '0', data_shaping_R2 => '0', - sample_f0_val => OPEN, - sample_f1_val => OPEN, - sample_f2_val => OPEN, - sample_f3_val => OPEN, - sample_f0_wdata => OPEN, - sample_f1_wdata => OPEN, - sample_f2_wdata => OPEN, - sample_f3_wdata => OPEN); + sample_f0_val => sample_f0_val, + sample_f1_val => sample_f1_val, + sample_f2_val => sample_f2_val, + sample_f3_val => sample_f3_val, + + sample_f0_wdata => sample_f0_wdata, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wdata => sample_f2_wdata, + sample_f3_wdata => sample_f3_wdata + ); ----------------------------------------------------------------------------- @@ -137,27 +163,22 @@ BEGIN BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) sample_val <= '0'; - sample_val_2 <= '0'; clk_24k_r <= '0'; temp <= '0'; ELSIF clk'event AND clk = '1' THEN -- rising clock edge clk_24k_r <= clk_24k; IF clk_24k = '1' AND clk_24k_r = '0' THEN sample_val <= '1'; - sample_val_2 <= temp; temp <= NOT temp; ELSE sample_val <= '0'; - sample_val_2 <= '0'; END IF; END IF; END PROCESS; ----------------------------------------------------------------------------- - chirp_1: chirp +generators: FOR I IN 0 TO 7 GENERATE + gen1: generator GENERIC MAP ( - LOW_FREQUENCY_LIMIT => 0, - HIGH_FREQUENCY_LIMIT => 2000, - NB_POINT_TO_GEN => 10000, AMPLITUDE => 100, NB_BITS => 16) PORT MAP ( @@ -165,97 +186,90 @@ BEGIN rstn => rstn, run => '1', data_ack => sample_val, - data => data_chirp); - - chirp_2: chirp - GENERIC MAP ( - LOW_FREQUENCY_LIMIT => 0, - HIGH_FREQUENCY_LIMIT => 2000, - NB_POINT_TO_GEN => 100000, - AMPLITUDE => 200, - NB_BITS => 16) - PORT MAP ( - clk => clk, - rstn => rstn, - run => '1', - data_ack => sample_val, - data => data_chirp_2); + offset => offset_gen(I), + data => signal_gen(I) + ); +offset_gen(I) <= std_logic_vector( to_signed((I*200),16) ); +END GENERATE generators; + +output_splitter: FOR CHAN IN 0 TO 5 GENERATE + bits_splitter: FOR BIT IN 0 TO 15 GENERATE + sample_f0(CHAN)(BIT) <= sample_f0_wdata((CHAN*16) + BIT); + sample_f1(CHAN)(BIT) <= sample_f1_wdata((CHAN*16) + BIT); + sample_f2(CHAN)(BIT) <= sample_f2_wdata((CHAN*16) + BIT); + sample_f3(CHAN)(BIT) <= sample_f3_wdata((CHAN*16) + BIT); + END GENERATE bits_splitter; +END GENERATE output_splitter; - all_channel: FOR I IN 0 TO 3 GENERATE - sample(2*I) <= data_chirp; - sample(2*I+1) <= data_chirp_2; - END GENERATE all_channel; - ----------------------------------------------------------------------------- - - all_channel_test: FOR I IN 0 TO 3 GENERATE - all_bit_test: FOR J IN 0 TO 15 GENERATE - sample_s(2*I ,J) <= data_chirp(J); - sample_s(2*I+1,J) <= data_chirp_2(J); - END GENERATE all_bit_test; - sample_s(2*I,16) <= data_chirp(15); - sample_s(2*I,17) <= data_chirp(15); - sample_s(2*I+1,16) <= data_chirp_2(15); - sample_s(2*I+1,17) <= data_chirp_2(15); - END GENERATE all_channel_test; - IIR_CEL_TEST_1: IIR_CEL_TEST - PORT MAP ( - rstn => rstn, - clk => clk, - sample_in_val => sample_val, - sample_in => sample_s, - sample_out_val => sample_out_val, - sample_out => sample_out_s); +sample <= signal_gen; - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - all_channel: FOR I IN 0 TO 7 LOOP - all_bit: FOR J IN 0 TO 17 LOOP - sample_out_s2(I,J) <= '0'; - END LOOP all_bit; - END LOOP all_channel; - - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - IF sample_out_val = '1' THEN - sample_out_s2 <= sample_out_s; - END IF; - END IF; - END PROCESS; + ----------------------------------------------------------------------------- + -- RECORD SIGNALS ----------------------------------------------------------------------------- - IIR_CEL_TEST_v3_1: IIR_CEL_TEST_v3 - PORT MAP ( - rstn => rstn, - clk => clk, - sample_in1_val => sample_val_v3, - sample_in1 => sample_s_v3, - sample_in2_val => sample_val_v3_2, - sample_in2 => sample_s_v3, - sample_out1_val => sample_out1_val, - sample_out1 => sample_out1, - sample_out2_val => sample_out2_val, - sample_out2 => sample_out2); + +process(sample_val) +variable line_var : line; +begin +if sample_val'event and sample_val='1' then + write(line_var,integer'image(TSTAMP) ); + for I IN 0 TO 7 loop + write(line_var, " " & integer'image(to_integer(signed(signal_gen(I))))); + end loop; + writeline(log_input,line_var); +end if; +end process; + +process(sample_f0_val) +variable line_var : line; +begin +if sample_f0_val'event and sample_f0_val='1' then + write(line_var,integer'image(TSTAMP) ); + for I IN 0 TO 5 loop + write(line_var, " " & integer'image(to_integer(signed(sample_f0(I))))); + end loop; + writeline(log_output_f0,line_var); +end if; +end process; + + +process(sample_f1_val) +variable line_var : line; +begin +if sample_f1_val'event and sample_f1_val='1' then + write(line_var,integer'image(TSTAMP) ); + for I IN 0 TO 5 loop + write(line_var, " " & integer'image(to_integer(signed(sample_f1(I))))); + end loop; + writeline(log_output_f1,line_var); +end if; +end process; + + +process(sample_f2_val) +variable line_var : line; +begin +if sample_f2_val'event and sample_f2_val='1' then + write(line_var,integer'image(TSTAMP) ); + for I IN 0 TO 5 loop + write(line_var, " " & integer'image(to_integer(signed(sample_f2(I))))); + end loop; + writeline(log_output_f2,line_var); +end if; +end process; + +process(sample_f3_val) +variable line_var : line; +begin +if sample_f3_val'event and sample_f3_val='1' then + write(line_var,integer'image(TSTAMP) ); + for I IN 0 TO 5 loop + write(line_var, " " & integer'image(to_integer(signed(sample_f3(I))))); + end loop; + writeline(log_output_f3,line_var); +end if; +end process; - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - IF sample_val = '1' THEN - sample_s_v3 <= sample_s; - END IF; - sample_val_v3 <= sample_val; - sample_val_v3_2 <= sample_val_2; - - IF sample_out1_val = '1' THEN - sample_out1_reg <= sample_out1; - END IF; - IF sample_out2_val = '1' THEN - sample_out2_reg <= sample_out2; - END IF; - END IF; - - END PROCESS; diff --git a/designs/beaglebone-test1/README.txt b/designs/beaglebone-test1/README.txt --- a/designs/beaglebone-test1/README.txt +++ b/designs/beaglebone-test1/README.txt @@ -1,209 +1,209 @@ -This leon3 design is tailored to the Xilinx SP605 Spartan6 board - -Simulation and synthesis ------------------------- - -The design uses the Xilinx MIG memory interface with an AHB-2.0 -interface. The MIG source code cannot be distributed due to the -prohibitive Xilinx license, so the MIG must be re-generated with -coregen before simulation and synthesis can be done. - -To generate the MIG and install tne Xilinx unisim simulation -library, do as follows: - - make mig - make install-secureip - -This will ONLY work with ISE-13.2 installed, and the XILINX variable -properly set in the shell. To synthesize the design, do - - make ise - -and then - - make ise-prog-fpga - -to program the FPGA. - -Design specifics ----------------- - -* System reset is mapped to the CPU RESET button - -* The AHB and processor is clocked by a 60 MHz clock, generated - from the 33 MHz SYSACE clock using a DCM. You can change the frequency - generation in the clocks menu of xconfig. The DDR3 (MIG) controller - runs at 667 MHz. - -* The GRETH core is enabled and runs without problems at 100 Mbit. - Ethernet debug link is enabled and has IP 192.168.0.51. - 1 Gbit operation is also possible (requires grlib com release), - uncomment related timing constraints in the leon3mp.ucf first. - -* 16-bit flash prom can be read at address 0. It can be programmed - with GRMON version 1.1.16 or later. - -* DDR3 is working with the provided Xilinx MIG DDR3 controller. - If you want to simulate this design, first install the secure - IP models with: - - make install-secureip - - Then rebuild the scripts and simulation model: - - make distclean vsim - - Modelsim v6.6e or newer is required to build the secure IP models. - Note that the regular leon3 test bench cannot be run in simulation - as the DDR3 model lacks data pre-load. - -* The application UART1 is connected to the USB/UART connector - -* The SVGA frame buffer uses a separate port on the DDR3 controller, - and therefore does not noticeably affect the performance of the processor. - Default output is analog VGA, to switch to DVI mode execute this - command in grmon: - - i2c dvi init_l4itx_vga - -* The JTAG DSU interface is enabled and accesible via the USB/JTAG port. - Start grmon with -xilusb to connect. - -* Output from GRMON is: - -$ grmon -xilusb -u - - GRMON LEON debug monitor v1.1.51 professional version (debug) - - Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved. - For latest updates, go to http://www.gaisler.com/ - Comments or bug-reports to support@gaisler.com - - Xilinx cable: Cable type/rev : 0x3 - JTAG chain: xc6slx45t xccace - - GRLIB build version: 4111 - - initialising ............... - detected frequency: 50 MHz - SRAM waitstates: 1 - - Component Vendor - LEON3 SPARC V8 Processor Gaisler Research - AHB Debug JTAG TAP Gaisler Research - GR Ethernet MAC Gaisler Research - LEON2 Memory Controller European Space Agency - AHB/APB Bridge Gaisler Research - LEON3 Debug Support Unit Gaisler Research - Xilinx MIG DDR2 controller Gaisler Research - AHB/APB Bridge Gaisler Research - Generic APB UART Gaisler Research - Multi-processor Interrupt Ctrl Gaisler Research - Modular Timer Unit Gaisler Research - SVGA Controller Gaisler Research - AMBA Wrapper for OC I2C-master Gaisler Research - General purpose I/O port Gaisler Research - AHB status register Gaisler Research - - Use command 'info sys' to print a detailed report of attached cores - -grlib> inf sys -00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0) - ahb master 0 -01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1) - ahb master 1 -02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0) - ahb master 2, irq 12 - apb: 80000e00 - 80000f00 - Device index: dev0 - edcl ip 192.168.1.51, buffer 2 kbyte -00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1) - ahb: 00000000 - 20000000 - apb: 80000000 - 80000100 - 16-bit prom @ 0x00000000 -01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) - ahb: 80000000 - 80100000 -02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1) - ahb: 90000000 - a0000000 - AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0 - CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1 - icache 2 * 8 kbyte, 32 byte/line rnd - dcache 2 * 4 kbyte, 16 byte/line rnd -04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0) - ahb: 40000000 - 48000000 - apb: 80100000 - 80100100 - DDR2: 128 Mbyte -0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) - ahb: 80100000 - 80200000 -01.01:00c Gaisler Research Generic APB UART (ver 0x1) - irq 2 - apb: 80000100 - 80000200 - baud rate 38343, DSU mode (FIFO debug) -02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3) - apb: 80000200 - 80000300 -03.01:011 Gaisler Research Modular Timer Unit (ver 0x0) - irq 8 - apb: 80000300 - 80000400 - 8-bit scaler, 2 * 32-bit timers, divisor 50 -06.01:063 Gaisler Research SVGA Controller (ver 0x0) - apb: 80000600 - 80000700 - clk0: 50.00 MHz -09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3) - irq 14 - apb: 80000900 - 80000a00 -0a.01:01a Gaisler Research General purpose I/O port (ver 0x1) - apb: 80000a00 - 80000b00 -0f.01:052 Gaisler Research AHB status register (ver 0x0) - irq 7 - apb: 80000f00 - 80001000 -grlib> fla - - Intel-style 16-bit flash on D[31:16] - - Manuf. Intel - Device Strataflash P30 - - Device ID 02e44603e127ffff - User ID ffffffffffffffff - - - 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000 - - - CFI info - flash family : 1 - flash size : 256 Mbit - erase regions : 2 - erase blocks : 259 - write buffer : 1024 bytes - lock-down : yes - region 0 : 255 blocks of 128 Kbytes - region 1 : 4 blocks of 32 Kbytes - -grlib> lo ~/ibm/src/bench/leonbench/coremark.exe -section: .text at 0x40000000, size 102544 bytes -section: .data at 0x40019090, size 2788 bytes -total size: 105332 bytes (1.2 Mbit/s) -read 272 symbols -entry point: 0x40000000 -grlib> run -2K performance run parameters for coremark. -CoreMark Size : 666 -Total ticks : 19945918 -Total time (secs): 19.945918 -Iterations/Sec : 100.271143 -Iterations : 2000 -Compiler version : GCC4.4.2 -Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float -Memory location : STACK -seedcrc : 0xe9f5 -[0]crclist : 0xe714 -[0]crcmatrix : 0x1fd7 -[0]crcstate : 0x8e3a -[0]crcfinal : 0x4983 -Correct operation validated. See readme.txt for run and reporting rules. -CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack - -Program exited normally. -grlib> - +This leon3 design is tailored to the Xilinx SP605 Spartan6 board + +Simulation and synthesis +------------------------ + +The design uses the Xilinx MIG memory interface with an AHB-2.0 +interface. The MIG source code cannot be distributed due to the +prohibitive Xilinx license, so the MIG must be re-generated with +coregen before simulation and synthesis can be done. + +To generate the MIG and install tne Xilinx unisim simulation +library, do as follows: + + make mig + make install-secureip + +This will ONLY work with ISE-13.2 installed, and the XILINX variable +properly set in the shell. To synthesize the design, do + + make ise + +and then + + make ise-prog-fpga + +to program the FPGA. + +Design specifics +---------------- + +* System reset is mapped to the CPU RESET button + +* The AHB and processor is clocked by a 60 MHz clock, generated + from the 33 MHz SYSACE clock using a DCM. You can change the frequency + generation in the clocks menu of xconfig. The DDR3 (MIG) controller + runs at 667 MHz. + +* The GRETH core is enabled and runs without problems at 100 Mbit. + Ethernet debug link is enabled and has IP 192.168.0.51. + 1 Gbit operation is also possible (requires grlib com release), + uncomment related timing constraints in the leon3mp.ucf first. + +* 16-bit flash prom can be read at address 0. It can be programmed + with GRMON version 1.1.16 or later. + +* DDR3 is working with the provided Xilinx MIG DDR3 controller. + If you want to simulate this design, first install the secure + IP models with: + + make install-secureip + + Then rebuild the scripts and simulation model: + + make distclean vsim + + Modelsim v6.6e or newer is required to build the secure IP models. + Note that the regular leon3 test bench cannot be run in simulation + as the DDR3 model lacks data pre-load. + +* The application UART1 is connected to the USB/UART connector + +* The SVGA frame buffer uses a separate port on the DDR3 controller, + and therefore does not noticeably affect the performance of the processor. + Default output is analog VGA, to switch to DVI mode execute this + command in grmon: + + i2c dvi init_l4itx_vga + +* The JTAG DSU interface is enabled and accesible via the USB/JTAG port. + Start grmon with -xilusb to connect. + +* Output from GRMON is: + +$ grmon -xilusb -u + + GRMON LEON debug monitor v1.1.51 professional version (debug) + + Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved. + For latest updates, go to http://www.gaisler.com/ + Comments or bug-reports to support@gaisler.com + + Xilinx cable: Cable type/rev : 0x3 + JTAG chain: xc6slx45t xccace + + GRLIB build version: 4111 + + initialising ............... + detected frequency: 50 MHz + SRAM waitstates: 1 + + Component Vendor + LEON3 SPARC V8 Processor Gaisler Research + AHB Debug JTAG TAP Gaisler Research + GR Ethernet MAC Gaisler Research + LEON2 Memory Controller European Space Agency + AHB/APB Bridge Gaisler Research + LEON3 Debug Support Unit Gaisler Research + Xilinx MIG DDR2 controller Gaisler Research + AHB/APB Bridge Gaisler Research + Generic APB UART Gaisler Research + Multi-processor Interrupt Ctrl Gaisler Research + Modular Timer Unit Gaisler Research + SVGA Controller Gaisler Research + AMBA Wrapper for OC I2C-master Gaisler Research + General purpose I/O port Gaisler Research + AHB status register Gaisler Research + + Use command 'info sys' to print a detailed report of attached cores + +grlib> inf sys +00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0) + ahb master 0 +01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1) + ahb master 1 +02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0) + ahb master 2, irq 12 + apb: 80000e00 - 80000f00 + Device index: dev0 + edcl ip 192.168.1.51, buffer 2 kbyte +00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1) + ahb: 00000000 - 20000000 + apb: 80000000 - 80000100 + 16-bit prom @ 0x00000000 +01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) + ahb: 80000000 - 80100000 +02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1) + ahb: 90000000 - a0000000 + AHB trace 256 lines, 32-bit bus, stack pointer 0x47fffff0 + CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1 + icache 2 * 8 kbyte, 32 byte/line rnd + dcache 2 * 4 kbyte, 16 byte/line rnd +04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0) + ahb: 40000000 - 48000000 + apb: 80100000 - 80100100 + DDR2: 128 Mbyte +0d.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) + ahb: 80100000 - 80200000 +01.01:00c Gaisler Research Generic APB UART (ver 0x1) + irq 2 + apb: 80000100 - 80000200 + baud rate 38343, DSU mode (FIFO debug) +02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3) + apb: 80000200 - 80000300 +03.01:011 Gaisler Research Modular Timer Unit (ver 0x0) + irq 8 + apb: 80000300 - 80000400 + 8-bit scaler, 2 * 32-bit timers, divisor 50 +06.01:063 Gaisler Research SVGA Controller (ver 0x0) + apb: 80000600 - 80000700 + clk0: 50.00 MHz +09.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x3) + irq 14 + apb: 80000900 - 80000a00 +0a.01:01a Gaisler Research General purpose I/O port (ver 0x1) + apb: 80000a00 - 80000b00 +0f.01:052 Gaisler Research AHB status register (ver 0x0) + irq 7 + apb: 80000f00 - 80001000 +grlib> fla + + Intel-style 16-bit flash on D[31:16] + + Manuf. Intel + Device Strataflash P30 + + Device ID 02e44603e127ffff + User ID ffffffffffffffff + + + 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000 + + + CFI info + flash family : 1 + flash size : 256 Mbit + erase regions : 2 + erase blocks : 259 + write buffer : 1024 bytes + lock-down : yes + region 0 : 255 blocks of 128 Kbytes + region 1 : 4 blocks of 32 Kbytes + +grlib> lo ~/ibm/src/bench/leonbench/coremark.exe +section: .text at 0x40000000, size 102544 bytes +section: .data at 0x40019090, size 2788 bytes +total size: 105332 bytes (1.2 Mbit/s) +read 272 symbols +entry point: 0x40000000 +grlib> run +2K performance run parameters for coremark. +CoreMark Size : 666 +Total ticks : 19945918 +Total time (secs): 19.945918 +Iterations/Sec : 100.271143 +Iterations : 2000 +Compiler version : GCC4.4.2 +Compiler flags : -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float +Memory location : STACK +seedcrc : 0xe9f5 +[0]crclist : 0xe714 +[0]crcmatrix : 0x1fd7 +[0]crcstate : 0x8e3a +[0]crcfinal : 0x4983 +Correct operation validated. See readme.txt for run and reporting rules. +CoreMark 1.0 : 100.271143 / GCC4.4.2 -O3 -mv8 -funroll-loops -fgcse-sm -combine -DPERFORMANCE_RUN=1 -mcpu=v8 -msoft-float / Stack + +Program exited normally. +grlib> + diff --git a/designs/beaglebone-test1/config.vhd.h b/designs/beaglebone-test1/config.vhd.h --- a/designs/beaglebone-test1/config.vhd.h +++ b/designs/beaglebone-test1/config.vhd.h @@ -1,190 +1,190 @@ --- Technology and synthesis options - constant CFG_FABTECH : integer := CONFIG_SYN_TECH; - constant CFG_MEMTECH : integer := CFG_RAM_TECH; - constant CFG_PADTECH : integer := CFG_PAD_TECH; - constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; - constant CFG_SCAN : integer := CONFIG_SYN_SCAN; - --- Clock generator - constant CFG_CLKTECH : integer := CFG_CLK_TECH; - constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; - constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; - constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; - constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV; - constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV; - constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; - constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; - constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; - --- LEON3 processor core - constant CFG_LEON3 : integer := CONFIG_LEON3; - constant CFG_NCPU : integer := CONFIG_PROC_NUM; - constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; - constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT; - constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; - constant CFG_BP : integer := CONFIG_IU_BP; - constant CFG_SVT : integer := CONFIG_IU_SVT; - constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; - constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; - constant CFG_NOTAG : integer := CONFIG_NOTAG; - constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; - constant CFG_PWD : integer := CONFIG_PWD*2; - constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED; - constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; - constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; - constant CFG_ISETS : integer := CFG_IU_ISETS; - constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; - constant CFG_ILINE : integer := CFG_ILINE_SZ; - constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; - constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; - constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; - constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; - constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; - constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; - constant CFG_DSETS : integer := CFG_IU_DSETS; - constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; - constant CFG_DLINE : integer := CFG_DLINE_SZ; - constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; - constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; - constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; - constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; - constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; - constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; - constant CFG_MMUEN : integer := CONFIG_MMUEN; - constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; - constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; - constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; - constant CFG_TLB_REP : integer := CONFIG_TLB_REP; - constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; - constant CFG_DSU : integer := CONFIG_DSU_ENABLE; - constant CFG_ITBSZ : integer := CFG_DSU_ITB; - constant CFG_ATBSZ : integer := CFG_DSU_ATB; - constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; - constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; - constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; - constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; - constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; - constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; - constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; - constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; - constant CFG_PCLOW : integer := CFG_DEBUG_PC32; - --- AMBA settings - constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; - constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; - constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; - constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; - constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; - constant CFG_AHB_MON : integer := CONFIG_AHB_MON; - constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; - constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; - constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS; - constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; - constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; - constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; - constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; - constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; - constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; - constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; - constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; - constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; - constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; - constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; - constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; - constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; - --- Xilinx MIG - constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2; - constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS; - constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS; - constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS; - constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS; - constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#; - - --- AHB status register - constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE; - constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV; - --- AHB ROM - constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; - constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; - constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; - constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; - constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; - constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; - constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; - constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; - constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; - --- UART 1 - constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; - constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; - constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; - --- Modular timer - constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; - constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; - constant CFG_GPT_SW : integer := CONFIG_GPT_SW; - constant CFG_GPT_TW : integer := CONFIG_GPT_TW; - constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; - constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; - constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; - constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; - constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; - constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; - --- VGA and PS2/ interface - constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE; - constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE; - constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE; - --- SPI memory controller - constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL; - constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD; - constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#; - constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE; - constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT; - constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER; - constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER; - constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT; - --- SPI controller - constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE; - constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM; - constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS; - constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO; - constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG; - constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE; - constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM; - constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL; - constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN; - constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN; - constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM; - constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT; - --- GRLIB debugging - constant CFG_DUART : integer := CONFIG_DEBUG_UART; - +-- Technology and synthesis options + constant CFG_FABTECH : integer := CONFIG_SYN_TECH; + constant CFG_MEMTECH : integer := CFG_RAM_TECH; + constant CFG_PADTECH : integer := CFG_PAD_TECH; + constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; + constant CFG_SCAN : integer := CONFIG_SYN_SCAN; + +-- Clock generator + constant CFG_CLKTECH : integer := CFG_CLK_TECH; + constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; + constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; + constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; + constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV; + constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV; + constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; + constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; + constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; + +-- LEON3 processor core + constant CFG_LEON3 : integer := CONFIG_LEON3; + constant CFG_NCPU : integer := CONFIG_PROC_NUM; + constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; + constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT; + constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; + constant CFG_BP : integer := CONFIG_IU_BP; + constant CFG_SVT : integer := CONFIG_IU_SVT; + constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; + constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; + constant CFG_NOTAG : integer := CONFIG_NOTAG; + constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; + constant CFG_PWD : integer := CONFIG_PWD*2; + constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED; + constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; + constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; + constant CFG_ISETS : integer := CFG_IU_ISETS; + constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; + constant CFG_ILINE : integer := CFG_ILINE_SZ; + constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; + constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; + constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; + constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; + constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; + constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; + constant CFG_DSETS : integer := CFG_IU_DSETS; + constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; + constant CFG_DLINE : integer := CFG_DLINE_SZ; + constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; + constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; + constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; + constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; + constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; + constant CFG_MMUEN : integer := CONFIG_MMUEN; + constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; + constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; + constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; + constant CFG_TLB_REP : integer := CONFIG_TLB_REP; + constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; + constant CFG_DSU : integer := CONFIG_DSU_ENABLE; + constant CFG_ITBSZ : integer := CFG_DSU_ITB; + constant CFG_ATBSZ : integer := CFG_DSU_ATB; + constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; + constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; + constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; + constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; + constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; + constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; + constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; + constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; + constant CFG_PCLOW : integer := CFG_DEBUG_PC32; + +-- AMBA settings + constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; + constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; + constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; + constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; + constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; + constant CFG_AHB_MON : integer := CONFIG_AHB_MON; + constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; + constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; + constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE; + +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; + +-- Ethernet DSU + constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS; + constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; + constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; + constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; + constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; + constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; + +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; + constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; + constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; + constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; + constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; + constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; + constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; + constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; + constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; + +-- Xilinx MIG + constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2; + constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS; + constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS; + constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS; + constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS; + constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#; + + +-- AHB status register + constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE; + constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV; + +-- AHB ROM + constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; + constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; + constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; + constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; + constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; + +-- AHB RAM + constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; + constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; + constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; + +-- Gaisler Ethernet core + constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; + constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; + constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; + +-- UART 1 + constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; + constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; + +-- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; + constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; + +-- Modular timer + constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; + constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; + constant CFG_GPT_SW : integer := CONFIG_GPT_SW; + constant CFG_GPT_TW : integer := CONFIG_GPT_TW; + constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; + constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; + constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; + constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; + +-- GPIO port + constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; + constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; + constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; + +-- VGA and PS2/ interface + constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE; + constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE; + constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE; + +-- SPI memory controller + constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL; + constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD; + constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#; + constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE; + constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT; + constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER; + constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER; + constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT; + +-- SPI controller + constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE; + constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM; + constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS; + constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO; + constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG; + constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE; + constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM; + constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL; + constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN; + constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN; + constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM; + constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT; + +-- GRLIB debugging + constant CFG_DUART : integer := CONFIG_DEBUG_UART; + diff --git a/designs/beaglebone-test1/leon3mp_envsettings.html b/designs/beaglebone-test1/leon3mp_envsettings.html --- a/designs/beaglebone-test1/leon3mp_envsettings.html +++ b/designs/beaglebone-test1/leon3mp_envsettings.html @@ -1,403 +1,403 @@ -Xilinx System Settings Report - -
System Settings

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Environment Settings
Environment Variablexstngdbuildmappar
LD_LIBRARY_PATH/opt/Xilinx/14.2/ISE_DS/ISE//lib/lin64:
/usr/lib64/alliance/lib		/opt/Xilinx/14.2/ISE_DS/ISE//lib/lin64:
/usr/lib64/alliance/lib		< data not available >< data not available >
PATH/opt/Xilinx/14.2/ISE_DS/ISE//bin/lin64:
/usr/lib64/qt-3.3/bin:
/usr/kerberos/sbin:
/usr/kerberos/bin:
/usr/lib64/ccache:
/usr/libexec/lightdm:
/usr/local/bin:
/usr/bin:
/bin:
/usr/local/sbin:
/usr/sbin:
/usr/lib64/alliance/bin:
/usr/libexec/sdcc:
/opt/sparc-elf-4.4.2/bin:
/usr/local/MATLAB/R2012b/bin:
/opt/gcc-arm-none-eabi-4_7-2012q4/bin:
/home/jeandet/.local/bin:
/home/jeandet/bin		/opt/Xilinx/14.2/ISE_DS/ISE//bin/lin64:
/usr/lib64/qt-3.3/bin:
/usr/kerberos/sbin:
/usr/kerberos/bin:
/usr/lib64/ccache:
/usr/libexec/lightdm:
/usr/local/bin:
/usr/bin:
/bin:
/usr/local/sbin:
/usr/sbin:
/usr/lib64/alliance/bin:
/usr/libexec/sdcc:
/opt/sparc-elf-4.4.2/bin:
/usr/local/MATLAB/R2012b/bin:
/opt/gcc-arm-none-eabi-4_7-2012q4/bin:
/home/jeandet/.local/bin:
/home/jeandet/bin		< data not available >< data not available >
XILINX/opt/Xilinx/14.2/ISE_DS/ISE//opt/Xilinx/14.2/ISE_DS/ISE/< data not available >< data not available >
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn leon3mp.prj 
-ofn leon3mp 
-ofmt NGCNGC
-p xc6slx45-3-fgg484 
-top leon3mp 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-powerPower ReductionNONo
-iucUse synthesis Constraints FileNONo
-keep_hierarchyKeep HierarchyNoNo
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNo
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYes
-write_timing_constraintsWrite Timing ConstraintsNONo
-cross_clock_analysisCross Clock AnalysisNONo
-bus_delimiterBus Delimiter()<>
-slice_utilization_ratioSlice Utilization Ratio100100
-bram_utilization_ratioBRAM Utilization Ratio100100
-dsp_utilization_ratioDSP Utilization Ratio100100
-reduce_control_sets AutoAuto
-fsm_extract NOYes
-fsm_style LUTLUT
-ram_extract YesYes
-ram_style AutoAuto
-rom_extract YesYes
-shreg_extract YESYes
-rom_style AutoAuto
-auto_bram_packing NONo
-resource_sharing YESYes
-async_to_sync NONo
-use_dsp48 AutoAuto
-iobuf YESYes
-max_fanout 100000100000
-bufg 1616
-register_duplication YESYes
-register_balancing NoNo
-optimize_primitives NONo
-use_clock_enable AutoAuto
-use_sync_set AutoAuto
-use_sync_reset AutoAuto
-iob TrueAuto
-equivalent_register_removal YESYes
-slice_utilization_ratio_maxmargin 50
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Translation Property Settings
Switch NameProperty NameValueDefault Value
-aulAllow Unmatched LOC Constraintstruefalse
-intstyle iseNone
-dd _ngoNone
-p xc6slx45-fgg484-3None
-sdMacro Search Path../../netlists/xilinx/Spartan3None
-uc leon3mp.ucfNone
- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i5-2557M CPU @ 1.70GHz/1701.000 MHzIntel(R) Core(TM) i5-2557M CPU @ 1.70GHz/800.000 MHz<  data not available  ><  data not available  >
Hostpc-de-jeandet3.lab-lpp.localpc-de-jeandet3.lab-lpp.local<  data not available  ><  data not available  >
OS NameFedoraFedora<  data not available  ><  data not available  >
OS ReleaseFedora release 18 (Spherical Cow)Fedora release 18 (Spherical Cow)<  data not available  ><  data not available  >
+Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
LD_LIBRARY_PATH/opt/Xilinx/14.2/ISE_DS/ISE//lib/lin64:
/usr/lib64/alliance/lib		/opt/Xilinx/14.2/ISE_DS/ISE//lib/lin64:
/usr/lib64/alliance/lib		< data not available >< data not available >
PATH/opt/Xilinx/14.2/ISE_DS/ISE//bin/lin64:
/usr/lib64/qt-3.3/bin:
/usr/kerberos/sbin:
/usr/kerberos/bin:
/usr/lib64/ccache:
/usr/libexec/lightdm:
/usr/local/bin:
/usr/bin:
/bin:
/usr/local/sbin:
/usr/sbin:
/usr/lib64/alliance/bin:
/usr/libexec/sdcc:
/opt/sparc-elf-4.4.2/bin:
/usr/local/MATLAB/R2012b/bin:
/opt/gcc-arm-none-eabi-4_7-2012q4/bin:
/home/jeandet/.local/bin:
/home/jeandet/bin		/opt/Xilinx/14.2/ISE_DS/ISE//bin/lin64:
/usr/lib64/qt-3.3/bin:
/usr/kerberos/sbin:
/usr/kerberos/bin:
/usr/lib64/ccache:
/usr/libexec/lightdm:
/usr/local/bin:
/usr/bin:
/bin:
/usr/local/sbin:
/usr/sbin:
/usr/lib64/alliance/bin:
/usr/libexec/sdcc:
/opt/sparc-elf-4.4.2/bin:
/usr/local/MATLAB/R2012b/bin:
/opt/gcc-arm-none-eabi-4_7-2012q4/bin:
/home/jeandet/.local/bin:
/home/jeandet/bin		< data not available >< data not available >
XILINX/opt/Xilinx/14.2/ISE_DS/ISE//opt/Xilinx/14.2/ISE_DS/ISE/< data not available >< data not available >
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Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn leon3mp.prj 
-ofn leon3mp 
-ofmt NGCNGC
-p xc6slx45-3-fgg484 
-top leon3mp 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-powerPower ReductionNONo
-iucUse synthesis Constraints FileNONo
-keep_hierarchyKeep HierarchyNoNo
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNo
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYes
-write_timing_constraintsWrite Timing ConstraintsNONo
-cross_clock_analysisCross Clock AnalysisNONo
-bus_delimiterBus Delimiter()<>
-slice_utilization_ratioSlice Utilization Ratio100100
-bram_utilization_ratioBRAM Utilization Ratio100100
-dsp_utilization_ratioDSP Utilization Ratio100100
-reduce_control_sets AutoAuto
-fsm_extract NOYes
-fsm_style LUTLUT
-ram_extract YesYes
-ram_style AutoAuto
-rom_extract YesYes
-shreg_extract YESYes
-rom_style AutoAuto
-auto_bram_packing NONo
-resource_sharing YESYes
-async_to_sync NONo
-use_dsp48 AutoAuto
-iobuf YESYes
-max_fanout 100000100000
-bufg 1616
-register_duplication YESYes
-register_balancing NoNo
-optimize_primitives NONo
-use_clock_enable AutoAuto
-use_sync_set AutoAuto
-use_sync_reset AutoAuto
-iob TrueAuto
-equivalent_register_removal YESYes
-slice_utilization_ratio_maxmargin 50
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Translation Property Settings
Switch NameProperty NameValueDefault Value
-aulAllow Unmatched LOC Constraintstruefalse
-intstyle iseNone
-dd _ngoNone
-p xc6slx45-fgg484-3None
-sdMacro Search Path../../netlists/xilinx/Spartan3None
-uc leon3mp.ucfNone
+ + 
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Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i5-2557M CPU @ 1.70GHz/1701.000 MHzIntel(R) Core(TM) i5-2557M CPU @ 1.70GHz/800.000 MHz<  data not available  ><  data not available  >
Hostpc-de-jeandet3.lab-lpp.localpc-de-jeandet3.lab-lpp.local<  data not available  ><  data not available  >
OS NameFedoraFedora<  data not available  ><  data not available  >
OS ReleaseFedora release 18 (Spherical Cow)Fedora release 18 (Spherical Cow)<  data not available  ><  data not available  >
\ No newline at end of file diff --git a/designs/beaglebone-test1/prom.h b/designs/beaglebone-test1/prom.h --- a/designs/beaglebone-test1/prom.h +++ b/designs/beaglebone-test1/prom.h @@ -1,10 +1,10 @@ -#define MCFG1 0x10380033 -#define MCFG2 0xe6B86e60 -#define MCFG3 0x000ff000 -#define ASDCFG 0x80000000 -#define DSDCFG 0xe6A06e60 -#define L2MCTRLIO 0x80000000 -#define IRQCTRL 0x80000200 -#define RAMSTART 0x40000000 -#define RAMSIZE 0x00100000 - +#define MCFG1 0x10380033 +#define MCFG2 0xe6B86e60 +#define MCFG3 0x000ff000 +#define ASDCFG 0x80000000 +#define DSDCFG 0xe6A06e60 +#define L2MCTRLIO 0x80000000 +#define IRQCTRL 0x80000200 +#define RAMSTART 0x40000000 +#define RAMSIZE 0x00100000 + diff --git a/designs/beaglebone-test1/res.txt b/designs/beaglebone-test1/res.txt --- a/designs/beaglebone-test1/res.txt +++ b/designs/beaglebone-test1/res.txt @@ -1,13 +1,13 @@ - -SPARTAN6 50 MHz, MIG DDR2, 2x8 + 2x4 cache, GRFPU - - LEON3 LEON3FTV2 -Dhrystone 78.4 78.4 -Whetstone DP 27.7 27.7 -gzip 43.98 s 41.38 s -bzip2 248.22 s 200.10 s -176.gcc 208.62 s 180.48 s -coremark 100.12 i/s 100.12 i/s -aocs_v8 12388.7 i/s 12388.7 i/s -basicmath_large 13245.0 i/s 13245.0 i/s -linpack_unroll_dp_v8 3265 KFLOPS 3563 KFLOPS + +SPARTAN6 50 MHz, MIG DDR2, 2x8 + 2x4 cache, GRFPU + + LEON3 LEON3FTV2 +Dhrystone 78.4 78.4 +Whetstone DP 27.7 27.7 +gzip 43.98 s 41.38 s +bzip2 248.22 s 200.10 s +176.gcc 208.62 s 180.48 s +coremark 100.12 i/s 100.12 i/s +aocs_v8 12388.7 i/s 12388.7 i/s +basicmath_large 13245.0 i/s 13245.0 i/s +linpack_unroll_dp_v8 3265 KFLOPS 3563 KFLOPS diff --git a/designs/beaglebone-test1/systest.c b/designs/beaglebone-test1/systest.c --- a/designs/beaglebone-test1/systest.c +++ b/designs/beaglebone-test1/systest.c @@ -1,18 +1,18 @@ - -main() - -{ - report_start(); - - -// svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); - base_test(); -/* - greth_test(0x80000e00); - spw_test(0x80100A00); - spw_test(0x80100B00); - spw_test(0x80100C00); - svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); -*/ - report_end(); -} + +main() + +{ + report_start(); + + +// svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); + base_test(); +/* + greth_test(0x80000e00); + spw_test(0x80100A00); + spw_test(0x80100B00); + spw_test(0x80100C00); + svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); +*/ + report_end(); +} diff --git a/designs/beaglebone-test1/tkconfig.h b/designs/beaglebone-test1/tkconfig.h --- a/designs/beaglebone-test1/tkconfig.h +++ b/designs/beaglebone-test1/tkconfig.h @@ -1,1051 +1,1051 @@ -#if defined CONFIG_SYN_INFERRED -#define CONFIG_SYN_TECH inferred -#elif defined CONFIG_SYN_UMC -#define CONFIG_SYN_TECH umc -#elif defined CONFIG_SYN_RHUMC -#define CONFIG_SYN_TECH rhumc -#elif defined CONFIG_SYN_ATC18 -#define CONFIG_SYN_TECH atc18s -#elif defined CONFIG_SYN_ATC18RHA -#define CONFIG_SYN_TECH atc18rha -#elif defined CONFIG_SYN_AXCEL -#define CONFIG_SYN_TECH axcel -#elif defined CONFIG_SYN_AXDSP -#define CONFIG_SYN_TECH axdsp -#elif defined CONFIG_SYN_PROASICPLUS -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_ALTERA -#define CONFIG_SYN_TECH altera -#elif defined CONFIG_SYN_STRATIX -#define CONFIG_SYN_TECH stratix1 -#elif defined CONFIG_SYN_STRATIXII -#define CONFIG_SYN_TECH stratix2 -#elif defined CONFIG_SYN_STRATIXIII -#define CONFIG_SYN_TECH stratix3 -#elif defined CONFIG_SYN_CYCLONEIII -#define CONFIG_SYN_TECH cyclone3 -#elif defined CONFIG_SYN_EASIC45 -#define CONFIG_SYN_TECH easic45 -#elif defined CONFIG_SYN_EASIC90 -#define CONFIG_SYN_TECH easic90 -#elif defined CONFIG_SYN_IHP25 -#define CONFIG_SYN_TECH ihp25 -#elif defined CONFIG_SYN_IHP25RH -#define CONFIG_SYN_TECH ihp25rh -#elif defined CONFIG_SYN_CMOS9SF -#define CONFIG_SYN_TECH cmos9sf -#elif defined CONFIG_SYN_LATTICE -#define CONFIG_SYN_TECH lattice -#elif defined CONFIG_SYN_ECLIPSE -#define CONFIG_SYN_TECH eclipse -#elif defined CONFIG_SYN_PEREGRINE -#define CONFIG_SYN_TECH peregrine -#elif defined CONFIG_SYN_PROASIC -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_PROASIC3 -#define CONFIG_SYN_TECH apa3 -#elif defined CONFIG_SYN_PROASIC3E -#define CONFIG_SYN_TECH apa3e -#elif defined CONFIG_SYN_PROASIC3L -#define CONFIG_SYN_TECH apa3l -#elif defined CONFIG_SYN_IGLOO -#define CONFIG_SYN_TECH apa3 -#elif defined CONFIG_SYN_FUSION -#define CONFIG_SYN_TECH actfus -#elif defined CONFIG_SYN_SPARTAN2 -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEX -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEXE -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_SPARTAN3 -#define CONFIG_SYN_TECH spartan3 -#elif defined CONFIG_SYN_SPARTAN3E -#define CONFIG_SYN_TECH spartan3e -#elif defined CONFIG_SYN_SPARTAN6 -#define CONFIG_SYN_TECH spartan6 -#elif defined CONFIG_SYN_VIRTEX2 -#define CONFIG_SYN_TECH virtex2 -#elif defined CONFIG_SYN_VIRTEX4 -#define CONFIG_SYN_TECH virtex4 -#elif defined CONFIG_SYN_VIRTEX5 -#define CONFIG_SYN_TECH virtex5 -#elif defined CONFIG_SYN_VIRTEX6 -#define CONFIG_SYN_TECH virtex6 -#elif defined CONFIG_SYN_RH_LIB18T -#define CONFIG_SYN_TECH rhlib18t -#elif defined CONFIG_SYN_SMIC13 -#define CONFIG_SYN_TECH smic013 -#elif defined CONFIG_SYN_UT025CRH -#define CONFIG_SYN_TECH ut25 -#elif defined CONFIG_SYN_UT130HBD -#define CONFIG_SYN_TECH ut130 -#elif defined CONFIG_SYN_UT90NHBD -#define CONFIG_SYN_TECH ut90 -#elif defined CONFIG_SYN_TSMC90 -#define CONFIG_SYN_TECH tsmc90 -#elif defined CONFIG_SYN_TM65GPLUS -#define CONFIG_SYN_TECH tm65gpl -#elif defined CONFIG_SYN_CUSTOM1 -#define CONFIG_SYN_TECH custom1 -#else -#error "unknown target technology" -#endif - -#if defined CONFIG_SYN_INFER_RAM -#define CFG_RAM_TECH inferred -#elif defined CONFIG_MEM_UMC -#define CFG_RAM_TECH umc -#elif defined CONFIG_MEM_RHUMC -#define CFG_RAM_TECH rhumc -#elif defined CONFIG_MEM_VIRAGE -#define CFG_RAM_TECH memvirage -#elif defined CONFIG_MEM_ARTISAN -#define CFG_RAM_TECH memartisan -#elif defined CONFIG_MEM_CUSTOM1 -#define CFG_RAM_TECH custom1 -#elif defined CONFIG_MEM_VIRAGE90 -#define CFG_RAM_TECH memvirage90 -#elif defined CONFIG_MEM_INFERRED -#define CFG_RAM_TECH inferred -#else -#define CFG_RAM_TECH CONFIG_SYN_TECH -#endif - -#if defined CONFIG_SYN_INFER_PADS -#define CFG_PAD_TECH inferred -#else -#define CFG_PAD_TECH CONFIG_SYN_TECH -#endif - -#ifndef CONFIG_SYN_NO_ASYNC -#define CONFIG_SYN_NO_ASYNC 0 -#endif - -#ifndef CONFIG_SYN_SCAN -#define CONFIG_SYN_SCAN 0 -#endif - - -#if defined CONFIG_CLK_ALTDLL -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_HCLKBUF -#define CFG_CLK_TECH axcel -#elif defined CONFIG_CLK_LATDLL -#define CFG_CLK_TECH lattice -#elif defined CONFIG_CLK_PRO3PLL -#define CFG_CLK_TECH apa3 -#elif defined CONFIG_CLK_PRO3EPLL -#define CFG_CLK_TECH apa3e -#elif defined CONFIG_CLK_PRO3LPLL -#define CFG_CLK_TECH apa3l -#elif defined CONFIG_CLK_FUSPLL -#define CFG_CLK_TECH actfus -#elif defined CONFIG_CLK_CLKDLL -#define CFG_CLK_TECH virtex -#elif defined CONFIG_CLK_DCM -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_LIB18T -#define CFG_CLK_TECH rhlib18t -#elif defined CONFIG_CLK_RHUMC -#define CFG_CLK_TECH rhumc -#elif defined CONFIG_CLK_UT130HBD -#define CFG_CLK_TECH ut130 -#else -#define CFG_CLK_TECH inferred -#endif - -#ifndef CONFIG_CLK_MUL -#define CONFIG_CLK_MUL 2 -#endif - -#ifndef CONFIG_CLK_DIV -#define CONFIG_CLK_DIV 2 -#endif - -#ifndef CONFIG_OCLK_DIV -#define CONFIG_OCLK_DIV 1 -#endif - -#ifndef CONFIG_OCLKB_DIV -#define CONFIG_OCLKB_DIV 0 -#endif - -#ifndef CONFIG_OCLKC_DIV -#define CONFIG_OCLKC_DIV 0 -#endif - -#ifndef CONFIG_PCI_CLKDLL -#define CONFIG_PCI_CLKDLL 0 -#endif - -#ifndef CONFIG_PCI_SYSCLK -#define CONFIG_PCI_SYSCLK 0 -#endif - -#ifndef CONFIG_CLK_NOFB -#define CONFIG_CLK_NOFB 0 -#endif -#ifndef CONFIG_LEON3 -#define CONFIG_LEON3 0 -#endif - -#ifndef CONFIG_PROC_NUM -#define CONFIG_PROC_NUM 1 -#endif - -#ifndef CONFIG_IU_NWINDOWS -#define CONFIG_IU_NWINDOWS 8 -#endif - -#ifndef CONFIG_IU_RSTADDR -#define CONFIG_IU_RSTADDR 8 -#endif - -#ifndef CONFIG_IU_LDELAY -#define CONFIG_IU_LDELAY 1 -#endif - -#ifndef CONFIG_IU_WATCHPOINTS -#define CONFIG_IU_WATCHPOINTS 0 -#endif - -#ifdef CONFIG_IU_V8MULDIV -#ifdef CONFIG_IU_MUL_LATENCY_4 -#define CFG_IU_V8 1 -#elif defined CONFIG_IU_MUL_LATENCY_5 -#define CFG_IU_V8 2 -#elif defined CONFIG_IU_MUL_LATENCY_2 -#define CFG_IU_V8 16#32# -#endif -#else -#define CFG_IU_V8 0 -#endif - -#ifdef CONFIG_IU_MUL_MODGEN -#define CFG_IU_MUL_STRUCT 1 -#elif defined CONFIG_IU_MUL_TECHSPEC -#define CFG_IU_MUL_STRUCT 2 -#elif defined CONFIG_IU_MUL_DW -#define CFG_IU_MUL_STRUCT 3 -#else -#define CFG_IU_MUL_STRUCT 0 -#endif - -#ifndef CONFIG_PWD -#define CONFIG_PWD 0 -#endif - -#ifndef CONFIG_IU_MUL_MAC -#define CONFIG_IU_MUL_MAC 0 -#endif - -#ifndef CONFIG_IU_BP -#define CONFIG_IU_BP 0 -#endif - -#ifndef CONFIG_NOTAG -#define CONFIG_NOTAG 0 -#endif - -#ifndef CONFIG_IU_SVT -#define CONFIG_IU_SVT 0 -#endif - -#if defined CONFIG_FPU_GRFPC1 -#define CONFIG_FPU_GRFPC 1 -#elif defined CONFIG_FPU_GRFPC2 -#define CONFIG_FPU_GRFPC 2 -#else -#define CONFIG_FPU_GRFPC 0 -#endif - -#if defined CONFIG_FPU_GRFPU_INFMUL -#define CONFIG_FPU_GRFPU_MUL 0 -#elif defined CONFIG_FPU_GRFPU_DWMUL -#define CONFIG_FPU_GRFPU_MUL 1 -#elif defined CONFIG_FPU_GRFPU_MODGEN -#define CONFIG_FPU_GRFPU_MUL 2 -#elif defined CONFIG_FPU_GRFPU_TECHSPEC -#define CONFIG_FPU_GRFPU_MUL 3 -#else -#define CONFIG_FPU_GRFPU_MUL 0 -#endif - -#if defined CONFIG_FPU_GRFPU_SH -#define CONFIG_FPU_GRFPU_SHARED 1 -#else -#define CONFIG_FPU_GRFPU_SHARED 0 -#endif - -#if defined CONFIG_FPU_GRFPU -#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) -#elif defined CONFIG_FPU_MEIKO -#define CONFIG_FPU 15 -#elif defined CONFIG_FPU_GRFPULITE -#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) -#else -#define CONFIG_FPU 0 -#endif - -#ifndef CONFIG_FPU_NETLIST -#define CONFIG_FPU_NETLIST 0 -#endif - -#ifndef CONFIG_ICACHE_ENABLE -#define CONFIG_ICACHE_ENABLE 0 -#endif - -#if defined CONFIG_ICACHE_ASSO1 -#define CFG_IU_ISETS 1 -#elif defined CONFIG_ICACHE_ASSO2 -#define CFG_IU_ISETS 2 -#elif defined CONFIG_ICACHE_ASSO3 -#define CFG_IU_ISETS 3 -#elif defined CONFIG_ICACHE_ASSO4 -#define CFG_IU_ISETS 4 -#else -#define CFG_IU_ISETS 1 -#endif - -#if defined CONFIG_ICACHE_SZ1 -#define CFG_ICACHE_SZ 1 -#elif defined CONFIG_ICACHE_SZ2 -#define CFG_ICACHE_SZ 2 -#elif defined CONFIG_ICACHE_SZ4 -#define CFG_ICACHE_SZ 4 -#elif defined CONFIG_ICACHE_SZ8 -#define CFG_ICACHE_SZ 8 -#elif defined CONFIG_ICACHE_SZ16 -#define CFG_ICACHE_SZ 16 -#elif defined CONFIG_ICACHE_SZ32 -#define CFG_ICACHE_SZ 32 -#elif defined CONFIG_ICACHE_SZ64 -#define CFG_ICACHE_SZ 64 -#elif defined CONFIG_ICACHE_SZ128 -#define CFG_ICACHE_SZ 128 -#elif defined CONFIG_ICACHE_SZ256 -#define CFG_ICACHE_SZ 256 -#else -#define CFG_ICACHE_SZ 1 -#endif - -#ifdef CONFIG_ICACHE_LZ16 -#define CFG_ILINE_SZ 4 -#else -#define CFG_ILINE_SZ 8 -#endif - -#if defined CONFIG_ICACHE_ALGODIR -#define CFG_ICACHE_ALGORND 3 -#elif defined CONFIG_ICACHE_ALGORND -#define CFG_ICACHE_ALGORND 2 -#elif defined CONFIG_ICACHE_ALGOLRR -#define CFG_ICACHE_ALGORND 1 -#else -#define CFG_ICACHE_ALGORND 0 -#endif - -#ifndef CONFIG_ICACHE_LOCK -#define CONFIG_ICACHE_LOCK 0 -#endif - -#ifndef CONFIG_ICACHE_LRAM -#define CONFIG_ICACHE_LRAM 0 -#endif - -#ifndef CONFIG_ICACHE_LRSTART -#define CONFIG_ICACHE_LRSTART 8E -#endif - -#if defined CONFIG_ICACHE_LRAM_SZ2 -#define CFG_ILRAM_SIZE 2 -#elif defined CONFIG_ICACHE_LRAM_SZ4 -#define CFG_ILRAM_SIZE 4 -#elif defined CONFIG_ICACHE_LRAM_SZ8 -#define CFG_ILRAM_SIZE 8 -#elif defined CONFIG_ICACHE_LRAM_SZ16 -#define CFG_ILRAM_SIZE 16 -#elif defined CONFIG_ICACHE_LRAM_SZ32 -#define CFG_ILRAM_SIZE 32 -#elif defined CONFIG_ICACHE_LRAM_SZ64 -#define CFG_ILRAM_SIZE 64 -#elif defined CONFIG_ICACHE_LRAM_SZ128 -#define CFG_ILRAM_SIZE 128 -#elif defined CONFIG_ICACHE_LRAM_SZ256 -#define CFG_ILRAM_SIZE 256 -#else -#define CFG_ILRAM_SIZE 1 -#endif - - -#ifndef CONFIG_DCACHE_ENABLE -#define CONFIG_DCACHE_ENABLE 0 -#endif - -#if defined CONFIG_DCACHE_ASSO1 -#define CFG_IU_DSETS 1 -#elif defined CONFIG_DCACHE_ASSO2 -#define CFG_IU_DSETS 2 -#elif defined CONFIG_DCACHE_ASSO3 -#define CFG_IU_DSETS 3 -#elif defined CONFIG_DCACHE_ASSO4 -#define CFG_IU_DSETS 4 -#else -#define CFG_IU_DSETS 1 -#endif - -#if defined CONFIG_DCACHE_SZ1 -#define CFG_DCACHE_SZ 1 -#elif defined CONFIG_DCACHE_SZ2 -#define CFG_DCACHE_SZ 2 -#elif defined CONFIG_DCACHE_SZ4 -#define CFG_DCACHE_SZ 4 -#elif defined CONFIG_DCACHE_SZ8 -#define CFG_DCACHE_SZ 8 -#elif defined CONFIG_DCACHE_SZ16 -#define CFG_DCACHE_SZ 16 -#elif defined CONFIG_DCACHE_SZ32 -#define CFG_DCACHE_SZ 32 -#elif defined CONFIG_DCACHE_SZ64 -#define CFG_DCACHE_SZ 64 -#elif defined CONFIG_DCACHE_SZ128 -#define CFG_DCACHE_SZ 128 -#elif defined CONFIG_DCACHE_SZ256 -#define CFG_DCACHE_SZ 256 -#else -#define CFG_DCACHE_SZ 1 -#endif - -#ifdef CONFIG_DCACHE_LZ16 -#define CFG_DLINE_SZ 4 -#else -#define CFG_DLINE_SZ 8 -#endif - -#if defined CONFIG_DCACHE_ALGODIR -#define CFG_DCACHE_ALGORND 3 -#elif defined CONFIG_DCACHE_ALGORND -#define CFG_DCACHE_ALGORND 2 -#elif defined CONFIG_DCACHE_ALGOLRR -#define CFG_DCACHE_ALGORND 1 -#else -#define CFG_DCACHE_ALGORND 0 -#endif - -#ifndef CONFIG_DCACHE_LOCK -#define CONFIG_DCACHE_LOCK 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP -#define CONFIG_DCACHE_SNOOP 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_SEPTAG -#define CONFIG_DCACHE_SNOOP_SEPTAG 0 -#endif - -#ifndef CONFIG_CACHE_FIXED -#define CONFIG_CACHE_FIXED 0 -#endif - -#ifndef CONFIG_DCACHE_LRAM -#define CONFIG_DCACHE_LRAM 0 -#endif - -#ifndef CONFIG_DCACHE_LRSTART -#define CONFIG_DCACHE_LRSTART 8F -#endif - -#if defined CONFIG_DCACHE_LRAM_SZ2 -#define CFG_DLRAM_SIZE 2 -#elif defined CONFIG_DCACHE_LRAM_SZ4 -#define CFG_DLRAM_SIZE 4 -#elif defined CONFIG_DCACHE_LRAM_SZ8 -#define CFG_DLRAM_SIZE 8 -#elif defined CONFIG_DCACHE_LRAM_SZ16 -#define CFG_DLRAM_SIZE 16 -#elif defined CONFIG_DCACHE_LRAM_SZ32 -#define CFG_DLRAM_SIZE 32 -#elif defined CONFIG_DCACHE_LRAM_SZ64 -#define CFG_DLRAM_SIZE 64 -#elif defined CONFIG_DCACHE_LRAM_SZ128 -#define CFG_DLRAM_SIZE 128 -#elif defined CONFIG_DCACHE_LRAM_SZ256 -#define CFG_DLRAM_SIZE 256 -#else -#define CFG_DLRAM_SIZE 1 -#endif - -#if defined CONFIG_MMU_PAGE_4K -#define CONFIG_MMU_PAGE 0 -#elif defined CONFIG_MMU_PAGE_8K -#define CONFIG_MMU_PAGE 1 -#elif defined CONFIG_MMU_PAGE_16K -#define CONFIG_MMU_PAGE 2 -#elif defined CONFIG_MMU_PAGE_32K -#define CONFIG_MMU_PAGE 3 -#elif defined CONFIG_MMU_PAGE_PROG -#define CONFIG_MMU_PAGE 4 -#else -#define CONFIG_MMU_PAGE 0 -#endif - -#ifdef CONFIG_MMU_ENABLE -#define CONFIG_MMUEN 1 - -#ifdef CONFIG_MMU_SPLIT -#define CONFIG_TLB_TYPE 0 -#endif -#ifdef CONFIG_MMU_COMBINED -#define CONFIG_TLB_TYPE 1 -#endif - -#ifdef CONFIG_MMU_REPARRAY -#define CONFIG_TLB_REP 0 -#endif -#ifdef CONFIG_MMU_REPINCREMENT -#define CONFIG_TLB_REP 1 -#endif - -#ifdef CONFIG_MMU_I2 -#define CONFIG_ITLBNUM 2 -#endif -#ifdef CONFIG_MMU_I4 -#define CONFIG_ITLBNUM 4 -#endif -#ifdef CONFIG_MMU_I8 -#define CONFIG_ITLBNUM 8 -#endif -#ifdef CONFIG_MMU_I16 -#define CONFIG_ITLBNUM 16 -#endif -#ifdef CONFIG_MMU_I32 -#define CONFIG_ITLBNUM 32 -#endif - -#define CONFIG_DTLBNUM 2 -#ifdef CONFIG_MMU_D2 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 2 -#endif -#ifdef CONFIG_MMU_D4 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 4 -#endif -#ifdef CONFIG_MMU_D8 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 8 -#endif -#ifdef CONFIG_MMU_D16 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 16 -#endif -#ifdef CONFIG_MMU_D32 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 32 -#endif -#ifdef CONFIG_MMU_FASTWB -#define CFG_MMU_FASTWB 1 -#else -#define CFG_MMU_FASTWB 0 -#endif - -#else -#define CONFIG_MMUEN 0 -#define CONFIG_ITLBNUM 2 -#define CONFIG_DTLBNUM 2 -#define CONFIG_TLB_TYPE 1 -#define CONFIG_TLB_REP 1 -#define CFG_MMU_FASTWB 0 -#endif - -#ifndef CONFIG_DSU_ENABLE -#define CONFIG_DSU_ENABLE 0 -#endif - -#if defined CONFIG_DSU_ITRACESZ1 -#define CFG_DSU_ITB 1 -#elif CONFIG_DSU_ITRACESZ2 -#define CFG_DSU_ITB 2 -#elif CONFIG_DSU_ITRACESZ4 -#define CFG_DSU_ITB 4 -#elif CONFIG_DSU_ITRACESZ8 -#define CFG_DSU_ITB 8 -#elif CONFIG_DSU_ITRACESZ16 -#define CFG_DSU_ITB 16 -#else -#define CFG_DSU_ITB 0 -#endif - -#if defined CONFIG_DSU_ATRACESZ1 -#define CFG_DSU_ATB 1 -#elif CONFIG_DSU_ATRACESZ2 -#define CFG_DSU_ATB 2 -#elif CONFIG_DSU_ATRACESZ4 -#define CFG_DSU_ATB 4 -#elif CONFIG_DSU_ATRACESZ8 -#define CFG_DSU_ATB 8 -#elif CONFIG_DSU_ATRACESZ16 -#define CFG_DSU_ATB 16 -#else -#define CFG_DSU_ATB 0 -#endif - -#ifndef CONFIG_LEON3FT_EN -#define CONFIG_LEON3FT_EN 0 -#endif - -#if defined CONFIG_IUFT_PAR -#define CONFIG_IUFT_EN 1 -#elif defined CONFIG_IUFT_DMR -#define CONFIG_IUFT_EN 2 -#elif defined CONFIG_IUFT_BCH -#define CONFIG_IUFT_EN 3 -#elif defined CONFIG_IUFT_TMR -#define CONFIG_IUFT_EN 4 -#else -#define CONFIG_IUFT_EN 0 -#endif -#ifndef CONFIG_RF_ERRINJ -#define CONFIG_RF_ERRINJ 0 -#endif - -#ifndef CONFIG_FPUFT_EN -#define CONFIG_FPUFT 0 -#else -#ifdef CONFIG_FPU_GRFPU -#define CONFIG_FPUFT 2 -#else -#define CONFIG_FPUFT 1 -#endif -#endif - -#ifndef CONFIG_CACHE_FT_EN -#define CONFIG_CACHE_FT_EN 0 -#endif -#ifndef CONFIG_CACHE_ERRINJ -#define CONFIG_CACHE_ERRINJ 0 -#endif - -#ifndef CONFIG_LEON3_NETLIST -#define CONFIG_LEON3_NETLIST 0 -#endif - -#ifdef CONFIG_DEBUG_PC32 -#define CFG_DEBUG_PC32 0 -#else -#define CFG_DEBUG_PC32 2 -#endif -#ifndef CONFIG_IU_DISAS -#define CONFIG_IU_DISAS 0 -#endif -#ifndef CONFIG_IU_DISAS_NET -#define CONFIG_IU_DISAS_NET 0 -#endif - - -#ifndef CONFIG_AHB_SPLIT -#define CONFIG_AHB_SPLIT 0 -#endif - -#ifndef CONFIG_AHB_RROBIN -#define CONFIG_AHB_RROBIN 0 -#endif - -#ifndef CONFIG_AHB_IOADDR -#define CONFIG_AHB_IOADDR FFF -#endif - -#ifndef CONFIG_APB_HADDR -#define CONFIG_APB_HADDR 800 -#endif - -#ifndef CONFIG_AHB_MON -#define CONFIG_AHB_MON 0 -#endif - -#ifndef CONFIG_AHB_MONERR -#define CONFIG_AHB_MONERR 0 -#endif - -#ifndef CONFIG_AHB_MONWAR -#define CONFIG_AHB_MONWAR 0 -#endif - -#ifndef CONFIG_AHB_DTRACE -#define CONFIG_AHB_DTRACE 0 -#endif - -#ifndef CONFIG_DSU_JTAG -#define CONFIG_DSU_JTAG 0 -#endif - -#ifndef CONFIG_DSU_ETH -#define CONFIG_DSU_ETH 0 -#endif - -#ifndef CONFIG_DSU_IPMSB -#define CONFIG_DSU_IPMSB C0A8 -#endif - -#ifndef CONFIG_DSU_IPLSB -#define CONFIG_DSU_IPLSB 0033 -#endif - -#ifndef CONFIG_DSU_ETHMSB -#define CONFIG_DSU_ETHMSB 020000 -#endif - -#ifndef CONFIG_DSU_ETHLSB -#define CONFIG_DSU_ETHLSB 000009 -#endif - -#if defined CONFIG_DSU_ETHSZ1 -#define CFG_DSU_ETHB 1 -#elif CONFIG_DSU_ETHSZ2 -#define CFG_DSU_ETHB 2 -#elif CONFIG_DSU_ETHSZ4 -#define CFG_DSU_ETHB 4 -#elif CONFIG_DSU_ETHSZ8 -#define CFG_DSU_ETHB 8 -#elif CONFIG_DSU_ETHSZ16 -#define CFG_DSU_ETHB 16 -#elif CONFIG_DSU_ETHSZ32 -#define CFG_DSU_ETHB 32 -#else -#define CFG_DSU_ETHB 1 -#endif - -#ifndef CONFIG_DSU_ETH_PROG -#define CONFIG_DSU_ETH_PROG 0 -#endif - -#ifndef CONFIG_DSU_ETH_DIS -#define CONFIG_DSU_ETH_DIS 0 -#endif - -#ifndef CONFIG_MCTRL_LEON2 -#define CONFIG_MCTRL_LEON2 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM -#define CONFIG_MCTRL_SDRAM 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_SEPBUS -#define CONFIG_MCTRL_SDRAM_SEPBUS 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_INVCLK -#define CONFIG_MCTRL_SDRAM_INVCLK 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_BUS64 -#define CONFIG_MCTRL_SDRAM_BUS64 0 -#endif - -#ifndef CONFIG_MCTRL_8BIT -#define CONFIG_MCTRL_8BIT 0 -#endif - -#ifndef CONFIG_MCTRL_16BIT -#define CONFIG_MCTRL_16BIT 0 -#endif - -#ifndef CONFIG_MCTRL_5CS -#define CONFIG_MCTRL_5CS 0 -#endif - -#ifndef CONFIG_MCTRL_EDAC -#define CONFIG_MCTRL_EDAC 0 -#endif - -#ifndef CONFIG_MCTRL_PAGE -#define CONFIG_MCTRL_PAGE 0 -#endif - -#ifndef CONFIG_MCTRL_PROGPAGE -#define CONFIG_MCTRL_PROGPAGE 0 -#endif - - -#ifndef CONFIG_MIG_DDR2 -#define CONFIG_MIG_DDR2 0 -#endif - -#ifndef CONFIG_MIG_RANKS -#define CONFIG_MIG_RANKS 1 -#endif - -#ifndef CONFIG_MIG_COLBITS -#define CONFIG_MIG_COLBITS 10 -#endif - -#ifndef CONFIG_MIG_ROWBITS -#define CONFIG_MIG_ROWBITS 13 -#endif - -#ifndef CONFIG_MIG_BANKBITS -#define CONFIG_MIG_BANKBITS 2 -#endif - -#ifndef CONFIG_MIG_HMASK -#define CONFIG_MIG_HMASK F00 -#endif -#ifndef CONFIG_AHBSTAT_ENABLE -#define CONFIG_AHBSTAT_ENABLE 0 -#endif - -#ifndef CONFIG_AHBSTAT_NFTSLV -#define CONFIG_AHBSTAT_NFTSLV 1 -#endif - -#ifndef CONFIG_AHBROM_ENABLE -#define CONFIG_AHBROM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBROM_START -#define CONFIG_AHBROM_START 000 -#endif - -#ifndef CONFIG_AHBROM_PIPE -#define CONFIG_AHBROM_PIPE 0 -#endif - -#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) -#define CONFIG_ROM_START 100 -#else -#define CONFIG_ROM_START 000 -#endif - - -#ifndef CONFIG_AHBRAM_ENABLE -#define CONFIG_AHBRAM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBRAM_START -#define CONFIG_AHBRAM_START A00 -#endif - -#if defined CONFIG_AHBRAM_SZ1 -#define CFG_AHBRAMSZ 1 -#elif CONFIG_AHBRAM_SZ2 -#define CFG_AHBRAMSZ 2 -#elif CONFIG_AHBRAM_SZ4 -#define CFG_AHBRAMSZ 4 -#elif CONFIG_AHBRAM_SZ8 -#define CFG_AHBRAMSZ 8 -#elif CONFIG_AHBRAM_SZ16 -#define CFG_AHBRAMSZ 16 -#elif CONFIG_AHBRAM_SZ32 -#define CFG_AHBRAMSZ 32 -#elif CONFIG_AHBRAM_SZ64 -#define CFG_AHBRAMSZ 64 -#else -#define CFG_AHBRAMSZ 1 -#endif - -#ifndef CONFIG_GRETH_ENABLE -#define CONFIG_GRETH_ENABLE 0 -#endif - -#ifndef CONFIG_GRETH_GIGA -#define CONFIG_GRETH_GIGA 0 -#endif - -#if defined CONFIG_GRETH_FIFO4 -#define CFG_GRETH_FIFO 4 -#elif defined CONFIG_GRETH_FIFO8 -#define CFG_GRETH_FIFO 8 -#elif defined CONFIG_GRETH_FIFO16 -#define CFG_GRETH_FIFO 16 -#elif defined CONFIG_GRETH_FIFO32 -#define CFG_GRETH_FIFO 32 -#elif defined CONFIG_GRETH_FIFO64 -#define CFG_GRETH_FIFO 64 -#else -#define CFG_GRETH_FIFO 8 -#endif - -#ifndef CONFIG_UART1_ENABLE -#define CONFIG_UART1_ENABLE 0 -#endif - -#if defined CONFIG_UA1_FIFO1 -#define CFG_UA1_FIFO 1 -#elif defined CONFIG_UA1_FIFO2 -#define CFG_UA1_FIFO 2 -#elif defined CONFIG_UA1_FIFO4 -#define CFG_UA1_FIFO 4 -#elif defined CONFIG_UA1_FIFO8 -#define CFG_UA1_FIFO 8 -#elif defined CONFIG_UA1_FIFO16 -#define CFG_UA1_FIFO 16 -#elif defined CONFIG_UA1_FIFO32 -#define CFG_UA1_FIFO 32 -#else -#define CFG_UA1_FIFO 1 -#endif - -#ifndef CONFIG_IRQ3_ENABLE -#define CONFIG_IRQ3_ENABLE 0 -#endif -#ifndef CONFIG_IRQ3_NSEC -#define CONFIG_IRQ3_NSEC 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif - -#ifndef CONFIG_GPT_WDOGEN -#define CONFIG_GPT_WDOGEN 0 -#endif - -#ifndef CONFIG_GPT_WDOG -#define CONFIG_GPT_WDOG 0 -#endif - -#ifndef CONFIG_GRGPIO_ENABLE -#define CONFIG_GRGPIO_ENABLE 0 -#endif -#ifndef CONFIG_GRGPIO_IMASK -#define CONFIG_GRGPIO_IMASK 0000 -#endif -#ifndef CONFIG_GRGPIO_WIDTH -#define CONFIG_GRGPIO_WIDTH 1 -#endif - -#ifndef CONFIG_VGA_ENABLE -#define CONFIG_VGA_ENABLE 0 -#endif -#ifndef CONFIG_SVGA_ENABLE -#define CONFIG_SVGA_ENABLE 0 -#endif -#ifndef CONFIG_KBD_ENABLE -#define CONFIG_KBD_ENABLE 0 -#endif - - -#ifndef CONFIG_SPIMCTRL -#define CONFIG_SPIMCTRL 0 -#endif - -#ifndef CONFIG_SPIMCTRL_SDCARD -#define CONFIG_SPIMCTRL_SDCARD 0 -#endif - -#ifndef CONFIG_SPIMCTRL_READCMD -#define CONFIG_SPIMCTRL_READCMD 0 -#endif - -#ifndef CONFIG_SPIMCTRL_DUMMYBYTE -#define CONFIG_SPIMCTRL_DUMMYBYTE 0 -#endif - -#ifndef CONFIG_SPIMCTRL_DUALOUTPUT -#define CONFIG_SPIMCTRL_DUALOUTPUT 0 -#endif - -#ifndef CONFIG_SPIMCTRL_SCALER -#define CONFIG_SPIMCTRL_SCALER 1 -#endif - -#ifndef CONFIG_SPIMCTRL_ASCALER -#define CONFIG_SPIMCTRL_ASCALER 1 -#endif - -#ifndef CONFIG_SPIMCTRL_PWRUPCNT -#define CONFIG_SPIMCTRL_PWRUPCNT 0 -#endif -#ifndef CONFIG_SPICTRL_ENABLE -#define CONFIG_SPICTRL_ENABLE 0 -#endif -#ifndef CONFIG_SPICTRL_NUM -#define CONFIG_SPICTRL_NUM 1 -#endif -#ifndef CONFIG_SPICTRL_SLVS -#define CONFIG_SPICTRL_SLVS 1 -#endif -#ifndef CONFIG_SPICTRL_FIFO -#define CONFIG_SPICTRL_FIFO 1 -#endif -#ifndef CONFIG_SPICTRL_SLVREG -#define CONFIG_SPICTRL_SLVREG 0 -#endif -#ifndef CONFIG_SPICTRL_ODMODE -#define CONFIG_SPICTRL_ODMODE 0 -#endif -#ifndef CONFIG_SPICTRL_AM -#define CONFIG_SPICTRL_AM 0 -#endif -#ifndef CONFIG_SPICTRL_ASEL -#define CONFIG_SPICTRL_ASEL 0 -#endif -#ifndef CONFIG_SPICTRL_TWEN -#define CONFIG_SPICTRL_TWEN 0 -#endif -#ifndef CONFIG_SPICTRL_MAXWLEN -#define CONFIG_SPICTRL_MAXWLEN 0 -#endif -#ifndef CONFIG_SPICTRL_SYNCRAM -#define CONFIG_SPICTRL_SYNCRAM 0 -#endif -#if defined(CONFIG_SPICTRL_DMRFT) -#define CONFIG_SPICTRL_FT 1 -#elif defined(CONFIG_SPICTRL_TMRFT) -#define CONFIG_SPICTRL_FT 2 -#else -#define CONFIG_SPICTRL_FT 0 -#endif - -#ifndef CONFIG_DEBUG_UART -#define CONFIG_DEBUG_UART 0 -#endif +#if defined CONFIG_SYN_INFERRED +#define CONFIG_SYN_TECH inferred +#elif defined CONFIG_SYN_UMC +#define CONFIG_SYN_TECH umc +#elif defined CONFIG_SYN_RHUMC +#define CONFIG_SYN_TECH rhumc +#elif defined CONFIG_SYN_ATC18 +#define CONFIG_SYN_TECH atc18s +#elif defined CONFIG_SYN_ATC18RHA +#define CONFIG_SYN_TECH atc18rha +#elif defined CONFIG_SYN_AXCEL +#define CONFIG_SYN_TECH axcel +#elif defined CONFIG_SYN_AXDSP +#define CONFIG_SYN_TECH axdsp +#elif defined CONFIG_SYN_PROASICPLUS +#define CONFIG_SYN_TECH proasic +#elif defined CONFIG_SYN_ALTERA +#define CONFIG_SYN_TECH altera +#elif defined CONFIG_SYN_STRATIX +#define CONFIG_SYN_TECH stratix1 +#elif defined CONFIG_SYN_STRATIXII +#define CONFIG_SYN_TECH stratix2 +#elif defined CONFIG_SYN_STRATIXIII +#define CONFIG_SYN_TECH stratix3 +#elif defined CONFIG_SYN_CYCLONEIII +#define CONFIG_SYN_TECH cyclone3 +#elif defined CONFIG_SYN_EASIC45 +#define CONFIG_SYN_TECH easic45 +#elif defined CONFIG_SYN_EASIC90 +#define CONFIG_SYN_TECH easic90 +#elif defined CONFIG_SYN_IHP25 +#define CONFIG_SYN_TECH ihp25 +#elif defined CONFIG_SYN_IHP25RH +#define CONFIG_SYN_TECH ihp25rh +#elif defined CONFIG_SYN_CMOS9SF +#define CONFIG_SYN_TECH cmos9sf +#elif defined CONFIG_SYN_LATTICE +#define CONFIG_SYN_TECH lattice +#elif defined CONFIG_SYN_ECLIPSE +#define CONFIG_SYN_TECH eclipse +#elif defined CONFIG_SYN_PEREGRINE +#define CONFIG_SYN_TECH peregrine +#elif defined CONFIG_SYN_PROASIC +#define CONFIG_SYN_TECH proasic +#elif defined CONFIG_SYN_PROASIC3 +#define CONFIG_SYN_TECH apa3 +#elif defined CONFIG_SYN_PROASIC3E +#define CONFIG_SYN_TECH apa3e +#elif defined CONFIG_SYN_PROASIC3L +#define CONFIG_SYN_TECH apa3l +#elif defined CONFIG_SYN_IGLOO +#define CONFIG_SYN_TECH apa3 +#elif defined CONFIG_SYN_FUSION +#define CONFIG_SYN_TECH actfus +#elif defined CONFIG_SYN_SPARTAN2 +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_VIRTEX +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_VIRTEXE +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_SPARTAN3 +#define CONFIG_SYN_TECH spartan3 +#elif defined CONFIG_SYN_SPARTAN3E +#define CONFIG_SYN_TECH spartan3e +#elif defined CONFIG_SYN_SPARTAN6 +#define CONFIG_SYN_TECH spartan6 +#elif defined CONFIG_SYN_VIRTEX2 +#define CONFIG_SYN_TECH virtex2 +#elif defined CONFIG_SYN_VIRTEX4 +#define CONFIG_SYN_TECH virtex4 +#elif defined CONFIG_SYN_VIRTEX5 +#define CONFIG_SYN_TECH virtex5 +#elif defined CONFIG_SYN_VIRTEX6 +#define CONFIG_SYN_TECH virtex6 +#elif defined CONFIG_SYN_RH_LIB18T +#define CONFIG_SYN_TECH rhlib18t +#elif defined CONFIG_SYN_SMIC13 +#define CONFIG_SYN_TECH smic013 +#elif defined CONFIG_SYN_UT025CRH +#define CONFIG_SYN_TECH ut25 +#elif defined CONFIG_SYN_UT130HBD +#define CONFIG_SYN_TECH ut130 +#elif defined CONFIG_SYN_UT90NHBD +#define CONFIG_SYN_TECH ut90 +#elif defined CONFIG_SYN_TSMC90 +#define CONFIG_SYN_TECH tsmc90 +#elif defined CONFIG_SYN_TM65GPLUS +#define CONFIG_SYN_TECH tm65gpl +#elif defined CONFIG_SYN_CUSTOM1 +#define CONFIG_SYN_TECH custom1 +#else +#error "unknown target technology" +#endif + +#if defined CONFIG_SYN_INFER_RAM +#define CFG_RAM_TECH inferred +#elif defined CONFIG_MEM_UMC +#define CFG_RAM_TECH umc +#elif defined CONFIG_MEM_RHUMC +#define CFG_RAM_TECH rhumc +#elif defined CONFIG_MEM_VIRAGE +#define CFG_RAM_TECH memvirage +#elif defined CONFIG_MEM_ARTISAN +#define CFG_RAM_TECH memartisan +#elif defined CONFIG_MEM_CUSTOM1 +#define CFG_RAM_TECH custom1 +#elif defined CONFIG_MEM_VIRAGE90 +#define CFG_RAM_TECH memvirage90 +#elif defined CONFIG_MEM_INFERRED +#define CFG_RAM_TECH inferred +#else +#define CFG_RAM_TECH CONFIG_SYN_TECH +#endif + +#if defined CONFIG_SYN_INFER_PADS +#define CFG_PAD_TECH inferred +#else +#define CFG_PAD_TECH CONFIG_SYN_TECH +#endif + +#ifndef CONFIG_SYN_NO_ASYNC +#define CONFIG_SYN_NO_ASYNC 0 +#endif + +#ifndef CONFIG_SYN_SCAN +#define CONFIG_SYN_SCAN 0 +#endif + + +#if defined CONFIG_CLK_ALTDLL +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_HCLKBUF +#define CFG_CLK_TECH axcel +#elif defined CONFIG_CLK_LATDLL +#define CFG_CLK_TECH lattice +#elif defined CONFIG_CLK_PRO3PLL +#define CFG_CLK_TECH apa3 +#elif defined CONFIG_CLK_PRO3EPLL +#define CFG_CLK_TECH apa3e +#elif defined CONFIG_CLK_PRO3LPLL +#define CFG_CLK_TECH apa3l +#elif defined CONFIG_CLK_FUSPLL +#define CFG_CLK_TECH actfus +#elif defined CONFIG_CLK_CLKDLL +#define CFG_CLK_TECH virtex +#elif defined CONFIG_CLK_DCM +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_LIB18T +#define CFG_CLK_TECH rhlib18t +#elif defined CONFIG_CLK_RHUMC +#define CFG_CLK_TECH rhumc +#elif defined CONFIG_CLK_UT130HBD +#define CFG_CLK_TECH ut130 +#else +#define CFG_CLK_TECH inferred +#endif + +#ifndef CONFIG_CLK_MUL +#define CONFIG_CLK_MUL 2 +#endif + +#ifndef CONFIG_CLK_DIV +#define CONFIG_CLK_DIV 2 +#endif + +#ifndef CONFIG_OCLK_DIV +#define CONFIG_OCLK_DIV 1 +#endif + +#ifndef CONFIG_OCLKB_DIV +#define CONFIG_OCLKB_DIV 0 +#endif + +#ifndef CONFIG_OCLKC_DIV +#define CONFIG_OCLKC_DIV 0 +#endif + +#ifndef CONFIG_PCI_CLKDLL +#define CONFIG_PCI_CLKDLL 0 +#endif + +#ifndef CONFIG_PCI_SYSCLK +#define CONFIG_PCI_SYSCLK 0 +#endif + +#ifndef CONFIG_CLK_NOFB +#define CONFIG_CLK_NOFB 0 +#endif +#ifndef CONFIG_LEON3 +#define CONFIG_LEON3 0 +#endif + +#ifndef CONFIG_PROC_NUM +#define CONFIG_PROC_NUM 1 +#endif + +#ifndef CONFIG_IU_NWINDOWS +#define CONFIG_IU_NWINDOWS 8 +#endif + +#ifndef CONFIG_IU_RSTADDR +#define CONFIG_IU_RSTADDR 8 +#endif + +#ifndef CONFIG_IU_LDELAY +#define CONFIG_IU_LDELAY 1 +#endif + +#ifndef CONFIG_IU_WATCHPOINTS +#define CONFIG_IU_WATCHPOINTS 0 +#endif + +#ifdef CONFIG_IU_V8MULDIV +#ifdef CONFIG_IU_MUL_LATENCY_4 +#define CFG_IU_V8 1 +#elif defined CONFIG_IU_MUL_LATENCY_5 +#define CFG_IU_V8 2 +#elif defined CONFIG_IU_MUL_LATENCY_2 +#define CFG_IU_V8 16#32# +#endif +#else +#define CFG_IU_V8 0 +#endif + +#ifdef CONFIG_IU_MUL_MODGEN +#define CFG_IU_MUL_STRUCT 1 +#elif defined CONFIG_IU_MUL_TECHSPEC +#define CFG_IU_MUL_STRUCT 2 +#elif defined CONFIG_IU_MUL_DW +#define CFG_IU_MUL_STRUCT 3 +#else +#define CFG_IU_MUL_STRUCT 0 +#endif + +#ifndef CONFIG_PWD +#define CONFIG_PWD 0 +#endif + +#ifndef CONFIG_IU_MUL_MAC +#define CONFIG_IU_MUL_MAC 0 +#endif + +#ifndef CONFIG_IU_BP +#define CONFIG_IU_BP 0 +#endif + +#ifndef CONFIG_NOTAG +#define CONFIG_NOTAG 0 +#endif + +#ifndef CONFIG_IU_SVT +#define CONFIG_IU_SVT 0 +#endif + +#if defined CONFIG_FPU_GRFPC1 +#define CONFIG_FPU_GRFPC 1 +#elif defined CONFIG_FPU_GRFPC2 +#define CONFIG_FPU_GRFPC 2 +#else +#define CONFIG_FPU_GRFPC 0 +#endif + +#if defined CONFIG_FPU_GRFPU_INFMUL +#define CONFIG_FPU_GRFPU_MUL 0 +#elif defined CONFIG_FPU_GRFPU_DWMUL +#define CONFIG_FPU_GRFPU_MUL 1 +#elif defined CONFIG_FPU_GRFPU_MODGEN +#define CONFIG_FPU_GRFPU_MUL 2 +#elif defined CONFIG_FPU_GRFPU_TECHSPEC +#define CONFIG_FPU_GRFPU_MUL 3 +#else +#define CONFIG_FPU_GRFPU_MUL 0 +#endif + +#if defined CONFIG_FPU_GRFPU_SH +#define CONFIG_FPU_GRFPU_SHARED 1 +#else +#define CONFIG_FPU_GRFPU_SHARED 0 +#endif + +#if defined CONFIG_FPU_GRFPU +#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) +#elif defined CONFIG_FPU_MEIKO +#define CONFIG_FPU 15 +#elif defined CONFIG_FPU_GRFPULITE +#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) +#else +#define CONFIG_FPU 0 +#endif + +#ifndef CONFIG_FPU_NETLIST +#define CONFIG_FPU_NETLIST 0 +#endif + +#ifndef CONFIG_ICACHE_ENABLE +#define CONFIG_ICACHE_ENABLE 0 +#endif + +#if defined CONFIG_ICACHE_ASSO1 +#define CFG_IU_ISETS 1 +#elif defined CONFIG_ICACHE_ASSO2 +#define CFG_IU_ISETS 2 +#elif defined CONFIG_ICACHE_ASSO3 +#define CFG_IU_ISETS 3 +#elif defined CONFIG_ICACHE_ASSO4 +#define CFG_IU_ISETS 4 +#else +#define CFG_IU_ISETS 1 +#endif + +#if defined CONFIG_ICACHE_SZ1 +#define CFG_ICACHE_SZ 1 +#elif defined CONFIG_ICACHE_SZ2 +#define CFG_ICACHE_SZ 2 +#elif defined CONFIG_ICACHE_SZ4 +#define CFG_ICACHE_SZ 4 +#elif defined CONFIG_ICACHE_SZ8 +#define CFG_ICACHE_SZ 8 +#elif defined CONFIG_ICACHE_SZ16 +#define CFG_ICACHE_SZ 16 +#elif defined CONFIG_ICACHE_SZ32 +#define CFG_ICACHE_SZ 32 +#elif defined CONFIG_ICACHE_SZ64 +#define CFG_ICACHE_SZ 64 +#elif defined CONFIG_ICACHE_SZ128 +#define CFG_ICACHE_SZ 128 +#elif defined CONFIG_ICACHE_SZ256 +#define CFG_ICACHE_SZ 256 +#else +#define CFG_ICACHE_SZ 1 +#endif + +#ifdef CONFIG_ICACHE_LZ16 +#define CFG_ILINE_SZ 4 +#else +#define CFG_ILINE_SZ 8 +#endif + +#if defined CONFIG_ICACHE_ALGODIR +#define CFG_ICACHE_ALGORND 3 +#elif defined CONFIG_ICACHE_ALGORND +#define CFG_ICACHE_ALGORND 2 +#elif defined CONFIG_ICACHE_ALGOLRR +#define CFG_ICACHE_ALGORND 1 +#else +#define CFG_ICACHE_ALGORND 0 +#endif + +#ifndef CONFIG_ICACHE_LOCK +#define CONFIG_ICACHE_LOCK 0 +#endif + +#ifndef CONFIG_ICACHE_LRAM +#define CONFIG_ICACHE_LRAM 0 +#endif + +#ifndef CONFIG_ICACHE_LRSTART +#define CONFIG_ICACHE_LRSTART 8E +#endif + +#if defined CONFIG_ICACHE_LRAM_SZ2 +#define CFG_ILRAM_SIZE 2 +#elif defined CONFIG_ICACHE_LRAM_SZ4 +#define CFG_ILRAM_SIZE 4 +#elif defined CONFIG_ICACHE_LRAM_SZ8 +#define CFG_ILRAM_SIZE 8 +#elif defined CONFIG_ICACHE_LRAM_SZ16 +#define CFG_ILRAM_SIZE 16 +#elif defined CONFIG_ICACHE_LRAM_SZ32 +#define CFG_ILRAM_SIZE 32 +#elif defined CONFIG_ICACHE_LRAM_SZ64 +#define CFG_ILRAM_SIZE 64 +#elif defined CONFIG_ICACHE_LRAM_SZ128 +#define CFG_ILRAM_SIZE 128 +#elif defined CONFIG_ICACHE_LRAM_SZ256 +#define CFG_ILRAM_SIZE 256 +#else +#define CFG_ILRAM_SIZE 1 +#endif + + +#ifndef CONFIG_DCACHE_ENABLE +#define CONFIG_DCACHE_ENABLE 0 +#endif + +#if defined CONFIG_DCACHE_ASSO1 +#define CFG_IU_DSETS 1 +#elif defined CONFIG_DCACHE_ASSO2 +#define CFG_IU_DSETS 2 +#elif defined CONFIG_DCACHE_ASSO3 +#define CFG_IU_DSETS 3 +#elif defined CONFIG_DCACHE_ASSO4 +#define CFG_IU_DSETS 4 +#else +#define CFG_IU_DSETS 1 +#endif + +#if defined CONFIG_DCACHE_SZ1 +#define CFG_DCACHE_SZ 1 +#elif defined CONFIG_DCACHE_SZ2 +#define CFG_DCACHE_SZ 2 +#elif defined CONFIG_DCACHE_SZ4 +#define CFG_DCACHE_SZ 4 +#elif defined CONFIG_DCACHE_SZ8 +#define CFG_DCACHE_SZ 8 +#elif defined CONFIG_DCACHE_SZ16 +#define CFG_DCACHE_SZ 16 +#elif defined CONFIG_DCACHE_SZ32 +#define CFG_DCACHE_SZ 32 +#elif defined CONFIG_DCACHE_SZ64 +#define CFG_DCACHE_SZ 64 +#elif defined CONFIG_DCACHE_SZ128 +#define CFG_DCACHE_SZ 128 +#elif defined CONFIG_DCACHE_SZ256 +#define CFG_DCACHE_SZ 256 +#else +#define CFG_DCACHE_SZ 1 +#endif + +#ifdef CONFIG_DCACHE_LZ16 +#define CFG_DLINE_SZ 4 +#else +#define CFG_DLINE_SZ 8 +#endif + +#if defined CONFIG_DCACHE_ALGODIR +#define CFG_DCACHE_ALGORND 3 +#elif defined CONFIG_DCACHE_ALGORND +#define CFG_DCACHE_ALGORND 2 +#elif defined CONFIG_DCACHE_ALGOLRR +#define CFG_DCACHE_ALGORND 1 +#else +#define CFG_DCACHE_ALGORND 0 +#endif + +#ifndef CONFIG_DCACHE_LOCK +#define CONFIG_DCACHE_LOCK 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP +#define CONFIG_DCACHE_SNOOP 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP_FAST +#define CONFIG_DCACHE_SNOOP_FAST 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP_SEPTAG +#define CONFIG_DCACHE_SNOOP_SEPTAG 0 +#endif + +#ifndef CONFIG_CACHE_FIXED +#define CONFIG_CACHE_FIXED 0 +#endif + +#ifndef CONFIG_DCACHE_LRAM +#define CONFIG_DCACHE_LRAM 0 +#endif + +#ifndef CONFIG_DCACHE_LRSTART +#define CONFIG_DCACHE_LRSTART 8F +#endif + +#if defined CONFIG_DCACHE_LRAM_SZ2 +#define CFG_DLRAM_SIZE 2 +#elif defined CONFIG_DCACHE_LRAM_SZ4 +#define CFG_DLRAM_SIZE 4 +#elif defined CONFIG_DCACHE_LRAM_SZ8 +#define CFG_DLRAM_SIZE 8 +#elif defined CONFIG_DCACHE_LRAM_SZ16 +#define CFG_DLRAM_SIZE 16 +#elif defined CONFIG_DCACHE_LRAM_SZ32 +#define CFG_DLRAM_SIZE 32 +#elif defined CONFIG_DCACHE_LRAM_SZ64 +#define CFG_DLRAM_SIZE 64 +#elif defined CONFIG_DCACHE_LRAM_SZ128 +#define CFG_DLRAM_SIZE 128 +#elif defined CONFIG_DCACHE_LRAM_SZ256 +#define CFG_DLRAM_SIZE 256 +#else +#define CFG_DLRAM_SIZE 1 +#endif + +#if defined CONFIG_MMU_PAGE_4K +#define CONFIG_MMU_PAGE 0 +#elif defined CONFIG_MMU_PAGE_8K +#define CONFIG_MMU_PAGE 1 +#elif defined CONFIG_MMU_PAGE_16K +#define CONFIG_MMU_PAGE 2 +#elif defined CONFIG_MMU_PAGE_32K +#define CONFIG_MMU_PAGE 3 +#elif defined CONFIG_MMU_PAGE_PROG +#define CONFIG_MMU_PAGE 4 +#else +#define CONFIG_MMU_PAGE 0 +#endif + +#ifdef CONFIG_MMU_ENABLE +#define CONFIG_MMUEN 1 + +#ifdef CONFIG_MMU_SPLIT +#define CONFIG_TLB_TYPE 0 +#endif +#ifdef CONFIG_MMU_COMBINED +#define CONFIG_TLB_TYPE 1 +#endif + +#ifdef CONFIG_MMU_REPARRAY +#define CONFIG_TLB_REP 0 +#endif +#ifdef CONFIG_MMU_REPINCREMENT +#define CONFIG_TLB_REP 1 +#endif + +#ifdef CONFIG_MMU_I2 +#define CONFIG_ITLBNUM 2 +#endif +#ifdef CONFIG_MMU_I4 +#define CONFIG_ITLBNUM 4 +#endif +#ifdef CONFIG_MMU_I8 +#define CONFIG_ITLBNUM 8 +#endif +#ifdef CONFIG_MMU_I16 +#define CONFIG_ITLBNUM 16 +#endif +#ifdef CONFIG_MMU_I32 +#define CONFIG_ITLBNUM 32 +#endif + +#define CONFIG_DTLBNUM 2 +#ifdef CONFIG_MMU_D2 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 2 +#endif +#ifdef CONFIG_MMU_D4 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 4 +#endif +#ifdef CONFIG_MMU_D8 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 8 +#endif +#ifdef CONFIG_MMU_D16 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 16 +#endif +#ifdef CONFIG_MMU_D32 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 32 +#endif +#ifdef CONFIG_MMU_FASTWB +#define CFG_MMU_FASTWB 1 +#else +#define CFG_MMU_FASTWB 0 +#endif + +#else +#define CONFIG_MMUEN 0 +#define CONFIG_ITLBNUM 2 +#define CONFIG_DTLBNUM 2 +#define CONFIG_TLB_TYPE 1 +#define CONFIG_TLB_REP 1 +#define CFG_MMU_FASTWB 0 +#endif + +#ifndef CONFIG_DSU_ENABLE +#define CONFIG_DSU_ENABLE 0 +#endif + +#if defined CONFIG_DSU_ITRACESZ1 +#define CFG_DSU_ITB 1 +#elif CONFIG_DSU_ITRACESZ2 +#define CFG_DSU_ITB 2 +#elif CONFIG_DSU_ITRACESZ4 +#define CFG_DSU_ITB 4 +#elif CONFIG_DSU_ITRACESZ8 +#define CFG_DSU_ITB 8 +#elif CONFIG_DSU_ITRACESZ16 +#define CFG_DSU_ITB 16 +#else +#define CFG_DSU_ITB 0 +#endif + +#if defined CONFIG_DSU_ATRACESZ1 +#define CFG_DSU_ATB 1 +#elif CONFIG_DSU_ATRACESZ2 +#define CFG_DSU_ATB 2 +#elif CONFIG_DSU_ATRACESZ4 +#define CFG_DSU_ATB 4 +#elif CONFIG_DSU_ATRACESZ8 +#define CFG_DSU_ATB 8 +#elif CONFIG_DSU_ATRACESZ16 +#define CFG_DSU_ATB 16 +#else +#define CFG_DSU_ATB 0 +#endif + +#ifndef CONFIG_LEON3FT_EN +#define CONFIG_LEON3FT_EN 0 +#endif + +#if defined CONFIG_IUFT_PAR +#define CONFIG_IUFT_EN 1 +#elif defined CONFIG_IUFT_DMR +#define CONFIG_IUFT_EN 2 +#elif defined CONFIG_IUFT_BCH +#define CONFIG_IUFT_EN 3 +#elif defined CONFIG_IUFT_TMR +#define CONFIG_IUFT_EN 4 +#else +#define CONFIG_IUFT_EN 0 +#endif +#ifndef CONFIG_RF_ERRINJ +#define CONFIG_RF_ERRINJ 0 +#endif + +#ifndef CONFIG_FPUFT_EN +#define CONFIG_FPUFT 0 +#else +#ifdef CONFIG_FPU_GRFPU +#define CONFIG_FPUFT 2 +#else +#define CONFIG_FPUFT 1 +#endif +#endif + +#ifndef CONFIG_CACHE_FT_EN +#define CONFIG_CACHE_FT_EN 0 +#endif +#ifndef CONFIG_CACHE_ERRINJ +#define CONFIG_CACHE_ERRINJ 0 +#endif + +#ifndef CONFIG_LEON3_NETLIST +#define CONFIG_LEON3_NETLIST 0 +#endif + +#ifdef CONFIG_DEBUG_PC32 +#define CFG_DEBUG_PC32 0 +#else +#define CFG_DEBUG_PC32 2 +#endif +#ifndef CONFIG_IU_DISAS +#define CONFIG_IU_DISAS 0 +#endif +#ifndef CONFIG_IU_DISAS_NET +#define CONFIG_IU_DISAS_NET 0 +#endif + + +#ifndef CONFIG_AHB_SPLIT +#define CONFIG_AHB_SPLIT 0 +#endif + +#ifndef CONFIG_AHB_RROBIN +#define CONFIG_AHB_RROBIN 0 +#endif + +#ifndef CONFIG_AHB_IOADDR +#define CONFIG_AHB_IOADDR FFF +#endif + +#ifndef CONFIG_APB_HADDR +#define CONFIG_APB_HADDR 800 +#endif + +#ifndef CONFIG_AHB_MON +#define CONFIG_AHB_MON 0 +#endif + +#ifndef CONFIG_AHB_MONERR +#define CONFIG_AHB_MONERR 0 +#endif + +#ifndef CONFIG_AHB_MONWAR +#define CONFIG_AHB_MONWAR 0 +#endif + +#ifndef CONFIG_AHB_DTRACE +#define CONFIG_AHB_DTRACE 0 +#endif + +#ifndef CONFIG_DSU_JTAG +#define CONFIG_DSU_JTAG 0 +#endif + +#ifndef CONFIG_DSU_ETH +#define CONFIG_DSU_ETH 0 +#endif + +#ifndef CONFIG_DSU_IPMSB +#define CONFIG_DSU_IPMSB C0A8 +#endif + +#ifndef CONFIG_DSU_IPLSB +#define CONFIG_DSU_IPLSB 0033 +#endif + +#ifndef CONFIG_DSU_ETHMSB +#define CONFIG_DSU_ETHMSB 020000 +#endif + +#ifndef CONFIG_DSU_ETHLSB +#define CONFIG_DSU_ETHLSB 000009 +#endif + +#if defined CONFIG_DSU_ETHSZ1 +#define CFG_DSU_ETHB 1 +#elif CONFIG_DSU_ETHSZ2 +#define CFG_DSU_ETHB 2 +#elif CONFIG_DSU_ETHSZ4 +#define CFG_DSU_ETHB 4 +#elif CONFIG_DSU_ETHSZ8 +#define CFG_DSU_ETHB 8 +#elif CONFIG_DSU_ETHSZ16 +#define CFG_DSU_ETHB 16 +#elif CONFIG_DSU_ETHSZ32 +#define CFG_DSU_ETHB 32 +#else +#define CFG_DSU_ETHB 1 +#endif + +#ifndef CONFIG_DSU_ETH_PROG +#define CONFIG_DSU_ETH_PROG 0 +#endif + +#ifndef CONFIG_DSU_ETH_DIS +#define CONFIG_DSU_ETH_DIS 0 +#endif + +#ifndef CONFIG_MCTRL_LEON2 +#define CONFIG_MCTRL_LEON2 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM +#define CONFIG_MCTRL_SDRAM 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_SEPBUS +#define CONFIG_MCTRL_SDRAM_SEPBUS 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_INVCLK +#define CONFIG_MCTRL_SDRAM_INVCLK 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_BUS64 +#define CONFIG_MCTRL_SDRAM_BUS64 0 +#endif + +#ifndef CONFIG_MCTRL_8BIT +#define CONFIG_MCTRL_8BIT 0 +#endif + +#ifndef CONFIG_MCTRL_16BIT +#define CONFIG_MCTRL_16BIT 0 +#endif + +#ifndef CONFIG_MCTRL_5CS +#define CONFIG_MCTRL_5CS 0 +#endif + +#ifndef CONFIG_MCTRL_EDAC +#define CONFIG_MCTRL_EDAC 0 +#endif + +#ifndef CONFIG_MCTRL_PAGE +#define CONFIG_MCTRL_PAGE 0 +#endif + +#ifndef CONFIG_MCTRL_PROGPAGE +#define CONFIG_MCTRL_PROGPAGE 0 +#endif + + +#ifndef CONFIG_MIG_DDR2 +#define CONFIG_MIG_DDR2 0 +#endif + +#ifndef CONFIG_MIG_RANKS +#define CONFIG_MIG_RANKS 1 +#endif + +#ifndef CONFIG_MIG_COLBITS +#define CONFIG_MIG_COLBITS 10 +#endif + +#ifndef CONFIG_MIG_ROWBITS +#define CONFIG_MIG_ROWBITS 13 +#endif + +#ifndef CONFIG_MIG_BANKBITS +#define CONFIG_MIG_BANKBITS 2 +#endif + +#ifndef CONFIG_MIG_HMASK +#define CONFIG_MIG_HMASK F00 +#endif +#ifndef CONFIG_AHBSTAT_ENABLE +#define CONFIG_AHBSTAT_ENABLE 0 +#endif + +#ifndef CONFIG_AHBSTAT_NFTSLV +#define CONFIG_AHBSTAT_NFTSLV 1 +#endif + +#ifndef CONFIG_AHBROM_ENABLE +#define CONFIG_AHBROM_ENABLE 0 +#endif + +#ifndef CONFIG_AHBROM_START +#define CONFIG_AHBROM_START 000 +#endif + +#ifndef CONFIG_AHBROM_PIPE +#define CONFIG_AHBROM_PIPE 0 +#endif + +#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) +#define CONFIG_ROM_START 100 +#else +#define CONFIG_ROM_START 000 +#endif + + +#ifndef CONFIG_AHBRAM_ENABLE +#define CONFIG_AHBRAM_ENABLE 0 +#endif + +#ifndef CONFIG_AHBRAM_START +#define CONFIG_AHBRAM_START A00 +#endif + +#if defined CONFIG_AHBRAM_SZ1 +#define CFG_AHBRAMSZ 1 +#elif CONFIG_AHBRAM_SZ2 +#define CFG_AHBRAMSZ 2 +#elif CONFIG_AHBRAM_SZ4 +#define CFG_AHBRAMSZ 4 +#elif CONFIG_AHBRAM_SZ8 +#define CFG_AHBRAMSZ 8 +#elif CONFIG_AHBRAM_SZ16 +#define CFG_AHBRAMSZ 16 +#elif CONFIG_AHBRAM_SZ32 +#define CFG_AHBRAMSZ 32 +#elif CONFIG_AHBRAM_SZ64 +#define CFG_AHBRAMSZ 64 +#else +#define CFG_AHBRAMSZ 1 +#endif + +#ifndef CONFIG_GRETH_ENABLE +#define CONFIG_GRETH_ENABLE 0 +#endif + +#ifndef CONFIG_GRETH_GIGA +#define CONFIG_GRETH_GIGA 0 +#endif + +#if defined CONFIG_GRETH_FIFO4 +#define CFG_GRETH_FIFO 4 +#elif defined CONFIG_GRETH_FIFO8 +#define CFG_GRETH_FIFO 8 +#elif defined CONFIG_GRETH_FIFO16 +#define CFG_GRETH_FIFO 16 +#elif defined CONFIG_GRETH_FIFO32 +#define CFG_GRETH_FIFO 32 +#elif defined CONFIG_GRETH_FIFO64 +#define CFG_GRETH_FIFO 64 +#else +#define CFG_GRETH_FIFO 8 +#endif + +#ifndef CONFIG_UART1_ENABLE +#define CONFIG_UART1_ENABLE 0 +#endif + +#if defined CONFIG_UA1_FIFO1 +#define CFG_UA1_FIFO 1 +#elif defined CONFIG_UA1_FIFO2 +#define CFG_UA1_FIFO 2 +#elif defined CONFIG_UA1_FIFO4 +#define CFG_UA1_FIFO 4 +#elif defined CONFIG_UA1_FIFO8 +#define CFG_UA1_FIFO 8 +#elif defined CONFIG_UA1_FIFO16 +#define CFG_UA1_FIFO 16 +#elif defined CONFIG_UA1_FIFO32 +#define CFG_UA1_FIFO 32 +#else +#define CFG_UA1_FIFO 1 +#endif + +#ifndef CONFIG_IRQ3_ENABLE +#define CONFIG_IRQ3_ENABLE 0 +#endif +#ifndef CONFIG_IRQ3_NSEC +#define CONFIG_IRQ3_NSEC 0 +#endif +#ifndef CONFIG_GPT_ENABLE +#define CONFIG_GPT_ENABLE 0 +#endif + +#ifndef CONFIG_GPT_NTIM +#define CONFIG_GPT_NTIM 1 +#endif + +#ifndef CONFIG_GPT_SW +#define CONFIG_GPT_SW 8 +#endif + +#ifndef CONFIG_GPT_TW +#define CONFIG_GPT_TW 8 +#endif + +#ifndef CONFIG_GPT_IRQ +#define CONFIG_GPT_IRQ 8 +#endif + +#ifndef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 0 +#endif +#ifndef CONFIG_GPT_ENABLE +#define CONFIG_GPT_ENABLE 0 +#endif + +#ifndef CONFIG_GPT_NTIM +#define CONFIG_GPT_NTIM 1 +#endif + +#ifndef CONFIG_GPT_SW +#define CONFIG_GPT_SW 8 +#endif + +#ifndef CONFIG_GPT_TW +#define CONFIG_GPT_TW 8 +#endif + +#ifndef CONFIG_GPT_IRQ +#define CONFIG_GPT_IRQ 8 +#endif + +#ifndef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 0 +#endif + +#ifndef CONFIG_GPT_WDOGEN +#define CONFIG_GPT_WDOGEN 0 +#endif + +#ifndef CONFIG_GPT_WDOG +#define CONFIG_GPT_WDOG 0 +#endif + +#ifndef CONFIG_GRGPIO_ENABLE +#define CONFIG_GRGPIO_ENABLE 0 +#endif +#ifndef CONFIG_GRGPIO_IMASK +#define CONFIG_GRGPIO_IMASK 0000 +#endif +#ifndef CONFIG_GRGPIO_WIDTH +#define CONFIG_GRGPIO_WIDTH 1 +#endif + +#ifndef CONFIG_VGA_ENABLE +#define CONFIG_VGA_ENABLE 0 +#endif +#ifndef CONFIG_SVGA_ENABLE +#define CONFIG_SVGA_ENABLE 0 +#endif +#ifndef CONFIG_KBD_ENABLE +#define CONFIG_KBD_ENABLE 0 +#endif + + +#ifndef CONFIG_SPIMCTRL +#define CONFIG_SPIMCTRL 0 +#endif + +#ifndef CONFIG_SPIMCTRL_SDCARD +#define CONFIG_SPIMCTRL_SDCARD 0 +#endif + +#ifndef CONFIG_SPIMCTRL_READCMD +#define CONFIG_SPIMCTRL_READCMD 0 +#endif + +#ifndef CONFIG_SPIMCTRL_DUMMYBYTE +#define CONFIG_SPIMCTRL_DUMMYBYTE 0 +#endif + +#ifndef CONFIG_SPIMCTRL_DUALOUTPUT +#define CONFIG_SPIMCTRL_DUALOUTPUT 0 +#endif + +#ifndef CONFIG_SPIMCTRL_SCALER +#define CONFIG_SPIMCTRL_SCALER 1 +#endif + +#ifndef CONFIG_SPIMCTRL_ASCALER +#define CONFIG_SPIMCTRL_ASCALER 1 +#endif + +#ifndef CONFIG_SPIMCTRL_PWRUPCNT +#define CONFIG_SPIMCTRL_PWRUPCNT 0 +#endif +#ifndef CONFIG_SPICTRL_ENABLE +#define CONFIG_SPICTRL_ENABLE 0 +#endif +#ifndef CONFIG_SPICTRL_NUM +#define CONFIG_SPICTRL_NUM 1 +#endif +#ifndef CONFIG_SPICTRL_SLVS +#define CONFIG_SPICTRL_SLVS 1 +#endif +#ifndef CONFIG_SPICTRL_FIFO +#define CONFIG_SPICTRL_FIFO 1 +#endif +#ifndef CONFIG_SPICTRL_SLVREG +#define CONFIG_SPICTRL_SLVREG 0 +#endif +#ifndef CONFIG_SPICTRL_ODMODE +#define CONFIG_SPICTRL_ODMODE 0 +#endif +#ifndef CONFIG_SPICTRL_AM +#define CONFIG_SPICTRL_AM 0 +#endif +#ifndef CONFIG_SPICTRL_ASEL +#define CONFIG_SPICTRL_ASEL 0 +#endif +#ifndef CONFIG_SPICTRL_TWEN +#define CONFIG_SPICTRL_TWEN 0 +#endif +#ifndef CONFIG_SPICTRL_MAXWLEN +#define CONFIG_SPICTRL_MAXWLEN 0 +#endif +#ifndef CONFIG_SPICTRL_SYNCRAM +#define CONFIG_SPICTRL_SYNCRAM 0 +#endif +#if defined(CONFIG_SPICTRL_DMRFT) +#define CONFIG_SPICTRL_FT 1 +#elif defined(CONFIG_SPICTRL_TMRFT) +#define CONFIG_SPICTRL_FT 2 +#else +#define CONFIG_SPICTRL_FT 0 +#endif + +#ifndef CONFIG_DEBUG_UART +#define CONFIG_DEBUG_UART 0 +#endif diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/README.txt b/designs/leon3-APB_LCD-digilent-xc3s1600e/README.txt --- a/designs/leon3-APB_LCD-digilent-xc3s1600e/README.txt +++ b/designs/leon3-APB_LCD-digilent-xc3s1600e/README.txt @@ -1,169 +1,169 @@ - -This leon3 design is tailored to the Digilent Spartan3-1600E Evaluation board: - -http://www.digilentinc.com/Products/Detail.cfm?Prod=S3E1600&Nav1=Products&Nav2=Programmable - -Design specifics: - -* System reset is mapped to SW_SOUTH (reset) - -* DSU break is mapped to SW_EAST - -* LED 0/1 indicates console UART RX and TX activity. - -* LED 2/3 indicates DSU UART RX and TX activity. - -* LED 4 indicates processor in debug mode - -* LED 7 indicates processor in error mode - -* The GRETH core is enabled and runs without problems at 100 Mbit. - Ethernet debug link is enabled, default IP is 192.168.0.51. - -* 16-bit flash prom can be read at address 0. It can be programmed - with GRMON version 1.1.16 or later. - -* DDR is mapped at address 0x40000000 (64 Mbyte) and is clocked - at 100 MHz. The processor and AMBA system runs on a different - clock, and can typically reach 40 MHz. The processor clock - is generated from the 50 MHz clock oscillator, scaled with the - DCM factors (4/5) in xconfig. - -* The APBPS2 PS/2 core is attached to the PS/2 connector - -* The SVGA frame buffer runs fine with 800x600 resolution. Due to the - limited number of clock buffers, no other resoltion is supported. - Note that the board does not have a video DAC, so only the MSB bit (7) - of the three colour channels is connected to the VGA connector. - - A test patter can be generated using grmon-1.1.18 or later with: - - draw test_screen 800 16 - -* The DSU uart is connected to the female RS232 connected. - The application UART1 is connected to the male RS232 connector. - -* The JTAG DSU interface is enabled. - -* Output from GRMON info sys is: - - - ethernet startup. - GRLIB build version: 4090 - - initialising .............. - detected frequency: 40 MHz - - Component Vendor - LEON3 SPARC V8 Processor Gaisler Research - AHB Debug UART Gaisler Research - AHB Debug JTAG TAP Gaisler Research - SVGA Controller Gaisler Research - GR Ethernet MAC Gaisler Research - AHB/APB Bridge Gaisler Research - LEON3 Debug Support Unit Gaisler Research - DDR266 Controller Gaisler Research - LEON2 Memory Controller European Space Agency - Generic APB UART Gaisler Research - Multi-processor Interrupt Ctrl Gaisler Research - Modular Timer Unit Gaisler Research - PS/2 interface Gaisler Research - General purpose I/O port Gaisler Research - - Use command 'info sys' to print a detailed report of attached cores - -grlib> inf sys -00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0) - ahb master 0 -01.01:007 Gaisler Research AHB Debug UART (ver 0x0) - ahb master 1 - apb: 80000700 - 80000800 - baud rate 115200, ahb frequency 40.00 -02.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0) - ahb master 2 -03.01:063 Gaisler Research SVGA Controller (ver 0x0) - ahb master 3 - apb: 80000600 - 80000700 - clk0: 40.00 MHz -04.01:01d Gaisler Research GR Ethernet MAC (ver 0x0) - ahb master 4, irq 12 - apb: 80000f00 - 80001000 - edcl ip 192.168.0.51, buffer 2 kbyte -01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) - ahb: 80000000 - 80100000 -02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1) - ahb: 90000000 - a0000000 - AHB trace 256 lines, 32-bit bus, stack pointer 0x43fffff0 - CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1, GRFPU-lite - icache 2 * 4 kbyte, 32 byte/line rnd - dcache 2 * 4 kbyte, 16 byte/line rnd -04.01:025 Gaisler Research DDR266 Controller (ver 0x0) - ahb: 40000000 - 50000000 - ahb: fff00100 - fff00200 - 16-bit DDR : 1 * 64 Mbyte @ 0x40000000 - 100 MHz, col 10, ref 7.8 us, trfc 80 ns -05.04:00f European Space Agency LEON2 Memory Controller (ver 0x1) - ahb: 00000000 - 20000000 - ahb: 20000000 - 40000000 - ahb: 60000000 - 70000000 - apb: 80000000 - 80000100 - 16-bit prom @ 0x00000000 -01.01:00c Gaisler Research Generic APB UART (ver 0x1) - irq 2 - apb: 80000100 - 80000200 - baud rate 38461, DSU mode (FIFO debug) -02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3) - apb: 80000200 - 80000300 -03.01:011 Gaisler Research Modular Timer Unit (ver 0x0) - irq 8 - apb: 80000300 - 80000400 - 8-bit scaler, 2 * 32-bit timers, divisor 40 -05.01:060 Gaisler Research PS/2 interface (ver 0x2) - irq 5 - apb: 80000500 - 80000600 -0b.01:01a Gaisler Research General purpose I/O port (ver 0x0) - apb: 80000b00 - 80000c00 -grlib> - -grlib> flas - - Intel-style 16-bit flash on D[31:16] - - Manuf. Intel - Device MT28F128J3 ) - - Device ID 0418ffff008844d1 - User ID ffffffffffffffff - - - 1 x 16 Mbyte = 16 Mbyte total @ 0x00000000 - - - CFI info - flash family : 1 - flash size : 128 Mbit - erase regions : 1 - erase blocks : 128 - write buffer : 32 bytes - region 0 : 128 blocks of 128 Kbytes - -grlib> - -grlib> lo ~/examples/dhry412 -section: .text at 0x40000000, size 53296 bytes -section: .data at 0x4000d030, size 2764 bytes -total size: 56060 bytes (63.3 Mbit/s) -read 262 symbols -entry point: 0x40000000 -grlib> run -Execution starts, 1000000 runs through Dhrystone -Total execution time: 10.5 s -Microseconds for one run through Dhrystone: 10.5 -Dhrystones per Second: 95073.0 - -Dhrystones MIPS : 54.1 - - -Program exited normally. -grlib> - + +This leon3 design is tailored to the Digilent Spartan3-1600E Evaluation board: + +http://www.digilentinc.com/Products/Detail.cfm?Prod=S3E1600&Nav1=Products&Nav2=Programmable + +Design specifics: + +* System reset is mapped to SW_SOUTH (reset) + +* DSU break is mapped to SW_EAST + +* LED 0/1 indicates console UART RX and TX activity. + +* LED 2/3 indicates DSU UART RX and TX activity. + +* LED 4 indicates processor in debug mode + +* LED 7 indicates processor in error mode + +* The GRETH core is enabled and runs without problems at 100 Mbit. + Ethernet debug link is enabled, default IP is 192.168.0.51. + +* 16-bit flash prom can be read at address 0. It can be programmed + with GRMON version 1.1.16 or later. + +* DDR is mapped at address 0x40000000 (64 Mbyte) and is clocked + at 100 MHz. The processor and AMBA system runs on a different + clock, and can typically reach 40 MHz. The processor clock + is generated from the 50 MHz clock oscillator, scaled with the + DCM factors (4/5) in xconfig. + +* The APBPS2 PS/2 core is attached to the PS/2 connector + +* The SVGA frame buffer runs fine with 800x600 resolution. Due to the + limited number of clock buffers, no other resoltion is supported. + Note that the board does not have a video DAC, so only the MSB bit (7) + of the three colour channels is connected to the VGA connector. + + A test patter can be generated using grmon-1.1.18 or later with: + + draw test_screen 800 16 + +* The DSU uart is connected to the female RS232 connected. + The application UART1 is connected to the male RS232 connector. + +* The JTAG DSU interface is enabled. + +* Output from GRMON info sys is: + + + ethernet startup. + GRLIB build version: 4090 + + initialising .............. + detected frequency: 40 MHz + + Component Vendor + LEON3 SPARC V8 Processor Gaisler Research + AHB Debug UART Gaisler Research + AHB Debug JTAG TAP Gaisler Research + SVGA Controller Gaisler Research + GR Ethernet MAC Gaisler Research + AHB/APB Bridge Gaisler Research + LEON3 Debug Support Unit Gaisler Research + DDR266 Controller Gaisler Research + LEON2 Memory Controller European Space Agency + Generic APB UART Gaisler Research + Multi-processor Interrupt Ctrl Gaisler Research + Modular Timer Unit Gaisler Research + PS/2 interface Gaisler Research + General purpose I/O port Gaisler Research + + Use command 'info sys' to print a detailed report of attached cores + +grlib> inf sys +00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0) + ahb master 0 +01.01:007 Gaisler Research AHB Debug UART (ver 0x0) + ahb master 1 + apb: 80000700 - 80000800 + baud rate 115200, ahb frequency 40.00 +02.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0) + ahb master 2 +03.01:063 Gaisler Research SVGA Controller (ver 0x0) + ahb master 3 + apb: 80000600 - 80000700 + clk0: 40.00 MHz +04.01:01d Gaisler Research GR Ethernet MAC (ver 0x0) + ahb master 4, irq 12 + apb: 80000f00 - 80001000 + edcl ip 192.168.0.51, buffer 2 kbyte +01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) + ahb: 80000000 - 80100000 +02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1) + ahb: 90000000 - a0000000 + AHB trace 256 lines, 32-bit bus, stack pointer 0x43fffff0 + CPU#0 win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1, GRFPU-lite + icache 2 * 4 kbyte, 32 byte/line rnd + dcache 2 * 4 kbyte, 16 byte/line rnd +04.01:025 Gaisler Research DDR266 Controller (ver 0x0) + ahb: 40000000 - 50000000 + ahb: fff00100 - fff00200 + 16-bit DDR : 1 * 64 Mbyte @ 0x40000000 + 100 MHz, col 10, ref 7.8 us, trfc 80 ns +05.04:00f European Space Agency LEON2 Memory Controller (ver 0x1) + ahb: 00000000 - 20000000 + ahb: 20000000 - 40000000 + ahb: 60000000 - 70000000 + apb: 80000000 - 80000100 + 16-bit prom @ 0x00000000 +01.01:00c Gaisler Research Generic APB UART (ver 0x1) + irq 2 + apb: 80000100 - 80000200 + baud rate 38461, DSU mode (FIFO debug) +02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3) + apb: 80000200 - 80000300 +03.01:011 Gaisler Research Modular Timer Unit (ver 0x0) + irq 8 + apb: 80000300 - 80000400 + 8-bit scaler, 2 * 32-bit timers, divisor 40 +05.01:060 Gaisler Research PS/2 interface (ver 0x2) + irq 5 + apb: 80000500 - 80000600 +0b.01:01a Gaisler Research General purpose I/O port (ver 0x0) + apb: 80000b00 - 80000c00 +grlib> + +grlib> flas + + Intel-style 16-bit flash on D[31:16] + + Manuf. Intel + Device MT28F128J3 ) + + Device ID 0418ffff008844d1 + User ID ffffffffffffffff + + + 1 x 16 Mbyte = 16 Mbyte total @ 0x00000000 + + + CFI info + flash family : 1 + flash size : 128 Mbit + erase regions : 1 + erase blocks : 128 + write buffer : 32 bytes + region 0 : 128 blocks of 128 Kbytes + +grlib> + +grlib> lo ~/examples/dhry412 +section: .text at 0x40000000, size 53296 bytes +section: .data at 0x4000d030, size 2764 bytes +total size: 56060 bytes (63.3 Mbit/s) +read 262 symbols +entry point: 0x40000000 +grlib> run +Execution starts, 1000000 runs through Dhrystone +Total execution time: 10.5 s +Microseconds for one run through Dhrystone: 10.5 +Dhrystones per Second: 95073.0 + +Dhrystones MIPS : 54.1 + + +Program exited normally. +grlib> + diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/config.vhd.h b/designs/leon3-APB_LCD-digilent-xc3s1600e/config.vhd.h --- a/designs/leon3-APB_LCD-digilent-xc3s1600e/config.vhd.h +++ b/designs/leon3-APB_LCD-digilent-xc3s1600e/config.vhd.h @@ -1,164 +1,164 @@ --- Technology and synthesis options - constant CFG_FABTECH : integer := CONFIG_SYN_TECH; - constant CFG_MEMTECH : integer := CFG_RAM_TECH; - constant CFG_PADTECH : integer := CFG_PAD_TECH; - constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; - constant CFG_SCAN : integer := CONFIG_SYN_SCAN; - --- Clock generator - constant CFG_CLKTECH : integer := CFG_CLK_TECH; - constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; - constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; - constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; - constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV; - constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV; - constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; - constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; - constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; - --- LEON3 processor core - constant CFG_LEON3 : integer := CONFIG_LEON3; - constant CFG_NCPU : integer := CONFIG_PROC_NUM; - constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; - constant CFG_V8 : integer := CFG_IU_V8; - constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; - constant CFG_BP : integer := CONFIG_IU_BP; - constant CFG_SVT : integer := CONFIG_IU_SVT; - constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; - constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; - constant CFG_NOTAG : integer := CONFIG_NOTAG; - constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; - constant CFG_PWD : integer := CONFIG_PWD*2; - constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST; - constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; - constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; - constant CFG_ISETS : integer := CFG_IU_ISETS; - constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; - constant CFG_ILINE : integer := CFG_ILINE_SZ; - constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; - constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; - constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; - constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; - constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; - constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; - constant CFG_DSETS : integer := CFG_IU_DSETS; - constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; - constant CFG_DLINE : integer := CFG_DLINE_SZ; - constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; - constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; - constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; - constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; - constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; - constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; - constant CFG_MMUEN : integer := CONFIG_MMUEN; - constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; - constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; - constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; - constant CFG_TLB_REP : integer := CONFIG_TLB_REP; - constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; - constant CFG_DSU : integer := CONFIG_DSU_ENABLE; - constant CFG_ITBSZ : integer := CFG_DSU_ITB; - constant CFG_ATBSZ : integer := CFG_DSU_ATB; - constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; - constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; - constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; - constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; - constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; - constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; - constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; - constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; - constant CFG_PCLOW : integer := CFG_DEBUG_PC32; - --- AMBA settings - constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; - constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; - constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; - constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; - constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; - constant CFG_AHB_MON : integer := CONFIG_AHB_MON; - constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; - constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; - constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE; - --- DSU UART - constant CFG_AHB_UART : integer := CONFIG_DSU_UART; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG; - constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; - constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; - constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; - constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; - constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; - constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; - constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; - constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; - constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; - constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; - constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; - constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; - constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; - --- DDR controller - constant CFG_DDRSP : integer := CONFIG_DDRSP; - constant CFG_DDRSP_INIT : integer := CONFIG_DDRSP_INIT; - constant CFG_DDRSP_FREQ : integer := CONFIG_DDRSP_FREQ; - constant CFG_DDRSP_COL : integer := CONFIG_DDRSP_COL; - constant CFG_DDRSP_SIZE : integer := CONFIG_DDRSP_MBYTE; - constant CFG_DDRSP_RSKEW : integer := CONFIG_DDRSP_RSKEW; - --- AHB ROM - constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; - constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; - constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; - constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; - constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; - constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; - constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; - constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; - constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; - --- UART 1 - constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; - constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; - constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; - --- Modular timer - constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; - constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; - constant CFG_GPT_SW : integer := CONFIG_GPT_SW; - constant CFG_GPT_TW : integer := CONFIG_GPT_TW; - constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; - constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; - constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; - constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; - constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; - constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; - --- VGA and PS2/ interface - constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE; - constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE; - constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE; - --- GRLIB debugging - constant CFG_DUART : integer := CONFIG_DEBUG_UART; - +-- Technology and synthesis options + constant CFG_FABTECH : integer := CONFIG_SYN_TECH; + constant CFG_MEMTECH : integer := CFG_RAM_TECH; + constant CFG_PADTECH : integer := CFG_PAD_TECH; + constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; + constant CFG_SCAN : integer := CONFIG_SYN_SCAN; + +-- Clock generator + constant CFG_CLKTECH : integer := CFG_CLK_TECH; + constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; + constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; + constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; + constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV; + constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV; + constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; + constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; + constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; + +-- LEON3 processor core + constant CFG_LEON3 : integer := CONFIG_LEON3; + constant CFG_NCPU : integer := CONFIG_PROC_NUM; + constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; + constant CFG_V8 : integer := CFG_IU_V8; + constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; + constant CFG_BP : integer := CONFIG_IU_BP; + constant CFG_SVT : integer := CONFIG_IU_SVT; + constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; + constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; + constant CFG_NOTAG : integer := CONFIG_NOTAG; + constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; + constant CFG_PWD : integer := CONFIG_PWD*2; + constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST; + constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; + constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; + constant CFG_ISETS : integer := CFG_IU_ISETS; + constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; + constant CFG_ILINE : integer := CFG_ILINE_SZ; + constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; + constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; + constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; + constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; + constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; + constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; + constant CFG_DSETS : integer := CFG_IU_DSETS; + constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; + constant CFG_DLINE : integer := CFG_DLINE_SZ; + constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; + constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; + constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; + constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; + constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; + constant CFG_MMUEN : integer := CONFIG_MMUEN; + constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; + constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; + constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; + constant CFG_TLB_REP : integer := CONFIG_TLB_REP; + constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; + constant CFG_DSU : integer := CONFIG_DSU_ENABLE; + constant CFG_ITBSZ : integer := CFG_DSU_ITB; + constant CFG_ATBSZ : integer := CFG_DSU_ATB; + constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; + constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; + constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; + constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; + constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; + constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; + constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; + constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; + constant CFG_PCLOW : integer := CFG_DEBUG_PC32; + +-- AMBA settings + constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; + constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; + constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; + constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; + constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; + constant CFG_AHB_MON : integer := CONFIG_AHB_MON; + constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; + constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; + constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE; + +-- DSU UART + constant CFG_AHB_UART : integer := CONFIG_DSU_UART; + +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; + +-- Ethernet DSU + constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG; + constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; + constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; + constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; + constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; + constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; + +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; + constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; + constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; + constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; + constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; + constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; + constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; + constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; + constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; + +-- DDR controller + constant CFG_DDRSP : integer := CONFIG_DDRSP; + constant CFG_DDRSP_INIT : integer := CONFIG_DDRSP_INIT; + constant CFG_DDRSP_FREQ : integer := CONFIG_DDRSP_FREQ; + constant CFG_DDRSP_COL : integer := CONFIG_DDRSP_COL; + constant CFG_DDRSP_SIZE : integer := CONFIG_DDRSP_MBYTE; + constant CFG_DDRSP_RSKEW : integer := CONFIG_DDRSP_RSKEW; + +-- AHB ROM + constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; + constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; + constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; + constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; + constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; + +-- AHB RAM + constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; + constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; + constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; + +-- Gaisler Ethernet core + constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; + constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; + constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; + +-- UART 1 + constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; + constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; + +-- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; + constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; + +-- Modular timer + constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; + constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; + constant CFG_GPT_SW : integer := CONFIG_GPT_SW; + constant CFG_GPT_TW : integer := CONFIG_GPT_TW; + constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; + constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; + constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; + constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; + +-- GPIO port + constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; + constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; + constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; + +-- VGA and PS2/ interface + constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE; + constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE; + constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE; + +-- GRLIB debugging + constant CFG_DUART : integer := CONFIG_DEBUG_UART; + diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/modelsim.ini b/designs/leon3-APB_LCD-digilent-xc3s1600e/modelsim.ini --- a/designs/leon3-APB_LCD-digilent-xc3s1600e/modelsim.ini +++ b/designs/leon3-APB_LCD-digilent-xc3s1600e/modelsim.ini @@ -1,227 +1,227 @@ -[Library] -grlib = modelsim/grlib -unisim = modelsim/unisim -dw02 = modelsim/dw02 -synplify = modelsim/synplify -techmap = modelsim/techmap -eth = modelsim/eth -gaisler = modelsim/gaisler -esa = modelsim/esa -fmf = modelsim/fmf -spansion = modelsim/spansion -gsi = modelsim/gsi -lpp = modelsim/lpp -cypress = modelsim/cypress -hynix = modelsim/hynix -micron = modelsim/micron -work = modelsim/work -std = $MODEL_TECH/../std -ieee = $MODEL_TECH/../ieee -vital2000 = $MODEL_TECH/../vital2000 -verilog = $MODEL_TECH/../verilog -arithmetic = $MODEL_TECH/../arithmetic -mgc_portable = $MODEL_TECH/../mgc_portable -std_developerskit = $MODEL_TECH/../std_developerskit -synopsys = $MODEL_TECH/../synopsys - -[vcom] -; Turn on VHDL-1993 as the default. Normally is off. -VHDL93 = 1 - -; Show source line containing error. Default is off. -Show_source = 1 - -; Turn off unbound-component warnings. Default is on. -Show_Warning1 = 0 - -; Turn off process-without-a-wait-statement warnings. Default is on. -; Show_Warning2 = 0 - -; Turn off null-range warnings. Default is on. -; Show_Warning3 = 0 - -; Turn off no-space-in-time-literal warnings. Default is on. -; Show_Warning4 = 0 - -; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. -Show_Warning5 = 0 - -; Turn off optimization for IEEE std_logic_1164 package. Default is on. -; Optimize_1164 = 0 - -; Turn on resolving of ambiguous function overloading in favor of the -; "explicit" function declaration (not the one automatically created by -; the compiler for each type declaration). Default is off. -Explicit = 1 - -; Turn off VITAL compliance checking. Default is checking on. -; NoVitalCheck = 1 - -; Ignore VITAL compliance checking errors. Default is to not ignore. -; IgnoreVitalErrors = 1 - -; Turn off VITAL compliance checking warnings. Default is to show warnings. -; Show_VitalChecksWarnings = false - -; Turn off acceleration of the VITAL packages. Default is to accelerate. -; NoVital = 1 - -; Turn off inclusion of debugging info within design units. Default is to include. -; NoDebug = 1 - -; Turn off "loading..." messages. Default is messages on. -Quiet = 1 - -; Turn on some limited synthesis rule compliance checking. Checks only: -; -- signals used (read) by a process must be in the sensitivity list -; CheckSynthesis = 1 - -[vlog] - -; Turn off inclusion of debugging info within design units. Default is to include. -; NoDebug = 1 - -; Turn off "loading..." messages. Default is messages on. -Quiet = 1 - -; Turn on Verilog hazard checking (order-dependent accessing of global vars). -; Default is off. -; Hazard = 1 - -; Turn on converting regular Verilog identifiers to uppercase. Allows case -; insensitivity for module names. Default is no conversion. -; UpCase = 1 - -[vsim] - -; vopt flow -; Set to turn on automatic optimization of a design. -; Default is off (pre-6.0 flow without vopt). -VoptFlow = 0 - -; Simulator resolution -; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. -Resolution = 1ps - -; User time unit for run commands -; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the -; unit specified for Resolution. For example, if Resolution is 100ps, -; then UserTimeUnit defaults to ps. -UserTimeUnit = ns - -; Default run length -RunLength = 100 - -; Maximum iterations that can be run without advancing simulation time -IterationLimit = 5000 - -; Directive to license manager: -; vhdl Immediately reserve a VHDL license -; vlog Immediately reserve a Verilog license -; plus Immediately reserve a VHDL and Verilog license -; nomgc Do not look for Mentor Graphics Licenses -; nomti Do not look for Model Technology Licenses -; noqueue Do not wait in the license queue when a license isn't available -; License = plus - -; Stop the simulator after an assertion message -; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 - -; Assertion Message Format -; %S - Severity Level -; %R - Report Message -; %T - Time of assertion -; %D - Delta -; %I - Instance or Region pathname (if available) -; %% - print '%' character -; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" - -; Default radix for all windows and commands... -; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned -DefaultRadix = symbolic - -; VSIM Startup command -; Startup = do startup.do - -; File for saving command transcript -TranscriptFile = transcript - -; Specify whether paths in simulator commands should be described -; in VHDL or Verilog format. For VHDL, PathSeparator = / -; for Verilog, PathSeparator = . -PathSeparator = / - -; Disable assertion messages -; IgnoreNote = 1 -; IgnoreWarning = 1 -; IgnoreError = 1 -; IgnoreFailure = 1 - -; Default force kind. May be freeze, drive, or deposit -; or in other terms, fixed, wired or charged. -; DefaultForceKind = freeze - -; If zero, open files when elaborated -; else open files on first read or write -; DelayFileOpen = 0 - -; Control VHDL files opened for write -; 0 = Buffered, 1 = Unbuffered -UnbufferedOutput = 0 - -; This controls the number of characters of a signal name -; shown in the waveform window and the postscript plot. -; The default value or a value of zero tells VSIM to display -; the full name. -; WaveSignalNameWidth = 10 - -; Turn off warnings from the std_logic_arith, std_logic_unsigned -; and std_logic_signed packages. -; StdArithNoWarnings = 1 - -; Turn off warnings from the IEEE numeric_std and numeric_bit -; packages. -; NumericStdNoWarnings = 1 - -; Control the format of a generate statement label. Don't quote it. -; GenerateFormat = %s__%d - -; Specify whether checkpoint files should be compressed. -; The default is to be compressed. -; CheckpointCompressMode = 0 - -; List of dynamically loaded objects for Verilog PLI applications -; Veriuser = veriuser.sl - -[lmc] -; ModelSim's interface to Logic Modeling's SmartModel SWIFT software -libsm = $MODEL_TECH/libsm.sl -; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) -; libsm = $MODEL_TECH/libsm.dll -; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) -; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl -; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) -; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o -; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) -; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Sun4 SunOS) -; do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib -; and run "vsim.swift". -; Logic Modeling's SmartModel SWIFT software (Windows NT) -; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll - -; ModelSim's interface to Logic Modeling's hardware modeler SFI software -libhm = $MODEL_TECH/libhm.sl -; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT) -; libhm = $MODEL_TECH/libhm.dll -; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) -; libsfi = /lib/hp700/libsfi.sl -; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) -; libsfi = /lib/rs6000/libsfi.a -; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) -; libsfi = /lib/sun4.solaris/libsfi.so -; Logic Modeling's hardware modeler SFI software (Sun4 SunOS) -; libsfi = /lib/sun4.sunos/libsfi.so -; Logic Modeling's hardware modeler SFI software (Window NT) -; libsfi = /lib/pcnt/lm_sfi.dll +[Library] +grlib = modelsim/grlib +unisim = modelsim/unisim +dw02 = modelsim/dw02 +synplify = modelsim/synplify +techmap = modelsim/techmap +eth = modelsim/eth +gaisler = modelsim/gaisler +esa = modelsim/esa +fmf = modelsim/fmf +spansion = modelsim/spansion +gsi = modelsim/gsi +lpp = modelsim/lpp +cypress = modelsim/cypress +hynix = modelsim/hynix +micron = modelsim/micron +work = modelsim/work +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +vital2000 = $MODEL_TECH/../vital2000 +verilog = $MODEL_TECH/../verilog +arithmetic = $MODEL_TECH/../arithmetic +mgc_portable = $MODEL_TECH/../mgc_portable +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys + +[vcom] +; Turn on VHDL-1993 as the default. Normally is off. +VHDL93 = 1 + +; Show source line containing error. Default is off. +Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +Explicit = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = false + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off inclusion of debugging info within design units. Default is to include. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. Default is to include. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +[vsim] + +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is off (pre-6.0 flow without vopt). +VoptFlow = 0 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = 1ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +UserTimeUnit = ns + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; License = plus + +; Stop the simulator after an assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. For VHDL, PathSeparator = / +; for Verilog, PathSeparator = . +PathSeparator = / + +; Disable assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, or deposit +; or in other terms, fixed, wired or charged. +; DefaultForceKind = freeze + +; If zero, open files when elaborated +; else open files on first read or write +; DelayFileOpen = 0 + +; Control VHDL files opened for write +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; This controls the number of characters of a signal name +; shown in the waveform window and the postscript plot. +; The default value or a value of zero tells VSIM to display +; the full name. +; WaveSignalNameWidth = 10 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit +; packages. +; NumericStdNoWarnings = 1 + +; Control the format of a generate statement label. Don't quote it. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is to be compressed. +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +[lmc] +; ModelSim's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Sun4 SunOS) +; do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib +; and run "vsim.swift". +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll + +; ModelSim's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Sun4 SunOS) +; libsfi = /lib/sun4.sunos/libsfi.so +; Logic Modeling's hardware modeler SFI software (Window NT) +; libsfi = /lib/pcnt/lm_sfi.dll diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/prom.h b/designs/leon3-APB_LCD-digilent-xc3s1600e/prom.h --- a/designs/leon3-APB_LCD-digilent-xc3s1600e/prom.h +++ b/designs/leon3-APB_LCD-digilent-xc3s1600e/prom.h @@ -1,10 +1,10 @@ -#define MCFG1 0x10380133 -#define MCFG2 0xe6B80e60 -#define MCFG3 0x000ff000 -#define ASDCFG 0xfff00100 -#define DSDCFG 0xe6A06e60 -#define L2MCTRLIO 0x80000000 -#define IRQCTRL 0x80000200 -#define RAMSTART 0x40000000 -#define RAMSIZE 0x00100000 - +#define MCFG1 0x10380133 +#define MCFG2 0xe6B80e60 +#define MCFG3 0x000ff000 +#define ASDCFG 0xfff00100 +#define DSDCFG 0xe6A06e60 +#define L2MCTRLIO 0x80000000 +#define IRQCTRL 0x80000200 +#define RAMSTART 0x40000000 +#define RAMSIZE 0x00100000 + diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/systest.c b/designs/leon3-APB_LCD-digilent-xc3s1600e/systest.c --- a/designs/leon3-APB_LCD-digilent-xc3s1600e/systest.c +++ b/designs/leon3-APB_LCD-digilent-xc3s1600e/systest.c @@ -1,10 +1,10 @@ - -main() - -{ - report_start(); - - base_test(); - - report_end(); -} + +main() + +{ + report_start(); + + base_test(); + + report_end(); +} diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/tkconfig.h b/designs/leon3-APB_LCD-digilent-xc3s1600e/tkconfig.h --- a/designs/leon3-APB_LCD-digilent-xc3s1600e/tkconfig.h +++ b/designs/leon3-APB_LCD-digilent-xc3s1600e/tkconfig.h @@ -1,949 +1,949 @@ -#if defined CONFIG_SYN_INFERRED -#define CONFIG_SYN_TECH inferred -#elif defined CONFIG_SYN_UMC -#define CONFIG_SYN_TECH umc -#elif defined CONFIG_SYN_RHUMC -#define CONFIG_SYN_TECH rhumc -#elif defined CONFIG_SYN_ATC18 -#define CONFIG_SYN_TECH atc18s -#elif defined CONFIG_SYN_ATC18RHA -#define CONFIG_SYN_TECH atc18rha -#elif defined CONFIG_SYN_AXCEL -#define CONFIG_SYN_TECH axcel -#elif defined CONFIG_SYN_AXDSP -#define CONFIG_SYN_TECH axdsp -#elif defined CONFIG_SYN_PROASICPLUS -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_ALTERA -#define CONFIG_SYN_TECH altera -#elif defined CONFIG_SYN_STRATIX -#define CONFIG_SYN_TECH stratix1 -#elif defined CONFIG_SYN_STRATIXII -#define CONFIG_SYN_TECH stratix2 -#elif defined CONFIG_SYN_STRATIXIII -#define CONFIG_SYN_TECH stratix3 -#elif defined CONFIG_SYN_CYCLONEIII -#define CONFIG_SYN_TECH cyclone3 -#elif defined CONFIG_SYN_EASIC90 -#define CONFIG_SYN_TECH easic90 -#elif defined CONFIG_SYN_IHP25 -#define CONFIG_SYN_TECH ihp25 -#elif defined CONFIG_SYN_IHP25RH -#define CONFIG_SYN_TECH ihp25rh -#elif defined CONFIG_SYN_CMOS9SF -#define CONFIG_SYN_TECH cmos9sf -#elif defined CONFIG_SYN_LATTICE -#define CONFIG_SYN_TECH lattice -#elif defined CONFIG_SYN_ECLIPSE -#define CONFIG_SYN_TECH eclipse -#elif defined CONFIG_SYN_PEREGRINE -#define CONFIG_SYN_TECH peregrine -#elif defined CONFIG_SYN_PROASIC -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_PROASIC3 -#define CONFIG_SYN_TECH apa3 -#elif defined CONFIG_SYN_PROASIC3E -#define CONFIG_SYN_TECH apa3e -#elif defined CONFIG_SYN_PROASIC3L -#define CONFIG_SYN_TECH apa3l -#elif defined CONFIG_SYN_IGLOO -#define CONFIG_SYN_TECH apa3 -#elif defined CONFIG_SYN_FUSION -#define CONFIG_SYN_TECH actfus -#elif defined CONFIG_SYN_SPARTAN2 -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEX -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEXE -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_SPARTAN3 -#define CONFIG_SYN_TECH spartan3 -#elif defined CONFIG_SYN_SPARTAN3E -#define CONFIG_SYN_TECH spartan3e -#elif defined CONFIG_SYN_SPARTAN6 -#define CONFIG_SYN_TECH spartan6 -#elif defined CONFIG_SYN_VIRTEX2 -#define CONFIG_SYN_TECH virtex2 -#elif defined CONFIG_SYN_VIRTEX4 -#define CONFIG_SYN_TECH virtex4 -#elif defined CONFIG_SYN_VIRTEX5 -#define CONFIG_SYN_TECH virtex5 -#elif defined CONFIG_SYN_VIRTEX6 -#define CONFIG_SYN_TECH virtex6 -#elif defined CONFIG_SYN_RH_LIB18T -#define CONFIG_SYN_TECH rhlib18t -#elif defined CONFIG_SYN_SMIC13 -#define CONFIG_SYN_TECH smic013 -#elif defined CONFIG_SYN_UT025CRH -#define CONFIG_SYN_TECH ut25 -#elif defined CONFIG_SYN_TSMC90 -#define CONFIG_SYN_TECH tsmc90 -#elif defined CONFIG_SYN_TM65GPLUS -#define CONFIG_SYN_TECH tm65gpl -#elif defined CONFIG_SYN_CUSTOM1 -#define CONFIG_SYN_TECH custom1 -#else -#error "unknown target technology" -#endif - -#if defined CONFIG_SYN_INFER_RAM -#define CFG_RAM_TECH inferred -#elif defined CONFIG_MEM_UMC -#define CFG_RAM_TECH umc -#elif defined CONFIG_MEM_RHUMC -#define CFG_RAM_TECH rhumc -#elif defined CONFIG_MEM_VIRAGE -#define CFG_RAM_TECH memvirage -#elif defined CONFIG_MEM_ARTISAN -#define CFG_RAM_TECH memartisan -#elif defined CONFIG_MEM_CUSTOM1 -#define CFG_RAM_TECH custom1 -#elif defined CONFIG_MEM_VIRAGE90 -#define CFG_RAM_TECH memvirage90 -#elif defined CONFIG_MEM_INFERRED -#define CFG_RAM_TECH inferred -#else -#define CFG_RAM_TECH CONFIG_SYN_TECH -#endif - -#if defined CONFIG_SYN_INFER_PADS -#define CFG_PAD_TECH inferred -#else -#define CFG_PAD_TECH CONFIG_SYN_TECH -#endif - -#ifndef CONFIG_SYN_NO_ASYNC -#define CONFIG_SYN_NO_ASYNC 0 -#endif - -#ifndef CONFIG_SYN_SCAN -#define CONFIG_SYN_SCAN 0 -#endif - - -#if defined CONFIG_CLK_ALTDLL -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_HCLKBUF -#define CFG_CLK_TECH axcel -#elif defined CONFIG_CLK_LATDLL -#define CFG_CLK_TECH lattice -#elif defined CONFIG_CLK_PRO3PLL -#define CFG_CLK_TECH apa3 -#elif defined CONFIG_CLK_PRO3EPLL -#define CFG_CLK_TECH apa3e -#elif defined CONFIG_CLK_PRO3LPLL -#define CFG_CLK_TECH apa3l -#elif defined CONFIG_CLK_FUSPLL -#define CFG_CLK_TECH actfus -#elif defined CONFIG_CLK_CLKDLL -#define CFG_CLK_TECH virtex -#elif defined CONFIG_CLK_DCM -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_LIB18T -#define CFG_CLK_TECH rhlib18t -#elif defined CONFIG_CLK_RHUMC -#define CFG_CLK_TECH rhumc -#else -#define CFG_CLK_TECH inferred -#endif - -#ifndef CONFIG_CLK_MUL -#define CONFIG_CLK_MUL 2 -#endif - -#ifndef CONFIG_CLK_DIV -#define CONFIG_CLK_DIV 2 -#endif - -#ifndef CONFIG_OCLK_DIV -#define CONFIG_OCLK_DIV 1 -#endif - -#ifndef CONFIG_OCLKB_DIV -#define CONFIG_OCLKB_DIV 0 -#endif - -#ifndef CONFIG_OCLKC_DIV -#define CONFIG_OCLKC_DIV 0 -#endif - -#ifndef CONFIG_PCI_CLKDLL -#define CONFIG_PCI_CLKDLL 0 -#endif - -#ifndef CONFIG_PCI_SYSCLK -#define CONFIG_PCI_SYSCLK 0 -#endif - -#ifndef CONFIG_CLK_NOFB -#define CONFIG_CLK_NOFB 0 -#endif -#ifndef CONFIG_LEON3 -#define CONFIG_LEON3 0 -#endif - -#ifndef CONFIG_PROC_NUM -#define CONFIG_PROC_NUM 1 -#endif - -#ifndef CONFIG_IU_NWINDOWS -#define CONFIG_IU_NWINDOWS 8 -#endif - -#ifndef CONFIG_IU_RSTADDR -#define CONFIG_IU_RSTADDR 8 -#endif - -#ifndef CONFIG_IU_LDELAY -#define CONFIG_IU_LDELAY 1 -#endif - -#ifndef CONFIG_IU_WATCHPOINTS -#define CONFIG_IU_WATCHPOINTS 0 -#endif - -#ifdef CONFIG_IU_V8MULDIV -#ifdef CONFIG_IU_MUL_LATENCY_4 -#define CFG_IU_V8 1 -#elif defined CONFIG_IU_MUL_LATENCY_5 -#define CFG_IU_V8 2 -#elif defined CONFIG_IU_MUL_LATENCY_2 -#define CFG_IU_V8 16#32# -#endif -#else -#define CFG_IU_V8 0 -#endif - -#ifndef CONFIG_PWD -#define CONFIG_PWD 0 -#endif - -#ifndef CONFIG_IU_MUL_MAC -#define CONFIG_IU_MUL_MAC 0 -#endif - -#ifndef CONFIG_IU_BP -#define CONFIG_IU_BP 0 -#endif - -#ifndef CONFIG_NOTAG -#define CONFIG_NOTAG 0 -#endif - -#ifndef CONFIG_IU_SVT -#define CONFIG_IU_SVT 0 -#endif - -#if defined CONFIG_FPU_GRFPC1 -#define CONFIG_FPU_GRFPC 1 -#elif defined CONFIG_FPU_GRFPC2 -#define CONFIG_FPU_GRFPC 2 -#else -#define CONFIG_FPU_GRFPC 0 -#endif - -#if defined CONFIG_FPU_GRFPU_INFMUL -#define CONFIG_FPU_GRFPU_MUL 0 -#elif defined CONFIG_FPU_GRFPU_DWMUL -#define CONFIG_FPU_GRFPU_MUL 1 -#elif defined CONFIG_FPU_GRFPU_MODGEN -#define CONFIG_FPU_GRFPU_MUL 2 -#elif defined CONFIG_FPU_GRFPU_TECHSPEC -#define CONFIG_FPU_GRFPU_MUL 3 -#else -#define CONFIG_FPU_GRFPU_MUL 0 -#endif - -#if defined CONFIG_FPU_GRFPU_SH -#define CONFIG_FPU_GRFPU_SHARED 1 -#else -#define CONFIG_FPU_GRFPU_SHARED 0 -#endif - -#if defined CONFIG_FPU_GRFPU -#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) -#elif defined CONFIG_FPU_MEIKO -#define CONFIG_FPU 15 -#elif defined CONFIG_FPU_GRFPULITE -#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) -#else -#define CONFIG_FPU 0 -#endif - -#ifndef CONFIG_FPU_NETLIST -#define CONFIG_FPU_NETLIST 0 -#endif - -#ifndef CONFIG_ICACHE_ENABLE -#define CONFIG_ICACHE_ENABLE 0 -#endif - -#if defined CONFIG_ICACHE_ASSO1 -#define CFG_IU_ISETS 1 -#elif defined CONFIG_ICACHE_ASSO2 -#define CFG_IU_ISETS 2 -#elif defined CONFIG_ICACHE_ASSO3 -#define CFG_IU_ISETS 3 -#elif defined CONFIG_ICACHE_ASSO4 -#define CFG_IU_ISETS 4 -#else -#define CFG_IU_ISETS 1 -#endif - -#if defined CONFIG_ICACHE_SZ1 -#define CFG_ICACHE_SZ 1 -#elif defined CONFIG_ICACHE_SZ2 -#define CFG_ICACHE_SZ 2 -#elif defined CONFIG_ICACHE_SZ4 -#define CFG_ICACHE_SZ 4 -#elif defined CONFIG_ICACHE_SZ8 -#define CFG_ICACHE_SZ 8 -#elif defined CONFIG_ICACHE_SZ16 -#define CFG_ICACHE_SZ 16 -#elif defined CONFIG_ICACHE_SZ32 -#define CFG_ICACHE_SZ 32 -#elif defined CONFIG_ICACHE_SZ64 -#define CFG_ICACHE_SZ 64 -#elif defined CONFIG_ICACHE_SZ128 -#define CFG_ICACHE_SZ 128 -#elif defined CONFIG_ICACHE_SZ256 -#define CFG_ICACHE_SZ 256 -#else -#define CFG_ICACHE_SZ 1 -#endif - -#ifdef CONFIG_ICACHE_LZ16 -#define CFG_ILINE_SZ 4 -#else -#define CFG_ILINE_SZ 8 -#endif - -#if defined CONFIG_ICACHE_ALGORND -#define CFG_ICACHE_ALGORND 2 -#elif defined CONFIG_ICACHE_ALGOLRR -#define CFG_ICACHE_ALGORND 1 -#else -#define CFG_ICACHE_ALGORND 0 -#endif - -#ifndef CONFIG_ICACHE_LOCK -#define CONFIG_ICACHE_LOCK 0 -#endif - -#ifndef CONFIG_ICACHE_LRAM -#define CONFIG_ICACHE_LRAM 0 -#endif - -#ifndef CONFIG_ICACHE_LRSTART -#define CONFIG_ICACHE_LRSTART 8E -#endif - -#if defined CONFIG_ICACHE_LRAM_SZ2 -#define CFG_ILRAM_SIZE 2 -#elif defined CONFIG_ICACHE_LRAM_SZ4 -#define CFG_ILRAM_SIZE 4 -#elif defined CONFIG_ICACHE_LRAM_SZ8 -#define CFG_ILRAM_SIZE 8 -#elif defined CONFIG_ICACHE_LRAM_SZ16 -#define CFG_ILRAM_SIZE 16 -#elif defined CONFIG_ICACHE_LRAM_SZ32 -#define CFG_ILRAM_SIZE 32 -#elif defined CONFIG_ICACHE_LRAM_SZ64 -#define CFG_ILRAM_SIZE 64 -#elif defined CONFIG_ICACHE_LRAM_SZ128 -#define CFG_ILRAM_SIZE 128 -#elif defined CONFIG_ICACHE_LRAM_SZ256 -#define CFG_ILRAM_SIZE 256 -#else -#define CFG_ILRAM_SIZE 1 -#endif - - -#ifndef CONFIG_DCACHE_ENABLE -#define CONFIG_DCACHE_ENABLE 0 -#endif - -#if defined CONFIG_DCACHE_ASSO1 -#define CFG_IU_DSETS 1 -#elif defined CONFIG_DCACHE_ASSO2 -#define CFG_IU_DSETS 2 -#elif defined CONFIG_DCACHE_ASSO3 -#define CFG_IU_DSETS 3 -#elif defined CONFIG_DCACHE_ASSO4 -#define CFG_IU_DSETS 4 -#else -#define CFG_IU_DSETS 1 -#endif - -#if defined CONFIG_DCACHE_SZ1 -#define CFG_DCACHE_SZ 1 -#elif defined CONFIG_DCACHE_SZ2 -#define CFG_DCACHE_SZ 2 -#elif defined CONFIG_DCACHE_SZ4 -#define CFG_DCACHE_SZ 4 -#elif defined CONFIG_DCACHE_SZ8 -#define CFG_DCACHE_SZ 8 -#elif defined CONFIG_DCACHE_SZ16 -#define CFG_DCACHE_SZ 16 -#elif defined CONFIG_DCACHE_SZ32 -#define CFG_DCACHE_SZ 32 -#elif defined CONFIG_DCACHE_SZ64 -#define CFG_DCACHE_SZ 64 -#elif defined CONFIG_DCACHE_SZ128 -#define CFG_DCACHE_SZ 128 -#elif defined CONFIG_DCACHE_SZ256 -#define CFG_DCACHE_SZ 256 -#else -#define CFG_DCACHE_SZ 1 -#endif - -#ifdef CONFIG_DCACHE_LZ16 -#define CFG_DLINE_SZ 4 -#else -#define CFG_DLINE_SZ 8 -#endif - -#if defined CONFIG_DCACHE_ALGORND -#define CFG_DCACHE_ALGORND 2 -#elif defined CONFIG_DCACHE_ALGOLRR -#define CFG_DCACHE_ALGORND 1 -#else -#define CFG_DCACHE_ALGORND 0 -#endif - -#ifndef CONFIG_DCACHE_LOCK -#define CONFIG_DCACHE_LOCK 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP -#define CONFIG_DCACHE_SNOOP 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_SEPTAG -#define CONFIG_DCACHE_SNOOP_SEPTAG 0 -#endif - -#ifndef CONFIG_CACHE_FIXED -#define CONFIG_CACHE_FIXED 0 -#endif - -#ifndef CONFIG_DCACHE_LRAM -#define CONFIG_DCACHE_LRAM 0 -#endif - -#ifndef CONFIG_DCACHE_LRSTART -#define CONFIG_DCACHE_LRSTART 8F -#endif - -#if defined CONFIG_DCACHE_LRAM_SZ2 -#define CFG_DLRAM_SIZE 2 -#elif defined CONFIG_DCACHE_LRAM_SZ4 -#define CFG_DLRAM_SIZE 4 -#elif defined CONFIG_DCACHE_LRAM_SZ8 -#define CFG_DLRAM_SIZE 8 -#elif defined CONFIG_DCACHE_LRAM_SZ16 -#define CFG_DLRAM_SIZE 16 -#elif defined CONFIG_DCACHE_LRAM_SZ32 -#define CFG_DLRAM_SIZE 32 -#elif defined CONFIG_DCACHE_LRAM_SZ64 -#define CFG_DLRAM_SIZE 64 -#elif defined CONFIG_DCACHE_LRAM_SZ128 -#define CFG_DLRAM_SIZE 128 -#elif defined CONFIG_DCACHE_LRAM_SZ256 -#define CFG_DLRAM_SIZE 256 -#else -#define CFG_DLRAM_SIZE 1 -#endif - -#if defined CONFIG_MMU_PAGE_4K -#define CONFIG_MMU_PAGE 0 -#elif defined CONFIG_MMU_PAGE_8K -#define CONFIG_MMU_PAGE 1 -#elif defined CONFIG_MMU_PAGE_16K -#define CONFIG_MMU_PAGE 2 -#elif defined CONFIG_MMU_PAGE_32K -#define CONFIG_MMU_PAGE 3 -#elif defined CONFIG_MMU_PAGE_PROG -#define CONFIG_MMU_PAGE 4 -#else -#define CONFIG_MMU_PAGE 0 -#endif - -#ifdef CONFIG_MMU_ENABLE -#define CONFIG_MMUEN 1 - -#ifdef CONFIG_MMU_SPLIT -#define CONFIG_TLB_TYPE 0 -#endif -#ifdef CONFIG_MMU_COMBINED -#define CONFIG_TLB_TYPE 1 -#endif - -#ifdef CONFIG_MMU_REPARRAY -#define CONFIG_TLB_REP 0 -#endif -#ifdef CONFIG_MMU_REPINCREMENT -#define CONFIG_TLB_REP 1 -#endif - -#ifdef CONFIG_MMU_I2 -#define CONFIG_ITLBNUM 2 -#endif -#ifdef CONFIG_MMU_I4 -#define CONFIG_ITLBNUM 4 -#endif -#ifdef CONFIG_MMU_I8 -#define CONFIG_ITLBNUM 8 -#endif -#ifdef CONFIG_MMU_I16 -#define CONFIG_ITLBNUM 16 -#endif -#ifdef CONFIG_MMU_I32 -#define CONFIG_ITLBNUM 32 -#endif - -#define CONFIG_DTLBNUM 2 -#ifdef CONFIG_MMU_D2 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 2 -#endif -#ifdef CONFIG_MMU_D4 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 4 -#endif -#ifdef CONFIG_MMU_D8 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 8 -#endif -#ifdef CONFIG_MMU_D16 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 16 -#endif -#ifdef CONFIG_MMU_D32 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 32 -#endif -#ifdef CONFIG_MMU_FASTWB -#define CFG_MMU_FASTWB 1 -#else -#define CFG_MMU_FASTWB 0 -#endif - -#else -#define CONFIG_MMUEN 0 -#define CONFIG_ITLBNUM 2 -#define CONFIG_DTLBNUM 2 -#define CONFIG_TLB_TYPE 1 -#define CONFIG_TLB_REP 1 -#define CFG_MMU_FASTWB 0 -#endif - -#ifndef CONFIG_DSU_ENABLE -#define CONFIG_DSU_ENABLE 0 -#endif - -#if defined CONFIG_DSU_ITRACESZ1 -#define CFG_DSU_ITB 1 -#elif CONFIG_DSU_ITRACESZ2 -#define CFG_DSU_ITB 2 -#elif CONFIG_DSU_ITRACESZ4 -#define CFG_DSU_ITB 4 -#elif CONFIG_DSU_ITRACESZ8 -#define CFG_DSU_ITB 8 -#elif CONFIG_DSU_ITRACESZ16 -#define CFG_DSU_ITB 16 -#else -#define CFG_DSU_ITB 0 -#endif - -#if defined CONFIG_DSU_ATRACESZ1 -#define CFG_DSU_ATB 1 -#elif CONFIG_DSU_ATRACESZ2 -#define CFG_DSU_ATB 2 -#elif CONFIG_DSU_ATRACESZ4 -#define CFG_DSU_ATB 4 -#elif CONFIG_DSU_ATRACESZ8 -#define CFG_DSU_ATB 8 -#elif CONFIG_DSU_ATRACESZ16 -#define CFG_DSU_ATB 16 -#else -#define CFG_DSU_ATB 0 -#endif - -#ifndef CONFIG_LEON3FT_EN -#define CONFIG_LEON3FT_EN 0 -#endif - -#if defined CONFIG_IUFT_PAR -#define CONFIG_IUFT_EN 1 -#elif defined CONFIG_IUFT_DMR -#define CONFIG_IUFT_EN 2 -#elif defined CONFIG_IUFT_BCH -#define CONFIG_IUFT_EN 3 -#elif defined CONFIG_IUFT_TMR -#define CONFIG_IUFT_EN 4 -#else -#define CONFIG_IUFT_EN 0 -#endif -#ifndef CONFIG_RF_ERRINJ -#define CONFIG_RF_ERRINJ 0 -#endif - -#ifndef CONFIG_FPUFT_EN -#define CONFIG_FPUFT 0 -#else -#ifdef CONFIG_FPU_GRFPU -#define CONFIG_FPUFT 2 -#else -#define CONFIG_FPUFT 1 -#endif -#endif - -#ifndef CONFIG_CACHE_FT_EN -#define CONFIG_CACHE_FT_EN 0 -#endif -#ifndef CONFIG_CACHE_ERRINJ -#define CONFIG_CACHE_ERRINJ 0 -#endif - -#ifndef CONFIG_LEON3_NETLIST -#define CONFIG_LEON3_NETLIST 0 -#endif - -#ifdef CONFIG_DEBUG_PC32 -#define CFG_DEBUG_PC32 0 -#else -#define CFG_DEBUG_PC32 2 -#endif -#ifndef CONFIG_IU_DISAS -#define CONFIG_IU_DISAS 0 -#endif -#ifndef CONFIG_IU_DISAS_NET -#define CONFIG_IU_DISAS_NET 0 -#endif - - -#ifndef CONFIG_AHB_SPLIT -#define CONFIG_AHB_SPLIT 0 -#endif - -#ifndef CONFIG_AHB_RROBIN -#define CONFIG_AHB_RROBIN 0 -#endif - -#ifndef CONFIG_AHB_IOADDR -#define CONFIG_AHB_IOADDR FFF -#endif - -#ifndef CONFIG_APB_HADDR -#define CONFIG_APB_HADDR 800 -#endif - -#ifndef CONFIG_AHB_MON -#define CONFIG_AHB_MON 0 -#endif - -#ifndef CONFIG_AHB_MONERR -#define CONFIG_AHB_MONERR 0 -#endif - -#ifndef CONFIG_AHB_MONWAR -#define CONFIG_AHB_MONWAR 0 -#endif - -#ifndef CONFIG_AHB_DTRACE -#define CONFIG_AHB_DTRACE 0 -#endif - -#ifndef CONFIG_DSU_UART -#define CONFIG_DSU_UART 0 -#endif - - -#ifndef CONFIG_DSU_JTAG -#define CONFIG_DSU_JTAG 0 -#endif - -#ifndef CONFIG_DSU_ETH -#define CONFIG_DSU_ETH 0 -#endif - -#ifndef CONFIG_DSU_IPMSB -#define CONFIG_DSU_IPMSB C0A8 -#endif - -#ifndef CONFIG_DSU_IPLSB -#define CONFIG_DSU_IPLSB 0033 -#endif - -#ifndef CONFIG_DSU_ETHMSB -#define CONFIG_DSU_ETHMSB 020000 -#endif - -#ifndef CONFIG_DSU_ETHLSB -#define CONFIG_DSU_ETHLSB 000009 -#endif - -#if defined CONFIG_DSU_ETHSZ1 -#define CFG_DSU_ETHB 1 -#elif CONFIG_DSU_ETHSZ2 -#define CFG_DSU_ETHB 2 -#elif CONFIG_DSU_ETHSZ4 -#define CFG_DSU_ETHB 4 -#elif CONFIG_DSU_ETHSZ8 -#define CFG_DSU_ETHB 8 -#elif CONFIG_DSU_ETHSZ16 -#define CFG_DSU_ETHB 16 -#elif CONFIG_DSU_ETHSZ32 -#define CFG_DSU_ETHB 32 -#else -#define CFG_DSU_ETHB 1 -#endif - -#ifndef CONFIG_DSU_ETH_PROG -#define CONFIG_DSU_ETH_PROG 0 -#endif - -#ifndef CONFIG_MCTRL_LEON2 -#define CONFIG_MCTRL_LEON2 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM -#define CONFIG_MCTRL_SDRAM 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_SEPBUS -#define CONFIG_MCTRL_SDRAM_SEPBUS 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_INVCLK -#define CONFIG_MCTRL_SDRAM_INVCLK 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_BUS64 -#define CONFIG_MCTRL_SDRAM_BUS64 0 -#endif - -#ifndef CONFIG_MCTRL_8BIT -#define CONFIG_MCTRL_8BIT 0 -#endif - -#ifndef CONFIG_MCTRL_16BIT -#define CONFIG_MCTRL_16BIT 0 -#endif - -#ifndef CONFIG_MCTRL_5CS -#define CONFIG_MCTRL_5CS 0 -#endif - -#ifndef CONFIG_MCTRL_EDAC -#define CONFIG_MCTRL_EDAC 0 -#endif - -#ifndef CONFIG_MCTRL_PAGE -#define CONFIG_MCTRL_PAGE 0 -#endif - -#ifndef CONFIG_MCTRL_PROGPAGE -#define CONFIG_MCTRL_PROGPAGE 0 -#endif - -#ifndef CONFIG_DDRSP -#define CONFIG_DDRSP 0 -#endif - -#ifndef CONFIG_DDRSP_INIT -#define CONFIG_DDRSP_INIT 0 -#endif - -#ifndef CONFIG_DDRSP_FREQ -#define CONFIG_DDRSP_FREQ 100 -#endif - -#ifndef CONFIG_DDRSP_COL -#define CONFIG_DDRSP_COL 9 -#endif - -#ifndef CONFIG_DDRSP_MBYTE -#define CONFIG_DDRSP_MBYTE 8 -#endif - -#ifndef CONFIG_DDRSP_RSKEW -#define CONFIG_DDRSP_RSKEW 0 -#endif -#ifndef CONFIG_AHBROM_ENABLE -#define CONFIG_AHBROM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBROM_START -#define CONFIG_AHBROM_START 000 -#endif - -#ifndef CONFIG_AHBROM_PIPE -#define CONFIG_AHBROM_PIPE 0 -#endif - -#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) -#define CONFIG_ROM_START 100 -#else -#define CONFIG_ROM_START 000 -#endif - - -#ifndef CONFIG_AHBRAM_ENABLE -#define CONFIG_AHBRAM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBRAM_START -#define CONFIG_AHBRAM_START A00 -#endif - -#if defined CONFIG_AHBRAM_SZ1 -#define CFG_AHBRAMSZ 1 -#elif CONFIG_AHBRAM_SZ2 -#define CFG_AHBRAMSZ 2 -#elif CONFIG_AHBRAM_SZ4 -#define CFG_AHBRAMSZ 4 -#elif CONFIG_AHBRAM_SZ8 -#define CFG_AHBRAMSZ 8 -#elif CONFIG_AHBRAM_SZ16 -#define CFG_AHBRAMSZ 16 -#elif CONFIG_AHBRAM_SZ32 -#define CFG_AHBRAMSZ 32 -#elif CONFIG_AHBRAM_SZ64 -#define CFG_AHBRAMSZ 64 -#else -#define CFG_AHBRAMSZ 1 -#endif - -#ifndef CONFIG_GRETH_ENABLE -#define CONFIG_GRETH_ENABLE 0 -#endif - -#ifndef CONFIG_GRETH_GIGA -#define CONFIG_GRETH_GIGA 0 -#endif - -#if defined CONFIG_GRETH_FIFO4 -#define CFG_GRETH_FIFO 4 -#elif defined CONFIG_GRETH_FIFO8 -#define CFG_GRETH_FIFO 8 -#elif defined CONFIG_GRETH_FIFO16 -#define CFG_GRETH_FIFO 16 -#elif defined CONFIG_GRETH_FIFO32 -#define CFG_GRETH_FIFO 32 -#elif defined CONFIG_GRETH_FIFO64 -#define CFG_GRETH_FIFO 64 -#else -#define CFG_GRETH_FIFO 8 -#endif - -#ifndef CONFIG_UART1_ENABLE -#define CONFIG_UART1_ENABLE 0 -#endif - -#if defined CONFIG_UA1_FIFO1 -#define CFG_UA1_FIFO 1 -#elif defined CONFIG_UA1_FIFO2 -#define CFG_UA1_FIFO 2 -#elif defined CONFIG_UA1_FIFO4 -#define CFG_UA1_FIFO 4 -#elif defined CONFIG_UA1_FIFO8 -#define CFG_UA1_FIFO 8 -#elif defined CONFIG_UA1_FIFO16 -#define CFG_UA1_FIFO 16 -#elif defined CONFIG_UA1_FIFO32 -#define CFG_UA1_FIFO 32 -#else -#define CFG_UA1_FIFO 1 -#endif - -#ifndef CONFIG_IRQ3_ENABLE -#define CONFIG_IRQ3_ENABLE 0 -#endif -#ifndef CONFIG_IRQ3_NSEC -#define CONFIG_IRQ3_NSEC 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif - -#ifndef CONFIG_GPT_WDOGEN -#define CONFIG_GPT_WDOGEN 0 -#endif - -#ifndef CONFIG_GPT_WDOG -#define CONFIG_GPT_WDOG 0 -#endif - -#ifndef CONFIG_GRGPIO_ENABLE -#define CONFIG_GRGPIO_ENABLE 0 -#endif -#ifndef CONFIG_GRGPIO_IMASK -#define CONFIG_GRGPIO_IMASK 0000 -#endif -#ifndef CONFIG_GRGPIO_WIDTH -#define CONFIG_GRGPIO_WIDTH 1 -#endif - -#ifndef CONFIG_VGA_ENABLE -#define CONFIG_VGA_ENABLE 0 -#endif -#ifndef CONFIG_SVGA_ENABLE -#define CONFIG_SVGA_ENABLE 0 -#endif -#ifndef CONFIG_KBD_ENABLE -#define CONFIG_KBD_ENABLE 0 -#endif - - -#ifndef CONFIG_DEBUG_UART -#define CONFIG_DEBUG_UART 0 -#endif +#if defined CONFIG_SYN_INFERRED +#define CONFIG_SYN_TECH inferred +#elif defined CONFIG_SYN_UMC +#define CONFIG_SYN_TECH umc +#elif defined CONFIG_SYN_RHUMC +#define CONFIG_SYN_TECH rhumc +#elif defined CONFIG_SYN_ATC18 +#define CONFIG_SYN_TECH atc18s +#elif defined CONFIG_SYN_ATC18RHA +#define CONFIG_SYN_TECH atc18rha +#elif defined CONFIG_SYN_AXCEL +#define CONFIG_SYN_TECH axcel +#elif defined CONFIG_SYN_AXDSP +#define CONFIG_SYN_TECH axdsp +#elif defined CONFIG_SYN_PROASICPLUS +#define CONFIG_SYN_TECH proasic +#elif defined CONFIG_SYN_ALTERA +#define CONFIG_SYN_TECH altera +#elif defined CONFIG_SYN_STRATIX +#define CONFIG_SYN_TECH stratix1 +#elif defined CONFIG_SYN_STRATIXII +#define CONFIG_SYN_TECH stratix2 +#elif defined CONFIG_SYN_STRATIXIII +#define CONFIG_SYN_TECH stratix3 +#elif defined CONFIG_SYN_CYCLONEIII +#define CONFIG_SYN_TECH cyclone3 +#elif defined CONFIG_SYN_EASIC90 +#define CONFIG_SYN_TECH easic90 +#elif defined CONFIG_SYN_IHP25 +#define CONFIG_SYN_TECH ihp25 +#elif defined CONFIG_SYN_IHP25RH +#define CONFIG_SYN_TECH ihp25rh +#elif defined CONFIG_SYN_CMOS9SF +#define CONFIG_SYN_TECH cmos9sf +#elif defined CONFIG_SYN_LATTICE +#define CONFIG_SYN_TECH lattice +#elif defined CONFIG_SYN_ECLIPSE +#define CONFIG_SYN_TECH eclipse +#elif defined CONFIG_SYN_PEREGRINE +#define CONFIG_SYN_TECH peregrine +#elif defined CONFIG_SYN_PROASIC +#define CONFIG_SYN_TECH proasic +#elif defined CONFIG_SYN_PROASIC3 +#define CONFIG_SYN_TECH apa3 +#elif defined CONFIG_SYN_PROASIC3E +#define CONFIG_SYN_TECH apa3e +#elif defined CONFIG_SYN_PROASIC3L +#define CONFIG_SYN_TECH apa3l +#elif defined CONFIG_SYN_IGLOO +#define CONFIG_SYN_TECH apa3 +#elif defined CONFIG_SYN_FUSION +#define CONFIG_SYN_TECH actfus +#elif defined CONFIG_SYN_SPARTAN2 +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_VIRTEX +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_VIRTEXE +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_SPARTAN3 +#define CONFIG_SYN_TECH spartan3 +#elif defined CONFIG_SYN_SPARTAN3E +#define CONFIG_SYN_TECH spartan3e +#elif defined CONFIG_SYN_SPARTAN6 +#define CONFIG_SYN_TECH spartan6 +#elif defined CONFIG_SYN_VIRTEX2 +#define CONFIG_SYN_TECH virtex2 +#elif defined CONFIG_SYN_VIRTEX4 +#define CONFIG_SYN_TECH virtex4 +#elif defined CONFIG_SYN_VIRTEX5 +#define CONFIG_SYN_TECH virtex5 +#elif defined CONFIG_SYN_VIRTEX6 +#define CONFIG_SYN_TECH virtex6 +#elif defined CONFIG_SYN_RH_LIB18T +#define CONFIG_SYN_TECH rhlib18t +#elif defined CONFIG_SYN_SMIC13 +#define CONFIG_SYN_TECH smic013 +#elif defined CONFIG_SYN_UT025CRH +#define CONFIG_SYN_TECH ut25 +#elif defined CONFIG_SYN_TSMC90 +#define CONFIG_SYN_TECH tsmc90 +#elif defined CONFIG_SYN_TM65GPLUS +#define CONFIG_SYN_TECH tm65gpl +#elif defined CONFIG_SYN_CUSTOM1 +#define CONFIG_SYN_TECH custom1 +#else +#error "unknown target technology" +#endif + +#if defined CONFIG_SYN_INFER_RAM +#define CFG_RAM_TECH inferred +#elif defined CONFIG_MEM_UMC +#define CFG_RAM_TECH umc +#elif defined CONFIG_MEM_RHUMC +#define CFG_RAM_TECH rhumc +#elif defined CONFIG_MEM_VIRAGE +#define CFG_RAM_TECH memvirage +#elif defined CONFIG_MEM_ARTISAN +#define CFG_RAM_TECH memartisan +#elif defined CONFIG_MEM_CUSTOM1 +#define CFG_RAM_TECH custom1 +#elif defined CONFIG_MEM_VIRAGE90 +#define CFG_RAM_TECH memvirage90 +#elif defined CONFIG_MEM_INFERRED +#define CFG_RAM_TECH inferred +#else +#define CFG_RAM_TECH CONFIG_SYN_TECH +#endif + +#if defined CONFIG_SYN_INFER_PADS +#define CFG_PAD_TECH inferred +#else +#define CFG_PAD_TECH CONFIG_SYN_TECH +#endif + +#ifndef CONFIG_SYN_NO_ASYNC +#define CONFIG_SYN_NO_ASYNC 0 +#endif + +#ifndef CONFIG_SYN_SCAN +#define CONFIG_SYN_SCAN 0 +#endif + + +#if defined CONFIG_CLK_ALTDLL +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_HCLKBUF +#define CFG_CLK_TECH axcel +#elif defined CONFIG_CLK_LATDLL +#define CFG_CLK_TECH lattice +#elif defined CONFIG_CLK_PRO3PLL +#define CFG_CLK_TECH apa3 +#elif defined CONFIG_CLK_PRO3EPLL +#define CFG_CLK_TECH apa3e +#elif defined CONFIG_CLK_PRO3LPLL +#define CFG_CLK_TECH apa3l +#elif defined CONFIG_CLK_FUSPLL +#define CFG_CLK_TECH actfus +#elif defined CONFIG_CLK_CLKDLL +#define CFG_CLK_TECH virtex +#elif defined CONFIG_CLK_DCM +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_LIB18T +#define CFG_CLK_TECH rhlib18t +#elif defined CONFIG_CLK_RHUMC +#define CFG_CLK_TECH rhumc +#else +#define CFG_CLK_TECH inferred +#endif + +#ifndef CONFIG_CLK_MUL +#define CONFIG_CLK_MUL 2 +#endif + +#ifndef CONFIG_CLK_DIV +#define CONFIG_CLK_DIV 2 +#endif + +#ifndef CONFIG_OCLK_DIV +#define CONFIG_OCLK_DIV 1 +#endif + +#ifndef CONFIG_OCLKB_DIV +#define CONFIG_OCLKB_DIV 0 +#endif + +#ifndef CONFIG_OCLKC_DIV +#define CONFIG_OCLKC_DIV 0 +#endif + +#ifndef CONFIG_PCI_CLKDLL +#define CONFIG_PCI_CLKDLL 0 +#endif + +#ifndef CONFIG_PCI_SYSCLK +#define CONFIG_PCI_SYSCLK 0 +#endif + +#ifndef CONFIG_CLK_NOFB +#define CONFIG_CLK_NOFB 0 +#endif +#ifndef CONFIG_LEON3 +#define CONFIG_LEON3 0 +#endif + +#ifndef CONFIG_PROC_NUM +#define CONFIG_PROC_NUM 1 +#endif + +#ifndef CONFIG_IU_NWINDOWS +#define CONFIG_IU_NWINDOWS 8 +#endif + +#ifndef CONFIG_IU_RSTADDR +#define CONFIG_IU_RSTADDR 8 +#endif + +#ifndef CONFIG_IU_LDELAY +#define CONFIG_IU_LDELAY 1 +#endif + +#ifndef CONFIG_IU_WATCHPOINTS +#define CONFIG_IU_WATCHPOINTS 0 +#endif + +#ifdef CONFIG_IU_V8MULDIV +#ifdef CONFIG_IU_MUL_LATENCY_4 +#define CFG_IU_V8 1 +#elif defined CONFIG_IU_MUL_LATENCY_5 +#define CFG_IU_V8 2 +#elif defined CONFIG_IU_MUL_LATENCY_2 +#define CFG_IU_V8 16#32# +#endif +#else +#define CFG_IU_V8 0 +#endif + +#ifndef CONFIG_PWD +#define CONFIG_PWD 0 +#endif + +#ifndef CONFIG_IU_MUL_MAC +#define CONFIG_IU_MUL_MAC 0 +#endif + +#ifndef CONFIG_IU_BP +#define CONFIG_IU_BP 0 +#endif + +#ifndef CONFIG_NOTAG +#define CONFIG_NOTAG 0 +#endif + +#ifndef CONFIG_IU_SVT +#define CONFIG_IU_SVT 0 +#endif + +#if defined CONFIG_FPU_GRFPC1 +#define CONFIG_FPU_GRFPC 1 +#elif defined CONFIG_FPU_GRFPC2 +#define CONFIG_FPU_GRFPC 2 +#else +#define CONFIG_FPU_GRFPC 0 +#endif + +#if defined CONFIG_FPU_GRFPU_INFMUL +#define CONFIG_FPU_GRFPU_MUL 0 +#elif defined CONFIG_FPU_GRFPU_DWMUL +#define CONFIG_FPU_GRFPU_MUL 1 +#elif defined CONFIG_FPU_GRFPU_MODGEN +#define CONFIG_FPU_GRFPU_MUL 2 +#elif defined CONFIG_FPU_GRFPU_TECHSPEC +#define CONFIG_FPU_GRFPU_MUL 3 +#else +#define CONFIG_FPU_GRFPU_MUL 0 +#endif + +#if defined CONFIG_FPU_GRFPU_SH +#define CONFIG_FPU_GRFPU_SHARED 1 +#else +#define CONFIG_FPU_GRFPU_SHARED 0 +#endif + +#if defined CONFIG_FPU_GRFPU +#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) +#elif defined CONFIG_FPU_MEIKO +#define CONFIG_FPU 15 +#elif defined CONFIG_FPU_GRFPULITE +#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) +#else +#define CONFIG_FPU 0 +#endif + +#ifndef CONFIG_FPU_NETLIST +#define CONFIG_FPU_NETLIST 0 +#endif + +#ifndef CONFIG_ICACHE_ENABLE +#define CONFIG_ICACHE_ENABLE 0 +#endif + +#if defined CONFIG_ICACHE_ASSO1 +#define CFG_IU_ISETS 1 +#elif defined CONFIG_ICACHE_ASSO2 +#define CFG_IU_ISETS 2 +#elif defined CONFIG_ICACHE_ASSO3 +#define CFG_IU_ISETS 3 +#elif defined CONFIG_ICACHE_ASSO4 +#define CFG_IU_ISETS 4 +#else +#define CFG_IU_ISETS 1 +#endif + +#if defined CONFIG_ICACHE_SZ1 +#define CFG_ICACHE_SZ 1 +#elif defined CONFIG_ICACHE_SZ2 +#define CFG_ICACHE_SZ 2 +#elif defined CONFIG_ICACHE_SZ4 +#define CFG_ICACHE_SZ 4 +#elif defined CONFIG_ICACHE_SZ8 +#define CFG_ICACHE_SZ 8 +#elif defined CONFIG_ICACHE_SZ16 +#define CFG_ICACHE_SZ 16 +#elif defined CONFIG_ICACHE_SZ32 +#define CFG_ICACHE_SZ 32 +#elif defined CONFIG_ICACHE_SZ64 +#define CFG_ICACHE_SZ 64 +#elif defined CONFIG_ICACHE_SZ128 +#define CFG_ICACHE_SZ 128 +#elif defined CONFIG_ICACHE_SZ256 +#define CFG_ICACHE_SZ 256 +#else +#define CFG_ICACHE_SZ 1 +#endif + +#ifdef CONFIG_ICACHE_LZ16 +#define CFG_ILINE_SZ 4 +#else +#define CFG_ILINE_SZ 8 +#endif + +#if defined CONFIG_ICACHE_ALGORND +#define CFG_ICACHE_ALGORND 2 +#elif defined CONFIG_ICACHE_ALGOLRR +#define CFG_ICACHE_ALGORND 1 +#else +#define CFG_ICACHE_ALGORND 0 +#endif + +#ifndef CONFIG_ICACHE_LOCK +#define CONFIG_ICACHE_LOCK 0 +#endif + +#ifndef CONFIG_ICACHE_LRAM +#define CONFIG_ICACHE_LRAM 0 +#endif + +#ifndef CONFIG_ICACHE_LRSTART +#define CONFIG_ICACHE_LRSTART 8E +#endif + +#if defined CONFIG_ICACHE_LRAM_SZ2 +#define CFG_ILRAM_SIZE 2 +#elif defined CONFIG_ICACHE_LRAM_SZ4 +#define CFG_ILRAM_SIZE 4 +#elif defined CONFIG_ICACHE_LRAM_SZ8 +#define CFG_ILRAM_SIZE 8 +#elif defined CONFIG_ICACHE_LRAM_SZ16 +#define CFG_ILRAM_SIZE 16 +#elif defined CONFIG_ICACHE_LRAM_SZ32 +#define CFG_ILRAM_SIZE 32 +#elif defined CONFIG_ICACHE_LRAM_SZ64 +#define CFG_ILRAM_SIZE 64 +#elif defined CONFIG_ICACHE_LRAM_SZ128 +#define CFG_ILRAM_SIZE 128 +#elif defined CONFIG_ICACHE_LRAM_SZ256 +#define CFG_ILRAM_SIZE 256 +#else +#define CFG_ILRAM_SIZE 1 +#endif + + +#ifndef CONFIG_DCACHE_ENABLE +#define CONFIG_DCACHE_ENABLE 0 +#endif + +#if defined CONFIG_DCACHE_ASSO1 +#define CFG_IU_DSETS 1 +#elif defined CONFIG_DCACHE_ASSO2 +#define CFG_IU_DSETS 2 +#elif defined CONFIG_DCACHE_ASSO3 +#define CFG_IU_DSETS 3 +#elif defined CONFIG_DCACHE_ASSO4 +#define CFG_IU_DSETS 4 +#else +#define CFG_IU_DSETS 1 +#endif + +#if defined CONFIG_DCACHE_SZ1 +#define CFG_DCACHE_SZ 1 +#elif defined CONFIG_DCACHE_SZ2 +#define CFG_DCACHE_SZ 2 +#elif defined CONFIG_DCACHE_SZ4 +#define CFG_DCACHE_SZ 4 +#elif defined CONFIG_DCACHE_SZ8 +#define CFG_DCACHE_SZ 8 +#elif defined CONFIG_DCACHE_SZ16 +#define CFG_DCACHE_SZ 16 +#elif defined CONFIG_DCACHE_SZ32 +#define CFG_DCACHE_SZ 32 +#elif defined CONFIG_DCACHE_SZ64 +#define CFG_DCACHE_SZ 64 +#elif defined CONFIG_DCACHE_SZ128 +#define CFG_DCACHE_SZ 128 +#elif defined CONFIG_DCACHE_SZ256 +#define CFG_DCACHE_SZ 256 +#else +#define CFG_DCACHE_SZ 1 +#endif + +#ifdef CONFIG_DCACHE_LZ16 +#define CFG_DLINE_SZ 4 +#else +#define CFG_DLINE_SZ 8 +#endif + +#if defined CONFIG_DCACHE_ALGORND +#define CFG_DCACHE_ALGORND 2 +#elif defined CONFIG_DCACHE_ALGOLRR +#define CFG_DCACHE_ALGORND 1 +#else +#define CFG_DCACHE_ALGORND 0 +#endif + +#ifndef CONFIG_DCACHE_LOCK +#define CONFIG_DCACHE_LOCK 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP +#define CONFIG_DCACHE_SNOOP 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP_FAST +#define CONFIG_DCACHE_SNOOP_FAST 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP_SEPTAG +#define CONFIG_DCACHE_SNOOP_SEPTAG 0 +#endif + +#ifndef CONFIG_CACHE_FIXED +#define CONFIG_CACHE_FIXED 0 +#endif + +#ifndef CONFIG_DCACHE_LRAM +#define CONFIG_DCACHE_LRAM 0 +#endif + +#ifndef CONFIG_DCACHE_LRSTART +#define CONFIG_DCACHE_LRSTART 8F +#endif + +#if defined CONFIG_DCACHE_LRAM_SZ2 +#define CFG_DLRAM_SIZE 2 +#elif defined CONFIG_DCACHE_LRAM_SZ4 +#define CFG_DLRAM_SIZE 4 +#elif defined CONFIG_DCACHE_LRAM_SZ8 +#define CFG_DLRAM_SIZE 8 +#elif defined CONFIG_DCACHE_LRAM_SZ16 +#define CFG_DLRAM_SIZE 16 +#elif defined CONFIG_DCACHE_LRAM_SZ32 +#define CFG_DLRAM_SIZE 32 +#elif defined CONFIG_DCACHE_LRAM_SZ64 +#define CFG_DLRAM_SIZE 64 +#elif defined CONFIG_DCACHE_LRAM_SZ128 +#define CFG_DLRAM_SIZE 128 +#elif defined CONFIG_DCACHE_LRAM_SZ256 +#define CFG_DLRAM_SIZE 256 +#else +#define CFG_DLRAM_SIZE 1 +#endif + +#if defined CONFIG_MMU_PAGE_4K +#define CONFIG_MMU_PAGE 0 +#elif defined CONFIG_MMU_PAGE_8K +#define CONFIG_MMU_PAGE 1 +#elif defined CONFIG_MMU_PAGE_16K +#define CONFIG_MMU_PAGE 2 +#elif defined CONFIG_MMU_PAGE_32K +#define CONFIG_MMU_PAGE 3 +#elif defined CONFIG_MMU_PAGE_PROG +#define CONFIG_MMU_PAGE 4 +#else +#define CONFIG_MMU_PAGE 0 +#endif + +#ifdef CONFIG_MMU_ENABLE +#define CONFIG_MMUEN 1 + +#ifdef CONFIG_MMU_SPLIT +#define CONFIG_TLB_TYPE 0 +#endif +#ifdef CONFIG_MMU_COMBINED +#define CONFIG_TLB_TYPE 1 +#endif + +#ifdef CONFIG_MMU_REPARRAY +#define CONFIG_TLB_REP 0 +#endif +#ifdef CONFIG_MMU_REPINCREMENT +#define CONFIG_TLB_REP 1 +#endif + +#ifdef CONFIG_MMU_I2 +#define CONFIG_ITLBNUM 2 +#endif +#ifdef CONFIG_MMU_I4 +#define CONFIG_ITLBNUM 4 +#endif +#ifdef CONFIG_MMU_I8 +#define CONFIG_ITLBNUM 8 +#endif +#ifdef CONFIG_MMU_I16 +#define CONFIG_ITLBNUM 16 +#endif +#ifdef CONFIG_MMU_I32 +#define CONFIG_ITLBNUM 32 +#endif + +#define CONFIG_DTLBNUM 2 +#ifdef CONFIG_MMU_D2 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 2 +#endif +#ifdef CONFIG_MMU_D4 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 4 +#endif +#ifdef CONFIG_MMU_D8 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 8 +#endif +#ifdef CONFIG_MMU_D16 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 16 +#endif +#ifdef CONFIG_MMU_D32 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 32 +#endif +#ifdef CONFIG_MMU_FASTWB +#define CFG_MMU_FASTWB 1 +#else +#define CFG_MMU_FASTWB 0 +#endif + +#else +#define CONFIG_MMUEN 0 +#define CONFIG_ITLBNUM 2 +#define CONFIG_DTLBNUM 2 +#define CONFIG_TLB_TYPE 1 +#define CONFIG_TLB_REP 1 +#define CFG_MMU_FASTWB 0 +#endif + +#ifndef CONFIG_DSU_ENABLE +#define CONFIG_DSU_ENABLE 0 +#endif + +#if defined CONFIG_DSU_ITRACESZ1 +#define CFG_DSU_ITB 1 +#elif CONFIG_DSU_ITRACESZ2 +#define CFG_DSU_ITB 2 +#elif CONFIG_DSU_ITRACESZ4 +#define CFG_DSU_ITB 4 +#elif CONFIG_DSU_ITRACESZ8 +#define CFG_DSU_ITB 8 +#elif CONFIG_DSU_ITRACESZ16 +#define CFG_DSU_ITB 16 +#else +#define CFG_DSU_ITB 0 +#endif + +#if defined CONFIG_DSU_ATRACESZ1 +#define CFG_DSU_ATB 1 +#elif CONFIG_DSU_ATRACESZ2 +#define CFG_DSU_ATB 2 +#elif CONFIG_DSU_ATRACESZ4 +#define CFG_DSU_ATB 4 +#elif CONFIG_DSU_ATRACESZ8 +#define CFG_DSU_ATB 8 +#elif CONFIG_DSU_ATRACESZ16 +#define CFG_DSU_ATB 16 +#else +#define CFG_DSU_ATB 0 +#endif + +#ifndef CONFIG_LEON3FT_EN +#define CONFIG_LEON3FT_EN 0 +#endif + +#if defined CONFIG_IUFT_PAR +#define CONFIG_IUFT_EN 1 +#elif defined CONFIG_IUFT_DMR +#define CONFIG_IUFT_EN 2 +#elif defined CONFIG_IUFT_BCH +#define CONFIG_IUFT_EN 3 +#elif defined CONFIG_IUFT_TMR +#define CONFIG_IUFT_EN 4 +#else +#define CONFIG_IUFT_EN 0 +#endif +#ifndef CONFIG_RF_ERRINJ +#define CONFIG_RF_ERRINJ 0 +#endif + +#ifndef CONFIG_FPUFT_EN +#define CONFIG_FPUFT 0 +#else +#ifdef CONFIG_FPU_GRFPU +#define CONFIG_FPUFT 2 +#else +#define CONFIG_FPUFT 1 +#endif +#endif + +#ifndef CONFIG_CACHE_FT_EN +#define CONFIG_CACHE_FT_EN 0 +#endif +#ifndef CONFIG_CACHE_ERRINJ +#define CONFIG_CACHE_ERRINJ 0 +#endif + +#ifndef CONFIG_LEON3_NETLIST +#define CONFIG_LEON3_NETLIST 0 +#endif + +#ifdef CONFIG_DEBUG_PC32 +#define CFG_DEBUG_PC32 0 +#else +#define CFG_DEBUG_PC32 2 +#endif +#ifndef CONFIG_IU_DISAS +#define CONFIG_IU_DISAS 0 +#endif +#ifndef CONFIG_IU_DISAS_NET +#define CONFIG_IU_DISAS_NET 0 +#endif + + +#ifndef CONFIG_AHB_SPLIT +#define CONFIG_AHB_SPLIT 0 +#endif + +#ifndef CONFIG_AHB_RROBIN +#define CONFIG_AHB_RROBIN 0 +#endif + +#ifndef CONFIG_AHB_IOADDR +#define CONFIG_AHB_IOADDR FFF +#endif + +#ifndef CONFIG_APB_HADDR +#define CONFIG_APB_HADDR 800 +#endif + +#ifndef CONFIG_AHB_MON +#define CONFIG_AHB_MON 0 +#endif + +#ifndef CONFIG_AHB_MONERR +#define CONFIG_AHB_MONERR 0 +#endif + +#ifndef CONFIG_AHB_MONWAR +#define CONFIG_AHB_MONWAR 0 +#endif + +#ifndef CONFIG_AHB_DTRACE +#define CONFIG_AHB_DTRACE 0 +#endif + +#ifndef CONFIG_DSU_UART +#define CONFIG_DSU_UART 0 +#endif + + +#ifndef CONFIG_DSU_JTAG +#define CONFIG_DSU_JTAG 0 +#endif + +#ifndef CONFIG_DSU_ETH +#define CONFIG_DSU_ETH 0 +#endif + +#ifndef CONFIG_DSU_IPMSB +#define CONFIG_DSU_IPMSB C0A8 +#endif + +#ifndef CONFIG_DSU_IPLSB +#define CONFIG_DSU_IPLSB 0033 +#endif + +#ifndef CONFIG_DSU_ETHMSB +#define CONFIG_DSU_ETHMSB 020000 +#endif + +#ifndef CONFIG_DSU_ETHLSB +#define CONFIG_DSU_ETHLSB 000009 +#endif + +#if defined CONFIG_DSU_ETHSZ1 +#define CFG_DSU_ETHB 1 +#elif CONFIG_DSU_ETHSZ2 +#define CFG_DSU_ETHB 2 +#elif CONFIG_DSU_ETHSZ4 +#define CFG_DSU_ETHB 4 +#elif CONFIG_DSU_ETHSZ8 +#define CFG_DSU_ETHB 8 +#elif CONFIG_DSU_ETHSZ16 +#define CFG_DSU_ETHB 16 +#elif CONFIG_DSU_ETHSZ32 +#define CFG_DSU_ETHB 32 +#else +#define CFG_DSU_ETHB 1 +#endif + +#ifndef CONFIG_DSU_ETH_PROG +#define CONFIG_DSU_ETH_PROG 0 +#endif + +#ifndef CONFIG_MCTRL_LEON2 +#define CONFIG_MCTRL_LEON2 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM +#define CONFIG_MCTRL_SDRAM 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_SEPBUS +#define CONFIG_MCTRL_SDRAM_SEPBUS 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_INVCLK +#define CONFIG_MCTRL_SDRAM_INVCLK 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_BUS64 +#define CONFIG_MCTRL_SDRAM_BUS64 0 +#endif + +#ifndef CONFIG_MCTRL_8BIT +#define CONFIG_MCTRL_8BIT 0 +#endif + +#ifndef CONFIG_MCTRL_16BIT +#define CONFIG_MCTRL_16BIT 0 +#endif + +#ifndef CONFIG_MCTRL_5CS +#define CONFIG_MCTRL_5CS 0 +#endif + +#ifndef CONFIG_MCTRL_EDAC +#define CONFIG_MCTRL_EDAC 0 +#endif + +#ifndef CONFIG_MCTRL_PAGE +#define CONFIG_MCTRL_PAGE 0 +#endif + +#ifndef CONFIG_MCTRL_PROGPAGE +#define CONFIG_MCTRL_PROGPAGE 0 +#endif + +#ifndef CONFIG_DDRSP +#define CONFIG_DDRSP 0 +#endif + +#ifndef CONFIG_DDRSP_INIT +#define CONFIG_DDRSP_INIT 0 +#endif + +#ifndef CONFIG_DDRSP_FREQ +#define CONFIG_DDRSP_FREQ 100 +#endif + +#ifndef CONFIG_DDRSP_COL +#define CONFIG_DDRSP_COL 9 +#endif + +#ifndef CONFIG_DDRSP_MBYTE +#define CONFIG_DDRSP_MBYTE 8 +#endif + +#ifndef CONFIG_DDRSP_RSKEW +#define CONFIG_DDRSP_RSKEW 0 +#endif +#ifndef CONFIG_AHBROM_ENABLE +#define CONFIG_AHBROM_ENABLE 0 +#endif + +#ifndef CONFIG_AHBROM_START +#define CONFIG_AHBROM_START 000 +#endif + +#ifndef CONFIG_AHBROM_PIPE +#define CONFIG_AHBROM_PIPE 0 +#endif + +#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) +#define CONFIG_ROM_START 100 +#else +#define CONFIG_ROM_START 000 +#endif + + +#ifndef CONFIG_AHBRAM_ENABLE +#define CONFIG_AHBRAM_ENABLE 0 +#endif + +#ifndef CONFIG_AHBRAM_START +#define CONFIG_AHBRAM_START A00 +#endif + +#if defined CONFIG_AHBRAM_SZ1 +#define CFG_AHBRAMSZ 1 +#elif CONFIG_AHBRAM_SZ2 +#define CFG_AHBRAMSZ 2 +#elif CONFIG_AHBRAM_SZ4 +#define CFG_AHBRAMSZ 4 +#elif CONFIG_AHBRAM_SZ8 +#define CFG_AHBRAMSZ 8 +#elif CONFIG_AHBRAM_SZ16 +#define CFG_AHBRAMSZ 16 +#elif CONFIG_AHBRAM_SZ32 +#define CFG_AHBRAMSZ 32 +#elif CONFIG_AHBRAM_SZ64 +#define CFG_AHBRAMSZ 64 +#else +#define CFG_AHBRAMSZ 1 +#endif + +#ifndef CONFIG_GRETH_ENABLE +#define CONFIG_GRETH_ENABLE 0 +#endif + +#ifndef CONFIG_GRETH_GIGA +#define CONFIG_GRETH_GIGA 0 +#endif + +#if defined CONFIG_GRETH_FIFO4 +#define CFG_GRETH_FIFO 4 +#elif defined CONFIG_GRETH_FIFO8 +#define CFG_GRETH_FIFO 8 +#elif defined CONFIG_GRETH_FIFO16 +#define CFG_GRETH_FIFO 16 +#elif defined CONFIG_GRETH_FIFO32 +#define CFG_GRETH_FIFO 32 +#elif defined CONFIG_GRETH_FIFO64 +#define CFG_GRETH_FIFO 64 +#else +#define CFG_GRETH_FIFO 8 +#endif + +#ifndef CONFIG_UART1_ENABLE +#define CONFIG_UART1_ENABLE 0 +#endif + +#if defined CONFIG_UA1_FIFO1 +#define CFG_UA1_FIFO 1 +#elif defined CONFIG_UA1_FIFO2 +#define CFG_UA1_FIFO 2 +#elif defined CONFIG_UA1_FIFO4 +#define CFG_UA1_FIFO 4 +#elif defined CONFIG_UA1_FIFO8 +#define CFG_UA1_FIFO 8 +#elif defined CONFIG_UA1_FIFO16 +#define CFG_UA1_FIFO 16 +#elif defined CONFIG_UA1_FIFO32 +#define CFG_UA1_FIFO 32 +#else +#define CFG_UA1_FIFO 1 +#endif + +#ifndef CONFIG_IRQ3_ENABLE +#define CONFIG_IRQ3_ENABLE 0 +#endif +#ifndef CONFIG_IRQ3_NSEC +#define CONFIG_IRQ3_NSEC 0 +#endif +#ifndef CONFIG_GPT_ENABLE +#define CONFIG_GPT_ENABLE 0 +#endif + +#ifndef CONFIG_GPT_NTIM +#define CONFIG_GPT_NTIM 1 +#endif + +#ifndef CONFIG_GPT_SW +#define CONFIG_GPT_SW 8 +#endif + +#ifndef CONFIG_GPT_TW +#define CONFIG_GPT_TW 8 +#endif + +#ifndef CONFIG_GPT_IRQ +#define CONFIG_GPT_IRQ 8 +#endif + +#ifndef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 0 +#endif +#ifndef CONFIG_GPT_ENABLE +#define CONFIG_GPT_ENABLE 0 +#endif + +#ifndef CONFIG_GPT_NTIM +#define CONFIG_GPT_NTIM 1 +#endif + +#ifndef CONFIG_GPT_SW +#define CONFIG_GPT_SW 8 +#endif + +#ifndef CONFIG_GPT_TW +#define CONFIG_GPT_TW 8 +#endif + +#ifndef CONFIG_GPT_IRQ +#define CONFIG_GPT_IRQ 8 +#endif + +#ifndef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 0 +#endif + +#ifndef CONFIG_GPT_WDOGEN +#define CONFIG_GPT_WDOGEN 0 +#endif + +#ifndef CONFIG_GPT_WDOG +#define CONFIG_GPT_WDOG 0 +#endif + +#ifndef CONFIG_GRGPIO_ENABLE +#define CONFIG_GRGPIO_ENABLE 0 +#endif +#ifndef CONFIG_GRGPIO_IMASK +#define CONFIG_GRGPIO_IMASK 0000 +#endif +#ifndef CONFIG_GRGPIO_WIDTH +#define CONFIG_GRGPIO_WIDTH 1 +#endif + +#ifndef CONFIG_VGA_ENABLE +#define CONFIG_VGA_ENABLE 0 +#endif +#ifndef CONFIG_SVGA_ENABLE +#define CONFIG_SVGA_ENABLE 0 +#endif +#ifndef CONFIG_KBD_ENABLE +#define CONFIG_KBD_ENABLE 0 +#endif + + +#ifndef CONFIG_DEBUG_UART +#define CONFIG_DEBUG_UART 0 +#endif diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/webtalk_pn.xml b/designs/leon3-APB_LCD-digilent-xc3s1600e/webtalk_pn.xml --- a/designs/leon3-APB_LCD-digilent-xc3s1600e/webtalk_pn.xml +++ b/designs/leon3-APB_LCD-digilent-xc3s1600e/webtalk_pn.xml @@ -1,56 +1,56 @@ - - - - -
- - - - -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - + + + + +
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd @@ -71,6 +71,7 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_ virg_pos : IN INTEGER; coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + init_mem_done : out STD_LOGIC; ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); ram_write : IN STD_LOGIC; ram_read : IN STD_LOGIC; @@ -97,6 +98,7 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_ sample_in_rot : OUT STD_LOGIC; sample_out_val : OUT STD_LOGIC; sample_out_rot : OUT STD_LOGIC; + init_mem_done : in STD_LOGIC; --TODO in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); ram_write : OUT STD_LOGIC; @@ -130,6 +132,8 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_ SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + signal init_mem_done : std_logic; + BEGIN IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW @@ -147,6 +151,7 @@ BEGIN coefs => coefs, --CTRL in_sel_src => in_sel_src, + init_mem_done => init_mem_done, --TODO ram_sel_Wdata => ram_sel_Wdata, ram_write => ram_write, ram_read => ram_read, @@ -174,6 +179,8 @@ BEGIN sample_in_rot => sample_in_rotate, sample_out_val => sample_out_val_s, sample_out_rot => sample_out_rot_s, + + init_mem_done => init_mem_done, --TODO in_sel_src => in_sel_src, ram_sel_Wdata => ram_sel_Wdata, diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd @@ -41,6 +41,8 @@ ENTITY IIR_CEL_CTRLR_v2_CONTROL IS sample_out_val : OUT STD_LOGIC; sample_out_rot : OUT STD_LOGIC; + init_mem_done : in STD_LOGIC; --TODO + in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); ram_write : OUT STD_LOGIC; @@ -117,7 +119,7 @@ BEGIN ram_sel_Wdata <= "00"; ram_write <= '0'; waddr_previous <= "00"; - IF sample_in_val = '1' THEN + IF sample_in_val = '1' and init_mem_done = '1' THEN raddr_rst <= '0'; alu_sel_input <= '1'; ram_read <= '1'; @@ -312,4 +314,4 @@ BEGIN END IF; END PROCESS; -END ar_IIR_CEL_CTRLR_v2_CONTROL; \ No newline at end of file +END ar_IIR_CEL_CTRLR_v2_CONTROL; diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd @@ -46,6 +46,7 @@ ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS -- CONTROL in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- + init_mem_done : out STD_LOGIC; ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); ram_write : IN STD_LOGIC; ram_read : IN STD_LOGIC; @@ -73,6 +74,7 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLO PORT ( rstn : IN STD_LOGIC; clk : IN STD_LOGIC; + init_mem_done : out STD_LOGIC; ram_write : IN STD_LOGIC; ram_read : IN STD_LOGIC; raddr_rst : IN STD_LOGIC; @@ -131,6 +133,7 @@ BEGIN PORT MAP ( clk => clk, rstn => rstn, + init_mem_done => init_mem_done, ram_write => ram_write, ram_read => ram_read, raddr_rst => raddr_rst, diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd @@ -69,6 +69,7 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_ PORT ( rstn : IN STD_LOGIC; clk : IN STD_LOGIC; + init_mem_done : out STD_LOGIC; ram_write : IN STD_LOGIC; ram_read : IN STD_LOGIC; raddr_rst : IN STD_LOGIC; @@ -113,6 +114,9 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_ sample_in_rot : OUT STD_LOGIC; sample_out_val : OUT STD_LOGIC; sample_out_rot : OUT STD_LOGIC; + + init_mem_done : in STD_LOGIC; --TODO + in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); ram_write : OUT STD_LOGIC; @@ -182,12 +186,14 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_ SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION; --SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); - + signal init_mem_done : std_logic; + signal init_mem_done_1 : std_logic; + signal init_mem_done_2 : std_logic; BEGIN ----------------------------------------------------------------------------- - channel_val(0) <= sample_in1_val; - channel_val(1) <= sample_in2_val; + channel_val(0) <= sample_in1_val when init_mem_done = '1' else '0'; + channel_val(1) <= sample_in2_val when init_mem_done = '1' else '0'; all_channel_input_valid : FOR I IN 1 DOWNTO 0 GENERATE PROCESS (clk, rstn) BEGIN -- PROCESS @@ -285,6 +291,8 @@ BEGIN raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0'; waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00"; + init_mem_done <= init_mem_done_1 and init_mem_done_2; + RAM_CTRLR_v2_1 : RAM_CTRLR_v2 GENERIC MAP ( tech => tech, @@ -293,6 +301,7 @@ BEGIN PORT MAP ( clk => clk, rstn => rstn, + init_mem_done => init_mem_done_1, ram_write => ram_write_1, ram_read => ram_read_1, raddr_rst => raddr_rst_1, @@ -309,6 +318,7 @@ BEGIN PORT MAP ( clk => clk, rstn => rstn, + init_mem_done => init_mem_done_2, ram_write => ram_write_2, ram_read => ram_read_2, raddr_rst => raddr_rst_2, @@ -359,6 +369,8 @@ BEGIN sample_out_val => sample_out_val_s, sample_out_rot => sample_out_rot_s, + init_mem_done => init_mem_done, + in_sel_src => in_sel_src, ram_sel_Wdata => ram_sel_Wdata, ram_write => ram_write, diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd --- a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd @@ -38,6 +38,8 @@ ENTITY RAM_CTRLR_v2 IS PORT( rstn : IN STD_LOGIC; clk : IN STD_LOGIC; + -- ram init done + init_mem_done: out STD_LOGIC; -- R/W Ctrl ram_write : IN STD_LOGIC; ram_read : IN STD_LOGIC; @@ -56,24 +58,28 @@ ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRL SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); - SIGNAL WEN, REN : STD_LOGIC; + SIGNAL WEN, REN : STD_LOGIC; SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); + + signal rst_mem_done_s : std_logic; + signal ram_write_s : std_logic; BEGIN - sample_out <= RD(Input_SZ_1-1 DOWNTO 0); - WD(Input_SZ_1-1 DOWNTO 0) <= sample_in; + init_mem_done <= rst_mem_done_s; + + sample_out <= RD(Input_SZ_1-1 DOWNTO 0) when rst_mem_done_s = '1' else (others => '0'); + WD(Input_SZ_1-1 DOWNTO 0) <= sample_in when rst_mem_done_s = '1' else (others => '0'); + ram_write_s <= ram_write when rst_mem_done_s = '1' else '1'; ----------------------------------------------------------------------------- -- RAM ----------------------------------------------------------------------------- memCEL : IF Mem_use = use_CEL GENERATE - WEN <= NOT ram_write; + WEN <= NOT ram_write_s; REN <= NOT ram_read; --- RAMblk : RAM_CEL_N --- GENERIC MAP(Input_SZ_1) RAMblk : RAM_CEL GENERIC MAP(Input_SZ_1, 8) PORT MAP( @@ -91,7 +97,7 @@ BEGIN memRAM : IF Mem_use = use_RAM GENERATE SRAM : syncram_2p GENERIC MAP(tech, 8, Input_SZ_1) - PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD); + PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write_s, WADDR, WD); END GENERATE; ----------------------------------------------------------------------------- @@ -100,13 +106,22 @@ BEGIN PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) - counter <= (OTHERS => '0'); + counter <= (OTHERS => '0'); + rst_mem_done_s <= '0'; ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF raddr_rst = '1' THEN - counter <= (OTHERS => '0'); - ELSIF raddr_add1 = '1' THEN + if rst_mem_done_s = '0' then counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); - END IF; + else + IF raddr_rst = '1' THEN + counter <= (OTHERS => '0'); + ELSIF raddr_add1 = '1' THEN + counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); + END IF; + end if; + if counter = x"FF" then + rst_mem_done_s <= '1'; + end if; + END IF; END PROCESS; RADDR <= counter; @@ -114,7 +129,8 @@ BEGIN ----------------------------------------------------------------------------- -- WADDR ----------------------------------------------------------------------------- - WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE + WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)) when rst_mem_done_s = '0' else + STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE STD_LOGIC_VECTOR(UNSIGNED(counter));