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Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...
Alexis Jeandet -
r655:2dbcdaf8bb73 default draft
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=testbench
5 BOARD=LFR-EQM
6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=
9 QSF=
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT=
13 VHDLSYNFILES=
14 VHDLSIMFILES= tb.vhd
15 SIMTOP=TB
16 CLEAN=soft-clean
17
18 TECHLIBS = axcelerator
19
20 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
21 tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi
22
23 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
24 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \
25 grlfpc \
26 ./dsp/lpp_fft_rtax \
27 ./amba_lcd_16x2_ctrlr \
28 ./general_purpose/lpp_AMR \
29 ./general_purpose/lpp_balise \
30 ./general_purpose/lpp_delay \
31 ./lpp_bootloader \
32 ./lpp_sim/CY7C1061DV33 \
33 ./lpp_uart \
34 ./lpp_usb \
35 ./dsp/lpp_fft \
36 ./lpp_leon3_soc \
37 ./lpp_debug_lfr
38
39 FILESKIP = i2cmst.vhd \
40 APB_MULTI_DIODE.vhd \
41 APB_MULTI_DIODE.vhd \
42 Top_MatrixSpec.vhd \
43 APB_FFT.vhd \
44 lpp_lfr_ms_FFT.vhd \
45 lpp_lfr_apbreg.vhd \
46 CoreFFT.vhd \
47 lpp_lfr_ms.vhd \
48 lpp_lfr_sim_pkg.vhd \
49 mtie_maps.vhd \
50 ftsrctrlc.vhd \
51 ftsdctrl.vhd \
52 ftsrctrl8.vhd \
53 ftmctrl.vhd \
54 ftsdctrl64.vhd \
55 ftahbram.vhd \
56 ftahbram2.vhd \
57 sramft.vhd \
58 nandfctrlx.vhd
59
60 include $(GRLIB)/bin/Makefile
61 include $(GRLIB)/software/leon3/Makefile
62
63 ################## project specific targets ##########################
64 distclean:myclean
65 vsim:cp_for_vsim
66
67 myclean:
68 rm -f input.txt output_fx.txt *.log
69 rm -rf ./2016*
70
71 generate :
72 # python ./generate.py
73
74 cp_for_vsim: generate
75 # cp ./input.txt simulation/
76
77 archivate:
78 xonsh ./archivate.xsh
79
80 test: | generate ghdl ghdl-run archivate
81
82
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31
32 LIBRARY lpp;
33 USE lpp.lpp_lfr_management.ALL;
34
35 ENTITY TB IS
36
37 PORT (
38 SIM_OK : OUT STD_LOGIC
39 );
40
41 END TB;
42
43
44 ARCHITECTURE beh OF TB IS
45
46 SIGNAL clk25MHz : STD_LOGIC := '0';
47
48 SIGNAL resetn : STD_LOGIC;
49 SIGNAL grspw_tick : STD_LOGIC;
50 SIGNAL apbi : apb_slv_in_type;
51 SIGNAL apbo : apb_slv_out_type;
52 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
53 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
54
55 SIGNAL TB_string : STRING(1 TO 8):= "12345678";
56
57 SIGNAL coarse_time_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
58 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
59 SIGNAL global_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
60 SIGNAL global_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
61 SIGNAL tick_ongoing : STD_LOGIC;
62
63 SIGNAL ASSERTION_1 : STD_LOGIC;
64 SIGNAL ASSERTION_2 : STD_LOGIC;
65 SIGNAL ASSERTION_3 : STD_LOGIC;
66
67 BEGIN -- beh
68
69 apb_lfr_management_1: apb_lfr_management
70 GENERIC MAP (
71 tech => 0,
72 pindex => 0,
73 paddr => 0,
74 pmask => 16#fff#,
75 -- FIRST_DIVISION => 20,
76 NB_SECOND_DESYNC => 4)
77 PORT MAP (
78 clk25MHz => clk25MHz,
79 resetn_25MHz => resetn,
80
81 grspw_tick => grspw_tick,
82 apbi => apbi,
83 apbo => apbo,
84
85 HK_sample => (others => '0'),
86 HK_val => '0',
87 HK_sel => OPEN,
88
89 DAC_SDO => OPEN,
90 DAC_SCK => OPEN,
91 DAC_SYNC => OPEN,
92 DAC_CAL_EN => OPEN,
93
94 coarse_time => coarse_time,
95 fine_time => fine_time,
96
97 LFR_soft_rstn => OPEN);
98
99 clk25MHz <= NOT clk25MHz AFTER 20000 ps;
100
101 PROCESS
102 BEGIN -- PROCESS
103 WAIT UNTIL clk25MHz = '1';
104 TB_string <= "RESET ";
105
106 resetn <= '0';
107
108 apbi.psel(0) <= '0';
109 apbi.pwrite <= '0';
110 apbi.penable <= '0';
111 apbi.paddr <= (OTHERS => '0');
112 apbi.pwdata <= (OTHERS => '0');
113 grspw_tick <= '0';
114 WAIT UNTIL clk25MHz = '1';
115 WAIT UNTIL clk25MHz = '1';
116 resetn <= '1';
117 WAIT FOR 60 ms;
118 ---------------------------------------------------------------------------
119 -- DESYNC TO SYNC
120 ---------------------------------------------------------------------------
121 WAIT UNTIL clk25MHz = '1';
122 TB_string <= "TICK 1 ";
123 grspw_tick <= '1';------------------------------------------------------1
124 WAIT UNTIL clk25MHz = '1';
125 grspw_tick <= '0';
126 WAIT FOR 53333 us;
127 WAIT UNTIL clk25MHz = '1';
128 TB_string <= "TICK 2 ";
129 grspw_tick <= '1';------------------------------------------------------2
130 WAIT UNTIL clk25MHz = '1';
131 grspw_tick <= '0';
132 WAIT FOR 56000 us;
133 WAIT UNTIL clk25MHz = '1';
134 TB_string <= "TICK 3 ";
135 grspw_tick <= '1';------------------------------------------------------3
136 WAIT UNTIL clk25MHz = '1';
137 grspw_tick <= '0';
138 WAIT FOR 200 ms;
139 WAIT UNTIL clk25MHz = '1';
140 TB_string <= "CT new ";
141 -- WRITE NEW COARSE_TIME
142 apbi.psel(0) <= '1';
143 apbi.pwrite <= '1';
144 apbi.penable <= '1';
145 apbi.paddr <= X"00000004";
146 apbi.pwdata <= X"00001234";
147 WAIT UNTIL clk25MHz = '1';
148 apbi.psel(0) <= '0';
149 apbi.pwrite <= '0';
150 apbi.penable <= '0';
151 apbi.paddr <= (OTHERS => '0');
152 apbi.pwdata <= (OTHERS => '0');
153 WAIT UNTIL clk25MHz = '1';
154
155 WAIT FOR 10 ms;
156 WAIT UNTIL clk25MHz = '1';
157 TB_string <= "TICK 4 ";
158 grspw_tick <= '1';------------------------------------------------------3
159 WAIT UNTIL clk25MHz = '1';
160 grspw_tick <= '0';
161
162
163 WAIT FOR 250 ms;
164 WAIT UNTIL clk25MHz = '1';
165 TB_string <= "CT new ";
166 -- WRITE NEW COARSE_TIME
167 apbi.psel(0) <= '1';
168 apbi.pwrite <= '1';
169 apbi.penable <= '1';
170 apbi.paddr <= X"00000004";
171 apbi.pwdata <= X"80005678";
172 WAIT UNTIL clk25MHz = '1';
173 apbi.psel(0) <= '0';
174 apbi.pwrite <= '0';
175 apbi.penable <= '0';
176 apbi.paddr <= (OTHERS => '0');
177 apbi.pwdata <= (OTHERS => '0');
178 WAIT UNTIL clk25MHz = '1';
179
180 WAIT FOR 10 ms;
181 WAIT UNTIL clk25MHz = '1';
182 TB_string <= "TICK 5 ";
183 grspw_tick <= '1';------------------------------------------------------3
184 WAIT UNTIL clk25MHz = '1';
185 grspw_tick <= '0';
186
187
188 WAIT FOR 20 ms;
189 WAIT UNTIL clk25MHz = '1';
190 TB_string <= "CT new ";
191 -- WRITE NEW COARSE_TIME
192 apbi.psel(0) <= '1';
193 apbi.pwrite <= '1';
194 apbi.penable <= '1';
195 apbi.paddr <= X"00000004";
196 apbi.pwdata <= X"00005678";
197 WAIT UNTIL clk25MHz = '1';
198 apbi.psel(0) <= '0';
199 apbi.pwrite <= '0';
200 apbi.penable <= '0';
201 apbi.paddr <= (OTHERS => '0');
202 apbi.pwdata <= (OTHERS => '0');
203 WAIT UNTIL clk25MHz = '1';
204
205 WAIT FOR 25 ms;
206 WAIT UNTIL clk25MHz = '1';
207 TB_string <= "Soft RST";
208 -- WRITE SOFT RESET
209 apbi.psel(0) <= '1';
210 apbi.pwrite <= '1';
211 apbi.penable <= '1';
212 apbi.paddr <= X"00000000";
213 apbi.pwdata <= X"00000002";
214 WAIT UNTIL clk25MHz = '1';
215 apbi.psel(0) <= '0';
216 apbi.pwrite <= '0';
217 apbi.penable <= '0';
218 apbi.paddr <= (OTHERS => '0');
219 apbi.pwdata <= (OTHERS => '0');
220 WAIT UNTIL clk25MHz = '1';
221
222 WAIT FOR 250 ms;
223 TB_string <= "READ 1 ";
224 apbi.psel(0) <= '1';
225 apbi.pwrite <= '0';
226 apbi.penable <= '1';
227 apbi.paddr <= X"00000008";
228 WAIT UNTIL clk25MHz = '1';
229 apbi.psel(0) <= '0';
230 apbi.pwrite <= '0';
231 apbi.penable <= '0';
232 apbi.paddr <= (OTHERS => '0');
233 WAIT UNTIL clk25MHz = '1';
234 WAIT FOR 250 ms;
235 TB_string <= "READ 2 ";
236 apbi.psel(0) <= '1';
237 apbi.pwrite <= '0';
238 apbi.penable <= '1';
239 apbi.paddr <= X"00000008";
240 WAIT UNTIL clk25MHz = '1';
241 apbi.psel(0) <= '0';
242 apbi.pwrite <= '0';
243 apbi.penable <= '0';
244 apbi.paddr <= (OTHERS => '0');
245 WAIT UNTIL clk25MHz = '1';
246 WAIT FOR 250 ms;
247 TB_string <= "READ 3 ";
248 apbi.psel(0) <= '1';
249 apbi.pwrite <= '0';
250 apbi.penable <= '1';
251 apbi.paddr <= X"00000008";
252 WAIT UNTIL clk25MHz = '1';
253 apbi.psel(0) <= '0';
254 apbi.pwrite <= '0';
255 apbi.penable <= '0';
256 apbi.paddr <= (OTHERS => '0');
257 WAIT UNTIL clk25MHz = '1';
258
259
260
261 REPORT "*** END simulation ***" SEVERITY failure;
262 WAIT;
263
264 END PROCESS;
265
266
267 -----------------------------------------------------------------------------
268 --
269 -----------------------------------------------------------------------------
270
271 global_time <= coarse_time & fine_time;
272
273 PROCESS (clk25MHz, resetn)
274 BEGIN -- PROCESS
275 IF resetn = '0' THEN -- asynchronous reset (active low)
276 coarse_time_reg <= (OTHERS => '0');
277 fine_time_reg <= (OTHERS => '0');
278 global_time_reg <= (OTHERS => '0');
279 tick_ongoing <= '0';
280 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
281 global_time_reg <= global_time;
282 coarse_time_reg <= coarse_time;
283 fine_time_reg <= fine_time;
284 IF grspw_tick ='1' THEN
285 tick_ongoing <= '1';
286 ELSIF tick_ongoing = '1' THEN
287 IF (fine_time_reg /= fine_time) OR (coarse_time_reg /= coarse_time) THEN
288 tick_ongoing <= '0';
289 END IF;
290 END IF;
291
292 END IF;
293 END PROCESS;
294
295 -----------------------------------------------------------------------------
296 -- ASSERTION 1 :
297 -- Coarse_time "changed" => FINE_TIME = 0
298 -- False after a TRANSITION !
299 -----------------------------------------------------------------------------
300 PROCESS (clk25MHz, resetn)
301 BEGIN -- PROCESS
302 IF resetn = '0' THEN -- asynchronous reset (active low)
303 ASSERTION_1 <= '1';
304 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
305 IF coarse_time /= coarse_time_reg THEN
306 IF fine_time /= X"0000" THEN
307 IF fine_time /= X"0041" THEN
308 ASSERTION_1 <= '0';
309 ELSE
310 ASSERTION_1 <= 'U';
311 END IF;
312 ELSE
313 ASSERTION_1 <= '1';
314 END IF;
315 END IF;
316 END IF;
317 END PROCESS;
318
319 -----------------------------------------------------------------------------
320 -- ASSERTION 2 :
321 -- tick => next(FINE_TIME) = 0
322 -----------------------------------------------------------------------------
323 PROCESS (clk25MHz, resetn)
324 BEGIN -- PROCESS
325 IF resetn = '0' THEN -- asynchronous reset (active low)
326 ASSERTION_2 <= '1';
327 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
328 IF tick_ongoing = '1' THEN
329 IF fine_time_reg /= fine_time OR coarse_time_reg /= coarse_time THEN
330 IF fine_time /= X"0000" THEN
331 ASSERTION_2 <= '0';
332 END IF;
333 END IF;
334 END IF;
335 END IF;
336 END PROCESS;
337
338 -----------------------------------------------------------------------------
339 -- ASSERTION 3 :
340 -- next(TIME) > TIME
341 -- false if resynchro, or new coarse_time
342 -----------------------------------------------------------------------------
343 PROCESS (clk25MHz, resetn)
344 BEGIN -- PROCESS
345 IF resetn = '0' THEN -- asynchronous reset (active low)
346 ASSERTION_3 <= '1';
347 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
348 ASSERTION_3 <= '1';
349 IF global_time_reg(46 DOWNTO 0) > global_time(46 DOWNTO 0) THEN
350 IF global_time(47) = '0' AND global_time_reg(47) = '1' THEN
351 ASSERTION_3 <= 'U'; -- RESYNCHRO ....
352 ELSE
353 ASSERTION_3 <= '0';
354 END IF;
355 END IF;
356 END IF;
357 END PROCESS;
358
359
360 END beh;
361
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1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
4
5 ENTITY general_counter IS
5 ENTITY general_counter IS
6
6
7 GENERIC (
7 GENERIC (
8 CYCLIC : STD_LOGIC := '1';
8 CYCLIC : STD_LOGIC := '1';
9 NB_BITS_COUNTER : INTEGER := 9;
9 NB_BITS_COUNTER : INTEGER := 9;
10 RST_VALUE : INTEGER := 0
10 RST_VALUE : INTEGER := 0
11 );
11 );
12
12
13 PORT (
13 PORT (
14 clk : IN STD_LOGIC;
14 clk : IN STD_LOGIC;
15 rstn : IN STD_LOGIC;
15 rstn : IN STD_LOGIC;
16 --
16 --
17 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
17 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
18 --
18 --
19 set : IN STD_LOGIC;
19 set : IN STD_LOGIC;
20 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
20 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
21 add1 : IN STD_LOGIC;
21 add1 : IN STD_LOGIC;
22 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0)
22 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0)
23 );
23 );
24
24
25 END general_counter;
25 END general_counter;
26
26
27 ARCHITECTURE beh OF general_counter IS
27 ARCHITECTURE beh OF general_counter IS
28 CONSTANT RST_VALUE_v : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(RST_VALUE, NB_BITS_COUNTER));
28 CONSTANT RST_VALUE_v : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(RST_VALUE, NB_BITS_COUNTER));
29 SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
29 SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
30
30
31 BEGIN -- beh
31 BEGIN -- beh
32
32
33 PROCESS (clk, rstn)
33 PROCESS (clk, rstn)
34 BEGIN -- PROCESS
34 BEGIN -- PROCESS
35 IF rstn = '0' THEN -- asynchronous reset (active low)
35 IF rstn = '0' THEN -- asynchronous reset (active low)
36 counter_s <= RST_VALUE_v;
36 counter_s <= RST_VALUE_v;
37 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
37 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
38 IF set = '1' THEN
38 IF set = '1' THEN
39 counter_s <= set_value;
39 counter_s <= set_value;
40 ELSIF add1 = '1' THEN
40 ELSIF add1 = '1' THEN
41 IF counter_s < MAX_VALUE THEN
41 IF counter_s < MAX_VALUE THEN
42 counter_s <= STD_LOGIC_VECTOR((UNSIGNED(counter_s) + 1));
42 counter_s <= STD_LOGIC_VECTOR((UNSIGNED(counter_s) + 1));
43 ELSE
43 ELSE
44 IF CYCLIC = '1' THEN
44 IF CYCLIC = '1' THEN
45 counter_s <= (OTHERS => '0');
45 counter_s <= (OTHERS => '0');
46 END IF;
46 END IF;
47 END IF;
47 END IF;
48 END IF;
48 END IF;
49 END IF;
49 END IF;
50 END PROCESS;
50 END PROCESS;
51
51
52 counter <= counter_s;
52 counter <= counter_s;
53
53
54 END beh;
54 END beh;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 --UPDATE
22 --UPDATE
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 14-03-2013 - Jean-christophe Pellion
24 -- 14-03-2013 - Jean-christophe Pellion
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27
27
28 LIBRARY ieee;
28 LIBRARY ieee;
29 USE ieee.std_logic_1164.ALL;
29 USE ieee.std_logic_1164.ALL;
30 USE IEEE.NUMERIC_STD.ALL;
30 USE IEEE.NUMERIC_STD.ALL;
31
31
32
32
33
33
34 PACKAGE general_purpose IS
34 PACKAGE general_purpose IS
35
35
36 COMPONENT general_counter
36 COMPONENT general_counter
37 GENERIC (
37 GENERIC (
38 CYCLIC : STD_LOGIC;
38 CYCLIC : STD_LOGIC := '1';
39 NB_BITS_COUNTER : INTEGER;
39 NB_BITS_COUNTER : INTEGER := 9;
40 RST_VALUE : INTEGER);
40 RST_VALUE : INTEGER := 0);
41 PORT (
41 PORT (
42 clk : IN STD_LOGIC;
42 clk : IN STD_LOGIC;
43 rstn : IN STD_LOGIC;
43 rstn : IN STD_LOGIC;
44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
45 set : IN STD_LOGIC;
45 set : IN STD_LOGIC;
46 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
46 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
47 add1 : IN STD_LOGIC;
47 add1 : IN STD_LOGIC;
48 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0));
48 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0));
49 END COMPONENT;
49 END COMPONENT;
50
50
51 COMPONENT Clk_divider IS
51 COMPONENT Clk_divider IS
52 GENERIC(OSC_freqHz : INTEGER := 50000000;
52 GENERIC(OSC_freqHz : INTEGER := 50000000;
53 TargetFreq_Hz : INTEGER := 50000);
53 TargetFreq_Hz : INTEGER := 50000);
54 PORT (clk : IN STD_LOGIC;
54 PORT (clk : IN STD_LOGIC;
55 reset : IN STD_LOGIC;
55 reset : IN STD_LOGIC;
56 clk_divided : OUT STD_LOGIC);
56 clk_divided : OUT STD_LOGIC);
57 END COMPONENT;
57 END COMPONENT;
58
58
59
59
60 COMPONENT Clk_divider2 IS
60 COMPONENT Clk_divider2 IS
61 GENERIC(N : INTEGER := 16);
61 GENERIC(N : INTEGER := 16);
62 PORT(
62 PORT(
63 clk_in : IN STD_LOGIC;
63 clk_in : IN STD_LOGIC;
64 clk_out : OUT STD_LOGIC);
64 clk_out : OUT STD_LOGIC);
65 END COMPONENT;
65 END COMPONENT;
66
66
67 COMPONENT Adder IS
67 COMPONENT Adder IS
68 GENERIC(
68 GENERIC(
69 Input_SZ_A : INTEGER := 16;
69 Input_SZ_A : INTEGER := 16;
70 Input_SZ_B : INTEGER := 16
70 Input_SZ_B : INTEGER := 16
71
71
72 );
72 );
73 PORT(
73 PORT(
74 clk : IN STD_LOGIC;
74 clk : IN STD_LOGIC;
75 reset : IN STD_LOGIC;
75 reset : IN STD_LOGIC;
76 clr : IN STD_LOGIC;
76 clr : IN STD_LOGIC;
77 load : IN STD_LOGIC;
77 load : IN STD_LOGIC;
78 add : IN STD_LOGIC;
78 add : IN STD_LOGIC;
79 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
79 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
80 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
80 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
81 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
81 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
82 );
82 );
83 END COMPONENT;
83 END COMPONENT;
84
84
85 COMPONENT Adder_V0 IS
85 COMPONENT Adder_V0 IS
86 GENERIC(
86 GENERIC(
87 Input_SZ_A : INTEGER := 16;
87 Input_SZ_A : INTEGER := 16;
88 Input_SZ_B : INTEGER := 16
88 Input_SZ_B : INTEGER := 16
89
89
90 );
90 );
91 PORT(
91 PORT(
92 clk : IN STD_LOGIC;
92 clk : IN STD_LOGIC;
93 reset : IN STD_LOGIC;
93 reset : IN STD_LOGIC;
94 clr : IN STD_LOGIC;
94 clr : IN STD_LOGIC;
95 add : IN STD_LOGIC;
95 add : IN STD_LOGIC;
96 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
96 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
97 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
97 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
98 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
98 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
99 );
99 );
100 END COMPONENT;
100 END COMPONENT;
101
101
102 COMPONENT ADDRcntr IS
102 COMPONENT ADDRcntr IS
103 PORT(
103 PORT(
104 clk : IN STD_LOGIC;
104 clk : IN STD_LOGIC;
105 reset : IN STD_LOGIC;
105 reset : IN STD_LOGIC;
106 count : IN STD_LOGIC;
106 count : IN STD_LOGIC;
107 clr : IN STD_LOGIC;
107 clr : IN STD_LOGIC;
108 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
108 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
109 );
109 );
110 END COMPONENT;
110 END COMPONENT;
111
111
112 COMPONENT ALU IS
112 COMPONENT ALU IS
113 GENERIC(
113 GENERIC(
114 Arith_en : INTEGER := 1;
114 Arith_en : INTEGER := 1;
115 Logic_en : INTEGER := 1;
115 Logic_en : INTEGER := 1;
116 Input_SZ_1 : INTEGER := 16;
116 Input_SZ_1 : INTEGER := 16;
117 Input_SZ_2 : INTEGER := 9;
117 Input_SZ_2 : INTEGER := 9;
118 COMP_EN : INTEGER := 0 -- 1 => No Comp
118 COMP_EN : INTEGER := 0 -- 1 => No Comp
119
119
120 );
120 );
121 PORT(
121 PORT(
122 clk : IN STD_LOGIC;
122 clk : IN STD_LOGIC;
123 reset : IN STD_LOGIC;
123 reset : IN STD_LOGIC;
124 ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
124 ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
125 comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
125 comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
126 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
126 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
127 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
127 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
128 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
128 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
129 );
129 );
130 END COMPONENT;
130 END COMPONENT;
131
131
132 COMPONENT ALU_V0 IS
132 COMPONENT ALU_V0 IS
133 GENERIC(
133 GENERIC(
134 Arith_en : INTEGER := 1;
134 Arith_en : INTEGER := 1;
135 Logic_en : INTEGER := 1;
135 Logic_en : INTEGER := 1;
136 Input_SZ_1 : INTEGER := 16;
136 Input_SZ_1 : INTEGER := 16;
137 Input_SZ_2 : INTEGER := 9
137 Input_SZ_2 : INTEGER := 9
138
138
139 );
139 );
140 PORT(
140 PORT(
141 clk : IN STD_LOGIC;
141 clk : IN STD_LOGIC;
142 reset : IN STD_LOGIC;
142 reset : IN STD_LOGIC;
143 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
143 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
144 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
144 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
145 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
145 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
146 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
146 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
147 );
147 );
148 END COMPONENT;
148 END COMPONENT;
149
149
150 COMPONENT MAC_V0 IS
150 COMPONENT MAC_V0 IS
151 GENERIC(
151 GENERIC(
152 Input_SZ_A : INTEGER := 8;
152 Input_SZ_A : INTEGER := 8;
153 Input_SZ_B : INTEGER := 8
153 Input_SZ_B : INTEGER := 8
154
154
155 );
155 );
156 PORT(
156 PORT(
157 clk : IN STD_LOGIC;
157 clk : IN STD_LOGIC;
158 reset : IN STD_LOGIC;
158 reset : IN STD_LOGIC;
159 clr_MAC : IN STD_LOGIC;
159 clr_MAC : IN STD_LOGIC;
160 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
160 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
161 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
161 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
162 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
162 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
163 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
163 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
164 );
164 );
165 END COMPONENT;
165 END COMPONENT;
166
166
167 ---------------------------------------------------------
167 ---------------------------------------------------------
168 -------- // Sélection grace a l'entrée "ctrl" \\ --------
168 -------- // Sélection grace a l'entrée "ctrl" \\ --------
169 ---------------------------------------------------------
169 ---------------------------------------------------------
170 CONSTANT ctrl_IDLE : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
170 CONSTANT ctrl_IDLE : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
171 CONSTANT ctrl_MAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
171 CONSTANT ctrl_MAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
172 CONSTANT ctrl_MULT : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
172 CONSTANT ctrl_MULT : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
173 CONSTANT ctrl_ADD : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
173 CONSTANT ctrl_ADD : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
174 CONSTANT ctrl_CLRMAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
174 CONSTANT ctrl_CLRMAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
175
175
176
176
177 CONSTANT IDLE_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
177 CONSTANT IDLE_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
178 CONSTANT MAC_op_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
178 CONSTANT MAC_op_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
179 CONSTANT MULT_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
179 CONSTANT MULT_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
180 CONSTANT ADD_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
180 CONSTANT ADD_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
181 CONSTANT CLR_MAC_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
181 CONSTANT CLR_MAC_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
182 ---------------------------------------------------------
182 ---------------------------------------------------------
183
183
184 COMPONENT MAC IS
184 COMPONENT MAC IS
185 GENERIC(
185 GENERIC(
186 Input_SZ_A : INTEGER := 8;
186 Input_SZ_A : INTEGER := 8;
187 Input_SZ_B : INTEGER := 8;
187 Input_SZ_B : INTEGER := 8;
188 COMP_EN : INTEGER := 0 -- 1 => No Comp
188 COMP_EN : INTEGER := 0 -- 1 => No Comp
189 );
189 );
190 PORT(
190 PORT(
191 clk : IN STD_LOGIC;
191 clk : IN STD_LOGIC;
192 reset : IN STD_LOGIC;
192 reset : IN STD_LOGIC;
193 clr_MAC : IN STD_LOGIC;
193 clr_MAC : IN STD_LOGIC;
194 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
194 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
195 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
195 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
196 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
196 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
197 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
197 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
198 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
198 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
199 );
199 );
200 END COMPONENT;
200 END COMPONENT;
201
201
202 COMPONENT TwoComplementer IS
202 COMPONENT TwoComplementer IS
203 GENERIC(
203 GENERIC(
204 Input_SZ : INTEGER := 16);
204 Input_SZ : INTEGER := 16);
205 PORT(
205 PORT(
206 clk : IN STD_LOGIC; --! Horloge du composant
206 clk : IN STD_LOGIC; --! Horloge du composant
207 reset : IN STD_LOGIC; --! Reset general du composant
207 reset : IN STD_LOGIC; --! Reset general du composant
208 clr : IN STD_LOGIC; --! Un reset spécifique au programme
208 clr : IN STD_LOGIC; --! Un reset spécifique au programme
209 TwoComp : IN STD_LOGIC; --! Autorise l'utilisation du complément
209 TwoComp : IN STD_LOGIC; --! Autorise l'utilisation du complément
210 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); --! Opérande d'entrée
210 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); --! Opérande d'entrée
211 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) --! Résultat, opérande complémenté ou non
211 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) --! Résultat, opérande complémenté ou non
212 );
212 );
213 END COMPONENT;
213 END COMPONENT;
214
214
215 COMPONENT MAC_CONTROLER IS
215 COMPONENT MAC_CONTROLER IS
216 PORT(
216 PORT(
217 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
217 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
218 MULT : OUT STD_LOGIC;
218 MULT : OUT STD_LOGIC;
219 ADD : OUT STD_LOGIC;
219 ADD : OUT STD_LOGIC;
220 -- LOAD_ADDER : out std_logic;
220 -- LOAD_ADDER : out std_logic;
221 MACMUX_sel : OUT STD_LOGIC;
221 MACMUX_sel : OUT STD_LOGIC;
222 MACMUX2_sel : OUT STD_LOGIC
222 MACMUX2_sel : OUT STD_LOGIC
223 );
223 );
224 END COMPONENT;
224 END COMPONENT;
225
225
226 COMPONENT MAC_MUX IS
226 COMPONENT MAC_MUX IS
227 GENERIC(
227 GENERIC(
228 Input_SZ_A : INTEGER := 16;
228 Input_SZ_A : INTEGER := 16;
229 Input_SZ_B : INTEGER := 16
229 Input_SZ_B : INTEGER := 16
230
230
231 );
231 );
232 PORT(
232 PORT(
233 sel : IN STD_LOGIC;
233 sel : IN STD_LOGIC;
234 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
234 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
235 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
235 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
236 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
236 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
237 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
237 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
238 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
238 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
239 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
239 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
240 );
240 );
241 END COMPONENT;
241 END COMPONENT;
242
242
243
243
244 COMPONENT MAC_MUX2 IS
244 COMPONENT MAC_MUX2 IS
245 GENERIC(Input_SZ : INTEGER := 16);
245 GENERIC(Input_SZ : INTEGER := 16);
246 PORT(
246 PORT(
247 sel : IN STD_LOGIC;
247 sel : IN STD_LOGIC;
248 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
248 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
249 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
249 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
250 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
250 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
251 );
251 );
252 END COMPONENT;
252 END COMPONENT;
253
253
254
254
255 COMPONENT MAC_REG IS
255 COMPONENT MAC_REG IS
256 GENERIC(size : INTEGER := 16);
256 GENERIC(size : INTEGER := 16);
257 PORT(
257 PORT(
258 reset : IN STD_LOGIC;
258 reset : IN STD_LOGIC;
259 clk : IN STD_LOGIC;
259 clk : IN STD_LOGIC;
260 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
260 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
261 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
261 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
262 );
262 );
263 END COMPONENT;
263 END COMPONENT;
264
264
265
265
266 COMPONENT MUX2 IS
266 COMPONENT MUX2 IS
267 GENERIC(Input_SZ : INTEGER := 16);
267 GENERIC(Input_SZ : INTEGER := 16);
268 PORT(
268 PORT(
269 sel : IN STD_LOGIC;
269 sel : IN STD_LOGIC;
270 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
270 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
271 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
271 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
272 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
272 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
273 );
273 );
274 END COMPONENT;
274 END COMPONENT;
275
275
276 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
276 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
277 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
277 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
278
278
279 COMPONENT MUXN
279 COMPONENT MUXN
280 GENERIC (
280 GENERIC (
281 Input_SZ : INTEGER;
281 Input_SZ : INTEGER;
282 NbStage : INTEGER);
282 NbStage : INTEGER);
283 PORT (
283 PORT (
284 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
284 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
285 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1, Input_SZ-1 DOWNTO 0);
285 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1, Input_SZ-1 DOWNTO 0);
286 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
286 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
287 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
287 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
288 END COMPONENT;
288 END COMPONENT;
289
289
290
290
291
291
292 COMPONENT Multiplier IS
292 COMPONENT Multiplier IS
293 GENERIC(
293 GENERIC(
294 Input_SZ_A : INTEGER := 16;
294 Input_SZ_A : INTEGER := 16;
295 Input_SZ_B : INTEGER := 16
295 Input_SZ_B : INTEGER := 16
296
296
297 );
297 );
298 PORT(
298 PORT(
299 clk : IN STD_LOGIC;
299 clk : IN STD_LOGIC;
300 reset : IN STD_LOGIC;
300 reset : IN STD_LOGIC;
301 mult : IN STD_LOGIC;
301 mult : IN STD_LOGIC;
302 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
302 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
303 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
303 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
304 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
304 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
305 );
305 );
306 END COMPONENT;
306 END COMPONENT;
307
307
308 COMPONENT REG IS
308 COMPONENT REG IS
309 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
309 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
310 PORT(
310 PORT(
311 reset : IN STD_LOGIC;
311 reset : IN STD_LOGIC;
312 clk : IN STD_LOGIC;
312 clk : IN STD_LOGIC;
313 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
313 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
314 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
314 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
315 );
315 );
316 END COMPONENT;
316 END COMPONENT;
317
317
318
318
319
319
320 COMPONENT RShifter IS
320 COMPONENT RShifter IS
321 GENERIC(
321 GENERIC(
322 Input_SZ : INTEGER := 16;
322 Input_SZ : INTEGER := 16;
323 shift_SZ : INTEGER := 4
323 shift_SZ : INTEGER := 4
324 );
324 );
325 PORT(
325 PORT(
326 clk : IN STD_LOGIC;
326 clk : IN STD_LOGIC;
327 reset : IN STD_LOGIC;
327 reset : IN STD_LOGIC;
328 shift : IN STD_LOGIC;
328 shift : IN STD_LOGIC;
329 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
329 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
330 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
330 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
331 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
331 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
332 );
332 );
333 END COMPONENT;
333 END COMPONENT;
334
334
335 COMPONENT SYNC_FF
335 COMPONENT SYNC_FF
336 GENERIC (
336 GENERIC (
337 NB_FF_OF_SYNC : INTEGER);
337 NB_FF_OF_SYNC : INTEGER);
338 PORT (
338 PORT (
339 clk : IN STD_LOGIC;
339 clk : IN STD_LOGIC;
340 rstn : IN STD_LOGIC;
340 rstn : IN STD_LOGIC;
341 A : IN STD_LOGIC;
341 A : IN STD_LOGIC;
342 A_sync : OUT STD_LOGIC);
342 A_sync : OUT STD_LOGIC);
343 END COMPONENT;
343 END COMPONENT;
344
344
345 COMPONENT lpp_front_to_level
345 COMPONENT lpp_front_to_level
346 PORT (
346 PORT (
347 clk : IN STD_LOGIC;
347 clk : IN STD_LOGIC;
348 rstn : IN STD_LOGIC;
348 rstn : IN STD_LOGIC;
349 sin : IN STD_LOGIC;
349 sin : IN STD_LOGIC;
350 sout : OUT STD_LOGIC);
350 sout : OUT STD_LOGIC);
351 END COMPONENT;
351 END COMPONENT;
352
352
353 COMPONENT lpp_front_detection
353 COMPONENT lpp_front_detection
354 PORT (
354 PORT (
355 clk : IN STD_LOGIC;
355 clk : IN STD_LOGIC;
356 rstn : IN STD_LOGIC;
356 rstn : IN STD_LOGIC;
357 sin : IN STD_LOGIC;
357 sin : IN STD_LOGIC;
358 sout : OUT STD_LOGIC);
358 sout : OUT STD_LOGIC);
359 END COMPONENT;
359 END COMPONENT;
360
360
361 COMPONENT lpp_front_positive_detection
361 COMPONENT lpp_front_positive_detection
362 PORT (
362 PORT (
363 clk : IN STD_LOGIC;
363 clk : IN STD_LOGIC;
364 rstn : IN STD_LOGIC;
364 rstn : IN STD_LOGIC;
365 sin : IN STD_LOGIC;
365 sin : IN STD_LOGIC;
366 sout : OUT STD_LOGIC);
366 sout : OUT STD_LOGIC);
367 END COMPONENT;
367 END COMPONENT;
368
368
369 --COMPONENT SYNC_VALID_BIT
369 --COMPONENT SYNC_VALID_BIT
370 -- GENERIC (
370 -- GENERIC (
371 -- NB_FF_OF_SYNC : INTEGER);
371 -- NB_FF_OF_SYNC : INTEGER);
372 -- PORT (
372 -- PORT (
373 -- clk_in : IN STD_LOGIC;
373 -- clk_in : IN STD_LOGIC;
374 -- clk_out : IN STD_LOGIC;
374 -- clk_out : IN STD_LOGIC;
375 -- rstn : IN STD_LOGIC;
375 -- rstn : IN STD_LOGIC;
376 -- sin : IN STD_LOGIC;
376 -- sin : IN STD_LOGIC;
377 -- sout : OUT STD_LOGIC);
377 -- sout : OUT STD_LOGIC);
378 --END COMPONENT;
378 --END COMPONENT;
379
379
380 COMPONENT SYNC_VALID_BIT
380 COMPONENT SYNC_VALID_BIT
381 GENERIC (
381 GENERIC (
382 NB_FF_OF_SYNC : INTEGER);
382 NB_FF_OF_SYNC : INTEGER);
383 PORT (
383 PORT (
384 clk_in : IN STD_LOGIC;
384 clk_in : IN STD_LOGIC;
385 rstn_in : IN STD_LOGIC;
385 rstn_in : IN STD_LOGIC;
386 clk_out : IN STD_LOGIC;
386 clk_out : IN STD_LOGIC;
387 rstn_out : IN STD_LOGIC;
387 rstn_out : IN STD_LOGIC;
388 sin : IN STD_LOGIC;
388 sin : IN STD_LOGIC;
389 sout : OUT STD_LOGIC);
389 sout : OUT STD_LOGIC);
390 END COMPONENT;
390 END COMPONENT;
391
391
392 COMPONENT RR_Arbiter_4
392 COMPONENT RR_Arbiter_4
393 PORT (
393 PORT (
394 clk : IN STD_LOGIC;
394 clk : IN STD_LOGIC;
395 rstn : IN STD_LOGIC;
395 rstn : IN STD_LOGIC;
396 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
396 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
397 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
397 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
398 END COMPONENT;
398 END COMPONENT;
399
399
400 COMPONENT Clock_Divider IS
400 COMPONENT Clock_Divider IS
401 GENERIC(N : INTEGER := 10);
401 GENERIC(N : INTEGER := 10);
402 PORT(
402 PORT(
403 clk, rst : IN STD_LOGIC;
403 clk, rst : IN STD_LOGIC;
404 sclk : OUT STD_LOGIC);
404 sclk : OUT STD_LOGIC);
405 END COMPONENT;
405 END COMPONENT;
406
406
407 COMPONENT ramp_generator
407 COMPONENT ramp_generator
408 GENERIC (
408 GENERIC (
409 DATA_SIZE : INTEGER;
409 DATA_SIZE : INTEGER;
410 VALUE_UNSIGNED_INIT : INTEGER;
410 VALUE_UNSIGNED_INIT : INTEGER;
411 VALUE_UNSIGNED_INCR : INTEGER;
411 VALUE_UNSIGNED_INCR : INTEGER;
412 VALUE_UNSIGNED_MASK : INTEGER);
412 VALUE_UNSIGNED_MASK : INTEGER);
413 PORT (
413 PORT (
414 clk : IN STD_LOGIC;
414 clk : IN STD_LOGIC;
415 rstn : IN STD_LOGIC;
415 rstn : IN STD_LOGIC;
416 new_data : IN STD_LOGIC;
416 new_data : IN STD_LOGIC;
417 output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0));
417 output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0));
418 END COMPONENT;
418 END COMPONENT;
419
419
420 COMPONENT TimeGenAdvancedTrigger
420 COMPONENT TimeGenAdvancedTrigger
421 PORT(
421 PORT(
422 clk : IN STD_LOGIC;
422 clk : IN STD_LOGIC;
423 rstn : IN STD_LOGIC;
423 rstn : IN STD_LOGIC;
424
424
425 SPW_Tickout : IN STD_LOGIC;
425 SPW_Tickout : IN STD_LOGIC;
426
426
427 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
427 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
428 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
428 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
429
429
430 TrigPeriod : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15
430 TrigPeriod : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15
431 TrigShift : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps
431 TrigShift : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps
432 Restart : IN STD_LOGIC;
432 Restart : IN STD_LOGIC;
433 StartDate : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch
433 StartDate : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch
434
434
435 BypassTickout : IN STD_LOGIC; -- if set then Trigger output is driven by SPW tickout
435 BypassTickout : IN STD_LOGIC; -- if set then Trigger output is driven by SPW tickout
436 -- else Trigger output is driven by advanced trig
436 -- else Trigger output is driven by advanced trig
437 Trigger : OUT STD_LOGIC
437 Trigger : OUT STD_LOGIC
438
438
439 );
439 );
440 END COMPONENT;
440 END COMPONENT;
441
441
442 END;
442 END;
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@@ -1,525 +1,465
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:17:05 07/02/2012
5 -- Create Date: 11:17:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: apb_lfr_time_management - Behavioral
7 -- Module Name: apb_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 USE lpp.general_purpose.ALL;
30 USE lpp.lpp_lfr_management.ALL;
30 USE lpp.lpp_lfr_management.ALL;
31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
32 USE lpp.lpp_cna.ALL;
32 USE lpp.lpp_cna.ALL;
33 LIBRARY techmap;
33 LIBRARY techmap;
34 USE techmap.gencomp.ALL;
34 USE techmap.gencomp.ALL;
35
35
36
36
37 ENTITY apb_lfr_management IS
37 ENTITY apb_lfr_management IS
38
38
39 GENERIC(
39 GENERIC(
40 tech : INTEGER := 0;
40 tech : INTEGER := 0;
41 pindex : INTEGER := 0; --! APB slave index
41 pindex : INTEGER := 0; --! APB slave index
42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
44 -- FIRST_DIVISION : INTEGER := 374;
44 -- FIRST_DIVISION : INTEGER := 374;
45 NB_SECOND_DESYNC : INTEGER := 60
45 NB_SECOND_DESYNC : INTEGER := 60
46 );
46 );
47
47
48 PORT (
48 PORT (
49 clk25MHz : IN STD_LOGIC; --! Clock
49 clk25MHz : IN STD_LOGIC; --! Clock
50 resetn_25MHz : IN STD_LOGIC; --! Reset
50 resetn_25MHz : IN STD_LOGIC; --! Reset
51 -- clk24_576MHz : IN STD_LOGIC; --! secondary clock
51 -- clk24_576MHz : IN STD_LOGIC; --! secondary clock
52 -- resetn_24_576MHz : IN STD_LOGIC; --! Reset
52 -- resetn_24_576MHz : IN STD_LOGIC; --! Reset
53
53
54 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
54 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
55
55
56 apbi : IN apb_slv_in_type; --! APB slave input signals
56 apbi : IN apb_slv_in_type; --! APB slave input signals
57 apbo : OUT apb_slv_out_type; --! APB slave output signals
57 apbo : OUT apb_slv_out_type; --! APB slave output signals
58 ---------------------------------------------------------------------------
58 ---------------------------------------------------------------------------
59 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
59 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
60 HK_val : IN STD_LOGIC;
60 HK_val : IN STD_LOGIC;
61 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
62 ---------------------------------------------------------------------------
62 ---------------------------------------------------------------------------
63 DAC_SDO : OUT STD_LOGIC;
63 DAC_SDO : OUT STD_LOGIC;
64 DAC_SCK : OUT STD_LOGIC;
64 DAC_SCK : OUT STD_LOGIC;
65 DAC_SYNC : OUT STD_LOGIC;
65 DAC_SYNC : OUT STD_LOGIC;
66 DAC_CAL_EN : OUT STD_LOGIC;
66 DAC_CAL_EN : OUT STD_LOGIC;
67 ---------------------------------------------------------------------------
67 ---------------------------------------------------------------------------
68 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
68 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
69 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
69 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
70 ---------------------------------------------------------------------------
70 ---------------------------------------------------------------------------
71 LFR_soft_rstn : OUT STD_LOGIC
71 LFR_soft_rstn : OUT STD_LOGIC
72 );
72 );
73
73
74 END apb_lfr_management;
74 END apb_lfr_management;
75
75
76 ARCHITECTURE Behavioral OF apb_lfr_management IS
76 ARCHITECTURE Behavioral OF apb_lfr_management IS
77
77
78 CONSTANT REVISION : INTEGER := 1;
78 CONSTANT REVISION : INTEGER := 1;
79 CONSTANT pconfig : apb_config_type := (
79 CONSTANT pconfig : apb_config_type := (
80 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
80 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
81 1 => apb_iobar(paddr, pmask)
81 1 => apb_iobar(paddr, pmask)
82 );
82 );
83
83
84 TYPE apb_lfr_time_management_Reg IS RECORD
84 TYPE apb_lfr_time_management_Reg IS RECORD
85 ctrl : STD_LOGIC;
85 ctrl : STD_LOGIC;
86 soft_reset : STD_LOGIC;
86 soft_reset : STD_LOGIC;
87 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
87 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
88 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
88 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
89 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
89 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
90 LFR_soft_reset : STD_LOGIC;
90 LFR_soft_reset : STD_LOGIC;
91 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
93 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
93 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
94 END RECORD;
94 END RECORD;
95 SIGNAL r : apb_lfr_time_management_Reg;
95 SIGNAL r : apb_lfr_time_management_Reg;
96
96
97 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL force_tick : STD_LOGIC;
98 SIGNAL force_tick : STD_LOGIC;
99 SIGNAL previous_force_tick : STD_LOGIC;
99 SIGNAL previous_force_tick : STD_LOGIC;
100 SIGNAL soft_tick : STD_LOGIC;
100 SIGNAL soft_tick : STD_LOGIC;
101
101
102 SIGNAL coarsetime_reg_updated : STD_LOGIC;
102 SIGNAL coarsetime_reg_updated : STD_LOGIC;
103 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
103 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
104
104
105 --SIGNAL coarse_time_new : STD_LOGIC;
105 --SIGNAL coarse_time_new : STD_LOGIC;
106 SIGNAL coarse_time_new_49 : STD_LOGIC;
106 SIGNAL coarse_time_new_49 : STD_LOGIC;
107 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
109
109
110 --SIGNAL fine_time_new : STD_LOGIC;
110 --SIGNAL fine_time_new : STD_LOGIC;
111 --SIGNAL fine_time_new_temp : STD_LOGIC;
111 --SIGNAL fine_time_new_temp : STD_LOGIC;
112 SIGNAL fine_time_new_49 : STD_LOGIC;
112 SIGNAL fine_time_new_49 : STD_LOGIC;
113 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
113 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
114 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
114 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
115 SIGNAL tick : STD_LOGIC;
115 SIGNAL tick : STD_LOGIC;
116 SIGNAL new_timecode : STD_LOGIC;
116 SIGNAL new_timecode : STD_LOGIC;
117 SIGNAL new_coarsetime : STD_LOGIC;
117 SIGNAL new_coarsetime : STD_LOGIC;
118
118
119 SIGNAL time_new_49 : STD_LOGIC;
119 SIGNAL time_new_49 : STD_LOGIC;
120 SIGNAL time_new : STD_LOGIC;
120 SIGNAL time_new : STD_LOGIC;
121
121
122 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
123 SIGNAL force_reset : STD_LOGIC;
123 SIGNAL force_reset : STD_LOGIC;
124 SIGNAL previous_force_reset : STD_LOGIC;
124 SIGNAL previous_force_reset : STD_LOGIC;
125 SIGNAL soft_reset : STD_LOGIC;
125 SIGNAL soft_reset : STD_LOGIC;
126
126
127 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
128 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
128 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
129
129
130 SIGNAL previous_fine_time_bit : STD_LOGIC;
130 SIGNAL previous_fine_time_bit : STD_LOGIC;
131
131
132 SIGNAL rstn_LFR_TM : STD_LOGIC;
132 SIGNAL rstn_LFR_TM : STD_LOGIC;
133
133
134 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
135 -- DAC
135 -- DAC
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 CONSTANT PRESZ : INTEGER := 8;
137 CONSTANT PRESZ : INTEGER := 8;
138 CONSTANT CPTSZ : INTEGER := 16;
138 CONSTANT CPTSZ : INTEGER := 16;
139 CONSTANT datawidth : INTEGER := 18;
139 CONSTANT datawidth : INTEGER := 18;
140 CONSTANT dacresolution : INTEGER := 12;
140 CONSTANT dacresolution : INTEGER := 12;
141 CONSTANT abits : INTEGER := 8;
141 CONSTANT abits : INTEGER := 8;
142
142
143 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
143 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
144 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
144 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
145 SIGNAL Reload : STD_LOGIC;
145 SIGNAL Reload : STD_LOGIC;
146 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
146 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
147 SIGNAL WEN : STD_LOGIC;
147 SIGNAL WEN : STD_LOGIC;
148 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
148 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
149 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
149 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
150 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
150 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
151 SIGNAL INTERLEAVED : STD_LOGIC;
151 SIGNAL INTERLEAVED : STD_LOGIC;
152 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
153 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
154
155 signal fine_time_reg_info : std_logic_vector(26 downto 0);
154
156
155 BEGIN
157 BEGIN
156
158
157 LFR_soft_rstn <= NOT r.LFR_soft_reset;
159 LFR_soft_rstn <= NOT r.LFR_soft_reset;
158
160
159 PROCESS(resetn_25MHz, clk25MHz)
161 PROCESS(resetn_25MHz, clk25MHz)
160 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
162 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
161 BEGIN
163 BEGIN
162
164
163 IF resetn_25MHz = '0' THEN
165 IF resetn_25MHz = '0' THEN
164 Rdata <= (OTHERS => '0');
166 Rdata <= (OTHERS => '0');
165 r.coarse_time_load <= (OTHERS => '0');
167 r.coarse_time_load <= (OTHERS => '0');
166 r.soft_reset <= '0';
168 r.soft_reset <= '0';
167 r.ctrl <= '0';
169 r.ctrl <= '0';
168 r.LFR_soft_reset <= '1';
170 r.LFR_soft_reset <= '1';
169
171
170 force_tick <= '0';
172 force_tick <= '0';
171 previous_force_tick <= '0';
173 previous_force_tick <= '0';
172 soft_tick <= '0';
174 soft_tick <= '0';
173
175
174 coarsetime_reg_updated <= '0';
176 coarsetime_reg_updated <= '0';
175 --DAC
177 --DAC
176 pre <= (OTHERS => '1');
178 pre <= (OTHERS => '1');
177 N <= (OTHERS => '1');
179 N <= (OTHERS => '1');
178 Reload <= '1';
180 Reload <= '1';
179 DATA_IN <= (OTHERS => '0');
181 DATA_IN <= (OTHERS => '0');
180 WEN <= '1';
182 WEN <= '1';
181 LOAD_ADDRESSN <= '1';
183 LOAD_ADDRESSN <= '1';
182 ADDRESS_IN <= (OTHERS => '1');
184 ADDRESS_IN <= (OTHERS => '1');
183 INTERLEAVED <= '0';
185 INTERLEAVED <= '0';
184 DAC_CFG <= (OTHERS => '0');
186 DAC_CFG <= (OTHERS => '0');
185 --
187 --
186 DAC_CAL_EN_s <= '0';
188 DAC_CAL_EN_s <= '0';
187 force_reset <= '0';
189 force_reset <= '0';
190
188 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
191 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
189 coarsetime_reg_updated <= '0';
192 coarsetime_reg_updated <= '0';
190
193
191 force_tick <= r.ctrl;
194 force_tick <= r.ctrl;
192 previous_force_tick <= force_tick;
195 previous_force_tick <= force_tick;
193 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
196 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
194 soft_tick <= '1';
197 soft_tick <= '1';
195 ELSE
198 ELSE
196 soft_tick <= '0';
199 soft_tick <= '0';
197 END IF;
200 END IF;
198
201
199 force_reset <= r.soft_reset;
202 force_reset <= r.soft_reset;
200 previous_force_reset <= force_reset;
203 previous_force_reset <= force_reset;
201 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
204 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
202 soft_reset <= '1';
205 soft_reset <= '1';
203 ELSE
206 ELSE
204 soft_reset <= '0';
207 soft_reset <= '0';
205 END IF;
208 END IF;
206
209
207 paddr := "000000";
210 paddr := "000000";
208 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
211 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
209 Rdata <= (OTHERS => '0');
212 Rdata <= (OTHERS => '0');
210
213
211 LOAD_ADDRESSN <= '1';
214 LOAD_ADDRESSN <= '1';
212 WEN <= '1';
215 WEN <= '1';
213
216
214 IF apbi.psel(pindex) = '1' THEN
217 IF apbi.psel(pindex) = '1' THEN
215 --APB READ OP
218 --APB READ OP
216 CASE paddr(7 DOWNTO 2) IS
219 CASE paddr(7 DOWNTO 2) IS
217 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
220 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
218 Rdata(0) <= r.ctrl;
221 Rdata(0) <= r.ctrl;
219 Rdata(1) <= r.soft_reset;
222 Rdata(1) <= r.soft_reset;
220 Rdata(2) <= r.LFR_soft_reset;
223 Rdata(2) <= r.LFR_soft_reset;
221 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
224 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
222 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
225 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
223 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
226 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
224 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
227 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
225 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
228 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
226 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
229 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
227 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
230 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
228 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
231 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
229 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
232 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
230 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
233 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
231 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
234 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
232 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
235 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
233 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
236 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
234 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
237 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
235 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
238 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
236 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
239 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
237 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
240 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
238 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
241 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
239 Rdata(3 DOWNTO 0) <= DAC_CFG;
242 Rdata(3 DOWNTO 0) <= DAC_CFG;
240 Rdata(4) <= Reload;
243 Rdata(4) <= Reload;
241 Rdata(5) <= INTERLEAVED;
244 Rdata(5) <= INTERLEAVED;
242 Rdata(6) <= DAC_CAL_EN_s;
245 Rdata(6) <= DAC_CAL_EN_s;
243 Rdata(31 DOWNTO 7) <= (OTHERS => '0');
246 Rdata(31 DOWNTO 7) <= (OTHERS => '0');
244 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
247 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
245 Rdata(PRESZ-1 DOWNTO 0) <= pre;
248 Rdata(PRESZ-1 DOWNTO 0) <= pre;
246 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
249 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
247 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
250 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
248 Rdata(CPTSZ-1 DOWNTO 0) <= N;
251 Rdata(CPTSZ-1 DOWNTO 0) <= N;
249 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
252 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
250 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
253 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
251 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
254 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
252 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
255 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
253 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
256 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
254 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
257 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
255 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
258 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
259 WHEN ADDR_LFR_MANAGMENT_TIME_FINE_DELTA =>
260 Rdata(26 downto 0) <= fine_time_reg_info;
256 WHEN OTHERS =>
261 WHEN OTHERS =>
257 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
262 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
258 END CASE;
263 END CASE;
259
264
260 --APB Write OP
265 --APB Write OP
261 IF (apbi.pwrite AND apbi.penable) = '1' THEN
266 IF (apbi.pwrite AND apbi.penable) = '1' THEN
262 CASE paddr(7 DOWNTO 2) IS
267 CASE paddr(7 DOWNTO 2) IS
263 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
268 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
264 r.ctrl <= apbi.pwdata(0);
269 r.ctrl <= apbi.pwdata(0);
265 r.soft_reset <= apbi.pwdata(1);
270 r.soft_reset <= apbi.pwdata(1);
266 r.LFR_soft_reset <= apbi.pwdata(2);
271 r.LFR_soft_reset <= apbi.pwdata(2);
267 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
272 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
268 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
273 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
269 coarsetime_reg_updated <= '1';
274 coarsetime_reg_updated <= '1';
270 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
275 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
271 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
276 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
272 Reload <= apbi.pwdata(4);
277 Reload <= apbi.pwdata(4);
273 INTERLEAVED <= apbi.pwdata(5);
278 INTERLEAVED <= apbi.pwdata(5);
274 DAC_CAL_EN_s <= apbi.pwdata(6);
279 DAC_CAL_EN_s <= apbi.pwdata(6);
275 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
280 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
276 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
281 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
277 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
282 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
278 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
283 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
279 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
284 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
280 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
285 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
281 LOAD_ADDRESSN <= '0';
286 LOAD_ADDRESSN <= '0';
282 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
287 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
283 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
288 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
284 WEN <= '0';
289 WEN <= '0';
285
290
286 WHEN OTHERS =>
291 WHEN OTHERS =>
287 NULL;
292 NULL;
288 END CASE;
293 END CASE;
289 ELSE
294 ELSE
290 IF r.ctrl = '1' THEN
295 IF r.ctrl = '1' THEN
291 r.ctrl <= '0';
296 r.ctrl <= '0';
292 END IF;
297 END IF;
293 IF r.soft_reset = '1' THEN
298 IF r.soft_reset = '1' THEN
294 r.soft_reset <= '0';
299 r.soft_reset <= '0';
295 END IF;
300 END IF;
296 END IF;
301 END IF;
297
302
298 END IF;
303 END IF;
299
304
300 END IF;
305 END IF;
301 END PROCESS;
306 END PROCESS;
302
307
303 apbo.pirq <= (OTHERS => '0');
308 apbo.pirq <= (OTHERS => '0');
304 apbo.prdata <= Rdata;
309 apbo.prdata <= Rdata;
305 apbo.pconfig <= pconfig;
310 apbo.pconfig <= pconfig;
306 apbo.pindex <= pindex;
311 apbo.pindex <= pindex;
307
312
308
313
309
314
310
315
311
316
312
317
313
314
315
316
317
318
319
320
318
321 -----------------------------------------------------------------------------
319 -----------------------------------------------------------------------------
322 -- IN
320 -- IN
323 coarse_time <= r.coarse_time;
321 coarse_time <= r.coarse_time;
324 fine_time <= r.fine_time;
322 fine_time <= r.fine_time;
325 coarsetime_reg <= r.coarse_time_load;
323 coarsetime_reg <= r.coarse_time_load;
326 -----------------------------------------------------------------------------
324 -----------------------------------------------------------------------------
327
325
328 -----------------------------------------------------------------------------
326 -----------------------------------------------------------------------------
329 -- OUT
327 -- OUT
330 r.coarse_time <= coarse_time_s;
328 r.coarse_time <= coarse_time_s;
331 r.fine_time <= fine_time_s;
329 r.fine_time <= fine_time_s;
332 -----------------------------------------------------------------------------
330 -----------------------------------------------------------------------------
333
331
334 -----------------------------------------------------------------------------
332 -----------------------------------------------------------------------------
335 tick <= grspw_tick OR soft_tick;
333 tick <= grspw_tick OR soft_tick;
336
334
337 --SYNC_VALID_BIT_1 : SYNC_VALID_BIT
338 -- GENERIC MAP (
339 -- NB_FF_OF_SYNC => 2)
340 -- PORT MAP (
341 -- clk_in => clk25MHz,
342 -- rstn_in => resetn_25MHz,
343 -- clk_out => clk24_576MHz,
344 -- rstn_out => resetn_24_576MHz,
345 -- sin => tick,
346 -- sout => new_timecode);
347 new_timecode <= tick;
335 new_timecode <= tick;
348
349 --SYNC_VALID_BIT_2 : SYNC_VALID_BIT
350 -- GENERIC MAP (
351 -- NB_FF_OF_SYNC => 2)
352 -- PORT MAP (
353 -- clk_in => clk25MHz,
354 -- rstn_in => resetn_25MHz,
355 -- clk_out => clk24_576MHz,
356 -- rstn_out => resetn_24_576MHz,
357 -- sin => coarsetime_reg_updated,
358 -- sout => new_coarsetime);
359
336
360 new_coarsetime <= coarsetime_reg_updated;
337 new_coarsetime <= coarsetime_reg_updated;
361
362 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
363 -- GENERIC MAP (
364 -- NB_FF_OF_SYNC => 2)
365 -- PORT MAP (
366 -- clk_in => clk25MHz,
367 -- rstn_in => resetn_25MHz,
368 -- clk_out => clk24_576MHz,
369 -- rstn_out => resetn_24_576MHz,
370 -- sin => soft_reset,
371 -- sout => soft_reset_sync);
372
373
338
374 -----------------------------------------------------------------------------
339 -----------------------------------------------------------------------------
375 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
340 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
376
341
377 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
378 -- GENERIC MAP (
379 -- NB_FF_OF_SYNC => 2)
380 -- PORT MAP (
381 -- clk_in => clk24_576MHz,
382 -- rstn_in => resetn_24_576MHz,
383 -- clk_out => clk25MHz,
384 -- rstn_out => resetn_25MHz,
385 -- sin => time_new_49,
386 -- sout => time_new);
387
388 time_new <= time_new_49;
342 time_new <= time_new_49;
389
390 --PROCESS (clk25MHz, resetn_25MHz)
391 --BEGIN -- PROCESS
392 -- IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
393 -- fine_time_s <= (OTHERS => '0');
394 -- coarse_time_s <= (OTHERS => '0');
395 -- ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
396 -- IF time_new = '1' THEN
397 -- END IF;
398 -- END IF;
399 --END PROCESS;
400
343
401 fine_time_s <= fine_time_49;
344 fine_time_s <= fine_time_49;
345
402 coarse_time_s <= coarse_time_49;
346 coarse_time_s <= coarse_time_49;
403
347
404
348
405 rstn_LFR_TM <= '0' WHEN resetn_25MHz = '0' ELSE
349 rstn_LFR_TM <= '0' WHEN resetn_25MHz = '0' ELSE
406 '0' WHEN soft_reset = '1' ELSE
350 '0' WHEN soft_reset = '1' ELSE
407 '1';
351 '1';
408
352
409 -----------------------------------------------------------------------------
353 -----------------------------------------------------------------------------
410 -- LFR_TIME_MANAGMENT
354 -- LFR_TIME_MANAGMENT
411 -----------------------------------------------------------------------------
355 -----------------------------------------------------------------------------
412 lfr_time_management_1 : lfr_time_management
356 lfr_time_management_1 : lfr_time_management
413 GENERIC MAP (
357 GENERIC MAP (
414 --FIRST_DIVISION => FIRST_DIVISION,
358 --FIRST_DIVISION => FIRST_DIVISION,
415 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
359 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
416 PORT MAP (
360 PORT MAP (
417 clk => clk25MHz,
361 clk => clk25MHz,
418 rstn => rstn_LFR_TM,
362 rstn => rstn_LFR_TM,
419
363
420 tick => new_timecode,
364 tick => new_timecode,
421 new_coarsetime => new_coarsetime,
365 new_coarsetime => new_coarsetime,
422 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
366 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
423
367
424 fine_time => fine_time_49,
368 fine_time => fine_time_49,
425 fine_time_new => fine_time_new_49,
369 fine_time_new => fine_time_new_49,
426 coarse_time => coarse_time_49,
370 coarse_time => coarse_time_49,
427 coarse_time_new => coarse_time_new_49);
371 coarse_time_new => coarse_time_new_49,
372
373 ft_counter_low => fine_time_reg_info( 8 downto 0),
374 ft_counter_low_max_value => fine_time_reg_info(26 downto 25),
375 ft_counter => fine_time_reg_info(24 downto 9)
376 );
428
377
429
378
430
379
431 -----------------------------------------------------------------------------
380 -----------------------------------------------------------------------------
432 -- HK
381 -- HK
433 -----------------------------------------------------------------------------
382 -----------------------------------------------------------------------------
434
383
435 PROCESS (clk25MHz, resetn_25MHz)
384 PROCESS (clk25MHz, resetn_25MHz)
436 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
385 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
437 -- for each HK, the update frequency is freq/3
386 -- for each HK, the update frequency is freq/3
438 --
387 --
439 -- for 14, the update frequency is
388 -- for 14, the update frequency is
440 -- 4Hz and update for each
389 -- 4Hz and update for each
441 -- HK is 1.33Hz
390 -- HK is 1.33Hz
442 BEGIN -- PROCESS
391 BEGIN -- PROCESS
443 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
392 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
444
393
445 r.HK_temp_0 <= (OTHERS => '0');
394 r.HK_temp_0 <= (OTHERS => '0');
446 r.HK_temp_1 <= (OTHERS => '0');
395 r.HK_temp_1 <= (OTHERS => '0');
447 r.HK_temp_2 <= (OTHERS => '0');
396 r.HK_temp_2 <= (OTHERS => '0');
448
397
449 HK_sel_s <= "00";
398 HK_sel_s <= "00";
450
399
451 previous_fine_time_bit <= '0';
400 previous_fine_time_bit <= '0';
452
401
453 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
402 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
454
403
455 IF HK_val = '1' THEN
404 IF HK_val = '1' THEN
456 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
405 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
457 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
406 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
458 CASE HK_sel_s IS
407 CASE HK_sel_s IS
459 WHEN "00" =>
408 WHEN "00" =>
460 r.HK_temp_0 <= HK_sample;
409 r.HK_temp_0 <= HK_sample;
461 HK_sel_s <= "01";
410 HK_sel_s <= "01";
462 WHEN "01" =>
411 WHEN "01" =>
463 r.HK_temp_1 <= HK_sample;
412 r.HK_temp_1 <= HK_sample;
464 HK_sel_s <= "10";
413 HK_sel_s <= "10";
465 WHEN "10" =>
414 WHEN "10" =>
466 r.HK_temp_2 <= HK_sample;
415 r.HK_temp_2 <= HK_sample;
467 HK_sel_s <= "00";
416 HK_sel_s <= "00";
468 WHEN OTHERS => NULL;
417 WHEN OTHERS => NULL;
469 END CASE;
418 END CASE;
470 END IF;
419 END IF;
471 END IF;
420 END IF;
472
421
473 END IF;
422 END IF;
474 END PROCESS;
423 END PROCESS;
475
424
476 HK_sel <= HK_sel_s;
425 HK_sel <= HK_sel_s;
477
426
478
427
479
428
480
481
482
483
484
485
486
487
488
489
429
490
430
491 -----------------------------------------------------------------------------
431 -----------------------------------------------------------------------------
492 -- DAC
432 -- DAC
493 -----------------------------------------------------------------------------
433 -----------------------------------------------------------------------------
494 cal : lfr_cal_driver
434 cal : lfr_cal_driver
495 GENERIC MAP(
435 GENERIC MAP(
496 tech => tech,
436 tech => tech,
497 PRESZ => PRESZ,
437 PRESZ => PRESZ,
498 CPTSZ => CPTSZ,
438 CPTSZ => CPTSZ,
499 datawidth => datawidth,
439 datawidth => datawidth,
500 abits => abits
440 abits => abits
501 )
441 )
502 PORT MAP(
442 PORT MAP(
503 clk => clk25MHz,
443 clk => clk25MHz,
504 rstn => resetn_25MHz,
444 rstn => resetn_25MHz,
505
445
506 pre => pre,
446 pre => pre,
507 N => N,
447 N => N,
508 Reload => Reload,
448 Reload => Reload,
509 DATA_IN => DATA_IN,
449 DATA_IN => DATA_IN,
510 WEN => WEN,
450 WEN => WEN,
511 LOAD_ADDRESSN => LOAD_ADDRESSN,
451 LOAD_ADDRESSN => LOAD_ADDRESSN,
512 ADDRESS_IN => ADDRESS_IN,
452 ADDRESS_IN => ADDRESS_IN,
513 ADDRESS_OUT => ADDRESS_OUT,
453 ADDRESS_OUT => ADDRESS_OUT,
514 INTERLEAVED => INTERLEAVED,
454 INTERLEAVED => INTERLEAVED,
515 DAC_CFG => DAC_CFG,
455 DAC_CFG => DAC_CFG,
516
456
517 SYNC => DAC_SYNC,
457 SYNC => DAC_SYNC,
518 DOUT => DAC_SDO,
458 DOUT => DAC_SDO,
519 SCLK => DAC_SCK,
459 SCLK => DAC_SCK,
520 SMPCLK => OPEN --DAC_SMPCLK
460 SMPCLK => OPEN --DAC_SMPCLK
521 );
461 );
522
462
523 DAC_CAL_EN <= DAC_CAL_EN_s;
463 DAC_CAL_EN <= DAC_CAL_EN_s;
524
464
525 END Behavioral;
465 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,106 +1,131
1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.general_purpose.ALL;
6 USE lpp.general_purpose.ALL;
7 USE lpp.lpp_lfr_management.ALL;
7 USE lpp.lpp_lfr_management.ALL;
8
8
9 ENTITY fine_time_counter IS
9 ENTITY fine_time_counter IS
10
10
11 GENERIC (
11 GENERIC (
12 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040"
12 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040"
13 );
13 );
14
14
15 PORT (
15 PORT (
16 clk : IN STD_LOGIC;
16 clk : IN STD_LOGIC;
17 rstn : IN STD_LOGIC;
17 rstn : IN STD_LOGIC;
18 --
18 --
19 tick : IN STD_LOGIC;
19 tick : IN STD_LOGIC;
20 fsm_transition : IN STD_LOGIC;
20 fsm_transition : IN STD_LOGIC;
21
21
22 FT_max : OUT STD_LOGIC;
22 FT_max : OUT STD_LOGIC;
23 FT_half : OUT STD_LOGIC;
23 FT_half : OUT STD_LOGIC;
24 FT_wait : OUT STD_LOGIC;
24 FT_wait : OUT STD_LOGIC;
25 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
25 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
26 fine_time_new : OUT STD_LOGIC
26 fine_time_new : OUT STD_LOGIC;
27
28 ft_counter_low : out STD_LOGIC_VECTOR( 8 downto 0);
29 ft_counter_low_max_value : out STD_LOGIC_VECTOR( 1 downto 0);
30 ft_counter : out STD_LOGIC_VECTOR(15 downto 0)
27 );
31 );
28
32
29 END fine_time_counter;
33 END fine_time_counter;
30
34
31 ARCHITECTURE beh OF fine_time_counter IS
35 ARCHITECTURE beh OF fine_time_counter IS
32
36
33 SIGNAL new_ft_counter : STD_LOGIC_VECTOR(8 DOWNTO 0);
37 SIGNAL new_ft_counter : STD_LOGIC_VECTOR(8 DOWNTO 0);
34 SIGNAL new_ft : STD_LOGIC;
38 SIGNAL new_ft : STD_LOGIC;
35 SIGNAL fine_time_counter : STD_LOGIC_VECTOR(15 DOWNTO 0);
39 SIGNAL fine_time_counter : STD_LOGIC_VECTOR(15 DOWNTO 0);
36
40
37 SIGNAL fine_time_max_value : STD_LOGIC_VECTOR(8 DOWNTO 0);
41 SIGNAL fine_time_max_value : STD_LOGIC_VECTOR(8 DOWNTO 0);
38 SIGNAL tick_value_gen : STD_LOGIC;
42 SIGNAL tick_value_gen : STD_LOGIC;
39 SIGNAL FT_max_s : STD_LOGIC;
43 SIGNAL FT_max_s : STD_LOGIC;
40
44
45 SIGNAL ft_counter_low_max_value_s : STD_LOGIC_VECTOR( 1 downto 0);
46
41 BEGIN -- beh
47 BEGIN -- beh
42
48
43 tick_value_gen <= tick OR FT_max_s;
49 tick_value_gen <= tick OR FT_max_s;
44
50
45 fine_time_max_value_gen_1: fine_time_max_value_gen
51 fine_time_max_value_gen_1: fine_time_max_value_gen
46 PORT MAP (
52 PORT MAP (
47 clk => clk,
53 clk => clk,
48 rstn => rstn,
54 rstn => rstn,
49 tick => tick_value_gen,
55 tick => tick_value_gen,
50 fine_time_add => new_ft,
56 fine_time_add => new_ft,
51 fine_time_max_value => fine_time_max_value);
57 fine_time_max_value => fine_time_max_value);
52
58
53 counter_1 : general_counter
59 counter_1 : general_counter
54 GENERIC MAP (
60 GENERIC MAP (
55 CYCLIC => '1',
61 CYCLIC => '1',
56 NB_BITS_COUNTER => 9,
62 NB_BITS_COUNTER => 9,
57 RST_VALUE => 0
63 RST_VALUE => 0
58 )
64 )
59 PORT MAP (
65 PORT MAP (
60 clk => clk,
66 clk => clk,
61 rstn => rstn,
67 rstn => rstn,
62 MAX_VALUE => fine_time_max_value,
68 MAX_VALUE => fine_time_max_value,
63 set => tick,
69 set => tick,
64 set_value => (OTHERS => '0'),
70 set_value => (OTHERS => '0'),
65 add1 => '1',
71 add1 => '1',
66 counter => new_ft_counter);
72 counter => new_ft_counter);
67
73
68 new_ft <= '1' WHEN new_ft_counter = fine_time_max_value ELSE '0';
74 new_ft <= '1' WHEN new_ft_counter = fine_time_max_value ELSE '0';
69
75
70 counter_2 : general_counter
76 counter_2 : general_counter
71 GENERIC MAP (
77 GENERIC MAP (
72 CYCLIC => '1',
78 CYCLIC => '1',
73 NB_BITS_COUNTER => 16,
79 NB_BITS_COUNTER => 16,
74 RST_VALUE => 0
80 RST_VALUE => 0
75 )
81 )
76 PORT MAP (
82 PORT MAP (
77 clk => clk,
83 clk => clk,
78 rstn => rstn,
84 rstn => rstn,
79 MAX_VALUE => X"FFFF",
85 MAX_VALUE => X"FFFF",
80 set => tick,
86 set => tick,
81 set_value => (OTHERS => '0'),
87 set_value => (OTHERS => '0'),
82 add1 => new_ft,
88 add1 => new_ft,
83 counter => fine_time_counter);
89 counter => fine_time_counter);
84
90
85 FT_max_s <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
91 FT_max_s <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
86
92
87 FT_max <= FT_max_s;
93 FT_max <= FT_max_s;
88 FT_half <= '1' WHEN fine_time_counter > X"7FFF" ELSE '0';
94 FT_half <= '1' WHEN fine_time_counter > X"7FFF" ELSE '0';
89 FT_wait <= '1' WHEN fine_time_counter > WAITING_TIME ELSE '0';
95 FT_wait <= '1' WHEN fine_time_counter > WAITING_TIME ELSE '0';
90
96
91 fine_time <= X"FFFF" WHEN fsm_transition = '1' ELSE fine_time_counter;
97 fine_time <= X"FFFF" WHEN fsm_transition = '1' ELSE fine_time_counter;
92
98
93 PROCESS (clk, rstn)
99 PROCESS (clk, rstn)
94 BEGIN -- PROCESS
100 BEGIN -- PROCESS
95 IF rstn = '0' THEN -- asynchronous reset (active low)
101 IF rstn = '0' THEN -- asynchronous reset (active low)
96 fine_time_new <= '0';
102 fine_time_new <= '0';
97 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
103 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
98 IF (new_ft = '1' AND fsm_transition = '0') OR tick = '1' THEN
104 IF (new_ft = '1' AND fsm_transition = '0') OR tick = '1' THEN
99 fine_time_new <= '1';
105 fine_time_new <= '1';
100 ELSE
106 ELSE
101 fine_time_new <= '0';
107 fine_time_new <= '0';
102 END IF;
108 END IF;
103 END IF;
109 END IF;
104 END PROCESS;
110 END PROCESS;
111
112 ft_counter_low_max_value_s <= "00" when fine_time_max_value = STD_LOGIC_VECTOR(to_unsigned(379,9)) else
113 "01" when fine_time_max_value = STD_LOGIC_VECTOR(to_unsigned(380,9)) else
114 "10";-- when fine_time_max_value = STD_LOGIC_VECTOR(to_unsigned(381,9))
115
116 process (clk, rstn) is
117 begin -- process
118 if rstn = '0' then -- asynchronous reset (active low)
119 ft_counter_low <= (others => '0');
120 ft_counter_low_max_value <= (others => '0');
121 ft_counter <= (others => '0');
122 elsif clk'event and clk = '1' then -- rising clock edge
123 if tick = '1' then
124 ft_counter_low <= new_ft_counter;
125 ft_counter_low_max_value <= ft_counter_low_max_value_s;
126 ft_counter <= fine_time_counter;
127 end if;
128 end if;
129 end process;
105
130
106 END beh;
131 END beh;
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@@ -1,160 +1,167
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:14:05 07/02/2012
5 -- Create Date: 11:14:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: lfr_time_management - Behavioral
7 -- Module Name: lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY lpp;
23 LIBRARY lpp;
24 USE lpp.lpp_lfr_management.ALL;
24 USE lpp.lpp_lfr_management.ALL;
25
25
26 ENTITY lfr_time_management IS
26 ENTITY lfr_time_management IS
27 GENERIC (
27 GENERIC (
28 NB_SECOND_DESYNC : INTEGER := 60);
28 NB_SECOND_DESYNC : INTEGER := 60);
29 PORT (
29 PORT (
30 clk : IN STD_LOGIC;
30 clk : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
32
32
33 tick : IN STD_LOGIC; -- transition signal information
33 tick : IN STD_LOGIC; -- transition signal information
34
34
35 new_coarsetime : IN STD_LOGIC; -- transition signal information
35 new_coarsetime : IN STD_LOGIC; -- transition signal information
36 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
36 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
37
37
38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
39 fine_time_new : OUT STD_LOGIC;
39 fine_time_new : OUT STD_LOGIC;
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
41 coarse_time_new : OUT STD_LOGIC
41 coarse_time_new : OUT STD_LOGIC;
42
43 ft_counter_low : out STD_LOGIC_VECTOR( 8 downto 0);
44 ft_counter_low_max_value : out STD_LOGIC_VECTOR( 1 downto 0);
45 ft_counter : out STD_LOGIC_VECTOR(15 downto 0)
42 );
46 );
43 END lfr_time_management;
47 END lfr_time_management;
44
48
45 ARCHITECTURE Behavioral OF lfr_time_management IS
49 ARCHITECTURE Behavioral OF lfr_time_management IS
46
50
47 SIGNAL FT_max : STD_LOGIC;
51 SIGNAL FT_max : STD_LOGIC;
48 SIGNAL FT_half : STD_LOGIC;
52 SIGNAL FT_half : STD_LOGIC;
49 SIGNAL FT_wait : STD_LOGIC;
53 SIGNAL FT_wait : STD_LOGIC;
50
54
51 TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
55 TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
52 SIGNAL state : state_fsm_time_management;
56 SIGNAL state : state_fsm_time_management;
53
57
54 SIGNAL fsm_desync : STD_LOGIC;
58 SIGNAL fsm_desync : STD_LOGIC;
55 SIGNAL fsm_transition : STD_LOGIC;
59 SIGNAL fsm_transition : STD_LOGIC;
56
60
57 SIGNAL set_TCU : STD_LOGIC;
61 SIGNAL set_TCU : STD_LOGIC;
58 SIGNAL CT_add1 : STD_LOGIC;
62 SIGNAL CT_add1 : STD_LOGIC;
59
63
60 SIGNAL new_coarsetime_reg : STD_LOGIC;
64 SIGNAL new_coarsetime_reg : STD_LOGIC;
61
65
62 BEGIN
66 BEGIN
63
67
64 -----------------------------------------------------------------------------
68 -----------------------------------------------------------------------------
65 --
69 --
66 -----------------------------------------------------------------------------
70 -----------------------------------------------------------------------------
67 PROCESS (clk, rstn)
71 PROCESS (clk, rstn)
68 BEGIN -- PROCESS
72 BEGIN -- PROCESS
69 IF rstn = '0' THEN -- asynchronous reset (active low)
73 IF rstn = '0' THEN -- asynchronous reset (active low)
70 new_coarsetime_reg <= '0';
74 new_coarsetime_reg <= '0';
71 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
75 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
72 IF new_coarsetime = '1' THEN
76 IF new_coarsetime = '1' THEN
73 new_coarsetime_reg <= '1';
77 new_coarsetime_reg <= '1';
74 ELSIF tick = '1' THEN
78 ELSIF tick = '1' THEN
75 new_coarsetime_reg <= '0';
79 new_coarsetime_reg <= '0';
76 END IF;
80 END IF;
77 END IF;
81 END IF;
78 END PROCESS;
82 END PROCESS;
79
83
80 -----------------------------------------------------------------------------
84 -----------------------------------------------------------------------------
81 -- FINE_TIME
85 -- FINE_TIME
82 -----------------------------------------------------------------------------
86 -----------------------------------------------------------------------------
83 fine_time_counter_1: fine_time_counter
87 fine_time_counter_1: fine_time_counter
84 GENERIC MAP (
88 GENERIC MAP (
85 WAITING_TIME => X"0040")
89 WAITING_TIME => X"0040")
86 PORT MAP (
90 PORT MAP (
87 clk => clk,
91 clk => clk,
88 rstn => rstn,
92 rstn => rstn,
89 tick => tick,
93 tick => tick,
90 fsm_transition => fsm_transition, -- todo
94 fsm_transition => fsm_transition, -- todo
91 FT_max => FT_max,
95 FT_max => FT_max,
92 FT_half => FT_half,
96 FT_half => FT_half,
93 FT_wait => FT_wait,
97 FT_wait => FT_wait,
94 fine_time => fine_time,
98 fine_time => fine_time,
95 fine_time_new => fine_time_new);
99 fine_time_new => fine_time_new,
96
100 ft_counter_low => ft_counter_low ,
101 ft_counter_low_max_value => ft_counter_low_max_value,
102 ft_counter => ft_counter
103 );
97 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
98 -- COARSE_TIME
105 -- COARSE_TIME
99 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
100 coarse_time_counter_1: coarse_time_counter
107 coarse_time_counter_1: coarse_time_counter
101 GENERIC MAP(
108 GENERIC MAP(
102 NB_SECOND_DESYNC => NB_SECOND_DESYNC )
109 NB_SECOND_DESYNC => NB_SECOND_DESYNC )
103 PORT MAP (
110 PORT MAP (
104 clk => clk,
111 clk => clk,
105 rstn => rstn,
112 rstn => rstn,
106 tick => tick,
113 tick => tick,
107 set_TCU => set_TCU, -- todo
114 set_TCU => set_TCU, -- todo
108 new_TCU => new_coarsetime_reg,
115 new_TCU => new_coarsetime_reg,
109 set_TCU_value => coarsetime_reg, -- todo
116 set_TCU_value => coarsetime_reg, -- todo
110 CT_add1 => CT_add1, -- todo
117 CT_add1 => CT_add1, -- todo
111 fsm_desync => fsm_desync, -- todo
118 fsm_desync => fsm_desync, -- todo
112 FT_max => FT_max,
119 FT_max => FT_max,
113 coarse_time => coarse_time,
120 coarse_time => coarse_time,
114 coarse_time_new => coarse_time_new);
121 coarse_time_new => coarse_time_new);
115
122
116 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
117 -- FSM
124 -- FSM
118 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
119 fsm_desync <= '1' WHEN state = DESYNC ELSE '0';
126 fsm_desync <= '1' WHEN state = DESYNC ELSE '0';
120 fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
127 fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
121
128
122 PROCESS (clk, rstn)
129 PROCESS (clk, rstn)
123 BEGIN -- PROCESS
130 BEGIN -- PROCESS
124 IF rstn = '0' THEN -- asynchronous reset (active low)
131 IF rstn = '0' THEN -- asynchronous reset (active low)
125 state <= DESYNC;
132 state <= DESYNC;
126 set_TCU <= '0';
133 set_TCU <= '0';
127 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
134 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
128 set_TCU <= '0';
135 set_TCU <= '0';
129 CASE state IS
136 CASE state IS
130 WHEN DESYNC =>
137 WHEN DESYNC =>
131 IF tick = '1' THEN
138 IF tick = '1' THEN
132 state <= SYNC;
139 state <= SYNC;
133 set_TCU <= new_coarsetime_reg;
140 set_TCU <= new_coarsetime_reg;
134 END IF;
141 END IF;
135 WHEN TRANSITION =>
142 WHEN TRANSITION =>
136 IF tick = '1' THEN
143 IF tick = '1' THEN
137 state <= SYNC;
144 state <= SYNC;
138 set_TCU <= new_coarsetime_reg;
145 set_TCU <= new_coarsetime_reg;
139 ELSIF FT_wait = '1' THEN
146 ELSIF FT_wait = '1' THEN
140 state <= DESYNC;
147 state <= DESYNC;
141 END IF;
148 END IF;
142 WHEN SYNC =>
149 WHEN SYNC =>
143 IF tick = '1' THEN
150 IF tick = '1' THEN
144 set_TCU <= new_coarsetime_reg;
151 set_TCU <= new_coarsetime_reg;
145 ELSIF FT_max = '1' THEN
152 ELSIF FT_max = '1' THEN
146 state <= TRANSITION;
153 state <= TRANSITION;
147 END IF;
154 END IF;
148 WHEN OTHERS => NULL;
155 WHEN OTHERS => NULL;
149 END CASE;
156 END CASE;
150 END IF;
157 END IF;
151 END PROCESS;
158 END PROCESS;
152
159
153
160
154 CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE
161 CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE
155 '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
162 '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
156 '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
163 '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
157 '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE
164 '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE
158 '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE
165 '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE
159 '0';
166 '0';
160 END Behavioral;
167 END Behavioral;
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@@ -1,144 +1,152
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 13:04:01 07/02/2012
5 -- Create Date: 13:04:01 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: lpp_lfr_time_management - Behavioral
7 -- Module Name: lpp_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 LIBRARY grlib;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
25 USE grlib.devices.ALL;
26
26
27 PACKAGE lpp_lfr_management IS
27 PACKAGE lpp_lfr_management IS
28
28
29 --***************************
29 --***************************
30 -- APB_LFR_MANAGEMENT
30 -- APB_LFR_MANAGEMENT
31
31
32 COMPONENT apb_lfr_management
32 COMPONENT apb_lfr_management
33 GENERIC (
33 GENERIC (
34 tech : INTEGER;
34 tech : INTEGER;
35 pindex : INTEGER;
35 pindex : INTEGER;
36 paddr : INTEGER;
36 paddr : INTEGER;
37 pmask : INTEGER;
37 pmask : INTEGER;
38 -- FIRST_DIVISION : INTEGER;
38 -- FIRST_DIVISION : INTEGER;
39 NB_SECOND_DESYNC : INTEGER);
39 NB_SECOND_DESYNC : INTEGER);
40 PORT (
40 PORT (
41 clk25MHz : IN STD_LOGIC;
41 clk25MHz : IN STD_LOGIC;
42 resetn_25MHz : IN STD_LOGIC;
42 resetn_25MHz : IN STD_LOGIC;
43 -- clk24_576MHz : IN STD_LOGIC;
43 -- clk24_576MHz : IN STD_LOGIC;
44 -- resetn_24_576MHz : IN STD_LOGIC;
44 -- resetn_24_576MHz : IN STD_LOGIC;
45 grspw_tick : IN STD_LOGIC;
45 grspw_tick : IN STD_LOGIC;
46 apbi : IN apb_slv_in_type;
46 apbi : IN apb_slv_in_type;
47 apbo : OUT apb_slv_out_type;
47 apbo : OUT apb_slv_out_type;
48 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
48 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
49 HK_val : IN STD_LOGIC;
49 HK_val : IN STD_LOGIC;
50 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
50 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 DAC_SDO : OUT STD_LOGIC;
51 DAC_SDO : OUT STD_LOGIC;
52 DAC_SCK : OUT STD_LOGIC;
52 DAC_SCK : OUT STD_LOGIC;
53 DAC_SYNC : OUT STD_LOGIC;
53 DAC_SYNC : OUT STD_LOGIC;
54 DAC_CAL_EN : OUT STD_LOGIC;
54 DAC_CAL_EN : OUT STD_LOGIC;
55 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
55 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
56 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
57 LFR_soft_rstn : OUT STD_LOGIC);
57 LFR_soft_rstn : OUT STD_LOGIC);
58 END COMPONENT;
58 END COMPONENT;
59
59
60 COMPONENT lfr_time_management
60 COMPONENT lfr_time_management
61 GENERIC (
61 GENERIC (
62 --FIRST_DIVISION : INTEGER;
62 --FIRST_DIVISION : INTEGER;
63 NB_SECOND_DESYNC : INTEGER);
63 NB_SECOND_DESYNC : INTEGER);
64 PORT (
64 PORT (
65 clk : IN STD_LOGIC;
65 clk : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
67 tick : IN STD_LOGIC;
67 tick : IN STD_LOGIC;
68 new_coarsetime : IN STD_LOGIC;
68 new_coarsetime : IN STD_LOGIC;
69 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
69 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
70 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
70 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
71 fine_time_new : OUT STD_LOGIC;
71 fine_time_new : OUT STD_LOGIC;
72 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 coarse_time_new : OUT STD_LOGIC);
73 coarse_time_new : OUT STD_LOGIC;
74 ft_counter_low : out STD_LOGIC_VECTOR( 8 downto 0);
75 ft_counter_low_max_value : out STD_LOGIC_VECTOR( 1 downto 0);
76 ft_counter : out STD_LOGIC_VECTOR(15 downto 0)
77 );
74 END COMPONENT;
78 END COMPONENT;
75
79
76 COMPONENT coarse_time_counter
80 COMPONENT coarse_time_counter
77 GENERIC (
81 GENERIC (
78 NB_SECOND_DESYNC : INTEGER);
82 NB_SECOND_DESYNC : INTEGER);
79 PORT (
83 PORT (
80 clk : IN STD_LOGIC;
84 clk : IN STD_LOGIC;
81 rstn : IN STD_LOGIC;
85 rstn : IN STD_LOGIC;
82 tick : IN STD_LOGIC;
86 tick : IN STD_LOGIC;
83 set_TCU : IN STD_LOGIC;
87 set_TCU : IN STD_LOGIC;
84 new_TCU : IN STD_LOGIC;
88 new_TCU : IN STD_LOGIC;
85 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
89 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 CT_add1 : IN STD_LOGIC;
90 CT_add1 : IN STD_LOGIC;
87 fsm_desync : IN STD_LOGIC;
91 fsm_desync : IN STD_LOGIC;
88 FT_max : IN STD_LOGIC;
92 FT_max : IN STD_LOGIC;
89 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 coarse_time_new : OUT STD_LOGIC);
94 coarse_time_new : OUT STD_LOGIC);
91 END COMPONENT;
95 END COMPONENT;
92
96
93 COMPONENT fine_time_counter
97 COMPONENT fine_time_counter
94 GENERIC (
98 GENERIC (
95 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0));--;
99 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0));--;
96 -- FIRST_DIVISION : INTEGER);
100 -- FIRST_DIVISION : INTEGER);
97 PORT (
101 PORT (
98 clk : IN STD_LOGIC;
102 clk : IN STD_LOGIC;
99 rstn : IN STD_LOGIC;
103 rstn : IN STD_LOGIC;
100 tick : IN STD_LOGIC;
104 tick : IN STD_LOGIC;
101 fsm_transition : IN STD_LOGIC;
105 fsm_transition : IN STD_LOGIC;
102 FT_max : OUT STD_LOGIC;
106 FT_max : OUT STD_LOGIC;
103 FT_half : OUT STD_LOGIC;
107 FT_half : OUT STD_LOGIC;
104 FT_wait : OUT STD_LOGIC;
108 FT_wait : OUT STD_LOGIC;
105 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
109 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
106 fine_time_new : OUT STD_LOGIC);
110 fine_time_new : OUT STD_LOGIC;
111 ft_counter_low : out STD_LOGIC_VECTOR( 8 downto 0);
112 ft_counter_low_max_value : out STD_LOGIC_VECTOR( 1 downto 0);
113 ft_counter : out STD_LOGIC_VECTOR(15 downto 0)
114 );
107 END COMPONENT;
115 END COMPONENT;
108
116
109 COMPONENT fine_time_max_value_gen
117 COMPONENT fine_time_max_value_gen
110 PORT (
118 PORT (
111 clk : IN STD_LOGIC;
119 clk : IN STD_LOGIC;
112 rstn : IN STD_LOGIC;
120 rstn : IN STD_LOGIC;
113 tick : IN STD_LOGIC;
121 tick : IN STD_LOGIC;
114 fine_time_add : IN STD_LOGIC;
122 fine_time_add : IN STD_LOGIC;
115 fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
123 fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
116 END COMPONENT;
124 END COMPONENT;
117
125
118 COMPONENT apb_lfr_management_nocal
126 COMPONENT apb_lfr_management_nocal
119 GENERIC (
127 GENERIC (
120 tech : INTEGER;
128 tech : INTEGER;
121 pindex : INTEGER;
129 pindex : INTEGER;
122 paddr : INTEGER;
130 paddr : INTEGER;
123 pmask : INTEGER;
131 pmask : INTEGER;
124 NB_SECOND_DESYNC : INTEGER);
132 NB_SECOND_DESYNC : INTEGER);
125 PORT (
133 PORT (
126 clk25MHz : IN STD_LOGIC;
134 clk25MHz : IN STD_LOGIC;
127 resetn_25MHz : IN STD_LOGIC;
135 resetn_25MHz : IN STD_LOGIC;
128 grspw_tick : IN STD_LOGIC;
136 grspw_tick : IN STD_LOGIC;
129 apbi : IN apb_slv_in_type;
137 apbi : IN apb_slv_in_type;
130 apbo : OUT apb_slv_out_type;
138 apbo : OUT apb_slv_out_type;
131 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
139 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
132 HK_val : IN STD_LOGIC;
140 HK_val : IN STD_LOGIC;
133 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
141 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
134 DAC_SDO : OUT STD_LOGIC;
142 DAC_SDO : OUT STD_LOGIC;
135 DAC_SCK : OUT STD_LOGIC;
143 DAC_SCK : OUT STD_LOGIC;
136 DAC_SYNC : OUT STD_LOGIC;
144 DAC_SYNC : OUT STD_LOGIC;
137 DAC_CAL_EN : OUT STD_LOGIC;
145 DAC_CAL_EN : OUT STD_LOGIC;
138 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
146 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
139 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
147 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
140 LFR_soft_rstn : OUT STD_LOGIC);
148 LFR_soft_rstn : OUT STD_LOGIC);
141 END COMPONENT;
149 END COMPONENT;
142
150
143 END lpp_lfr_management;
151 END lpp_lfr_management;
144
152
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@@ -1,20 +1,21
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 PACKAGE lpp_lfr_management_apbreg_pkg IS
5 PACKAGE lpp_lfr_management_apbreg_pkg IS
6
6
7 CONSTANT ADDR_LFR_MANAGMENT_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";
7 CONSTANT ADDR_LFR_MANAGMENT_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";
8 CONSTANT ADDR_LFR_MANAGMENT_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";
8 CONSTANT ADDR_LFR_MANAGMENT_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";
9 CONSTANT ADDR_LFR_MANAGMENT_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";
9 CONSTANT ADDR_LFR_MANAGMENT_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";
10 CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";
10 CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";
11 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";
11 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";
12 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";
12 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";
13 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";
13 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";
14 CONSTANT ADDR_LFR_MANAGMENT_DAC_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000111";
14 CONSTANT ADDR_LFR_MANAGMENT_DAC_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000111";
15 CONSTANT ADDR_LFR_MANAGMENT_DAC_PRE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001000";
15 CONSTANT ADDR_LFR_MANAGMENT_DAC_PRE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001000";
16 CONSTANT ADDR_LFR_MANAGMENT_DAC_N : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";
16 CONSTANT ADDR_LFR_MANAGMENT_DAC_N : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";
17 CONSTANT ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";
17 CONSTANT ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";
18 CONSTANT ADDR_LFR_MANAGMENT_DAC_DATA_IN : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";
18 CONSTANT ADDR_LFR_MANAGMENT_DAC_DATA_IN : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";
19 CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE_DELTA : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001100";
19
20
20 END lpp_lfr_management_apbreg_pkg;
21 END lpp_lfr_management_apbreg_pkg;
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@@ -1,158 +1,157
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2016, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2016, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 --use ieee.numeric_std.all;
24 --use ieee.numeric_std.all;
25 library grlib;
25 library grlib;
26 use grlib.amba.all;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
28 use grlib.devices.all;
29 library lpp;
29 library lpp;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_amba.all;
31 use lpp.lpp_amba.all;
32 use lpp.general_purpose.TimeGenAdvancedTrigger;
32 use lpp.general_purpose.TimeGenAdvancedTrigger;
33
33
34
34
35 entity APB_ADVANCED_TRIGGER is
35 entity APB_ADVANCED_TRIGGER is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0);
41 abits : integer := 8);
42 port (
41 port (
43 rstn : in std_ulogic;
42 rstn : in std_ulogic;
44 clk : in std_ulogic;
43 clk : in std_ulogic;
45 apbi : in apb_slv_in_type;
44 apbi : in apb_slv_in_type;
46 apbo : out apb_slv_out_type;
45 apbo : out apb_slv_out_type;
47
46
48 SPW_Tickout : IN STD_LOGIC;
47 SPW_Tickout : IN STD_LOGIC;
49 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
50 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
49 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
51
50
52 Trigger : OUT STD_LOGIC
51 Trigger : OUT STD_LOGIC
53 );
52 );
54 end;
53 end;
55
54
56
55
57 architecture beh of APB_ADVANCED_TRIGGER is
56 architecture beh of APB_ADVANCED_TRIGGER is
58
57
59 constant REVISION : integer := 1;
58 constant REVISION : integer := 1;
60
59
61 constant pconfig : apb_config_type := (
60 constant pconfig : apb_config_type := (
62 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADVANCED_TRIGGER, 0, REVISION, 0),
61 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADVANCED_TRIGGER, 0, REVISION, 0),
63 1 => apb_iobar(paddr, pmask));
62 1 => apb_iobar(paddr, pmask));
64
63
65
64
66
65
67 type adv_trig_type is record
66 type adv_trig_type is record
68 TrigPeriod : STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15
67 TrigPeriod : STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15
69 TrigShift : STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps
68 TrigShift : STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps
70 Restart : STD_LOGIC;
69 Restart : STD_LOGIC;
71 StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch
70 StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch
72 BypassTickout : STD_LOGIC; -- if set then Trigger output is driven by SPW tickout
71 BypassTickout : STD_LOGIC; -- if set then Trigger output is driven by SPW tickout
73 end record;
72 end record;
74
73
75 type adv_trig_regs is record
74 type adv_trig_regs is record
76 CFG : STD_LOGIC_VECTOR(31 DOWNTO 0);
75 CFG : STD_LOGIC_VECTOR(31 DOWNTO 0);
77 Restart : STD_LOGIC_VECTOR(31 DOWNTO 0);
76 Restart : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0);
77 StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 end record;
78 end record;
80
79
81 signal r : adv_trig_regs;
80 signal r : adv_trig_regs;
82 signal adv_trig : adv_trig_type;
81 signal adv_trig : adv_trig_type;
83 signal Rdata : std_logic_vector(31 downto 0);
82 signal Rdata : std_logic_vector(31 downto 0);
84
83
85
84
86 begin
85 begin
87
86
88
87
89
88
90 adv_trig0: TimeGenAdvancedTrigger
89 adv_trig0: TimeGenAdvancedTrigger
91 PORT MAP(
90 PORT MAP(
92 clk => clk,
91 clk => clk,
93 rstn => rstn,
92 rstn => rstn,
94
93
95 SPW_Tickout => SPW_Tickout,
94 SPW_Tickout => SPW_Tickout,
96
95
97 CoarseTime => CoarseTime,
96 CoarseTime => CoarseTime,
98 FineTime => FineTime,
97 FineTime => FineTime,
99
98
100 TrigPeriod => adv_trig.TrigPeriod,
99 TrigPeriod => adv_trig.TrigPeriod,
101 TrigShift => adv_trig.TrigShift,
100 TrigShift => adv_trig.TrigShift,
102 Restart => adv_trig.Restart,
101 Restart => adv_trig.Restart,
103 StartDate => adv_trig.StartDate,
102 StartDate => adv_trig.StartDate,
104
103
105 BypassTickout => adv_trig.BypassTickout,
104 BypassTickout => adv_trig.BypassTickout,
106 Trigger => Trigger
105 Trigger => Trigger
107
106
108 );
107 );
109
108
110 adv_trig.BypassTickout <= r.CFG(0);
109 adv_trig.BypassTickout <= r.CFG(0);
111 adv_trig.TrigPeriod <= r.CFG(7 downto 4);
110 adv_trig.TrigPeriod <= r.CFG(7 downto 4);
112 adv_trig.TrigShift <= r.CFG(31 downto 16);
111 adv_trig.TrigShift <= r.CFG(31 downto 16);
113 adv_trig.Restart <= r.Restart(0);
112 adv_trig.Restart <= r.Restart(0);
114 adv_trig.StartDate <= r.StartDate;
113 adv_trig.StartDate <= r.StartDate;
115
114
116
115
117 process(rstn,clk)
116 process(rstn,clk)
118 begin
117 begin
119 if rstn = '0' then
118 if rstn = '0' then
120 r.CFG <= (others=>'0');
119 r.CFG <= (others=>'0');
121 r.Restart <= (others=>'0');
120 r.Restart <= (others=>'0');
122 r.StartDate <= (others=>'0');
121 r.StartDate <= (others=>'0');
123 elsif clk'event and clk = '1' then
122 elsif clk'event and clk = '1' then
124
123
125 --APB Write OP
124 --APB Write OP
126 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
125 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
127 case apbi.paddr(abits-1 downto 2) is
126 case apbi.paddr(3 downto 2) is
128 when "000000" =>
127 when "00" =>
129 r.CFG <= apbi.pwdata;
128 r.CFG <= apbi.pwdata;
130 when "000001" =>
129 when "01" =>
131 r.Restart <= apbi.pwdata;
130 r.Restart <= apbi.pwdata;
132 when "000010" =>
131 when "10" =>
133 r.StartDate <= apbi.pwdata;
132 r.StartDate <= apbi.pwdata;
134 when others =>
133 when others =>
135 null;
134 null;
136 end case;
135 end case;
137 end if;
136 end if;
138
137
139 --APB READ OP
138 --APB READ OP
140 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
139 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
141 case apbi.paddr(abits-1 downto 2) is
140 case apbi.paddr(3 downto 2) is
142 when "000000" =>
141 when "00" =>
143 Rdata <= r.CFG;
142 Rdata <= r.CFG;
144 when "000001" =>
143 when "01" =>
145 Rdata <= r.Restart;
144 Rdata <= r.Restart;
146 when "000010" =>
145 when "10" =>
147 Rdata <= r.StartDate;
146 Rdata <= r.StartDate;
148 when others =>
147 when others =>
149 Rdata <= r.Restart;
148 Rdata <= r.Restart;
150 end case;
149 end case;
151 end if;
150 end if;
152
151
153 end if;
152 end if;
154 apbo.pconfig <= pconfig;
153 apbo.pconfig <= pconfig;
155 end process;
154 end process;
156
155
157 apbo.prdata <= Rdata when apbi.penable = '1';
156 apbo.prdata <= Rdata when apbi.penable = '1';
158 end beh; No newline at end of file
157 end beh;
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@@ -1,86 +1,85
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27
27
28
28
29
29
30 package lpp_amba is
30 package lpp_amba is
31
31
32 component APB_ADVANCED_TRIGGER is
32 component APB_ADVANCED_TRIGGER is
33 generic (
33 generic (
34 pindex : integer := 0;
34 pindex : integer := 0;
35 paddr : integer := 0;
35 paddr : integer := 0;
36 pmask : integer := 16#fff#;
36 pmask : integer := 16#fff#;
37 pirq : integer := 0;
37 pirq : integer := 0);
38 abits : integer := 8);
39 port (
38 port (
40 rstn : in std_ulogic;
39 rstn : in std_ulogic;
41 clk : in std_ulogic;
40 clk : in std_ulogic;
42 apbi : in apb_slv_in_type;
41 apbi : in apb_slv_in_type;
43 apbo : out apb_slv_out_type;
42 apbo : out apb_slv_out_type;
44
43
45 SPW_Tickout : IN STD_LOGIC;
44 SPW_Tickout : IN STD_LOGIC;
46 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
45 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
46 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
48
47
49 Trigger : OUT STD_LOGIC
48 Trigger : OUT STD_LOGIC
50 );
49 );
51 end component;
50 end component;
52
51
53 component APB_SIMPLE_DIODE is
52 component APB_SIMPLE_DIODE is
54 generic (
53 generic (
55 pindex : integer := 0;
54 pindex : integer := 0;
56 paddr : integer := 0;
55 paddr : integer := 0;
57 pmask : integer := 16#fff#;
56 pmask : integer := 16#fff#;
58 pirq : integer := 0;
57 pirq : integer := 0;
59 abits : integer := 8);
58 abits : integer := 8);
60 port (
59 port (
61 rst : in std_ulogic;
60 rst : in std_ulogic;
62 clk : in std_ulogic;
61 clk : in std_ulogic;
63 apbi : in apb_slv_in_type;
62 apbi : in apb_slv_in_type;
64 apbo : out apb_slv_out_type;
63 apbo : out apb_slv_out_type;
65 LED : out std_ulogic
64 LED : out std_ulogic
66 );
65 );
67 end component;
66 end component;
68
67
69
68
70 component APB_MULTI_DIODE is
69 component APB_MULTI_DIODE is
71 generic (
70 generic (
72 pindex : integer := 0;
71 pindex : integer := 0;
73 paddr : integer := 0;
72 paddr : integer := 0;
74 pmask : integer := 16#fff#;
73 pmask : integer := 16#fff#;
75 pirq : integer := 0;
74 pirq : integer := 0;
76 abits : integer := 8);
75 abits : integer := 8);
77 port (
76 port (
78 rst : in std_ulogic;
77 rst : in std_ulogic;
79 clk : in std_ulogic;
78 clk : in std_ulogic;
80 apbi : in apb_slv_in_type;
79 apbi : in apb_slv_in_type;
81 apbo : out apb_slv_out_type;
80 apbo : out apb_slv_out_type;
82 LED : out std_logic_vector(2 downto 0)
81 LED : out std_logic_vector(2 downto 0)
83 );
82 );
84 end component;
83 end component;
85
84
86 end;
85 end;
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@@ -1,183 +1,183
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY ieee;
22 LIBRARY ieee;
23 USE ieee.std_logic_1164.ALL;
23 USE ieee.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 USE grlib.devices.ALL;
28 USE grlib.devices.ALL;
29 LIBRARY lpp;
29 LIBRARY lpp;
30 USE lpp.lpp_amba.ALL;
30 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_cna.ALL;
31 USE lpp.lpp_cna.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33
33
34 ENTITY apb_lfr_cal IS
34 ENTITY apb_lfr_cal IS
35 GENERIC (
35 GENERIC (
36 pindex : INTEGER := 0;
36 pindex : INTEGER := 0;
37 paddr : INTEGER := 0;
37 paddr : INTEGER := 0;
38 pmask : INTEGER := 16#fff#;
38 pmask : INTEGER := 16#fff#;
39 tech : INTEGER := 0;
39 tech : INTEGER := 0;
40 PRESZ : INTEGER := 8;
40 PRESZ : INTEGER := 8;
41 CPTSZ : INTEGER := 16;
41 CPTSZ : INTEGER := 16;
42 datawidth : INTEGER := 18;
42 datawidth : INTEGER := 18;
43 dacresolution : INTEGER := 12;
43 dacresolution : INTEGER := 12;
44 abits : INTEGER := 8
44 abits : INTEGER := 8
45 );
45 );
46 PORT (
46 PORT (
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 clk : IN STD_LOGIC;
48 clk : IN STD_LOGIC;
49 apbi : IN apb_slv_in_type;
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
50 apbo : OUT apb_slv_out_type;
51 SDO : OUT STD_LOGIC;
51 SDO : OUT STD_LOGIC;
52 SCK : OUT STD_LOGIC;
52 SCK : OUT STD_LOGIC;
53 SYNC : OUT STD_LOGIC;
53 SYNC : OUT STD_LOGIC;
54 SMPCLK : OUT STD_LOGIC
54 SMPCLK : OUT STD_LOGIC
55 );
55 );
56 END ENTITY;
56 END ENTITY;
57
57
58 --! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
58 --! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
59 --! et les sorties seront cabl�es vers le convertisseur.
59 --! et les sorties seront cabl�es vers le convertisseur.
60
60
61 ARCHITECTURE ar_apb_lfr_cal OF apb_lfr_cal IS
61 ARCHITECTURE ar_apb_lfr_cal OF apb_lfr_cal IS
62
62
63 CONSTANT REVISION : INTEGER := 1;
63 CONSTANT REVISION : INTEGER := 1;
64
64
65 CONSTANT pconfig : apb_config_type := (
65 CONSTANT pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
66 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
67 1 => apb_iobar(paddr, pmask));
68
68
69 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
69 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
70 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
70 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
71 SIGNAL Reload : STD_LOGIC;
71 SIGNAL Reload : STD_LOGIC;
72 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
72 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
73 SIGNAL WEN : STD_LOGIC;
73 SIGNAL WEN : STD_LOGIC;
74 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
74 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
75 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
75 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
76 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
76 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
77 SIGNAL INTERLEAVED : STD_LOGIC;
77 SIGNAL INTERLEAVED : STD_LOGIC;
78 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
78 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
79 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
80
80
81 BEGIN
81 BEGIN
82
82
83 cal : lfr_cal_driver
83 cal : lfr_cal_driver
84 GENERIC MAP(
84 GENERIC MAP(
85 tech => tech,
85 tech => tech,
86 PRESZ => PRESZ,
86 PRESZ => PRESZ,
87 CPTSZ => CPTSZ,
87 CPTSZ => CPTSZ,
88 datawidth => datawidth,
88 datawidth => datawidth,
89 abits => abits
89 abits => abits
90 )
90 )
91 PORT MAP(
91 PORT MAP(
92 clk => clk,
92 clk => clk,
93 rstn => rstn,
93 rstn => rstn,
94
94
95 pre => pre,
95 pre => pre,
96 N => N,
96 N => N,
97 Reload => Reload,
97 Reload => Reload,
98 DATA_IN => DATA_IN,
98 DATA_IN => DATA_IN,
99 WEN => WEN,
99 WEN => WEN,
100 LOAD_ADDRESSN => LOAD_ADDRESSN,
100 LOAD_ADDRESSN => LOAD_ADDRESSN,
101 ADDRESS_IN => ADDRESS_IN,
101 ADDRESS_IN => ADDRESS_IN,
102 ADDRESS_OUT => ADDRESS_OUT,
102 ADDRESS_OUT => ADDRESS_OUT,
103 INTERLEAVED => INTERLEAVED,
103 INTERLEAVED => INTERLEAVED,
104 DAC_CFG => DAC_CFG,
104 DAC_CFG => DAC_CFG,
105
105
106 SYNC => SYNC,
106 SYNC => SYNC,
107 DOUT => SDO,
107 DOUT => SDO,
108 SCLK => SCK,
108 SCLK => SCK,
109 SMPCLK => SMPCLK -- OPEN
109 SMPCLK => SMPCLK -- OPEN
110 );
110 );
111
111
112 PROCESS(rstn, clk)
112 PROCESS(rstn, clk)
113 BEGIN
113 BEGIN
114 IF(rstn = '0')then
114 IF(rstn = '0')then
115 pre <= (OTHERS => '1');
115 pre <= (OTHERS => '1');
116 N <= (OTHERS => '1');
116 N <= (OTHERS => '1');
117 Reload <= '1';
117 Reload <= '1';
118 DATA_IN <= (OTHERS => '0');
118 DATA_IN <= (OTHERS => '0');
119 WEN <= '1';
119 WEN <= '1';
120 LOAD_ADDRESSN <= '1';
120 LOAD_ADDRESSN <= '1';
121 ADDRESS_IN <= (OTHERS => '1');
121 ADDRESS_IN <= (OTHERS => '1');
122 INTERLEAVED <= '0';
122 INTERLEAVED <= '0';
123 DAC_CFG <= (OTHERS => '0');
123 DAC_CFG <= (OTHERS => '0');
124 Rdata <= (OTHERS => '0');
124 Rdata <= (OTHERS => '0');
125 ELSIF(clk'EVENT AND clk = '1')then
125 ELSIF(clk'EVENT AND clk = '1')then
126
126
127
127
128 --APB Write OP
128 --APB Write OP
129 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
129 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
130 CASE apbi.paddr(abits-1 DOWNTO 2) IS
130 CASE apbi.paddr(4 DOWNTO 2) IS
131 WHEN "000000" =>
131 WHEN "000" =>
132 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
132 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
133 Reload <= apbi.pwdata(4);
133 Reload <= apbi.pwdata(4);
134 INTERLEAVED <= apbi.pwdata(5);
134 INTERLEAVED <= apbi.pwdata(5);
135 WHEN "000001" =>
135 WHEN "001" =>
136 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
136 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
137 WHEN "000010" =>
137 WHEN "010" =>
138 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
138 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
139 WHEN "000011" =>
139 WHEN "011" =>
140 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
140 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
141 LOAD_ADDRESSN <= '0';
141 LOAD_ADDRESSN <= '0';
142 WHEN "000100" =>
142 WHEN "100" =>
143 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
143 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
144 WEN <= '0';
144 WEN <= '0';
145 WHEN OTHERS =>
145 WHEN OTHERS =>
146 NULL;
146 NULL;
147 END CASE;
147 END CASE;
148 ELSE
148 ELSE
149 LOAD_ADDRESSN <= '1';
149 LOAD_ADDRESSN <= '1';
150 WEN <= '1';
150 WEN <= '1';
151 END IF;
151 END IF;
152
152
153 --APB Read OP
153 --APB Read OP
154 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
154 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
155 CASE apbi.paddr(abits-1 DOWNTO 2) IS
155 CASE apbi.paddr(4 DOWNTO 2) IS
156 WHEN "000000" =>
156 WHEN "000" =>
157 Rdata(3 DOWNTO 0) <= DAC_CFG;
157 Rdata(3 DOWNTO 0) <= DAC_CFG;
158 Rdata(4) <= Reload;
158 Rdata(4) <= Reload;
159 Rdata(5) <= INTERLEAVED;
159 Rdata(5) <= INTERLEAVED;
160 Rdata(31 DOWNTO 6) <= (OTHERS => '0');
160 Rdata(31 DOWNTO 6) <= (OTHERS => '0');
161 WHEN "000001" =>
161 WHEN "001" =>
162 Rdata(PRESZ-1 DOWNTO 0) <= pre;
162 Rdata(PRESZ-1 DOWNTO 0) <= pre;
163 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
163 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
164 WHEN "000010" =>
164 WHEN "010" =>
165 Rdata(CPTSZ-1 DOWNTO 0) <= N;
165 Rdata(CPTSZ-1 DOWNTO 0) <= N;
166 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
166 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
167 WHEN "000011" =>
167 WHEN "011" =>
168 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
168 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
169 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
169 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
170 WHEN "000100" =>
170 WHEN "100" =>
171 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
171 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
172 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
172 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
173 WHEN OTHERS =>
173 WHEN OTHERS =>
174 Rdata <= (OTHERS => '0');
174 Rdata <= (OTHERS => '0');
175 END CASE;
175 END CASE;
176 END IF;
176 END IF;
177
177
178 END IF;
178 END IF;
179 apbo.pconfig <= pconfig;
179 apbo.pconfig <= pconfig;
180 END PROCESS;
180 END PROCESS;
181
181
182 apbo.prdata <= Rdata WHEN apbi.penable = '1';
182 apbo.prdata <= Rdata WHEN apbi.penable = '1';
183 END ARCHITECTURE ar_apb_lfr_cal;
183 END ARCHITECTURE ar_apb_lfr_cal;
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@@ -1,238 +1,238
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_cna is
32 package lpp_cna is
33
33
34 component apb_lfr_cal is
34 component apb_lfr_cal is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 tech : integer := 0;
39 tech : integer := 0;
40 PRESZ : integer := 8;
40 PRESZ : integer := 8;
41 CPTSZ : integer := 16;
41 CPTSZ : integer := 16;
42 datawidth : integer := 18;
42 datawidth : integer := 18;
43 dacresolution : integer := 12;
43 dacresolution : integer := 12;
44 abits : integer := 8);
44 abits : INTEGER := 8);
45 port (
45 port (
46 rstn : in std_logic;
46 rstn : in std_logic;
47 clk : in std_logic;
47 clk : in std_logic;
48 apbi : in apb_slv_in_type;
48 apbi : in apb_slv_in_type;
49 apbo : out apb_slv_out_type;
49 apbo : out apb_slv_out_type;
50 SDO : out std_logic;
50 SDO : out std_logic;
51 SCK : out std_logic;
51 SCK : out std_logic;
52 SYNC : out std_logic;
52 SYNC : out std_logic;
53 SMPCLK : out std_logic
53 SMPCLK : out std_logic
54 );
54 );
55 end component;
55 end component;
56
56
57 component SPI_DAC_DRIVER is
57 component SPI_DAC_DRIVER is
58 Generic(
58 Generic(
59 datawidth : INTEGER := 16;
59 datawidth : INTEGER := 16;
60 MSBFIRST : INTEGER := 1
60 MSBFIRST : INTEGER := 1
61 );
61 );
62 Port (
62 Port (
63 clk : in STD_LOGIC;
63 clk : in STD_LOGIC;
64 rstn : in STD_LOGIC;
64 rstn : in STD_LOGIC;
65 DATA : in STD_LOGIC_VECTOR(datawidth-1 downto 0);
65 DATA : in STD_LOGIC_VECTOR(datawidth-1 downto 0);
66 SMP_CLK : in STD_LOGIC;
66 SMP_CLK : in STD_LOGIC;
67 SYNC : out STD_LOGIC;
67 SYNC : out STD_LOGIC;
68 DOUT : out STD_LOGIC;
68 DOUT : out STD_LOGIC;
69 SCLK : out STD_LOGIC
69 SCLK : out STD_LOGIC
70 );
70 );
71 end component;
71 end component;
72
72
73 component dynamic_freq_div is
73 component dynamic_freq_div is
74 generic(
74 generic(
75 PRESZ : integer range 1 to 32:=4;
75 PRESZ : integer range 1 to 32:=4;
76 PREMAX : integer := 16#FFFFFF#;
76 PREMAX : integer := 16#FFFFFF#;
77 CPTSZ : integer range 1 to 32:=16
77 CPTSZ : integer range 1 to 32:=16
78 );
78 );
79 Port (
79 Port (
80 clk : in STD_LOGIC;
80 clk : in STD_LOGIC;
81 rstn : in STD_LOGIC;
81 rstn : in STD_LOGIC;
82 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
82 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
83 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
83 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
84 Reload : in std_logic;
84 Reload : in std_logic;
85 clk_out : out STD_LOGIC
85 clk_out : out STD_LOGIC
86 );
86 );
87 end component;
87 end component;
88
88
89 component lfr_cal_driver is
89 component lfr_cal_driver is
90 generic(
90 generic(
91 tech : integer := 0;
91 tech : integer := 0;
92 PRESZ : integer range 1 to 32:=4;
92 PRESZ : integer range 1 to 32:=4;
93 PREMAX : integer := 16#FFFFFF#;
93 PREMAX : integer := 16#FFFFFF#;
94 CPTSZ : integer range 1 to 32:=16;
94 CPTSZ : integer range 1 to 32:=16;
95 datawidth : integer := 18;
95 datawidth : integer := 18;
96 abits : integer := 8
96 abits : integer := 8
97 );
97 );
98 Port (
98 Port (
99 clk : in STD_LOGIC;
99 clk : in STD_LOGIC;
100 rstn : in STD_LOGIC;
100 rstn : in STD_LOGIC;
101 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
101 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
102 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
102 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
103 Reload : in std_logic;
103 Reload : in std_logic;
104 DATA_IN : in STD_LOGIC_VECTOR(datawidth-1 downto 0);
104 DATA_IN : in STD_LOGIC_VECTOR(datawidth-1 downto 0);
105 WEN : in STD_LOGIC;
105 WEN : in STD_LOGIC;
106 LOAD_ADDRESSN : IN STD_LOGIC;
106 LOAD_ADDRESSN : IN STD_LOGIC;
107 ADDRESS_IN : IN STD_LOGIC_VECTOR(abits-1 downto 0);
107 ADDRESS_IN : IN STD_LOGIC_VECTOR(abits-1 downto 0);
108 ADDRESS_OUT : OUT STD_LOGIC_VECTOR(abits-1 downto 0);
108 ADDRESS_OUT : OUT STD_LOGIC_VECTOR(abits-1 downto 0);
109 INTERLEAVED : IN STD_LOGIC;
109 INTERLEAVED : IN STD_LOGIC;
110 DAC_CFG : IN STD_LOGIC_VECTOR(3 downto 0);
110 DAC_CFG : IN STD_LOGIC_VECTOR(3 downto 0);
111 SYNC : out STD_LOGIC;
111 SYNC : out STD_LOGIC;
112 DOUT : out STD_LOGIC;
112 DOUT : out STD_LOGIC;
113 SCLK : out STD_LOGIC;
113 SCLK : out STD_LOGIC;
114 SMPCLK : out STD_lOGIC
114 SMPCLK : out STD_lOGIC
115 );
115 );
116 end component;
116 end component;
117
117
118 component RAM_READER is
118 component RAM_READER is
119 Generic(
119 Generic(
120 datawidth : integer := 18;
120 datawidth : integer := 18;
121 dacresolution : integer := 12;
121 dacresolution : integer := 12;
122 abits : integer := 8
122 abits : integer := 8
123 );
123 );
124 Port (
124 Port (
125 clk : in STD_LOGIC; --! clock input
125 clk : in STD_LOGIC; --! clock input
126 rstn : in STD_LOGIC; --! Active low restet input
126 rstn : in STD_LOGIC; --! Active low restet input
127 DATA_IN : in STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA input vector -> connect to RAM DATA output
127 DATA_IN : in STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA input vector -> connect to RAM DATA output
128 ADDRESS : out STD_LOGIC_VECTOR (abits-1 downto 0); --! ADDRESS output vector -> connect to RAM read ADDRESS input
128 ADDRESS : out STD_LOGIC_VECTOR (abits-1 downto 0); --! ADDRESS output vector -> connect to RAM read ADDRESS input
129 REN : out STD_LOGIC; --! Active low read enable -> connect to RAM read enable
129 REN : out STD_LOGIC; --! Active low read enable -> connect to RAM read enable
130 DATA_OUT : out STD_LOGIC_VECTOR (dacresolution-1 downto 0); --! DATA output vector
130 DATA_OUT : out STD_LOGIC_VECTOR (dacresolution-1 downto 0); --! DATA output vector
131 SMP_CLK : in STD_LOGIC; --! Sampling clock input, each rising edge will provide a DATA to the output and read a new one in RAM
131 SMP_CLK : in STD_LOGIC; --! Sampling clock input, each rising edge will provide a DATA to the output and read a new one in RAM
132 INTERLEAVED : in STD_LOGIC --! When 1, interleaved mode is actived.
132 INTERLEAVED : in STD_LOGIC --! When 1, interleaved mode is actived.
133 );
133 );
134 end component;
134 end component;
135
135
136
136
137 component RAM_WRITER is
137 component RAM_WRITER is
138 Generic(
138 Generic(
139 datawidth : integer := 18;
139 datawidth : integer := 18;
140 abits : integer := 8
140 abits : integer := 8
141 );
141 );
142 Port (
142 Port (
143 clk : in STD_LOGIC; --! clk input
143 clk : in STD_LOGIC; --! clk input
144 rstn : in STD_LOGIC; --! Active low reset input
144 rstn : in STD_LOGIC; --! Active low reset input
145 DATA_IN : in STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA input vector
145 DATA_IN : in STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA input vector
146 DATA_OUT : out STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA output vector
146 DATA_OUT : out STD_LOGIC_VECTOR (datawidth-1 downto 0); --! DATA output vector
147 WEN_IN : in STD_LOGIC; --! Active low Write Enable input
147 WEN_IN : in STD_LOGIC; --! Active low Write Enable input
148 WEN_OUT : out STD_LOGIC; --! Active low Write Enable output
148 WEN_OUT : out STD_LOGIC; --! Active low Write Enable output
149 LOAD_ADDRESSN : in STD_LOGIC; --! Active low address load input
149 LOAD_ADDRESSN : in STD_LOGIC; --! Active low address load input
150 ADDRESS_IN : in STD_LOGIC_VECTOR (abits-1 downto 0); --! Adress input vector
150 ADDRESS_IN : in STD_LOGIC_VECTOR (abits-1 downto 0); --! Adress input vector
151 ADDRESS_OUT : out STD_LOGIC_VECTOR (abits-1 downto 0) --! Adress output vector
151 ADDRESS_OUT : out STD_LOGIC_VECTOR (abits-1 downto 0) --! Adress output vector
152 );
152 );
153 end component;
153 end component;
154
154
155 component APB_DAC is
155 component APB_DAC is
156 generic (
156 generic (
157 pindex : integer := 0;
157 pindex : integer := 0;
158 paddr : integer := 0;
158 paddr : integer := 0;
159 pmask : integer := 16#fff#;
159 pmask : integer := 16#fff#;
160 pirq : integer := 0;
160 pirq : integer := 0;
161 abits : integer := 8;
161 abits : integer := 8;
162 Nmax : integer := 7);
162 Nmax : integer := 7);
163 port (
163 port (
164 clk : in std_logic; --! Horloge du composant
164 clk : in std_logic; --! Horloge du composant
165 rst : in std_logic; --! Reset general du composant
165 rst : in std_logic; --! Reset general du composant
166 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
166 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
167 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
167 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
168 DataIN : in std_logic_vector(15 downto 0);
168 DataIN : in std_logic_vector(15 downto 0);
169 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
169 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
170 Readn : out std_logic;
170 Readn : out std_logic;
171 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
171 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
172 SCLK : out std_logic; --! Horloge systeme du convertisseur
172 SCLK : out std_logic; --! Horloge systeme du convertisseur
173 CLK_VAR : out std_logic;
173 CLK_VAR : out std_logic;
174 DATA : out std_logic --! Donn�e num�rique s�rialis�
174 DATA : out std_logic --! Donn�e num�rique s�rialis�
175 );
175 );
176 end component;
176 end component;
177
177
178
178
179 component DacDriver is
179 component DacDriver is
180 --generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
180 --generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
181 port(
181 port(
182 clk : in std_logic; --! Horloge du composant
182 clk : in std_logic; --! Horloge du composant
183 rst : in std_logic; --! Reset general du composant
183 rst : in std_logic; --! Reset general du composant
184 SysClk : in std_logic;
184 SysClk : in std_logic;
185 enable : in std_logic; --! Autorise ou non l'utilisation du composant
185 enable : in std_logic; --! Autorise ou non l'utilisation du composant
186 Data_IN : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
186 Data_IN : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
187 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
187 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
188 SCLK : out std_logic; --! Horloge systeme du convertisseur
188 SCLK : out std_logic; --! Horloge systeme du convertisseur
189 Readn : out std_logic;
189 Readn : out std_logic;
190 -- Ready : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
190 -- Ready : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
191 Data : out std_logic --! Donn�e num�rique s�rialis�
191 Data : out std_logic --! Donn�e num�rique s�rialis�
192 );
192 );
193 end component;
193 end component;
194
194
195
195
196 component Gene_SYNC is
196 component Gene_SYNC is
197 port(
197 port(
198 SysClk,raz : in std_logic; --! Horloge systeme et Reset du composant
198 SysClk,raz : in std_logic; --! Horloge systeme et Reset du composant
199 SCLK : in std_logic;
199 SCLK : in std_logic;
200 enable : in std_logic; --! Autorise ou non l'utilisation du composant
200 enable : in std_logic; --! Autorise ou non l'utilisation du composant
201 sended : in std_logic;
201 sended : in std_logic;
202 send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
202 send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
203 Readn : out std_logic;
203 Readn : out std_logic;
204 SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�
204 SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�
205 );
205 );
206 end component;
206 end component;
207
207
208
208
209 component Serialize is
209 component Serialize is
210 port(
210 port(
211 clk,raz : in std_logic; --! Horloge et Reset du composant
211 clk,raz : in std_logic; --! Horloge et Reset du composant
212 sclk : in std_logic; --! Horloge Systeme
212 sclk : in std_logic; --! Horloge Systeme
213 vectin : in std_logic_vector(15 downto 0); --! Vecteur d'entr�e
213 vectin : in std_logic_vector(15 downto 0); --! Vecteur d'entr�e
214 send : in std_logic; --! Flag, Une nouvelle donn�e est pr�sente
214 send : in std_logic; --! Flag, Une nouvelle donn�e est pr�sente
215 sended : out std_logic; --! Flag, La donn�e a �t� s�rialis�e
215 sended : out std_logic; --! Flag, La donn�e a �t� s�rialis�e
216 Data : out std_logic --! Donn�e num�rique s�rialis�
216 Data : out std_logic --! Donn�e num�rique s�rialis�
217 );
217 );
218 end component;
218 end component;
219
219
220 component ReadFifo_GEN is
220 component ReadFifo_GEN is
221 port(
221 port(
222 clk,raz : in std_logic; --! Horloge et Reset du composant
222 clk,raz : in std_logic; --! Horloge et Reset du composant
223 SYNC : in std_logic;
223 SYNC : in std_logic;
224 Readn : out std_logic
224 Readn : out std_logic
225 );
225 );
226 end component;
226 end component;
227
227
228
228
229 component ClkSetting is
229 component ClkSetting is
230 generic(Nmax : integer := 7);
230 generic(Nmax : integer := 7);
231 port(
231 port(
232 clk, rst : in std_logic; --! Horloge et Reset globale
232 clk, rst : in std_logic; --! Horloge et Reset globale
233 N : in integer range 0 to Nmax;
233 N : in integer range 0 to Nmax;
234 sclk : out std_logic --! Horloge Systeme g�n�r�e
234 sclk : out std_logic --! Horloge Systeme g�n�r�e
235 );
235 );
236 end component;
236 end component;
237
237
238 end; No newline at end of file
238 end;
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