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Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...
Alexis Jeandet -
r655:2dbcdaf8bb73 default draft
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=testbench
5 BOARD=LFR-EQM
6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=
9 QSF=
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT=
13 VHDLSYNFILES=
14 VHDLSIMFILES= tb.vhd
15 SIMTOP=TB
16 CLEAN=soft-clean
17
18 TECHLIBS = axcelerator
19
20 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
21 tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi
22
23 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
24 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \
25 grlfpc \
26 ./dsp/lpp_fft_rtax \
27 ./amba_lcd_16x2_ctrlr \
28 ./general_purpose/lpp_AMR \
29 ./general_purpose/lpp_balise \
30 ./general_purpose/lpp_delay \
31 ./lpp_bootloader \
32 ./lpp_sim/CY7C1061DV33 \
33 ./lpp_uart \
34 ./lpp_usb \
35 ./dsp/lpp_fft \
36 ./lpp_leon3_soc \
37 ./lpp_debug_lfr
38
39 FILESKIP = i2cmst.vhd \
40 APB_MULTI_DIODE.vhd \
41 APB_MULTI_DIODE.vhd \
42 Top_MatrixSpec.vhd \
43 APB_FFT.vhd \
44 lpp_lfr_ms_FFT.vhd \
45 lpp_lfr_apbreg.vhd \
46 CoreFFT.vhd \
47 lpp_lfr_ms.vhd \
48 lpp_lfr_sim_pkg.vhd \
49 mtie_maps.vhd \
50 ftsrctrlc.vhd \
51 ftsdctrl.vhd \
52 ftsrctrl8.vhd \
53 ftmctrl.vhd \
54 ftsdctrl64.vhd \
55 ftahbram.vhd \
56 ftahbram2.vhd \
57 sramft.vhd \
58 nandfctrlx.vhd
59
60 include $(GRLIB)/bin/Makefile
61 include $(GRLIB)/software/leon3/Makefile
62
63 ################## project specific targets ##########################
64 distclean:myclean
65 vsim:cp_for_vsim
66
67 myclean:
68 rm -f input.txt output_fx.txt *.log
69 rm -rf ./2016*
70
71 generate :
72 # python ./generate.py
73
74 cp_for_vsim: generate
75 # cp ./input.txt simulation/
76
77 archivate:
78 xonsh ./archivate.xsh
79
80 test: | generate ghdl ghdl-run archivate
81
82
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@@ -0,0 +1,361
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31
32 LIBRARY lpp;
33 USE lpp.lpp_lfr_management.ALL;
34
35 ENTITY TB IS
36
37 PORT (
38 SIM_OK : OUT STD_LOGIC
39 );
40
41 END TB;
42
43
44 ARCHITECTURE beh OF TB IS
45
46 SIGNAL clk25MHz : STD_LOGIC := '0';
47
48 SIGNAL resetn : STD_LOGIC;
49 SIGNAL grspw_tick : STD_LOGIC;
50 SIGNAL apbi : apb_slv_in_type;
51 SIGNAL apbo : apb_slv_out_type;
52 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
53 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
54
55 SIGNAL TB_string : STRING(1 TO 8):= "12345678";
56
57 SIGNAL coarse_time_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
58 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
59 SIGNAL global_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
60 SIGNAL global_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
61 SIGNAL tick_ongoing : STD_LOGIC;
62
63 SIGNAL ASSERTION_1 : STD_LOGIC;
64 SIGNAL ASSERTION_2 : STD_LOGIC;
65 SIGNAL ASSERTION_3 : STD_LOGIC;
66
67 BEGIN -- beh
68
69 apb_lfr_management_1: apb_lfr_management
70 GENERIC MAP (
71 tech => 0,
72 pindex => 0,
73 paddr => 0,
74 pmask => 16#fff#,
75 -- FIRST_DIVISION => 20,
76 NB_SECOND_DESYNC => 4)
77 PORT MAP (
78 clk25MHz => clk25MHz,
79 resetn_25MHz => resetn,
80
81 grspw_tick => grspw_tick,
82 apbi => apbi,
83 apbo => apbo,
84
85 HK_sample => (others => '0'),
86 HK_val => '0',
87 HK_sel => OPEN,
88
89 DAC_SDO => OPEN,
90 DAC_SCK => OPEN,
91 DAC_SYNC => OPEN,
92 DAC_CAL_EN => OPEN,
93
94 coarse_time => coarse_time,
95 fine_time => fine_time,
96
97 LFR_soft_rstn => OPEN);
98
99 clk25MHz <= NOT clk25MHz AFTER 20000 ps;
100
101 PROCESS
102 BEGIN -- PROCESS
103 WAIT UNTIL clk25MHz = '1';
104 TB_string <= "RESET ";
105
106 resetn <= '0';
107
108 apbi.psel(0) <= '0';
109 apbi.pwrite <= '0';
110 apbi.penable <= '0';
111 apbi.paddr <= (OTHERS => '0');
112 apbi.pwdata <= (OTHERS => '0');
113 grspw_tick <= '0';
114 WAIT UNTIL clk25MHz = '1';
115 WAIT UNTIL clk25MHz = '1';
116 resetn <= '1';
117 WAIT FOR 60 ms;
118 ---------------------------------------------------------------------------
119 -- DESYNC TO SYNC
120 ---------------------------------------------------------------------------
121 WAIT UNTIL clk25MHz = '1';
122 TB_string <= "TICK 1 ";
123 grspw_tick <= '1';------------------------------------------------------1
124 WAIT UNTIL clk25MHz = '1';
125 grspw_tick <= '0';
126 WAIT FOR 53333 us;
127 WAIT UNTIL clk25MHz = '1';
128 TB_string <= "TICK 2 ";
129 grspw_tick <= '1';------------------------------------------------------2
130 WAIT UNTIL clk25MHz = '1';
131 grspw_tick <= '0';
132 WAIT FOR 56000 us;
133 WAIT UNTIL clk25MHz = '1';
134 TB_string <= "TICK 3 ";
135 grspw_tick <= '1';------------------------------------------------------3
136 WAIT UNTIL clk25MHz = '1';
137 grspw_tick <= '0';
138 WAIT FOR 200 ms;
139 WAIT UNTIL clk25MHz = '1';
140 TB_string <= "CT new ";
141 -- WRITE NEW COARSE_TIME
142 apbi.psel(0) <= '1';
143 apbi.pwrite <= '1';
144 apbi.penable <= '1';
145 apbi.paddr <= X"00000004";
146 apbi.pwdata <= X"00001234";
147 WAIT UNTIL clk25MHz = '1';
148 apbi.psel(0) <= '0';
149 apbi.pwrite <= '0';
150 apbi.penable <= '0';
151 apbi.paddr <= (OTHERS => '0');
152 apbi.pwdata <= (OTHERS => '0');
153 WAIT UNTIL clk25MHz = '1';
154
155 WAIT FOR 10 ms;
156 WAIT UNTIL clk25MHz = '1';
157 TB_string <= "TICK 4 ";
158 grspw_tick <= '1';------------------------------------------------------3
159 WAIT UNTIL clk25MHz = '1';
160 grspw_tick <= '0';
161
162
163 WAIT FOR 250 ms;
164 WAIT UNTIL clk25MHz = '1';
165 TB_string <= "CT new ";
166 -- WRITE NEW COARSE_TIME
167 apbi.psel(0) <= '1';
168 apbi.pwrite <= '1';
169 apbi.penable <= '1';
170 apbi.paddr <= X"00000004";
171 apbi.pwdata <= X"80005678";
172 WAIT UNTIL clk25MHz = '1';
173 apbi.psel(0) <= '0';
174 apbi.pwrite <= '0';
175 apbi.penable <= '0';
176 apbi.paddr <= (OTHERS => '0');
177 apbi.pwdata <= (OTHERS => '0');
178 WAIT UNTIL clk25MHz = '1';
179
180 WAIT FOR 10 ms;
181 WAIT UNTIL clk25MHz = '1';
182 TB_string <= "TICK 5 ";
183 grspw_tick <= '1';------------------------------------------------------3
184 WAIT UNTIL clk25MHz = '1';
185 grspw_tick <= '0';
186
187
188 WAIT FOR 20 ms;
189 WAIT UNTIL clk25MHz = '1';
190 TB_string <= "CT new ";
191 -- WRITE NEW COARSE_TIME
192 apbi.psel(0) <= '1';
193 apbi.pwrite <= '1';
194 apbi.penable <= '1';
195 apbi.paddr <= X"00000004";
196 apbi.pwdata <= X"00005678";
197 WAIT UNTIL clk25MHz = '1';
198 apbi.psel(0) <= '0';
199 apbi.pwrite <= '0';
200 apbi.penable <= '0';
201 apbi.paddr <= (OTHERS => '0');
202 apbi.pwdata <= (OTHERS => '0');
203 WAIT UNTIL clk25MHz = '1';
204
205 WAIT FOR 25 ms;
206 WAIT UNTIL clk25MHz = '1';
207 TB_string <= "Soft RST";
208 -- WRITE SOFT RESET
209 apbi.psel(0) <= '1';
210 apbi.pwrite <= '1';
211 apbi.penable <= '1';
212 apbi.paddr <= X"00000000";
213 apbi.pwdata <= X"00000002";
214 WAIT UNTIL clk25MHz = '1';
215 apbi.psel(0) <= '0';
216 apbi.pwrite <= '0';
217 apbi.penable <= '0';
218 apbi.paddr <= (OTHERS => '0');
219 apbi.pwdata <= (OTHERS => '0');
220 WAIT UNTIL clk25MHz = '1';
221
222 WAIT FOR 250 ms;
223 TB_string <= "READ 1 ";
224 apbi.psel(0) <= '1';
225 apbi.pwrite <= '0';
226 apbi.penable <= '1';
227 apbi.paddr <= X"00000008";
228 WAIT UNTIL clk25MHz = '1';
229 apbi.psel(0) <= '0';
230 apbi.pwrite <= '0';
231 apbi.penable <= '0';
232 apbi.paddr <= (OTHERS => '0');
233 WAIT UNTIL clk25MHz = '1';
234 WAIT FOR 250 ms;
235 TB_string <= "READ 2 ";
236 apbi.psel(0) <= '1';
237 apbi.pwrite <= '0';
238 apbi.penable <= '1';
239 apbi.paddr <= X"00000008";
240 WAIT UNTIL clk25MHz = '1';
241 apbi.psel(0) <= '0';
242 apbi.pwrite <= '0';
243 apbi.penable <= '0';
244 apbi.paddr <= (OTHERS => '0');
245 WAIT UNTIL clk25MHz = '1';
246 WAIT FOR 250 ms;
247 TB_string <= "READ 3 ";
248 apbi.psel(0) <= '1';
249 apbi.pwrite <= '0';
250 apbi.penable <= '1';
251 apbi.paddr <= X"00000008";
252 WAIT UNTIL clk25MHz = '1';
253 apbi.psel(0) <= '0';
254 apbi.pwrite <= '0';
255 apbi.penable <= '0';
256 apbi.paddr <= (OTHERS => '0');
257 WAIT UNTIL clk25MHz = '1';
258
259
260
261 REPORT "*** END simulation ***" SEVERITY failure;
262 WAIT;
263
264 END PROCESS;
265
266
267 -----------------------------------------------------------------------------
268 --
269 -----------------------------------------------------------------------------
270
271 global_time <= coarse_time & fine_time;
272
273 PROCESS (clk25MHz, resetn)
274 BEGIN -- PROCESS
275 IF resetn = '0' THEN -- asynchronous reset (active low)
276 coarse_time_reg <= (OTHERS => '0');
277 fine_time_reg <= (OTHERS => '0');
278 global_time_reg <= (OTHERS => '0');
279 tick_ongoing <= '0';
280 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
281 global_time_reg <= global_time;
282 coarse_time_reg <= coarse_time;
283 fine_time_reg <= fine_time;
284 IF grspw_tick ='1' THEN
285 tick_ongoing <= '1';
286 ELSIF tick_ongoing = '1' THEN
287 IF (fine_time_reg /= fine_time) OR (coarse_time_reg /= coarse_time) THEN
288 tick_ongoing <= '0';
289 END IF;
290 END IF;
291
292 END IF;
293 END PROCESS;
294
295 -----------------------------------------------------------------------------
296 -- ASSERTION 1 :
297 -- Coarse_time "changed" => FINE_TIME = 0
298 -- False after a TRANSITION !
299 -----------------------------------------------------------------------------
300 PROCESS (clk25MHz, resetn)
301 BEGIN -- PROCESS
302 IF resetn = '0' THEN -- asynchronous reset (active low)
303 ASSERTION_1 <= '1';
304 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
305 IF coarse_time /= coarse_time_reg THEN
306 IF fine_time /= X"0000" THEN
307 IF fine_time /= X"0041" THEN
308 ASSERTION_1 <= '0';
309 ELSE
310 ASSERTION_1 <= 'U';
311 END IF;
312 ELSE
313 ASSERTION_1 <= '1';
314 END IF;
315 END IF;
316 END IF;
317 END PROCESS;
318
319 -----------------------------------------------------------------------------
320 -- ASSERTION 2 :
321 -- tick => next(FINE_TIME) = 0
322 -----------------------------------------------------------------------------
323 PROCESS (clk25MHz, resetn)
324 BEGIN -- PROCESS
325 IF resetn = '0' THEN -- asynchronous reset (active low)
326 ASSERTION_2 <= '1';
327 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
328 IF tick_ongoing = '1' THEN
329 IF fine_time_reg /= fine_time OR coarse_time_reg /= coarse_time THEN
330 IF fine_time /= X"0000" THEN
331 ASSERTION_2 <= '0';
332 END IF;
333 END IF;
334 END IF;
335 END IF;
336 END PROCESS;
337
338 -----------------------------------------------------------------------------
339 -- ASSERTION 3 :
340 -- next(TIME) > TIME
341 -- false if resynchro, or new coarse_time
342 -----------------------------------------------------------------------------
343 PROCESS (clk25MHz, resetn)
344 BEGIN -- PROCESS
345 IF resetn = '0' THEN -- asynchronous reset (active low)
346 ASSERTION_3 <= '1';
347 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
348 ASSERTION_3 <= '1';
349 IF global_time_reg(46 DOWNTO 0) > global_time(46 DOWNTO 0) THEN
350 IF global_time(47) = '0' AND global_time_reg(47) = '1' THEN
351 ASSERTION_3 <= 'U'; -- RESYNCHRO ....
352 ELSE
353 ASSERTION_3 <= '0';
354 END IF;
355 END IF;
356 END IF;
357 END PROCESS;
358
359
360 END beh;
361
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@@ -14,7 +14,7 ENTITY general_counter IS
14 clk : IN STD_LOGIC;
14 clk : IN STD_LOGIC;
15 rstn : IN STD_LOGIC;
15 rstn : IN STD_LOGIC;
16 --
16 --
17 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
17 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
18 --
18 --
19 set : IN STD_LOGIC;
19 set : IN STD_LOGIC;
20 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
20 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
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@@ -35,13 +35,13 PACKAGE general_purpose IS
35
35
36 COMPONENT general_counter
36 COMPONENT general_counter
37 GENERIC (
37 GENERIC (
38 CYCLIC : STD_LOGIC;
38 CYCLIC : STD_LOGIC := '1';
39 NB_BITS_COUNTER : INTEGER;
39 NB_BITS_COUNTER : INTEGER := 9;
40 RST_VALUE : INTEGER);
40 RST_VALUE : INTEGER := 0);
41 PORT (
41 PORT (
42 clk : IN STD_LOGIC;
42 clk : IN STD_LOGIC;
43 rstn : IN STD_LOGIC;
43 rstn : IN STD_LOGIC;
44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
45 set : IN STD_LOGIC;
45 set : IN STD_LOGIC;
46 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
46 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
47 add1 : IN STD_LOGIC;
47 add1 : IN STD_LOGIC;
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@@ -151,6 +151,8 ARCHITECTURE Behavioral OF apb_lfr_manag
151 SIGNAL INTERLEAVED : STD_LOGIC;
151 SIGNAL INTERLEAVED : STD_LOGIC;
152 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
153 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
154
155 signal fine_time_reg_info : std_logic_vector(26 downto 0);
154
156
155 BEGIN
157 BEGIN
156
158
@@ -185,6 +187,7 BEGIN
185 --
187 --
186 DAC_CAL_EN_s <= '0';
188 DAC_CAL_EN_s <= '0';
187 force_reset <= '0';
189 force_reset <= '0';
190
188 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
191 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
189 coarsetime_reg_updated <= '0';
192 coarsetime_reg_updated <= '0';
190
193
@@ -253,6 +256,8 BEGIN
253 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
256 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
254 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
257 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
255 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
258 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
259 WHEN ADDR_LFR_MANAGMENT_TIME_FINE_DELTA =>
260 Rdata(26 downto 0) <= fine_time_reg_info;
256 WHEN OTHERS =>
261 WHEN OTHERS =>
257 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
262 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
258 END CASE;
263 END CASE;
@@ -310,13 +315,6 BEGIN
310
315
311
316
312
317
313
314
315
316
317
318
319
320
318
321 -----------------------------------------------------------------------------
319 -----------------------------------------------------------------------------
322 -- IN
320 -- IN
@@ -333,72 +331,18 BEGIN
333
331
334 -----------------------------------------------------------------------------
332 -----------------------------------------------------------------------------
335 tick <= grspw_tick OR soft_tick;
333 tick <= grspw_tick OR soft_tick;
336
334
337 --SYNC_VALID_BIT_1 : SYNC_VALID_BIT
338 -- GENERIC MAP (
339 -- NB_FF_OF_SYNC => 2)
340 -- PORT MAP (
341 -- clk_in => clk25MHz,
342 -- rstn_in => resetn_25MHz,
343 -- clk_out => clk24_576MHz,
344 -- rstn_out => resetn_24_576MHz,
345 -- sin => tick,
346 -- sout => new_timecode);
347 new_timecode <= tick;
335 new_timecode <= tick;
348
349 --SYNC_VALID_BIT_2 : SYNC_VALID_BIT
350 -- GENERIC MAP (
351 -- NB_FF_OF_SYNC => 2)
352 -- PORT MAP (
353 -- clk_in => clk25MHz,
354 -- rstn_in => resetn_25MHz,
355 -- clk_out => clk24_576MHz,
356 -- rstn_out => resetn_24_576MHz,
357 -- sin => coarsetime_reg_updated,
358 -- sout => new_coarsetime);
359
336
360 new_coarsetime <= coarsetime_reg_updated;
337 new_coarsetime <= coarsetime_reg_updated;
361
362 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
363 -- GENERIC MAP (
364 -- NB_FF_OF_SYNC => 2)
365 -- PORT MAP (
366 -- clk_in => clk25MHz,
367 -- rstn_in => resetn_25MHz,
368 -- clk_out => clk24_576MHz,
369 -- rstn_out => resetn_24_576MHz,
370 -- sin => soft_reset,
371 -- sout => soft_reset_sync);
372
373
338
374 -----------------------------------------------------------------------------
339 -----------------------------------------------------------------------------
375 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
340 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
376
341
377 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
378 -- GENERIC MAP (
379 -- NB_FF_OF_SYNC => 2)
380 -- PORT MAP (
381 -- clk_in => clk24_576MHz,
382 -- rstn_in => resetn_24_576MHz,
383 -- clk_out => clk25MHz,
384 -- rstn_out => resetn_25MHz,
385 -- sin => time_new_49,
386 -- sout => time_new);
387
388 time_new <= time_new_49;
342 time_new <= time_new_49;
389
390 --PROCESS (clk25MHz, resetn_25MHz)
391 --BEGIN -- PROCESS
392 -- IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
393 -- fine_time_s <= (OTHERS => '0');
394 -- coarse_time_s <= (OTHERS => '0');
395 -- ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
396 -- IF time_new = '1' THEN
397 -- END IF;
398 -- END IF;
399 --END PROCESS;
400
343
401 fine_time_s <= fine_time_49;
344 fine_time_s <= fine_time_49;
345
402 coarse_time_s <= coarse_time_49;
346 coarse_time_s <= coarse_time_49;
403
347
404
348
@@ -424,7 +368,12 BEGIN
424 fine_time => fine_time_49,
368 fine_time => fine_time_49,
425 fine_time_new => fine_time_new_49,
369 fine_time_new => fine_time_new_49,
426 coarse_time => coarse_time_49,
370 coarse_time => coarse_time_49,
427 coarse_time_new => coarse_time_new_49);
371 coarse_time_new => coarse_time_new_49,
372
373 ft_counter_low => fine_time_reg_info( 8 downto 0),
374 ft_counter_low_max_value => fine_time_reg_info(26 downto 25),
375 ft_counter => fine_time_reg_info(24 downto 9)
376 );
428
377
429
378
430
379
@@ -477,15 +426,6 BEGIN
477
426
478
427
479
428
480
481
482
483
484
485
486
487
488
489
429
490
430
491 -----------------------------------------------------------------------------
431 -----------------------------------------------------------------------------
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@@ -23,7 +23,11 ENTITY fine_time_counter IS
23 FT_half : OUT STD_LOGIC;
23 FT_half : OUT STD_LOGIC;
24 FT_wait : OUT STD_LOGIC;
24 FT_wait : OUT STD_LOGIC;
25 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
25 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
26 fine_time_new : OUT STD_LOGIC
26 fine_time_new : OUT STD_LOGIC;
27
28 ft_counter_low : out STD_LOGIC_VECTOR( 8 downto 0);
29 ft_counter_low_max_value : out STD_LOGIC_VECTOR( 1 downto 0);
30 ft_counter : out STD_LOGIC_VECTOR(15 downto 0)
27 );
31 );
28
32
29 END fine_time_counter;
33 END fine_time_counter;
@@ -38,6 +42,8 ARCHITECTURE beh OF fine_time_counter IS
38 SIGNAL tick_value_gen : STD_LOGIC;
42 SIGNAL tick_value_gen : STD_LOGIC;
39 SIGNAL FT_max_s : STD_LOGIC;
43 SIGNAL FT_max_s : STD_LOGIC;
40
44
45 SIGNAL ft_counter_low_max_value_s : STD_LOGIC_VECTOR( 1 downto 0);
46
41 BEGIN -- beh
47 BEGIN -- beh
42
48
43 tick_value_gen <= tick OR FT_max_s;
49 tick_value_gen <= tick OR FT_max_s;
@@ -102,5 +108,24 BEGIN -- beh
102 END IF;
108 END IF;
103 END IF;
109 END IF;
104 END PROCESS;
110 END PROCESS;
111
112 ft_counter_low_max_value_s <= "00" when fine_time_max_value = STD_LOGIC_VECTOR(to_unsigned(379,9)) else
113 "01" when fine_time_max_value = STD_LOGIC_VECTOR(to_unsigned(380,9)) else
114 "10";-- when fine_time_max_value = STD_LOGIC_VECTOR(to_unsigned(381,9))
115
116 process (clk, rstn) is
117 begin -- process
118 if rstn = '0' then -- asynchronous reset (active low)
119 ft_counter_low <= (others => '0');
120 ft_counter_low_max_value <= (others => '0');
121 ft_counter <= (others => '0');
122 elsif clk'event and clk = '1' then -- rising clock edge
123 if tick = '1' then
124 ft_counter_low <= new_ft_counter;
125 ft_counter_low_max_value <= ft_counter_low_max_value_s;
126 ft_counter <= fine_time_counter;
127 end if;
128 end if;
129 end process;
105
130
106 END beh;
131 END beh;
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@@ -38,7 +38,11 ENTITY lfr_time_management IS
38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
39 fine_time_new : OUT STD_LOGIC;
39 fine_time_new : OUT STD_LOGIC;
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
41 coarse_time_new : OUT STD_LOGIC
41 coarse_time_new : OUT STD_LOGIC;
42
43 ft_counter_low : out STD_LOGIC_VECTOR( 8 downto 0);
44 ft_counter_low_max_value : out STD_LOGIC_VECTOR( 1 downto 0);
45 ft_counter : out STD_LOGIC_VECTOR(15 downto 0)
42 );
46 );
43 END lfr_time_management;
47 END lfr_time_management;
44
48
@@ -92,8 +96,11 BEGIN
92 FT_half => FT_half,
96 FT_half => FT_half,
93 FT_wait => FT_wait,
97 FT_wait => FT_wait,
94 fine_time => fine_time,
98 fine_time => fine_time,
95 fine_time_new => fine_time_new);
99 fine_time_new => fine_time_new,
96
100 ft_counter_low => ft_counter_low ,
101 ft_counter_low_max_value => ft_counter_low_max_value,
102 ft_counter => ft_counter
103 );
97 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
98 -- COARSE_TIME
105 -- COARSE_TIME
99 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
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@@ -70,7 +70,11 PACKAGE lpp_lfr_management IS
70 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
70 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
71 fine_time_new : OUT STD_LOGIC;
71 fine_time_new : OUT STD_LOGIC;
72 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 coarse_time_new : OUT STD_LOGIC);
73 coarse_time_new : OUT STD_LOGIC;
74 ft_counter_low : out STD_LOGIC_VECTOR( 8 downto 0);
75 ft_counter_low_max_value : out STD_LOGIC_VECTOR( 1 downto 0);
76 ft_counter : out STD_LOGIC_VECTOR(15 downto 0)
77 );
74 END COMPONENT;
78 END COMPONENT;
75
79
76 COMPONENT coarse_time_counter
80 COMPONENT coarse_time_counter
@@ -103,7 +107,11 PACKAGE lpp_lfr_management IS
103 FT_half : OUT STD_LOGIC;
107 FT_half : OUT STD_LOGIC;
104 FT_wait : OUT STD_LOGIC;
108 FT_wait : OUT STD_LOGIC;
105 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
109 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
106 fine_time_new : OUT STD_LOGIC);
110 fine_time_new : OUT STD_LOGIC;
111 ft_counter_low : out STD_LOGIC_VECTOR( 8 downto 0);
112 ft_counter_low_max_value : out STD_LOGIC_VECTOR( 1 downto 0);
113 ft_counter : out STD_LOGIC_VECTOR(15 downto 0)
114 );
107 END COMPONENT;
115 END COMPONENT;
108
116
109 COMPONENT fine_time_max_value_gen
117 COMPONENT fine_time_max_value_gen
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@@ -16,5 +16,6 PACKAGE lpp_lfr_management_apbreg_pkg IS
16 CONSTANT ADDR_LFR_MANAGMENT_DAC_N : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";
16 CONSTANT ADDR_LFR_MANAGMENT_DAC_N : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";
17 CONSTANT ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";
17 CONSTANT ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";
18 CONSTANT ADDR_LFR_MANAGMENT_DAC_DATA_IN : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";
18 CONSTANT ADDR_LFR_MANAGMENT_DAC_DATA_IN : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";
19 CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE_DELTA : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001100";
19
20
20 END lpp_lfr_management_apbreg_pkg;
21 END lpp_lfr_management_apbreg_pkg;
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@@ -37,8 +37,7 entity APB_ADVANCED_TRIGGER is
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0);
41 abits : integer := 8);
42 port (
41 port (
43 rstn : in std_ulogic;
42 rstn : in std_ulogic;
44 clk : in std_ulogic;
43 clk : in std_ulogic;
@@ -124,12 +123,12 begin
124
123
125 --APB Write OP
124 --APB Write OP
126 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
125 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
127 case apbi.paddr(abits-1 downto 2) is
126 case apbi.paddr(3 downto 2) is
128 when "000000" =>
127 when "00" =>
129 r.CFG <= apbi.pwdata;
128 r.CFG <= apbi.pwdata;
130 when "000001" =>
129 when "01" =>
131 r.Restart <= apbi.pwdata;
130 r.Restart <= apbi.pwdata;
132 when "000010" =>
131 when "10" =>
133 r.StartDate <= apbi.pwdata;
132 r.StartDate <= apbi.pwdata;
134 when others =>
133 when others =>
135 null;
134 null;
@@ -138,12 +137,12 begin
138
137
139 --APB READ OP
138 --APB READ OP
140 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
139 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
141 case apbi.paddr(abits-1 downto 2) is
140 case apbi.paddr(3 downto 2) is
142 when "000000" =>
141 when "00" =>
143 Rdata <= r.CFG;
142 Rdata <= r.CFG;
144 when "000001" =>
143 when "01" =>
145 Rdata <= r.Restart;
144 Rdata <= r.Restart;
146 when "000010" =>
145 when "10" =>
147 Rdata <= r.StartDate;
146 Rdata <= r.StartDate;
148 when others =>
147 when others =>
149 Rdata <= r.Restart;
148 Rdata <= r.Restart;
@@ -155,4 +154,4 begin
155 end process;
154 end process;
156
155
157 apbo.prdata <= Rdata when apbi.penable = '1';
156 apbo.prdata <= Rdata when apbi.penable = '1';
158 end beh; No newline at end of file
157 end beh;
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@@ -34,8 +34,7 component APB_ADVANCED_TRIGGER is
34 pindex : integer := 0;
34 pindex : integer := 0;
35 paddr : integer := 0;
35 paddr : integer := 0;
36 pmask : integer := 16#fff#;
36 pmask : integer := 16#fff#;
37 pirq : integer := 0;
37 pirq : integer := 0);
38 abits : integer := 8);
39 port (
38 port (
40 rstn : in std_ulogic;
39 rstn : in std_ulogic;
41 clk : in std_ulogic;
40 clk : in std_ulogic;
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@@ -127,19 +127,19 BEGIN
127
127
128 --APB Write OP
128 --APB Write OP
129 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
129 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
130 CASE apbi.paddr(abits-1 DOWNTO 2) IS
130 CASE apbi.paddr(4 DOWNTO 2) IS
131 WHEN "000000" =>
131 WHEN "000" =>
132 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
132 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
133 Reload <= apbi.pwdata(4);
133 Reload <= apbi.pwdata(4);
134 INTERLEAVED <= apbi.pwdata(5);
134 INTERLEAVED <= apbi.pwdata(5);
135 WHEN "000001" =>
135 WHEN "001" =>
136 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
136 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
137 WHEN "000010" =>
137 WHEN "010" =>
138 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
138 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
139 WHEN "000011" =>
139 WHEN "011" =>
140 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
140 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
141 LOAD_ADDRESSN <= '0';
141 LOAD_ADDRESSN <= '0';
142 WHEN "000100" =>
142 WHEN "100" =>
143 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
143 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
144 WEN <= '0';
144 WEN <= '0';
145 WHEN OTHERS =>
145 WHEN OTHERS =>
@@ -152,22 +152,22 BEGIN
152
152
153 --APB Read OP
153 --APB Read OP
154 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
154 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
155 CASE apbi.paddr(abits-1 DOWNTO 2) IS
155 CASE apbi.paddr(4 DOWNTO 2) IS
156 WHEN "000000" =>
156 WHEN "000" =>
157 Rdata(3 DOWNTO 0) <= DAC_CFG;
157 Rdata(3 DOWNTO 0) <= DAC_CFG;
158 Rdata(4) <= Reload;
158 Rdata(4) <= Reload;
159 Rdata(5) <= INTERLEAVED;
159 Rdata(5) <= INTERLEAVED;
160 Rdata(31 DOWNTO 6) <= (OTHERS => '0');
160 Rdata(31 DOWNTO 6) <= (OTHERS => '0');
161 WHEN "000001" =>
161 WHEN "001" =>
162 Rdata(PRESZ-1 DOWNTO 0) <= pre;
162 Rdata(PRESZ-1 DOWNTO 0) <= pre;
163 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
163 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
164 WHEN "000010" =>
164 WHEN "010" =>
165 Rdata(CPTSZ-1 DOWNTO 0) <= N;
165 Rdata(CPTSZ-1 DOWNTO 0) <= N;
166 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
166 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
167 WHEN "000011" =>
167 WHEN "011" =>
168 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
168 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
169 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
169 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
170 WHEN "000100" =>
170 WHEN "100" =>
171 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
171 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
172 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
172 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
173 WHEN OTHERS =>
173 WHEN OTHERS =>
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@@ -41,7 +41,7 component apb_lfr_cal is
41 CPTSZ : integer := 16;
41 CPTSZ : integer := 16;
42 datawidth : integer := 18;
42 datawidth : integer := 18;
43 dacresolution : integer := 12;
43 dacresolution : integer := 12;
44 abits : integer := 8);
44 abits : INTEGER := 8);
45 port (
45 port (
46 rstn : in std_logic;
46 rstn : in std_logic;
47 clk : in std_logic;
47 clk : in std_logic;
@@ -235,4 +235,4 port(
235 );
235 );
236 end component;
236 end component;
237
237
238 end; No newline at end of file
238 end;
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