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Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...
Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.

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lpp_lfr_management_apbreg_pkg.vhd
21 lines | 1.3 KiB | text/x-vhdl | VhdlLexer
/ lib / lpp / lfr_management / lpp_lfr_management_apbreg_pkg.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
PACKAGE lpp_lfr_management_apbreg_pkg IS
CONSTANT ADDR_LFR_MANAGMENT_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";
CONSTANT ADDR_LFR_MANAGMENT_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";
CONSTANT ADDR_LFR_MANAGMENT_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";
CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";
CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";
CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";
CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";
CONSTANT ADDR_LFR_MANAGMENT_DAC_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000111";
CONSTANT ADDR_LFR_MANAGMENT_DAC_PRE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001000";
CONSTANT ADDR_LFR_MANAGMENT_DAC_N : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";
CONSTANT ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";
CONSTANT ADDR_LFR_MANAGMENT_DAC_DATA_IN : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";
CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE_DELTA : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001100";
END lpp_lfr_management_apbreg_pkg;