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Activated F2 and F3 IIR Filters for LFR_FILTERS tests....
Activated F2 and F3 IIR Filters for LFR_FILTERS tests. Improved Makefiles for LFR_FILTERS tests.
Alexis Jeandet - - Load All Authors

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DISCOSPACE_top_libero.prj
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KEY LIBERO "9.1"
KEY CAPTURE "9.1.5.1"
KEY DEFAULT_IMPORT_LOC "C:\opt\VHDLIB\tests\Validation_LFR_Filters"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "2f64e589-285c-45b2-b6c4-709f59f83db9"
KEY HDLTechnology "VHDL"
KEY VendorTechnology_Family "ProASIC3E"
KEY VendorTechnology_Die "IT14X14M4"
KEY VendorTechnology_Package "fg324"
KEY ProjectLocation "C:\opt\VHDLIB\designs\TIMEGEN"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "DISCOSPACE_top::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
VALUE="Impl2",NUM=2
CURREV=2
ENDLIST
LIST LIBRARIES
grlib
synplify
techmap
spw
eth
opencores
gaisler
esa
fmf
spansion
gsi
iap
lpp
cypress
ENDLIST
LIST LIBRARY_grlib
ALIAS=grlib
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_synplify
ALIAS=synplify
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_techmap
ALIAS=techmap
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_spw
ALIAS=spw
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_eth
ALIAS=eth
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_opencores
ALIAS=opencores
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_gaisler
ALIAS=gaisler
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_esa
ALIAS=esa
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_fmf
ALIAS=fmf
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_spansion
ALIAS=spansion
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_gsi
ALIAS=gsi
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_iap
ALIAS=iap
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_lpp
ALIAS=lpp
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARY_cypress
ALIAS=cypress
COMPILE_OPTION=COMPILE
ENDLIST
LIST FileManager
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl"
STATE="utd"
TIME="1472547172"
SIZE="3091"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl"
STATE="utd"
TIME="1472547172"
SIZE="1890"
LIBRARY="lpp"
ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_comb.vhd,hdl"
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SIZE="3112"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_downsampler.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_integrator.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_address_gen.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_add_sub.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control_r2.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_r2.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_pkg.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3_DATAFLOW.vhd,hdl"
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ENDFILE
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ENDFILE
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\FFT.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
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ENDFILE
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
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ENDFILE
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_rom.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function_pkg.vhd,hdl"
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ENDFILE
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_reader.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_recorder.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_sim_pkg.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_lfr_sim_pkg.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\components.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\package_utility.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1380d.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\work\debug\debug.vhd,hdl"
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ENDFILELIST
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=true
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
EnableFileDetection=FALSE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=stp
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="Synplify 2012-03A-SP1-2"
FUNCTION="Synthesis"
TOOL="Synplify"
LOCATION="C:\Synopsys\synplify_F201203ASP1-2\bin\synplify_pro.exe"
PARAM=""
BATCH=0
EndProfile
NAME="Questa"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\questasim64_10.5c\win64\questasim.exe"
PARAM=""
BATCH=0
EndProfile
NAME="WFL"
FUNCTION="Stimulus"
TOOL="WFL"
LOCATION="syncad.exe"
PARAM="-pwflite"
BATCH=0
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Microsemi\Libero_v9.1\Designer\bin\FlashPro.exe"
PARAM=""
BATCH=0
EndProfile
ENDLIST
LIST ProjectState5.1
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
LIST DISCOSPACE_top
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst_pkg.vhd,hdl"
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ENDLIST
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
LIST "DISCOSPACE_top"
LIST "ideSYNTHESIS"
USE_LIST=TRUE
FILELIST
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmul.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\nandtree.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad_ds.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ds.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iodpad.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ds.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\lvds_combo.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\odpad.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\skew_outpad.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\cpu_disas_net.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl"
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl"
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