|
|
KEY LIBERO "9.1"
|
|
|
KEY CAPTURE "9.1.5.1"
|
|
|
KEY DEFAULT_IMPORT_LOC "C:\opt\VHDLIB\tests\Validation_LFR_Filters"
|
|
|
KEY DEFAULT_OPEN_LOC ""
|
|
|
KEY ProjectID "2f64e589-285c-45b2-b6c4-709f59f83db9"
|
|
|
KEY HDLTechnology "VHDL"
|
|
|
KEY VendorTechnology_Family "ProASIC3E"
|
|
|
KEY VendorTechnology_Die "IT14X14M4"
|
|
|
KEY VendorTechnology_Package "fg324"
|
|
|
KEY ProjectLocation "C:\opt\VHDLIB\designs\TIMEGEN"
|
|
|
KEY SimulationType "VHDL"
|
|
|
KEY Vendor "Actel"
|
|
|
KEY ActiveRoot "DISCOSPACE_top::work"
|
|
|
LIST REVISIONS
|
|
|
VALUE="Impl1",NUM=1
|
|
|
VALUE="Impl2",NUM=2
|
|
|
CURREV=2
|
|
|
ENDLIST
|
|
|
LIST LIBRARIES
|
|
|
grlib
|
|
|
synplify
|
|
|
techmap
|
|
|
spw
|
|
|
eth
|
|
|
opencores
|
|
|
gaisler
|
|
|
esa
|
|
|
fmf
|
|
|
spansion
|
|
|
gsi
|
|
|
iap
|
|
|
lpp
|
|
|
cypress
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_grlib
|
|
|
ALIAS=grlib
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_synplify
|
|
|
ALIAS=synplify
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_techmap
|
|
|
ALIAS=techmap
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_spw
|
|
|
ALIAS=spw
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_eth
|
|
|
ALIAS=eth
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_opencores
|
|
|
ALIAS=opencores
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_gaisler
|
|
|
ALIAS=gaisler
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_esa
|
|
|
ALIAS=esa
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_fmf
|
|
|
ALIAS=fmf
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_spansion
|
|
|
ALIAS=spansion
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_gsi
|
|
|
ALIAS=gsi
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_iap
|
|
|
ALIAS=iap
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_lpp
|
|
|
ALIAS=lpp
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_cypress
|
|
|
ALIAS=cypress
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST FileManager
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="3091"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="1890"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="4795"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_comb.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="3112"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_downsampler.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="3141"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_integrator.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="2735"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="15484"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_address_gen.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="2919"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_add_sub.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="3324"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="10820"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control_r2.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="10988"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_r2.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="15918"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_pkg.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="6861"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="7426"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1478688463"
|
|
|
SIZE="9785"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1478082550"
|
|
|
SIZE="11300"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1478196483"
|
|
|
SIZE="7913"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1478082253"
|
|
|
SIZE="17692"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3_DATAFLOW.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="6368"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1478688463"
|
|
|
SIZE="11622"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="2383"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1478688463"
|
|
|
SIZE="3777"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1478196483"
|
|
|
SIZE="5046"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="2773"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="141871"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="4034"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="12457"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="3995"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\FFT.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="3947"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="25884"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="32249"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="5049"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="3730"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="9069"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="3997"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="12080"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_processing.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="3794"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_rom.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="4946"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="3069"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function_pkg.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="2981"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Adder.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="2284"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="1930"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ALU.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="2952"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="1958"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_Divider2.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="685"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clock_Divider.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="2306"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\data_type_pkg.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="2319"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_counter.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="1537"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1479489159"
|
|
|
SIZE="13529"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_detection.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1472547172"
|
|
|
SIZE="2014"
|
|
|
LIBRARY="lpp"
|
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncrambw.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2pbw.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\sdram_phy.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\from.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncreg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\serdes.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\synpe_maps.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\spw\comp\spwcomp.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\spw\core\synpe_core.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_gen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw2_gen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_codec_gen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\eth\comp\ethcomp.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_pkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_rstgen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_edcl_ahb_mst.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst_gbit.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_rx.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_tx.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_gtx.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_tx.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_rx.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbitc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\grethc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gbit_gen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\cancomp.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_sync.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_core_sync.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\arith.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\mul32.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\div32.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\memctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl64.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdmctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\srctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ssrctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrlc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl8.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdmctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftmctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl64.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\synpe_grlfpu.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\synpe_grlfpc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuconfig.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuiface.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\libmmu.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlbcam.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulrue.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulru.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlb.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutw.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmu.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\leon3.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\grfpushwx.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\synpe_leon3v3.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp2x.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp2x.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\l2cache\v2-pkg\l2cache.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mod.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\canmux.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_rd.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc_core.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\grcan.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\misc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\rstgen.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gptimer.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbdpram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mmb.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mb.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpio.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbstat.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\logan.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbps2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom_package.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbvga.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb2ahb.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbbridge.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\svgactrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grfifo.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gradcdac.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grsysmon.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gracectrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpreg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\memscrub.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb_mst_iface.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgprbank.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate2x.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grtimer.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grpulse.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grversion.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbfrom.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\net\net.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\uart.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\libdcom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\apbuart.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom_uart.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\ahbuart.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtag.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\libjtagcom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag_bsd.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregs.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregsbd.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\ethernet_mac.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_mb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit_mb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\grethm.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\rgmii.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\comma_detect.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\elastic_buffer.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\spacewire.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspwm.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2_phy.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_codec_clockgate.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_phy.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pads.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandpkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrlx.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\clk2x.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod_prect.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\memoryctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\mctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices_list.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\memctrlr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-0ws.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-1ws.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\data_type_pkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ALU.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Adder.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_Divider2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUX2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUXN.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Multiplier.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\REG.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_FF.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Shifter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TwoComplementer.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clock_Divider.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_to_level.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_detection.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_VALID_BIT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\RR_Arbiter_4.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_counter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ramp_generator.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TimeGenAdvancedTrigger.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\APB_ADVANCED_TRIGGER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3_DATAFLOW.vhd,hdl"
|
|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_integrator.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_downsampler.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_comb.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_add_sub.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_address_gen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_r2.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control_r2.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_processing.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_rom.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_memory.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_control.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_0.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_1.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lppFIFOxN.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\FFT.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\APB_LFR_CAL.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_READER.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_WRITER.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\SPI_DAC_DRIVER.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\dynamic_freq_div.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lfr_cal_driver.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management_apbreg_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\apb_lfr_management.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lfr_time_management.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_counter.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\coarse_time_counter.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_max_value_gen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\RHF1401.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401_withFilter.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\TestModule_RHF1401.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_ADS7886_v2.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr_v2.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_lfr_hk.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_package.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_calculation.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_control.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_switch_f0.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_time_managment.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\DEMUX.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\lpp_demux.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_GestionBuffer.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_Arbiter.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_burst.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_dma_genvalid.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter_reg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_pkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl"
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|
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VALUE "<project>\DISCOSPACE_top.vhd,hdl"
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ENDFILELIST
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ENDLIST
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LIST "ideSIMULATION"
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USE_LIST=TRUE
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FILELIST
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\version.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config_types.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdlib.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdio.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\testlib.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\ftlib\mtie_ftlib.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\util\util.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc_disas.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\cpu_disas.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\multlib.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\leaves.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\devices.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\defmst.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbctrl.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbctrl.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmst.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmon.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbmon.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ambamon.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba_tp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_util.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahbs.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_ctrl.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synplify.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synattr.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\gencomp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\netcomp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\memory_inferred.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\tap_inferred.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_inferred.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\mul_inferred.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_phy_inferred.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddrphy_datapath.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\sim_pll.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\lpddr2_phy_inferred.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\buffer_apa3e.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\clkgen_proasic3e.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\ddr_proasic3e.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\memory_apa3e.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\pads_apa3e.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\tap_proasic3e.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allclkgen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allddr.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmem.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmul.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allpads.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\alltap.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkgen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkmux.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkinv.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkand.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_ireg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_oreg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddrphy.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram64.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2p.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_dp.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncfifo_2p.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\regfile_3p.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\tap.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techbuf.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\nandtree.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad_ds.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ds.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iodpad.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ds.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\lvds_combo.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\odpad.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ds.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\toutpad.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\skew_outpad.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mul_61x61.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\cpu_disas_net.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ringosc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grpci2_phy_net.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\system_monitor.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grgates.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ddr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ddr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ddr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128bw.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram256bw.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram156bw.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techmult.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\spictrl_net.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncrambw.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2pbw.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\sdram_phy.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\from.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncreg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\serdes.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mtie_maps.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\spw\comp\spwcomp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\spw\core\mtie_core.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_gen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw2_gen.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_codec_gen.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\comp\ethcomp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_rstgen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_edcl_ahb_mst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst_gbit.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_rx.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_tx.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_gtx.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_tx.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_rx.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbitc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\grethc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gen.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gbit_gen.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\cancomp.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_sync.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_core_sync.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\arith.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\mul32.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\div32.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\memctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl64.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdmctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\srctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ssrctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrlc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl8.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdmctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftmctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl64.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\mtie_grlfpu.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\mtie_grlfpc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuconfig.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuiface.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\libmmu.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlbcam.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulrue.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulru.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmu.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\leon3.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\grfpushwx.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\mtie_leon3v3.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp2x.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp2x.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\l2cache\v2-pkg\l2cache.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mod.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\canmux.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_rd.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc_core.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\grcan.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\misc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\rstgen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gptimer.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbdpram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mmb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpio.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbstat.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\logan.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbps2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom_package.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbvga.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb2ahb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbbridge.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\svgactrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grfifo.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gradcdac.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grsysmon.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gracectrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpreg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\memscrub.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb_mst_iface.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgprbank.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate2x.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grtimer.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grpulse.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grversion.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbfrom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbp.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbm.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\net\net.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\uart.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\libdcom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\apbuart.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom_uart.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\ahbuart.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sim.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sramft.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram16.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\phy.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ahbrep.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\delay_wire.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\pwm_check.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ramback.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\zbtssram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\slavecheck.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtrace.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtracev.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddrram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr2ram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr3ram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtag.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\libjtagcom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag_bsd.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregs.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregsbd.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagtst.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\ethernet_mac.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_mb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit_mb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\grethm.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\rgmii.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\comma_detect.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\elastic_buffer.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\spacewire.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspwm.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2_phy.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_codec_clockgate.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_phy.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pads.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\simtrans1553.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandpkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrlx.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\clk2x.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod_prect.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\memoryctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\mctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\conversions.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\gen_utils.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\flash.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\s25fl064a.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\m25p80.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\fifo\idt7202.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\functions.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\core_burst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\g880e18bt.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices_list.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\memctrlr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-0ws.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-1ws.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\data_type_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ALU.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Adder.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_Divider2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUX2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUXN.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Multiplier.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\REG.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_FF.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Shifter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TwoComplementer.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clock_Divider.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_to_level.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_detection.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_VALID_BIT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\RR_Arbiter_4.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_counter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ramp_generator.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TimeGenAdvancedTrigger.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\APB_ADVANCED_TRIGGER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3_DATAFLOW.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_integrator.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_downsampler.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_comb.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_add_sub.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_address_gen.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_r2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control_r2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_processing.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_rom.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_memory.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_control.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_0.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_1.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lppFIFOxN.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\FFT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\APB_LFR_CAL.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_READER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_WRITER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\SPI_DAC_DRIVER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\dynamic_freq_div.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lfr_cal_driver.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management_apbreg_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\apb_lfr_management.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lfr_time_management.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_counter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\coarse_time_counter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_max_value_gen.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\RHF1401.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401_withFilter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\TestModule_RHF1401.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_ADS7886_v2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr_v2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_lfr_hk.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_package.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_calculation.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_control.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_switch_f0.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_time_managment.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\DEMUX.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\lpp_demux.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_GestionBuffer.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_Arbiter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_burst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_dma_genvalid.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter_reg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_reader.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_recorder.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_sim_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_lfr_sim_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\components.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\package_utility.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1380d.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\work\debug\debug.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\work\debug\grtestmod.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\work\debug\cpu_disas.vhd,hdl"
|
|
|
VALUE "<project>\DISCOSPACE_top.vhd,hdl"
|
|
|
ENDFILELIST
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
LIST AssociatedStimulus
|
|
|
ENDLIST
|
|
|
LIST Other_Association
|
|
|
ENDLIST
|
|
|
LIST SimulationOptions
|
|
|
UseAutomaticDoFile=true
|
|
|
IncludeWaveDo=true
|
|
|
Type=max
|
|
|
RunTime=1000ns
|
|
|
Resolution=1ps
|
|
|
VsimOpt=
|
|
|
EntityName=testbench
|
|
|
TopInstanceName=<top>_0
|
|
|
DoFileName=
|
|
|
DoFileName2=wave.do
|
|
|
DoFileParams=
|
|
|
DisplayDUTWave=false
|
|
|
LogAllSignals=false
|
|
|
DumpVCD=false
|
|
|
VCDFileName=power.vcd
|
|
|
ENDLIST
|
|
|
LIST ModelSimLibPath
|
|
|
UseCustomPath=FALSE
|
|
|
LibraryPath=
|
|
|
ENDLIST
|
|
|
LIST GlobalFlowOptions
|
|
|
GenerateHDLAfterSynthesis=FALSE
|
|
|
GenerateHDLAfterPhySynthesis=FALSE
|
|
|
RunDRCAfterSynthesis=FALSE
|
|
|
AutoCheckConstraints=TRUE
|
|
|
UpdateViewDrawIni=TRUE
|
|
|
UpdateModelSimIni=TRUE
|
|
|
EnableFileDetection=FALSE
|
|
|
NoIOMode=FALSE
|
|
|
GenerateHDLFromSchematic=TRUE
|
|
|
FlashProInputFile=stp
|
|
|
SmartGenCompileReport=T
|
|
|
ENDLIST
|
|
|
LIST PhySynthesisOptions
|
|
|
ENDLIST
|
|
|
LIST Profiles
|
|
|
NAME="Synplify 2012-03A-SP1-2"
|
|
|
FUNCTION="Synthesis"
|
|
|
TOOL="Synplify"
|
|
|
LOCATION="C:\Synopsys\synplify_F201203ASP1-2\bin\synplify_pro.exe"
|
|
|
PARAM=""
|
|
|
BATCH=0
|
|
|
EndProfile
|
|
|
NAME="Questa"
|
|
|
FUNCTION="Simulation"
|
|
|
TOOL="ModelSim"
|
|
|
LOCATION="C:\questasim64_10.5c\win64\questasim.exe"
|
|
|
PARAM=""
|
|
|
BATCH=0
|
|
|
EndProfile
|
|
|
NAME="WFL"
|
|
|
FUNCTION="Stimulus"
|
|
|
TOOL="WFL"
|
|
|
LOCATION="syncad.exe"
|
|
|
PARAM="-pwflite"
|
|
|
BATCH=0
|
|
|
EndProfile
|
|
|
NAME="FlashPro"
|
|
|
FUNCTION="Program"
|
|
|
TOOL="FlashPro"
|
|
|
LOCATION="C:\Microsemi\Libero_v9.1\Designer\bin\FlashPro.exe"
|
|
|
PARAM=""
|
|
|
BATCH=0
|
|
|
EndProfile
|
|
|
ENDLIST
|
|
|
LIST ProjectState5.1
|
|
|
ENDLIST
|
|
|
LIST ExcludePackageForSimulation
|
|
|
ENDLIST
|
|
|
LIST ExcludePackageForSynthesis
|
|
|
LIST DISCOSPACE_top
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdio.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\testlib.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\ftlib\mtie_ftlib.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\util\util.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc_disas.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\cpu_disas.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmon.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbmon.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ambamon.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba_tp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_util.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahbs.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_ctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synplify.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synattr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\sim_pll.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\lpddr2_phy_inferred.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mtie_maps.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\spw\core\mtie_core.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\mtie_grlfpu.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\mtie_grlfpc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\mtie_leon3v3.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbm.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sim.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sramft.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram16.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\phy.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ahbrep.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\delay_wire.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\pwm_check.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ramback.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\zbtssram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\slavecheck.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtrace.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtracev.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddrram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr2ram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr3ram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagtst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\simtrans1553.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\conversions.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\gen_utils.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\flash.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\s25fl064a.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\m25p80.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\fifo\idt7202.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\functions.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\core_burst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\g880e18bt.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_reader.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_recorder.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_sim_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_lfr_sim_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\components.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\package_utility.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1380d.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\work\debug\debug.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\work\debug\grtestmod.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\work\debug\cpu_disas.vhd,hdl"
|
|
|
ENDLIST
|
|
|
ENDLIST
|
|
|
LIST IncludeModuleForSimulation
|
|
|
ENDLIST
|
|
|
LIST CDBOrder
|
|
|
ENDLIST
|
|
|
LIST UserCustomizedFileList
|
|
|
LIST "DISCOSPACE_top"
|
|
|
LIST "ideSYNTHESIS"
|
|
|
USE_LIST=TRUE
|
|
|
FILELIST
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\version.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config_types.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdlib.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\ftlib\synpe_ftlib.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\multlib.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\leaves.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\devices.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\defmst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\gencomp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\netcomp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\memory_inferred.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\tap_inferred.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_inferred.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\mul_inferred.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_phy_inferred.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddrphy_datapath.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\buffer_apa3e.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\clkgen_proasic3e.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\ddr_proasic3e.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\memory_apa3e.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\pads_apa3e.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\tap_proasic3e.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allclkgen.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allddr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmem.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmul.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allpads.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\alltap.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkgen.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkmux.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkinv.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkand.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_ireg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_oreg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddrphy.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram64.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2p.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_dp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncfifo_2p.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\regfile_3p.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\tap.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techbuf.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\nandtree.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad_ds.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ds.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iodpad.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ds.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\lvds_combo.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\odpad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ds.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\toutpad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\skew_outpad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mul_61x61.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\cpu_disas_net.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ringosc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grpci2_phy_net.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\system_monitor.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grgates.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ddr.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ddr.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ddr.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128bw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram256bw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram156bw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techmult.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\spictrl_net.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncrambw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2pbw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\sdram_phy.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\from.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncreg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\serdes.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\synpe_maps.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\spw\comp\spwcomp.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\spw\core\synpe_core.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_gen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw2_gen.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_codec_gen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\eth\comp\ethcomp.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_pkg.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_rstgen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_edcl_ahb_mst.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst_gbit.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_rx.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_tx.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_gtx.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_tx.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_rx.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbitc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\grethc.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gbit_gen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\cancomp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_sync.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_core_sync.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\arith.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\mul32.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\div32.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\memctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl64.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdmctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\srctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ssrctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrlc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl8.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdmctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftmctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl64.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\synpe_grlfpu.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\synpe_grlfpc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuconfig.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuiface.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\libmmu.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlbcam.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulrue.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulru.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlb.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmu.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\leon3.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\grfpushwx.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\synpe_leon3v3.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp2x.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp2x.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\l2cache\v2-pkg\l2cache.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mod.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\canmux.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_rd.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc_core.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\grcan.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\misc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\rstgen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gptimer.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbdpram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mmb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpio.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbstat.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\logan.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbps2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom_package.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbvga.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb2ahb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbbridge.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\svgactrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grfifo.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gradcdac.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grsysmon.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gracectrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpreg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\memscrub.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb_mst_iface.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgprbank.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate2x.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grtimer.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grpulse.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grversion.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbfrom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\net\net.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\uart.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\libdcom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\apbuart.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom_uart.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\ahbuart.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtag.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\libjtagcom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag_bsd.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregs.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregsbd.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\ethernet_mac.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_mb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit_mb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\grethm.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\rgmii.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\comma_detect.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\elastic_buffer.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\spacewire.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspwm.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2_phy.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_codec_clockgate.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_phy.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pads.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandpkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrlx.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrl.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\clk2x.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod_prect.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\memoryctrl.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\mctrl.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices_list.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\memctrlr.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-0ws.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-1ws.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\data_type_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ALU.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Adder.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_Divider2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUX2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUXN.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Multiplier.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\REG.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_FF.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Shifter.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TwoComplementer.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clock_Divider.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_to_level.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_detection.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_VALID_BIT.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\RR_Arbiter_4.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_counter.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ramp_generator.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TimeGenAdvancedTrigger.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\APB_ADVANCED_TRIGGER.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3_DATAFLOW.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_integrator.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_downsampler.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_comb.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_add_sub.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_address_gen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_r2.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control_r2.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_processing.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_rom.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_memory.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_control.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_0.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_1.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lppFIFOxN.vhd,hdl"
|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\FFT.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\APB_LFR_CAL.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_READER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_WRITER.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\SPI_DAC_DRIVER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\dynamic_freq_div.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lfr_cal_driver.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management_apbreg_pkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\apb_lfr_management.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lfr_time_management.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_counter.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\coarse_time_counter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_max_value_gen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\RHF1401.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401_withFilter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\TestModule_RHF1401.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_ADS7886_v2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr_v2.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_lfr_hk.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_package.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_calculation.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_control.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_switch_f0.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_time_managment.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\DEMUX.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\lpp_demux.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_GestionBuffer.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_Arbiter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_burst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_dma_genvalid.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter_reg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_pkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl"
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|
|
VALUE "<project>\DISCOSPACE_top.vhd,hdl"
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ENDFILELIST
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ENDLIST
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LIST "ideSIMULATION"
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USE_LIST=TRUE
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FILELIST
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\version.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config_types.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdlib.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdio.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\testlib.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\ftlib\mtie_ftlib.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\util\util.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc_disas.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\cpu_disas.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\multlib.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\leaves.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\devices.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\defmst.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbctrl.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbctrl.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmst.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmon.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbmon.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ambamon.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba_tp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv_pkg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_util.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahbs.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_ctrl.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synplify.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synattr.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\gencomp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\netcomp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\memory_inferred.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\tap_inferred.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_inferred.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\mul_inferred.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_phy_inferred.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddrphy_datapath.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\sim_pll.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\lpddr2_phy_inferred.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\buffer_apa3e.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\clkgen_proasic3e.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\ddr_proasic3e.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\memory_apa3e.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\pads_apa3e.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\tap_proasic3e.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allclkgen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allddr.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmem.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmul.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allpads.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\alltap.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkgen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkmux.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkinv.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkand.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_ireg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_oreg.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddrphy.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram64.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2p.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_dp.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncfifo_2p.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\regfile_3p.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\tap.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techbuf.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\nandtree.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad_ds.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ds.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iodpad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ds.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\lvds_combo.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\odpad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ds.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\toutpad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\skew_outpad.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mul_61x61.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\cpu_disas_net.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ringosc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grpci2_phy_net.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\system_monitor.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grgates.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ddr.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ddr.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ddr.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128bw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram256bw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram156bw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techmult.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\spictrl_net.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncrambw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2pbw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\sdram_phy.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\from.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncreg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\serdes.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mtie_maps.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\spw\comp\spwcomp.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\spw\core\mtie_core.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_gen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw2_gen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_codec_gen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\eth\comp\ethcomp.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_pkg.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_rstgen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_edcl_ahb_mst.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst_gbit.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_rx.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_tx.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_gtx.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_tx.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_rx.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbitc.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\eth\core\grethc.vhd,hdl"
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|
VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gbit_gen.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\cancomp.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_sync.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_core_sync.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\arith.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\mul32.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\div32.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\memctrl.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl64.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdmctrl.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\srctrl.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ssrctrl.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrlc.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl8.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdmctrl.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftmctrl.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl64.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\mtie_grlfpu.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\mtie_grlfpc.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuconfig.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuiface.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\libmmu.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlbcam.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulrue.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulru.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutw.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmu.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\leon3.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\grfpushwx.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\mtie_leon3v3.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp2x.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp2x.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\l2cache\v2-pkg\l2cache.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mod.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\canmux.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_rd.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc_core.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\grcan.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\misc.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\rstgen.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gptimer.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbdpram.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mmb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mb.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpio.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram2.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbstat.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\logan.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbps2.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom_package.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbvga.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb2ahb.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbbridge.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\svgactrl.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grfifo.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gradcdac.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grsysmon.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gracectrl.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpreg.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\memscrub.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb_mst_iface.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgprbank.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate2x.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grtimer.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grpulse.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grversion.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbfrom.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbp.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbm.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\net\net.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\uart.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\libdcom.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\apbuart.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom_uart.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\ahbuart.vhd,hdl"
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|
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sim.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram.vhd,hdl"
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VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sramft.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram16.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\phy.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ahbrep.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\delay_wire.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\pwm_check.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ramback.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\zbtssram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\slavecheck.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtrace.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtracev.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddrram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr2ram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr3ram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtag.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\libjtagcom.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag_bsd.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregs.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregsbd.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagtst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\ethernet_mac.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_mb.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit_mb.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\grethm.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\rgmii.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\comma_detect.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\elastic_buffer.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\spacewire.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspwm.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2_phy.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_codec_clockgate.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_phy.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pads.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\simtrans1553.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandpkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrlx.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\clk2x.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod_prect.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\memoryctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\mctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\conversions.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\gen_utils.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\flash.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\s25fl064a.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\m25p80.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\fmf\fifo\idt7202.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\functions.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\core_burst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\g880e18bt.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices_list.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\memctrlr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-0ws.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-1ws.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\data_type_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ALU.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Adder.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_Divider2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUX2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUXN.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Multiplier.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\REG.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_FF.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Shifter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TwoComplementer.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clock_Divider.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_to_level.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_detection.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_VALID_BIT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\RR_Arbiter_4.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_counter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ramp_generator.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TimeGenAdvancedTrigger.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\APB_ADVANCED_TRIGGER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3_DATAFLOW.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_integrator.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_downsampler.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_comb.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_add_sub.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_address_gen.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_r2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control_r2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_processing.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_rom.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_memory.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_control.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_0.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_1.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lppFIFOxN.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\FFT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\APB_LFR_CAL.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_READER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_WRITER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\SPI_DAC_DRIVER.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\dynamic_freq_div.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lfr_cal_driver.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management_apbreg_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\apb_lfr_management.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lfr_time_management.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_counter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\coarse_time_counter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_max_value_gen.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\RHF1401.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401_withFilter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\TestModule_RHF1401.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_ADS7886_v2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr_v2.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_lfr_hk.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_package.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_calculation.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_control.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_switch_f0.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_time_managment.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\DEMUX.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\lpp_demux.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd,hdl"
|
|
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VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_GestionBuffer.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_Arbiter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_burst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_dma_genvalid.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter_reg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_reader.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_recorder.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_sim_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_lfr_sim_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\components.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\package_utility.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1380d.vhd,hdl"
|
|
|
VALUE "<project>\..\..\..\GRLIB\lib\work\debug\debug.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\work\debug\grtestmod.vhd,hdl"
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|
|
VALUE "<project>\..\..\..\GRLIB\lib\work\debug\cpu_disas.vhd,hdl"
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|
|
VALUE "<project>\DISCOSPACE_top.vhd,hdl"
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|
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