diff --git a/designs/TIMEGEN/DISCOSPACE_top - Copie.vhd b/designs/TIMEGEN/DISCOSPACE_top - Copie.vhd deleted file mode 100644 --- a/designs/TIMEGEN/DISCOSPACE_top - Copie.vhd +++ /dev/null @@ -1,584 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2016, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -use lpp.lpp_amba.all; -USE lpp.lpp_lfr_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - -ENTITY DISCOSPACE_top IS - - PORT ( - clk100MHz : IN STD_LOGIC; - clk49_152MHz : IN STD_LOGIC; - reset : IN STD_LOGIC; - --BPs - BP0 : IN STD_LOGIC; - BP1 : IN STD_LOGIC; - --LEDs - LED0 : OUT STD_LOGIC; - LED1 : OUT STD_LOGIC; - LED2 : OUT STD_LOGIC; - --UARTs - TXD1 : IN STD_LOGIC; - RXD1 : OUT STD_LOGIC; - nCTS1 : OUT STD_LOGIC; - nRTS1 : IN STD_LOGIC; - - TXD2 : IN STD_LOGIC; - RXD2 : OUT STD_LOGIC; - nCTS2 : OUT STD_LOGIC; - nDTR2 : IN STD_LOGIC; - nRTS2 : IN STD_LOGIC; - nDCD2 : OUT STD_LOGIC; - - --EXT CONNECTOR - DISCO1_TRIG1 : OUT STD_LOGIC; - DISCO2_TRIG1 : OUT STD_LOGIC; - DISCO3_TRIG1 : OUT STD_LOGIC; - DISCO4_TRIG1 : OUT STD_LOGIC; - - -- MINI LFR ADC INPUTS - ADC_nCS : OUT STD_LOGIC; - ADC_CLK : OUT STD_LOGIC; - ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - --SPACE WIRE - SPW_EN : OUT STD_LOGIC; -- 0 => off - SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK - SPW_NOM_SIN : IN STD_LOGIC; - SPW_NOM_DOUT : OUT STD_LOGIC; - SPW_NOM_SOUT : OUT STD_LOGIC; - SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK - SPW_RED_SIN : IN STD_LOGIC; - SPW_RED_DOUT : OUT STD_LOGIC; - SPW_RED_SOUT : OUT STD_LOGIC; - - -- SRAM - SRAM_nWE : OUT STD_LOGIC; - SRAM_CE : OUT STD_LOGIC; - SRAM_nOE : OUT STD_LOGIC; - SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - -END DISCOSPACE_top; - - -ARCHITECTURE beh OF DISCOSPACE_top IS - ---========================================================================== --- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board --- when enabled, chip enable polarity should be reversed and bank size also --- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9 --- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8 ---========================================================================== - CONSTANT USE_IAP_MEMCTRL : integer := 1; ---========================================================================== - - SIGNAL clk_50_s : STD_LOGIC := '0'; - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - -- - SIGNAL errorn : STD_LOGIC; - -- - SIGNAL I00_s : STD_LOGIC; - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - -- - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxtxclk : STD_ULOGIC; - SIGNAL spw_rxclkn : STD_ULOGIC; - SIGNAL spw_clk : STD_LOGIC; - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; - - --- AdvancedTrigger - SIGNAL Trigger : STD_LOGIC; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_s : Samples(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_nCS_sig : STD_LOGIC; - SIGNAL ADC_CLK_sig : STD_LOGIC; - SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); - - SIGNAL bias_fail_sw_sig : STD_LOGIC; - - - ----------------------------------------------------------------------------- - - SIGNAL LFR_soft_rstn : STD_LOGIC; - SIGNAL LFR_rstn : STD_LOGIC; - - - SIGNAL rstn_25 : STD_LOGIC; - SIGNAL rstn_25_d1 : STD_LOGIC; - SIGNAL rstn_25_d2 : STD_LOGIC; - SIGNAL rstn_25_d3 : STD_LOGIC; - - SIGNAL rstn_24 : STD_LOGIC; - SIGNAL rstn_24_d1 : STD_LOGIC; - SIGNAL rstn_24_d2 : STD_LOGIC; - SIGNAL rstn_24_d3 : STD_LOGIC; - - SIGNAL rstn_50 : STD_LOGIC; - SIGNAL rstn_50_d1 : STD_LOGIC; - SIGNAL rstn_50_d2 : STD_LOGIC; - SIGNAL rstn_50_d3 : STD_LOGIC; - -- - SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); - - -- - SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL nSRAM_READY : STD_LOGIC; - -BEGIN -- beh - - ----------------------------------------------------------------------------- - PROCESS (clk100MHz, reset) - BEGIN -- PROCESS - IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge - clk_50_s <= NOT clk_50_s; - END IF; - END PROCESS; - ----------------------------------------------------------------------------- - - PROCESS (clk_50_s, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - clk_25 <= '0'; - rstn_25 <= '0'; - rstn_25_d1 <= '0'; - rstn_25_d2 <= '0'; - rstn_25_d3 <= '0'; - ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge - clk_25 <= NOT clk_25; - rstn_25_d1 <= '1'; - rstn_25_d2 <= rstn_25_d1; - rstn_25_d3 <= rstn_25_d2; - rstn_25 <= rstn_25_d3; - END IF; - END PROCESS; - - PROCESS (clk49_152MHz, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - clk_24 <= '0'; - rstn_24_d1 <= '0'; - rstn_24_d2 <= '0'; - rstn_24_d3 <= '0'; - rstn_24 <= '0'; - ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge - clk_24 <= NOT clk_24; - rstn_24_d1 <= '1'; - rstn_24_d2 <= rstn_24_d1; - rstn_24_d3 <= rstn_24_d2; - rstn_24 <= rstn_24_d3; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - PROCESS (clk_25, rstn_25) - BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) - LED0 <= '0'; - LED1 <= '0'; - LED2 <= '0'; - ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge - LED0 <= '0'; - LED1 <= '1'; - LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; - END IF; - END PROCESS; - - PROCESS (clk49_152MHz, rstn_24) - BEGIN -- PROCESS - IF rstn_24 = '0' THEN -- asynchronous reset (active low) - I00_s <= '0'; - ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge - I00_s <= NOT I00_s; - END IF; - END PROCESS; - - --UARTs - nCTS1 <= '1'; - nCTS2 <= '1'; - nDCD2 <= '1'; - -- No AHB UART - RXD1 <= TXD1; - - -- - - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => apa3e, - memtech => apa3e, - padtech => inferred, - clktech => inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - IS_RADHARD => 0, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 0, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 20, - USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL, - BYPASS_EDAC_MEMCTRLR => '0', - SRBANKSZ => 9) - PORT MAP ( - clk => clk_25, - reset => rstn_25, - errorn => errorn, - ahbrxd => OPEN,--TXD1, - ahbtxd => OPEN,--RXD1, - urxd1 => TXD2, - utxd1 => RXD2, - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE_s, - nSRAM_OE => SRAM_nOE, - nSRAM_READY => nSRAM_READY, - SRAM_MBE => OPEN, - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - - PROCESS (clk_25, rstn_25) - BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) - nSRAM_READY <= '1'; - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge - nSRAM_READY <= '1'; - END IF; - END PROCESS; - - - - IAP:if USE_IAP_MEMCTRL = 1 GENERATE - SRAM_CE <= not SRAM_CE_s(0); - END GENERATE; - - NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE - SRAM_CE <= SRAM_CE_s(0); - END GENERATE; -------------------------------------------------------------------------------- --- APB_LFR_MANAGEMENT --------------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_management_1 : apb_lfr_management - GENERIC MAP ( - tech => apa3e, - pindex => 6, - paddr => 6, - pmask => 16#fff#, - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - resetn_25MHz => rstn_25, - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - HK_sample => sample_hk, - HK_val => sample_val, - HK_sel => HK_SEL, - DAC_SDO => OPEN, - DAC_SCK => OPEN, - DAC_SYNC => OPEN, - DAC_CAL_EN => OPEN, - coarse_time => coarse_time, - fine_time => fine_time, - LFR_soft_rstn => LFR_soft_rstn - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - SPW_EN <= '1'; - - spw_clk <= clk_50_s; - spw_rxtxclk <= spw_clk; - spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_DIN, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_SIN, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_DOUT, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_SOUT, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (SPW_RED_SIN, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (SPW_RED_DIN, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_RED_DOUT, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_RED_SOUT, swno.s(1)); - - -- GRSPW PHY - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => apa3e, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - swni.rmapnodeaddr <= (OTHERS => '0'); - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn_25, clk_25, spw_rxclk(0), - spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - - - LFR_rstn <= LFR_soft_rstn AND rstn_25; - - lpp_lfr_1 : lpp_lfr - GENERIC MAP ( - Mem_use => use_RAM, - nb_data_by_buffer_size => 32, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"000159") -- aa.bb.cc version - PORT MAP ( - clk => clk_25, - rstn => LFR_rstn, - sample_B => sample_s(2 DOWNTO 0), - sample_E => sample_s(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi_ext, - apbo => apbo_ext(15), - ahbi => ahbi_m_ext, - ahbo => ahbo_m_ext(2), - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw_sig, - debug_vector => open, - debug_vector_ms => open - ); - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; - END GENERATE all_sample; - - top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 - GENERIC MAP( - ChannelCount => 8, - SampleNbBits => 14, - ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 - ncycle_cnv => 249) -- 49 152 000 / 98304 /2 - PORT MAP ( - -- CONV - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_nCS_sig, - -- DATA - clk => clk_25, - rstn => rstn_25, - sck => ADC_CLK_sig, - sdo => ADC_SDO_sig, - -- SAMPLE - sample => sample, - sample_val => sample_val); - - ADC_nCS <= ADC_nCS_sig; - ADC_CLK <= ADC_CLK_sig; - ADC_SDO_sig <= ADC_SDO; - - sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE - "0010001000100010" WHEN HK_SEL = "01" ELSE - "0100010001000100" WHEN HK_SEL = "10" ELSE - (OTHERS => '0'); - - - ----------------------------------------------------------------------- ---- APB_ADVANCED_TRIGGER ----------------------------------------------------------- ----------------------------------------------------------------------- -advtrig0: APB_ADVANCED_TRIGGER - generic map( - pindex => 12, - paddr => 12) - port map( - rstn => rstn_25, - clk => clk_25, - apbi => apbi_ext, - apbo => apbo_ext(12), - - SPW_Tickout => swno.tickout, - CoarseTime => coarse_time, - FineTime => fine_time, - - Trigger => Trigger - ); - - - DISCO1_TRIG1_PAD : outpad GENERIC MAP (tech => inferred) - PORT MAP (DISCO1_TRIG1, Trigger); - DISCO2_TRIG1_PAD : outpad GENERIC MAP (tech => inferred) - PORT MAP (DISCO2_TRIG1, Trigger); - DISCO3_TRIG1_PAD : outpad GENERIC MAP (tech => inferred) - PORT MAP (DISCO3_TRIG1, Trigger); - DISCO4_TRIG1_PAD : outpad GENERIC MAP (tech => inferred) - PORT MAP (DISCO4_TRIG1, Trigger); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE - apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 12 AND I /= 15 GENERATE - apbo_ext(I) <= apb_none; - END GENERATE apbo_ext_not_used; - END GENERATE all_apbo_ext; - - - all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE - ahbo_s_ext(I) <= ahbs_none; - END GENERATE all_ahbo_ext; - - all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE - ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE - ahbo_m_ext(I) <= ahbm_none; - END GENERATE ahbo_m_ext_not_used; - END GENERATE all_ahbo_m_ext; - -END beh; \ No newline at end of file diff --git a/designs/TIMEGEN/DISCOSPACE_top_libero.prj b/designs/TIMEGEN/DISCOSPACE_top_libero.prj deleted file mode 100644 --- a/designs/TIMEGEN/DISCOSPACE_top_libero.prj +++ /dev/null @@ -1,4865 +0,0 @@ -KEY LIBERO "9.1" -KEY CAPTURE "9.1.5.1" -KEY DEFAULT_IMPORT_LOC "C:\opt\VHDLIB\tests\Validation_LFR_Filters" -KEY DEFAULT_OPEN_LOC "" -KEY ProjectID "2f64e589-285c-45b2-b6c4-709f59f83db9" -KEY HDLTechnology "VHDL" -KEY VendorTechnology_Family "ProASIC3E" -KEY VendorTechnology_Die "IT14X14M4" -KEY VendorTechnology_Package "fg324" -KEY ProjectLocation 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"\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\apb_lfr_management.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lfr_time_management.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_counter.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\coarse_time_counter.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_max_value_gen.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\RHF1401.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401_withFilter.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\TestModule_RHF1401.vhd,hdl" -VALUE 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"\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_GestionBuffer.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_Arbiter.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_pkg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_burst.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_dma_genvalid.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter_reg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_pkg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_reader.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_recorder.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_sim_pkg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_lfr_sim_pkg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\cypress\ssram\components.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\cypress\ssram\package_utility.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\cypress\ssram\cy7c1380d.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\work\debug\debug.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\work\debug\grtestmod.vhd,hdl" -VALUE "\..\..\..\GRLIB\lib\work\debug\cpu_disas.vhd,hdl" -VALUE "\DISCOSPACE_top.vhd,hdl" -ENDFILELIST -ENDLIST -ENDLIST -ENDLIST -LIST OpenedFileList -ENDLIST diff --git a/designs/Validation_LFR_TIME_MANAGEMENT/Makefile b/designs/Validation_LFR_TIME_MANAGEMENT/Makefile deleted file mode 100644 --- a/designs/Validation_LFR_TIME_MANAGEMENT/Makefile +++ /dev/null @@ -1,151 +0,0 @@ -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ - -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=TB - -##VHDLSYNFILES= TB.vhd - -##LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ -## tmtc openchip hynix ihp gleichmann micron usbhc - -##DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ -## pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ -## ./amba_lcd_16x2_ctrlr \ -## ./general_purpose/lpp_AMR \ -## ./general_purpose/lpp_balise \ -## ./general_purpose/lpp_delay \ -## ./dsp/lpp_fft \ -## ./lpp_bootloader \ -## ./lpp_cna \ -## ./lpp_demux \ -## ./lpp_matrix \ -## ./lpp_uart \ -## ./lpp_usb \ -## ./lpp_Header \ - -##FILESKIP =lpp_lfr_ms.vhd \x -## i2cmst.vhd \ -## APB_MULTI_DIODE.vhd \ -## APB_SIMPLE_DIODE.vhd \ -## Top_MatrixSpec.vhd \ -## APB_FFT.vhd - -##include $(GRLIB)/bin/Makefile -##include $(GRLIB)/software/leon3/Makefile - -CMD_VLIB=vlib -CMD_VMAP=vmap -CMD_VCOM=@vcom -quiet -93 -work - -################## project specific targets ########################## - -all: - @echo "make vsim" - @echo "make libs" - @echo "make clean" - @echo "make vcom_grlib vcom_lpp vcom_tb" - -run: - @vsim work.TB -do run.do - -vsim: libs vcom run - -libs: - @$(CMD_VLIB) modelsim - @$(CMD_VMAP) modelsim modelsim - @$(CMD_VLIB) modelsim/grlib - @$(CMD_VMAP) grlib modelsim/grlib - @$(CMD_VLIB) modelsim/work - @$(CMD_VMAP) work modelsim/work - @$(CMD_VLIB) modelsim/lpp - @$(CMD_VMAP) lpp modelsim/lpp - @echo "libs done" - - -clean: - @rm -Rf modelsim - @rm -Rf modelsim.ini - @rm -Rf *~ - @rm -Rf transcript - @rm -Rf wlft* - @rm -Rf *.wlf - @rm -Rf vish_stacktrace.vstf - @rm -Rf libs.do - -vcom: vcom_grlib vcom_lpp vcom_tb - -vcom_tb: - $(CMD_VCOM) work TB.vhd - @echo "vcom work done" - -vcom_grlib: - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd - $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd - @echo "vcom grlib done" - -vcom_lpp: - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd - @echo "vcom lpp done" diff --git a/designs/Validation_LFR_TIME_MANAGEMENT/TB.vhd b/designs/Validation_LFR_TIME_MANAGEMENT/TB.vhd deleted file mode 100644 --- a/designs/Validation_LFR_TIME_MANAGEMENT/TB.vhd +++ /dev/null @@ -1,352 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; - -LIBRARY lpp; -USE lpp.lpp_lfr_time_management.ALL; - -ENTITY TB IS - - PORT ( - SIM_OK : OUT STD_LOGIC - ); - -END TB; - - -ARCHITECTURE beh OF TB IS - - SIGNAL clk25MHz : STD_LOGIC := '0'; - SIGNAL clk24_576MHz : STD_LOGIC := '0'; - SIGNAL resetn : STD_LOGIC; - SIGNAL grspw_tick : STD_LOGIC; - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_type; - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - - SIGNAL TB_string : STRING(1 TO 8):= "12345678"; - - SIGNAL coarse_time_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL global_time : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL global_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL tick_ongoing : STD_LOGIC; - - SIGNAL ASSERTION_1 : STD_LOGIC; - SIGNAL ASSERTION_2 : STD_LOGIC; - SIGNAL ASSERTION_3 : STD_LOGIC; - -BEGIN -- beh - - apb_lfr_time_management_1: apb_lfr_time_management - GENERIC MAP ( - pindex => 0, - paddr => 0, - pmask => 16#fff#, - FIRST_DIVISION => 20, - NB_SECOND_DESYNC => 4) - PORT MAP ( - clk25MHz => clk25MHz, - clk24_576MHz => clk24_576MHz, - resetn => resetn, - grspw_tick => grspw_tick, - apbi => apbi, - apbo => apbo, - coarse_time => coarse_time, - fine_time => fine_time); - - clk25MHz <= NOT clk25MHz AFTER 20000 ps; - clk24_576MHz <= NOT clk24_576MHz AFTER 20345 ps; - - - - - PROCESS - BEGIN -- PROCESS - WAIT UNTIL clk25MHz = '1'; - TB_string <= "RESET "; - - resetn <= '0'; - - apbi.psel(0) <= '0'; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - apbi.paddr <= (OTHERS => '0'); - apbi.pwdata <= (OTHERS => '0'); - grspw_tick <= '0'; - WAIT UNTIL clk25MHz = '1'; - WAIT UNTIL clk25MHz = '1'; - resetn <= '1'; - WAIT FOR 60 ms; - --------------------------------------------------------------------------- - -- DESYNC TO SYNC - --------------------------------------------------------------------------- - WAIT UNTIL clk25MHz = '1'; - TB_string <= "TICK 1 "; - grspw_tick <= '1';------------------------------------------------------1 - WAIT UNTIL clk25MHz = '1'; - grspw_tick <= '0'; - WAIT FOR 53333 us; - WAIT UNTIL clk25MHz = '1'; - TB_string <= "TICK 2 "; - grspw_tick <= '1';------------------------------------------------------2 - WAIT UNTIL clk25MHz = '1'; - grspw_tick <= '0'; - WAIT FOR 56000 us; - WAIT UNTIL clk25MHz = '1'; - TB_string <= "TICK 3 "; - grspw_tick <= '1';------------------------------------------------------3 - WAIT UNTIL clk25MHz = '1'; - grspw_tick <= '0'; - WAIT FOR 200 ms; - WAIT UNTIL clk25MHz = '1'; - TB_string <= "CT new "; - -- WRITE NEW COARSE_TIME - apbi.psel(0) <= '1'; - apbi.pwrite <= '1'; - apbi.penable <= '1'; - apbi.paddr <= X"00000004"; - apbi.pwdata <= X"00001234"; - WAIT UNTIL clk25MHz = '1'; - apbi.psel(0) <= '0'; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - apbi.paddr <= (OTHERS => '0'); - apbi.pwdata <= (OTHERS => '0'); - WAIT UNTIL clk25MHz = '1'; - - WAIT FOR 10 ms; - WAIT UNTIL clk25MHz = '1'; - TB_string <= "TICK 4 "; - grspw_tick <= '1';------------------------------------------------------3 - WAIT UNTIL clk25MHz = '1'; - grspw_tick <= '0'; - - - WAIT FOR 250 ms; - WAIT UNTIL clk25MHz = '1'; - TB_string <= "CT new "; - -- WRITE NEW COARSE_TIME - apbi.psel(0) <= '1'; - apbi.pwrite <= '1'; - apbi.penable <= '1'; - apbi.paddr <= X"00000004"; - apbi.pwdata <= X"80005678"; - WAIT UNTIL clk25MHz = '1'; - apbi.psel(0) <= '0'; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - apbi.paddr <= (OTHERS => '0'); - apbi.pwdata <= (OTHERS => '0'); - WAIT UNTIL clk25MHz = '1'; - - WAIT FOR 10 ms; - WAIT UNTIL clk25MHz = '1'; - TB_string <= "TICK 5 "; - grspw_tick <= '1';------------------------------------------------------3 - WAIT UNTIL clk25MHz = '1'; - grspw_tick <= '0'; - - - WAIT FOR 20 ms; - WAIT UNTIL clk25MHz = '1'; - TB_string <= "CT new "; - -- WRITE NEW COARSE_TIME - apbi.psel(0) <= '1'; - apbi.pwrite <= '1'; - apbi.penable <= '1'; - apbi.paddr <= X"00000004"; - apbi.pwdata <= X"00005678"; - WAIT UNTIL clk25MHz = '1'; - apbi.psel(0) <= '0'; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - apbi.paddr <= (OTHERS => '0'); - apbi.pwdata <= (OTHERS => '0'); - WAIT UNTIL clk25MHz = '1'; - - WAIT FOR 25 ms; - WAIT UNTIL clk25MHz = '1'; - TB_string <= "Soft RST"; - -- WRITE SOFT RESET - apbi.psel(0) <= '1'; - apbi.pwrite <= '1'; - apbi.penable <= '1'; - apbi.paddr <= X"00000000"; - apbi.pwdata <= X"00000002"; - WAIT UNTIL clk25MHz = '1'; - apbi.psel(0) <= '0'; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - apbi.paddr <= (OTHERS => '0'); - apbi.pwdata <= (OTHERS => '0'); - WAIT UNTIL clk25MHz = '1'; - - WAIT FOR 250 ms; - TB_string <= "READ 1 "; - apbi.psel(0) <= '1'; - apbi.pwrite <= '0'; - apbi.penable <= '1'; - apbi.paddr <= X"00000008"; - WAIT UNTIL clk25MHz = '1'; - apbi.psel(0) <= '0'; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - apbi.paddr <= (OTHERS => '0'); - WAIT UNTIL clk25MHz = '1'; - WAIT FOR 250 ms; - TB_string <= "READ 2 "; - apbi.psel(0) <= '1'; - apbi.pwrite <= '0'; - apbi.penable <= '1'; - apbi.paddr <= X"00000008"; - WAIT UNTIL clk25MHz = '1'; - apbi.psel(0) <= '0'; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - apbi.paddr <= (OTHERS => '0'); - WAIT UNTIL clk25MHz = '1'; - WAIT FOR 250 ms; - TB_string <= "READ 3 "; - apbi.psel(0) <= '1'; - apbi.pwrite <= '0'; - apbi.penable <= '1'; - apbi.paddr <= X"00000008"; - WAIT UNTIL clk25MHz = '1'; - apbi.psel(0) <= '0'; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - apbi.paddr <= (OTHERS => '0'); - WAIT UNTIL clk25MHz = '1'; - - - - REPORT "*** END simulation ***" SEVERITY failure; - WAIT; - - END PROCESS; - - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - - global_time <= coarse_time & fine_time; - - PROCESS (clk25MHz, resetn) - BEGIN -- PROCESS - IF resetn = '0' THEN -- asynchronous reset (active low) - coarse_time_reg <= (OTHERS => '0'); - fine_time_reg <= (OTHERS => '0'); - global_time_reg <= (OTHERS => '0'); - tick_ongoing <= '0'; - ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge - global_time_reg <= global_time; - coarse_time_reg <= coarse_time; - fine_time_reg <= fine_time; - IF grspw_tick ='1' THEN - tick_ongoing <= '1'; - ELSIF tick_ongoing = '1' THEN - IF (fine_time_reg /= fine_time) OR (coarse_time_reg /= coarse_time) THEN - tick_ongoing <= '0'; - END IF; - END IF; - - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- ASSERTION 1 : - -- Coarse_time "changed" => FINE_TIME = 0 - -- False after a TRANSITION ! - ----------------------------------------------------------------------------- - PROCESS (clk25MHz, resetn) - BEGIN -- PROCESS - IF resetn = '0' THEN -- asynchronous reset (active low) - ASSERTION_1 <= '1'; - ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge - IF coarse_time /= coarse_time_reg THEN - IF fine_time /= X"0000" THEN - IF fine_time /= X"0041" THEN - ASSERTION_1 <= '0'; - ELSE - ASSERTION_1 <= 'U'; - END IF; - ELSE - ASSERTION_1 <= '1'; - END IF; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- ASSERTION 2 : - -- tick => next(FINE_TIME) = 0 - ----------------------------------------------------------------------------- - PROCESS (clk25MHz, resetn) - BEGIN -- PROCESS - IF resetn = '0' THEN -- asynchronous reset (active low) - ASSERTION_2 <= '1'; - ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge - IF tick_ongoing = '1' THEN - IF fine_time_reg /= fine_time OR coarse_time_reg /= coarse_time THEN - IF fine_time /= X"0000" THEN - ASSERTION_2 <= '0'; - END IF; - END IF; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- ASSERTION 3 : - -- next(TIME) > TIME - -- false if resynchro, or new coarse_time - ----------------------------------------------------------------------------- - PROCESS (clk25MHz, resetn) - BEGIN -- PROCESS - IF resetn = '0' THEN -- asynchronous reset (active low) - ASSERTION_3 <= '1'; - ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge - ASSERTION_3 <= '1'; - IF global_time_reg(46 DOWNTO 0) > global_time(46 DOWNTO 0) THEN - IF global_time(47) = '0' AND global_time_reg(47) = '1' THEN - ASSERTION_3 <= 'U'; -- RESYNCHRO .... - ELSE - ASSERTION_3 <= '0'; - END IF; - END IF; - END IF; - END PROCESS; - - -END beh; - diff --git a/designs/Validation_LFR_TIME_MANAGEMENT/run.do b/designs/Validation_LFR_TIME_MANAGEMENT/run.do deleted file mode 100644 --- a/designs/Validation_LFR_TIME_MANAGEMENT/run.do +++ /dev/null @@ -1,3 +0,0 @@ -log -R * -do wave.do -run -all \ No newline at end of file diff --git a/designs/Validation_LFR_TIME_MANAGEMENT/wave.do b/designs/Validation_LFR_TIME_MANAGEMENT/wave.do deleted file mode 100644 --- a/designs/Validation_LFR_TIME_MANAGEMENT/wave.do +++ /dev/null @@ -1,34 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate /tb/tb_string -add wave -noupdate /tb/assertion_1 -add wave -noupdate /tb/assertion_2 -add wave -noupdate /tb/assertion_3 -add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/state -add wave -noupdate -format Analog-Step -height 74 -max 66000.0 -radix hexadecimal /tb/apb_lfr_time_management_1/lfr_time_management_1/fine_time -add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/coarse_time_new -add wave -noupdate -radix hexadecimal /tb/apb_lfr_time_management_1/lfr_time_management_1/coarse_time -add wave -noupdate /tb/apb_lfr_time_management_1/grspw_tick -add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/fine_time -add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/coarse_time -add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/fine_time_new -add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/apbi.psel {-radix hexadecimal} /tb/apbi.psel(0) {-radix hexadecimal} /tb/apbi.psel(1) {-radix hexadecimal} /tb/apbi.psel(2) {-radix hexadecimal} /tb/apbi.psel(3) {-radix hexadecimal} /tb/apbi.psel(4) {-radix hexadecimal} /tb/apbi.psel(5) {-radix hexadecimal} /tb/apbi.psel(6) {-radix hexadecimal} /tb/apbi.psel(7) {-radix hexadecimal} /tb/apbi.psel(8) {-radix hexadecimal} /tb/apbi.psel(9) {-radix hexadecimal} /tb/apbi.psel(10) {-radix hexadecimal} /tb/apbi.psel(11) {-radix hexadecimal} /tb/apbi.psel(12) {-radix hexadecimal} /tb/apbi.psel(13) {-radix hexadecimal} /tb/apbi.psel(14) {-radix hexadecimal} /tb/apbi.psel(15) {-radix hexadecimal} /tb/apbi.penable {-radix hexadecimal} /tb/apbi.paddr {-radix hexadecimal} /tb/apbi.pwrite {-radix hexadecimal} /tb/apbi.pwdata {-radix hexadecimal} /tb/apbi.pirq {-radix hexadecimal} /tb/apbi.testen {-radix hexadecimal} /tb/apbi.testrst {-radix hexadecimal} /tb/apbi.scanen {-radix hexadecimal} /tb/apbi.testoen {-radix hexadecimal} /tb/apbi.testin {-radix hexadecimal}} /tb/apbi -add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/apbo.prdata {-radix hexadecimal} /tb/apbo.pirq {-radix hexadecimal} /tb/apbo.pconfig {-radix hexadecimal} /tb/apbo.pindex {-radix hexadecimal}} /tb/apbo -add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/apb_lfr_time_management_1/r.ctrl {-radix hexadecimal} /tb/apb_lfr_time_management_1/r.coarse_time_load {-radix hexadecimal} /tb/apb_lfr_time_management_1/r.coarse_time {-radix hexadecimal} /tb/apb_lfr_time_management_1/r.fine_time {-radix hexadecimal}} /tb/apb_lfr_time_management_1/r -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{FT 1} {15279095 ps} 1} {{FT 1 + 1s} {1000012719095 ps} 1} {{Cursor 3} {750199620000 ps} 0} {TRANSITION {169333245705 ps} 1} -configure wave -namecolwidth 512 -configure wave -valuecolwidth 139 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ps -update -WaveRestoreZoom {0 ps} {1185800469 ns} diff --git a/lib/lpp/general_purpose/general_counter.vhd b/lib/lpp/general_purpose/general_counter.vhd --- a/lib/lpp/general_purpose/general_counter.vhd +++ b/lib/lpp/general_purpose/general_counter.vhd @@ -14,7 +14,7 @@ ENTITY general_counter IS clk : IN STD_LOGIC; rstn : IN STD_LOGIC; -- - MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1'); + MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); -- set : IN STD_LOGIC; set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd --- a/lib/lpp/general_purpose/general_purpose.vhd +++ b/lib/lpp/general_purpose/general_purpose.vhd @@ -35,13 +35,13 @@ PACKAGE general_purpose IS COMPONENT general_counter GENERIC ( - CYCLIC : STD_LOGIC; - NB_BITS_COUNTER : INTEGER; - RST_VALUE : INTEGER); + CYCLIC : STD_LOGIC := '1'; + NB_BITS_COUNTER : INTEGER := 9; + RST_VALUE : INTEGER := 0); PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; - MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); + MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1'); set : IN STD_LOGIC; set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); add1 : IN STD_LOGIC; diff --git a/lib/lpp/lfr_management/apb_lfr_management.vhd b/lib/lpp/lfr_management/apb_lfr_management.vhd --- a/lib/lpp/lfr_management/apb_lfr_management.vhd +++ b/lib/lpp/lfr_management/apb_lfr_management.vhd @@ -151,6 +151,8 @@ ARCHITECTURE Behavioral OF apb_lfr_manag SIGNAL INTERLEAVED : STD_LOGIC; SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL DAC_CAL_EN_s : STD_LOGIC; + + signal fine_time_reg_info : std_logic_vector(26 downto 0); BEGIN @@ -185,6 +187,7 @@ BEGIN -- DAC_CAL_EN_s <= '0'; force_reset <= '0'; + ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN coarsetime_reg_updated <= '0'; @@ -253,6 +256,8 @@ BEGIN WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN => Rdata(datawidth-1 DOWNTO 0) <= DATA_IN; Rdata(31 DOWNTO datawidth) <= (OTHERS => '0'); + WHEN ADDR_LFR_MANAGMENT_TIME_FINE_DELTA => + Rdata(26 downto 0) <= fine_time_reg_info; WHEN OTHERS => Rdata(31 DOWNTO 0) <= (OTHERS => '0'); END CASE; @@ -310,13 +315,6 @@ BEGIN - - - - - - - ----------------------------------------------------------------------------- -- IN @@ -333,72 +331,18 @@ BEGIN ----------------------------------------------------------------------------- tick <= grspw_tick OR soft_tick; - - --SYNC_VALID_BIT_1 : SYNC_VALID_BIT - -- GENERIC MAP ( - -- NB_FF_OF_SYNC => 2) - -- PORT MAP ( - -- clk_in => clk25MHz, - -- rstn_in => resetn_25MHz, - -- clk_out => clk24_576MHz, - -- rstn_out => resetn_24_576MHz, - -- sin => tick, - -- sout => new_timecode); + new_timecode <= tick; - - --SYNC_VALID_BIT_2 : SYNC_VALID_BIT - -- GENERIC MAP ( - -- NB_FF_OF_SYNC => 2) - -- PORT MAP ( - -- clk_in => clk25MHz, - -- rstn_in => resetn_25MHz, - -- clk_out => clk24_576MHz, - -- rstn_out => resetn_24_576MHz, - -- sin => coarsetime_reg_updated, - -- sout => new_coarsetime); - new_coarsetime <= coarsetime_reg_updated; - - --SYNC_VALID_BIT_3 : SYNC_VALID_BIT - -- GENERIC MAP ( - -- NB_FF_OF_SYNC => 2) - -- PORT MAP ( - -- clk_in => clk25MHz, - -- rstn_in => resetn_25MHz, - -- clk_out => clk24_576MHz, - -- rstn_out => resetn_24_576MHz, - -- sin => soft_reset, - -- sout => soft_reset_sync); - + new_coarsetime <= coarsetime_reg_updated; ----------------------------------------------------------------------------- time_new_49 <= coarse_time_new_49 OR fine_time_new_49; - --SYNC_VALID_BIT_4 : SYNC_VALID_BIT - -- GENERIC MAP ( - -- NB_FF_OF_SYNC => 2) - -- PORT MAP ( - -- clk_in => clk24_576MHz, - -- rstn_in => resetn_24_576MHz, - -- clk_out => clk25MHz, - -- rstn_out => resetn_25MHz, - -- sin => time_new_49, - -- sout => time_new); - time_new <= time_new_49; - - --PROCESS (clk25MHz, resetn_25MHz) - --BEGIN -- PROCESS - -- IF resetn_25MHz = '0' THEN -- asynchronous reset (active low) - -- fine_time_s <= (OTHERS => '0'); - -- coarse_time_s <= (OTHERS => '0'); - -- ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge - -- IF time_new = '1' THEN - -- END IF; - -- END IF; - --END PROCESS; fine_time_s <= fine_time_49; + coarse_time_s <= coarse_time_49; @@ -424,7 +368,12 @@ BEGIN fine_time => fine_time_49, fine_time_new => fine_time_new_49, coarse_time => coarse_time_49, - coarse_time_new => coarse_time_new_49); + coarse_time_new => coarse_time_new_49, + + ft_counter_low => fine_time_reg_info( 8 downto 0), + ft_counter_low_max_value => fine_time_reg_info(26 downto 25), + ft_counter => fine_time_reg_info(24 downto 9) + ); @@ -477,15 +426,6 @@ BEGIN - - - - - - - - - ----------------------------------------------------------------------------- diff --git a/lib/lpp/lfr_management/fine_time_counter.vhd b/lib/lpp/lfr_management/fine_time_counter.vhd --- a/lib/lpp/lfr_management/fine_time_counter.vhd +++ b/lib/lpp/lfr_management/fine_time_counter.vhd @@ -23,7 +23,11 @@ ENTITY fine_time_counter IS FT_half : OUT STD_LOGIC; FT_wait : OUT STD_LOGIC; fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - fine_time_new : OUT STD_LOGIC + fine_time_new : OUT STD_LOGIC; + + ft_counter_low : out STD_LOGIC_VECTOR( 8 downto 0); + ft_counter_low_max_value : out STD_LOGIC_VECTOR( 1 downto 0); + ft_counter : out STD_LOGIC_VECTOR(15 downto 0) ); END fine_time_counter; @@ -38,6 +42,8 @@ ARCHITECTURE beh OF fine_time_counter IS SIGNAL tick_value_gen : STD_LOGIC; SIGNAL FT_max_s : STD_LOGIC; + SIGNAL ft_counter_low_max_value_s : STD_LOGIC_VECTOR( 1 downto 0); + BEGIN -- beh tick_value_gen <= tick OR FT_max_s; @@ -102,5 +108,24 @@ BEGIN -- beh END IF; END IF; END PROCESS; + + ft_counter_low_max_value_s <= "00" when fine_time_max_value = STD_LOGIC_VECTOR(to_unsigned(379,9)) else + "01" when fine_time_max_value = STD_LOGIC_VECTOR(to_unsigned(380,9)) else + "10";-- when fine_time_max_value = STD_LOGIC_VECTOR(to_unsigned(381,9)) + + process (clk, rstn) is + begin -- process + if rstn = '0' then -- asynchronous reset (active low) + ft_counter_low <= (others => '0'); + ft_counter_low_max_value <= (others => '0'); + ft_counter <= (others => '0'); + elsif clk'event and clk = '1' then -- rising clock edge + if tick = '1' then + ft_counter_low <= new_ft_counter; + ft_counter_low_max_value <= ft_counter_low_max_value_s; + ft_counter <= fine_time_counter; + end if; + end if; + end process; END beh; diff --git a/lib/lpp/lfr_management/lfr_time_management.vhd b/lib/lpp/lfr_management/lfr_time_management.vhd --- a/lib/lpp/lfr_management/lfr_time_management.vhd +++ b/lib/lpp/lfr_management/lfr_time_management.vhd @@ -38,7 +38,11 @@ ENTITY lfr_time_management IS fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); fine_time_new : OUT STD_LOGIC; coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - coarse_time_new : OUT STD_LOGIC + coarse_time_new : OUT STD_LOGIC; + + ft_counter_low : out STD_LOGIC_VECTOR( 8 downto 0); + ft_counter_low_max_value : out STD_LOGIC_VECTOR( 1 downto 0); + ft_counter : out STD_LOGIC_VECTOR(15 downto 0) ); END lfr_time_management; @@ -92,8 +96,11 @@ BEGIN FT_half => FT_half, FT_wait => FT_wait, fine_time => fine_time, - fine_time_new => fine_time_new); - + fine_time_new => fine_time_new, + ft_counter_low => ft_counter_low , + ft_counter_low_max_value => ft_counter_low_max_value, + ft_counter => ft_counter + ); ----------------------------------------------------------------------------- -- COARSE_TIME ----------------------------------------------------------------------------- diff --git a/lib/lpp/lfr_management/lpp_lfr_management.vhd b/lib/lpp/lfr_management/lpp_lfr_management.vhd --- a/lib/lpp/lfr_management/lpp_lfr_management.vhd +++ b/lib/lpp/lfr_management/lpp_lfr_management.vhd @@ -70,7 +70,11 @@ PACKAGE lpp_lfr_management IS fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); fine_time_new : OUT STD_LOGIC; coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - coarse_time_new : OUT STD_LOGIC); + coarse_time_new : OUT STD_LOGIC; + ft_counter_low : out STD_LOGIC_VECTOR( 8 downto 0); + ft_counter_low_max_value : out STD_LOGIC_VECTOR( 1 downto 0); + ft_counter : out STD_LOGIC_VECTOR(15 downto 0) + ); END COMPONENT; COMPONENT coarse_time_counter @@ -103,7 +107,11 @@ PACKAGE lpp_lfr_management IS FT_half : OUT STD_LOGIC; FT_wait : OUT STD_LOGIC; fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - fine_time_new : OUT STD_LOGIC); + fine_time_new : OUT STD_LOGIC; + ft_counter_low : out STD_LOGIC_VECTOR( 8 downto 0); + ft_counter_low_max_value : out STD_LOGIC_VECTOR( 1 downto 0); + ft_counter : out STD_LOGIC_VECTOR(15 downto 0) + ); END COMPONENT; COMPONENT fine_time_max_value_gen diff --git a/lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd b/lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd --- a/lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd +++ b/lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd @@ -16,5 +16,6 @@ PACKAGE lpp_lfr_management_apbreg_pkg IS CONSTANT ADDR_LFR_MANAGMENT_DAC_N : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001"; CONSTANT ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010"; CONSTANT ADDR_LFR_MANAGMENT_DAC_DATA_IN : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011"; + CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE_DELTA : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001100"; END lpp_lfr_management_apbreg_pkg; diff --git a/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER.vhd b/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER.vhd --- a/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER.vhd +++ b/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER.vhd @@ -37,8 +37,7 @@ entity APB_ADVANCED_TRIGGER is pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8); + pirq : integer := 0); port ( rstn : in std_ulogic; clk : in std_ulogic; @@ -124,12 +123,12 @@ begin --APB Write OP if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => + case apbi.paddr(3 downto 2) is + when "00" => r.CFG <= apbi.pwdata; - when "000001" => + when "01" => r.Restart <= apbi.pwdata; - when "000010" => + when "10" => r.StartDate <= apbi.pwdata; when others => null; @@ -138,12 +137,12 @@ begin --APB READ OP if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => + case apbi.paddr(3 downto 2) is + when "00" => Rdata <= r.CFG; - when "000001" => + when "01" => Rdata <= r.Restart; - when "000010" => + when "10" => Rdata <= r.StartDate; when others => Rdata <= r.Restart; @@ -155,4 +154,4 @@ begin end process; apbo.prdata <= Rdata when apbi.penable = '1'; -end beh; \ No newline at end of file +end beh; diff --git a/lib/lpp/lpp_amba/lpp_amba.vhd b/lib/lpp/lpp_amba/lpp_amba.vhd --- a/lib/lpp/lpp_amba/lpp_amba.vhd +++ b/lib/lpp/lpp_amba/lpp_amba.vhd @@ -34,8 +34,7 @@ component APB_ADVANCED_TRIGGER is pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8); + pirq : integer := 0); port ( rstn : in std_ulogic; clk : in std_ulogic; diff --git a/lib/lpp/lpp_cna/APB_LFR_CAL.vhd b/lib/lpp/lpp_cna/APB_LFR_CAL.vhd --- a/lib/lpp/lpp_cna/APB_LFR_CAL.vhd +++ b/lib/lpp/lpp_cna/APB_LFR_CAL.vhd @@ -127,19 +127,19 @@ BEGIN --APB Write OP IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN - CASE apbi.paddr(abits-1 DOWNTO 2) IS - WHEN "000000" => + CASE apbi.paddr(4 DOWNTO 2) IS + WHEN "000" => DAC_CFG <= apbi.pwdata(3 DOWNTO 0); Reload <= apbi.pwdata(4); INTERLEAVED <= apbi.pwdata(5); - WHEN "000001" => + WHEN "001" => pre <= apbi.pwdata(PRESZ-1 DOWNTO 0); - WHEN "000010" => + WHEN "010" => N <= apbi.pwdata(CPTSZ-1 DOWNTO 0); - WHEN "000011" => + WHEN "011" => ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0); LOAD_ADDRESSN <= '0'; - WHEN "000100" => + WHEN "100" => DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0); WEN <= '0'; WHEN OTHERS => @@ -152,22 +152,22 @@ BEGIN --APB Read OP IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN - CASE apbi.paddr(abits-1 DOWNTO 2) IS - WHEN "000000" => + CASE apbi.paddr(4 DOWNTO 2) IS + WHEN "000" => Rdata(3 DOWNTO 0) <= DAC_CFG; Rdata(4) <= Reload; Rdata(5) <= INTERLEAVED; Rdata(31 DOWNTO 6) <= (OTHERS => '0'); - WHEN "000001" => + WHEN "001" => Rdata(PRESZ-1 DOWNTO 0) <= pre; Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0'); - WHEN "000010" => + WHEN "010" => Rdata(CPTSZ-1 DOWNTO 0) <= N; Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0'); - WHEN "000011" => + WHEN "011" => Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT; Rdata(31 DOWNTO abits) <= (OTHERS => '0'); - WHEN "000100" => + WHEN "100" => Rdata(datawidth-1 DOWNTO 0) <= DATA_IN; Rdata(31 DOWNTO datawidth) <= (OTHERS => '0'); WHEN OTHERS => diff --git a/lib/lpp/lpp_cna/lpp_cna.vhd b/lib/lpp/lpp_cna/lpp_cna.vhd --- a/lib/lpp/lpp_cna/lpp_cna.vhd +++ b/lib/lpp/lpp_cna/lpp_cna.vhd @@ -41,7 +41,7 @@ component apb_lfr_cal is CPTSZ : integer := 16; datawidth : integer := 18; dacresolution : integer := 12; - abits : integer := 8); + abits : INTEGER := 8); port ( rstn : in std_logic; clk : in std_logic; @@ -235,4 +235,4 @@ port( ); end component; -end; \ No newline at end of file +end; diff --git a/tests/LFR_time_managment/Makefile b/tests/LFR_time_managment/Makefile new file mode 100644 --- /dev/null +++ b/tests/LFR_time_managment/Makefile @@ -0,0 +1,82 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=testbench +BOARD=LFR-EQM +include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF= +QSF= +EFFORT=high +XSTOPT= +SYNPOPT= +VHDLSYNFILES= +VHDLSIMFILES= tb.vhd +SIMTOP=TB +CLEAN=soft-clean + +TECHLIBS = axcelerator + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi + +DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \ + grlfpc \ + ./dsp/lpp_fft_rtax \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_sim/CY7C1061DV33 \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft \ + ./lpp_leon3_soc \ + ./lpp_debug_lfr + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_ms_FFT.vhd \ + lpp_lfr_apbreg.vhd \ + CoreFFT.vhd \ + lpp_lfr_ms.vhd \ + lpp_lfr_sim_pkg.vhd \ + mtie_maps.vhd \ + ftsrctrlc.vhd \ + ftsdctrl.vhd \ + ftsrctrl8.vhd \ + ftmctrl.vhd \ + ftsdctrl64.vhd \ + ftahbram.vhd \ + ftahbram2.vhd \ + sramft.vhd \ + nandfctrlx.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## +distclean:myclean +vsim:cp_for_vsim + +myclean: + rm -f input.txt output_fx.txt *.log + rm -rf ./2016* + +generate : +# python ./generate.py + +cp_for_vsim: generate +# cp ./input.txt simulation/ + +archivate: + xonsh ./archivate.xsh + +test: | generate ghdl ghdl-run archivate + + diff --git a/tests/LFR_time_managment/TB.vhd b/tests/LFR_time_managment/TB.vhd new file mode 100644 --- /dev/null +++ b/tests/LFR_time_managment/TB.vhd @@ -0,0 +1,361 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; + +LIBRARY lpp; +USE lpp.lpp_lfr_management.ALL; + +ENTITY TB IS + + PORT ( + SIM_OK : OUT STD_LOGIC + ); + +END TB; + + +ARCHITECTURE beh OF TB IS + + SIGNAL clk25MHz : STD_LOGIC := '0'; + + SIGNAL resetn : STD_LOGIC; + SIGNAL grspw_tick : STD_LOGIC; + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_type; + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL TB_string : STRING(1 TO 8):= "12345678"; + + SIGNAL coarse_time_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL global_time : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL global_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL tick_ongoing : STD_LOGIC; + + SIGNAL ASSERTION_1 : STD_LOGIC; + SIGNAL ASSERTION_2 : STD_LOGIC; + SIGNAL ASSERTION_3 : STD_LOGIC; + +BEGIN -- beh + + apb_lfr_management_1: apb_lfr_management + GENERIC MAP ( + tech => 0, + pindex => 0, + paddr => 0, + pmask => 16#fff#, +-- FIRST_DIVISION => 20, + NB_SECOND_DESYNC => 4) + PORT MAP ( + clk25MHz => clk25MHz, + resetn_25MHz => resetn, + + grspw_tick => grspw_tick, + apbi => apbi, + apbo => apbo, + + HK_sample => (others => '0'), + HK_val => '0', + HK_sel => OPEN, + + DAC_SDO => OPEN, + DAC_SCK => OPEN, + DAC_SYNC => OPEN, + DAC_CAL_EN => OPEN, + + coarse_time => coarse_time, + fine_time => fine_time, + + LFR_soft_rstn => OPEN); + + clk25MHz <= NOT clk25MHz AFTER 20000 ps; + + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk25MHz = '1'; + TB_string <= "RESET "; + + resetn <= '0'; + + apbi.psel(0) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + grspw_tick <= '0'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + resetn <= '1'; + WAIT FOR 60 ms; + --------------------------------------------------------------------------- + -- DESYNC TO SYNC + --------------------------------------------------------------------------- + WAIT UNTIL clk25MHz = '1'; + TB_string <= "TICK 1 "; + grspw_tick <= '1';------------------------------------------------------1 + WAIT UNTIL clk25MHz = '1'; + grspw_tick <= '0'; + WAIT FOR 53333 us; + WAIT UNTIL clk25MHz = '1'; + TB_string <= "TICK 2 "; + grspw_tick <= '1';------------------------------------------------------2 + WAIT UNTIL clk25MHz = '1'; + grspw_tick <= '0'; + WAIT FOR 56000 us; + WAIT UNTIL clk25MHz = '1'; + TB_string <= "TICK 3 "; + grspw_tick <= '1';------------------------------------------------------3 + WAIT UNTIL clk25MHz = '1'; + grspw_tick <= '0'; + WAIT FOR 200 ms; + WAIT UNTIL clk25MHz = '1'; + TB_string <= "CT new "; + -- WRITE NEW COARSE_TIME + apbi.psel(0) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= X"00000004"; + apbi.pwdata <= X"00001234"; + WAIT UNTIL clk25MHz = '1'; + apbi.psel(0) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; + + WAIT FOR 10 ms; + WAIT UNTIL clk25MHz = '1'; + TB_string <= "TICK 4 "; + grspw_tick <= '1';------------------------------------------------------3 + WAIT UNTIL clk25MHz = '1'; + grspw_tick <= '0'; + + + WAIT FOR 250 ms; + WAIT UNTIL clk25MHz = '1'; + TB_string <= "CT new "; + -- WRITE NEW COARSE_TIME + apbi.psel(0) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= X"00000004"; + apbi.pwdata <= X"80005678"; + WAIT UNTIL clk25MHz = '1'; + apbi.psel(0) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; + + WAIT FOR 10 ms; + WAIT UNTIL clk25MHz = '1'; + TB_string <= "TICK 5 "; + grspw_tick <= '1';------------------------------------------------------3 + WAIT UNTIL clk25MHz = '1'; + grspw_tick <= '0'; + + + WAIT FOR 20 ms; + WAIT UNTIL clk25MHz = '1'; + TB_string <= "CT new "; + -- WRITE NEW COARSE_TIME + apbi.psel(0) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= X"00000004"; + apbi.pwdata <= X"00005678"; + WAIT UNTIL clk25MHz = '1'; + apbi.psel(0) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; + + WAIT FOR 25 ms; + WAIT UNTIL clk25MHz = '1'; + TB_string <= "Soft RST"; + -- WRITE SOFT RESET + apbi.psel(0) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= X"00000000"; + apbi.pwdata <= X"00000002"; + WAIT UNTIL clk25MHz = '1'; + apbi.psel(0) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; + + WAIT FOR 250 ms; + TB_string <= "READ 1 "; + apbi.psel(0) <= '1'; + apbi.pwrite <= '0'; + apbi.penable <= '1'; + apbi.paddr <= X"00000008"; + WAIT UNTIL clk25MHz = '1'; + apbi.psel(0) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; + WAIT FOR 250 ms; + TB_string <= "READ 2 "; + apbi.psel(0) <= '1'; + apbi.pwrite <= '0'; + apbi.penable <= '1'; + apbi.paddr <= X"00000008"; + WAIT UNTIL clk25MHz = '1'; + apbi.psel(0) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; + WAIT FOR 250 ms; + TB_string <= "READ 3 "; + apbi.psel(0) <= '1'; + apbi.pwrite <= '0'; + apbi.penable <= '1'; + apbi.paddr <= X"00000008"; + WAIT UNTIL clk25MHz = '1'; + apbi.psel(0) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; + + + + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + + END PROCESS; + + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + + global_time <= coarse_time & fine_time; + + PROCESS (clk25MHz, resetn) + BEGIN -- PROCESS + IF resetn = '0' THEN -- asynchronous reset (active low) + coarse_time_reg <= (OTHERS => '0'); + fine_time_reg <= (OTHERS => '0'); + global_time_reg <= (OTHERS => '0'); + tick_ongoing <= '0'; + ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge + global_time_reg <= global_time; + coarse_time_reg <= coarse_time; + fine_time_reg <= fine_time; + IF grspw_tick ='1' THEN + tick_ongoing <= '1'; + ELSIF tick_ongoing = '1' THEN + IF (fine_time_reg /= fine_time) OR (coarse_time_reg /= coarse_time) THEN + tick_ongoing <= '0'; + END IF; + END IF; + + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- ASSERTION 1 : + -- Coarse_time "changed" => FINE_TIME = 0 + -- False after a TRANSITION ! + ----------------------------------------------------------------------------- + PROCESS (clk25MHz, resetn) + BEGIN -- PROCESS + IF resetn = '0' THEN -- asynchronous reset (active low) + ASSERTION_1 <= '1'; + ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge + IF coarse_time /= coarse_time_reg THEN + IF fine_time /= X"0000" THEN + IF fine_time /= X"0041" THEN + ASSERTION_1 <= '0'; + ELSE + ASSERTION_1 <= 'U'; + END IF; + ELSE + ASSERTION_1 <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- ASSERTION 2 : + -- tick => next(FINE_TIME) = 0 + ----------------------------------------------------------------------------- + PROCESS (clk25MHz, resetn) + BEGIN -- PROCESS + IF resetn = '0' THEN -- asynchronous reset (active low) + ASSERTION_2 <= '1'; + ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge + IF tick_ongoing = '1' THEN + IF fine_time_reg /= fine_time OR coarse_time_reg /= coarse_time THEN + IF fine_time /= X"0000" THEN + ASSERTION_2 <= '0'; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- ASSERTION 3 : + -- next(TIME) > TIME + -- false if resynchro, or new coarse_time + ----------------------------------------------------------------------------- + PROCESS (clk25MHz, resetn) + BEGIN -- PROCESS + IF resetn = '0' THEN -- asynchronous reset (active low) + ASSERTION_3 <= '1'; + ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge + ASSERTION_3 <= '1'; + IF global_time_reg(46 DOWNTO 0) > global_time(46 DOWNTO 0) THEN + IF global_time(47) = '0' AND global_time_reg(47) = '1' THEN + ASSERTION_3 <= 'U'; -- RESYNCHRO .... + ELSE + ASSERTION_3 <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + + +END beh; +