##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

MiniSpartan6:...
MiniSpartan6: added ftdi chip config to switch between UART and Async FIFO. added few WIP designs with either spwlight core, FIFO_deom IP... Libs: added SpaceWire Light IP (Works really well!) started design of ahb_ftdi_fifo -> same protocol than AHBUART but over FTDI's Async FIFO interface. This might lead to much faster transfers UP to 12MB/s.
jeandet -
r681:9d85f9f8f05a default
Show More
This tree as .zip
Name Size Modified Last Commit Author
/ designs / EGSE_ICI
.config Loading ...
DC_GATE_GEN.vhd Loading ...
EGSE_ICI.vhd Loading ...
ICI_EGSE_PROTOCOL.vhd Loading ...
ICI_EGSE_PROTOCOL2.vhd Loading ...
LF_GATE_GEN.vhd Loading ...
MajF_Gen.vhd Loading ...
Makefile Loading ...
MinF_Gen.vhd Loading ...
Serial_driver.vhd Loading ...
config.help Loading ...
config.in Loading ...
config.vhd Loading ...
config.vhd.h Loading ...
config.vhd.in Loading ...
defconfig Loading ...
indata Loading ...
lconfig.tk Loading ...
rhumc.dc Loading ...
testbench.vhd Loading ...
tkconfig.h Loading ...
top.qsf Loading ...
top.rc Loading ...
top.xise Loading ...
top_dc.tcl Loading ...
top_designer.tcl Loading ...
top_designer_act.tcl Loading ...
tsmc13.rc Loading ...
wave.do Loading ...